A circuit package test system and method based on intelligent computing power algorithm

Abstract

The application discloses a circuit package test system and method based on an intelligent computing power algorithm, relates to the technical field of circuit package test, and screens out a first target test node containing abnormal data and constructs a target parameter data group by calling historical test data; average abnormal frequency and signal bias ratio of the first test node are calculated, and a fault influence factor is calculated to determine a second target test node; a fault risk probability of the second target test node is predicted, and then, according to the fault risk probability, a test path is dynamically regulated and controlled, and a high-risk test node is preferentially tested; the problems that a traditional fixed test process is poor in adaptability and high in labor and time cost are solved, and circuit package test efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit packaging and testing technology, specifically a circuit packaging and testing system and method based on intelligent computing algorithms. Background Technology

[0002] Currently, circuit packaging testing typically employs a fixed testing procedure, testing the circuit according to a preset node sequence and parameters. Testers then track and analyze the testing process and results in the background. This method often requires significant manpower and time investment. Furthermore, due to differences in the characteristics of different batches and circuits of varying complexity, the fixed testing procedure may be difficult to adapt precisely, leading to test result deviations or insufficient targeted testing of circuit characteristics. This can further cause potential packaging quality issues or malfunctions during subsequent circuit use. Once a malfunction occurs, the circuit design or packaging structure needs to be optimized and debugged based on the test results. This often requires testers to re-examine the testing procedure, adjust the test node sequence and parameters, and repeatedly debug among a large amount of test data and circuit characteristic parameters, resulting in a huge workload and burden for testers. Summary of the Invention

[0003] The purpose of this invention is to provide a circuit packaging testing system and method based on intelligent computing power algorithms to solve the problems raised in the prior art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a circuit packaging testing method based on intelligent computing power algorithms, the circuit packaging testing method comprising:

[0005] Step S100: Retrieve historical circuit package test data records; filter the historical circuit package test data records, extract target data, and set the test node corresponding to the target data as the first target test node; based on the target data, obtain the target parameter data group of the first target test node;

[0006] Step S200: Analyze the target data in the target parameter data group and calculate the average anomaly frequency of the first target test node;

[0007] Step S300: Analyze the target parameter data set of the first target test node to obtain the signal bias ratio of the first target test node;

[0008] Step S400: Calculate the fault impact factor of each first target test node based on the average anomaly frequency and signal bias ratio of the first target test node; integrate and analyze the fault impact factors corresponding to all first target test nodes to obtain the second target test node;

[0009] Step S500: Perform fault risk probability prediction on the second target test node respectively; based on the prediction results, intelligently adjust the test path in the circuit packaging test system to obtain a dynamic test path.

[0010] Furthermore, step S100 includes:

[0011] Step S101: The testing equipment periodically monitors the operating status of each test node in the circuit and generates test data records; the testing equipment includes a voltage probe, a current probe, a temperature sensor, and a signal analyzer;

[0012] Step S102: Extract the voltage data monitored by the voltage probe from each of the historical circuit package test data records. Current data monitored by the current probe and temperature data monitored by temperature sensors To form data tuples If the data tuple If a data item in the data tuple exceeds the corresponding data threshold, then the data tuple is set to... The data in the middle is the target data. The target data The corresponding test node is the first target test node; among them, This represents the j-th target data of the i-th first target test node;

[0013] Step S103: Extract the signal change monitored by the signal analyzer from the historical circuit package test data record corresponding to the first target test node. ;in, This represents the signal change corresponding to the j-th target data of the i-th first target test node;

[0014] Step S104: Integrate the target data and corresponding signal changes corresponding to all first target test nodes to obtain the target parameter data set of the first target test nodes. .

[0015] Furthermore, step S200 includes:

[0016] Step S201: Extract the target parameter data set of the first target test node. The same signal change is divided into target changes, and all target data corresponding to the target changes are extracted to form a target data sequence:

[0017] ;

[0018] Step S202: Sort the target data in the target data sequence D according to the time series, compare two adjacent target data, and if the difference between two adjacent target data exceeds a preset range, accumulate the number of abnormalities of the first target test node; obtain the total number of abnormalities of the first target test node corresponding to the target change amount, and record the time interval corresponding to each abnormality of the first target test node corresponding to the target change amount, and obtain the total time interval corresponding to the abnormality of the first target test node corresponding to the target change amount;

[0019] Step S203: Calculate the average anomaly frequency of the first target test node:

[0020] ;

[0021] in, This represents the average anomaly frequency of the first target test node. This represents the total number of anomalies corresponding to the j-th type of target change. This represents the weighting factor corresponding to the total number of anomalies. This represents the total time interval corresponding to the occurrence of an anomaly at the first target test node corresponding to the j-th type of target change. This indicates the number of types of target changes;

[0022] In the above steps, the "average anomaly frequency" is used to quantify the frequency of anomalies occurring at the test node within a specific time range. This indicator can intuitively reflect the stability of the circuit corresponding to the test node. The higher the average anomaly frequency, the higher the frequency of anomalies occurring in the historical tests of the circuit corresponding to the test node, the more unstable its operating state, and the greater the possibility of potential faults.

[0023] Furthermore, step S300 includes:

[0024] Step S301: From the target parameter data group of the first target test node In the process, all signal changes of the first target test node are extracted, and the signal changes are numbered according to the time series to obtain the signal change sequence of the first target test node:

[0025] ;

[0026] Step S302: Calculate the difference in change ,in, , Let represent the (j+1)th and (j)th signal changes of the i-th first target test node, respectively;

[0027] Step S303: If the change difference If the signal at the first target test node changes, it is determined that a signal enhancement change has occurred, and the number of positive offsets of the first target test node is accumulated. If the difference in the change If the signal attenuation at the first target test node changes, then the number of reverse offsets of the first target test node is accumulated. ; Calculate the signal bias ratio of the first target test node:

[0028] ;

[0029] in, Indicates the signal bias ratio of the first target test node;

[0030] In the above steps, the "signal bias ratio" is used to reflect the overall trend of signal changes. The significance of this indicator lies in revealing the long-term deviation pattern of the signal characteristics of the test node. Different deviation trends correspond to different types of potential faults.

[0031] Furthermore, step S400 includes:

[0032] Step S401: Calculate the fault impact factor of the first target test node:

[0033] ;

[0034] in, This represents the failure impact factor of the first target test node. This represents the average anomaly frequency of the first target test node. This represents the weighting factor corresponding to the average anomaly frequency. This indicates the signal bias ratio of the first target test node. This represents the weighting factor corresponding to the signal bias ratio;

[0035] Step S402: Integrate the fault impact factors of all first target test nodes; if the fault impact factor is greater than the preset fault impact factor threshold, then set the first target test node corresponding to the fault impact factor as the second target test node;

[0036] In the above steps, the "fault impact factor" is used to quantify the impact of the circuit fault corresponding to the test node on the overall circuit. The larger the fault impact factor, the higher the potential harm of the circuit corresponding to the test node to the overall circuit.

[0037] Furthermore, step S500 includes:

[0038] Step S501: Retrieve historical fault data for all second target test nodes from the historical database, and calculate the cumulative test duration of the second target test nodes; calculate the fault risk probability of each second target test node:

[0039] ;

[0040] in, This represents the probability of failure for the second target test node. This indicates the cumulative test duration of the second target test node. This indicates the fault-free runtime of the second target test node. Indicates the adjustment factor;

[0041] Step S502: Organize all test paths in the circuit packaging test system, mark the second target test node in the test path corresponding to each circuit, and test the marked second target test node in the test path in order of failure risk probability from large to small. The test order of the remaining test nodes in the test path is correspondingly rearranged to form a dynamic test path.

[0042] In the above steps, "fault risk probability" combines historical data with current operating status data to dynamically assess the real-time risk level at the test node. This indicator is used to adjust the test path, prioritizing the testing of nodes with high risk probability, enabling the early detection and handling of potential faults and shortening the fault investigation time.

[0043] Furthermore, in order to better implement the above method, a circuit packaging test system based on intelligent computing power algorithm is also provided. The circuit packaging test system includes: a data acquisition module, an analysis and calculation module, a fault risk prediction module, and a path control module.

[0044] The data acquisition module is used to acquire, filter, and integrate circuit test data, providing data support for the subsequent analysis and calculation module.

[0045] The analysis and calculation module analyzes the target data acquired by the data acquisition module, calculates the average frequency of change and the signal bias ratio, in order to identify high-priority test nodes.

[0046] The fault risk prediction module predicts the fault risk probability of the selected high-priority test nodes.

[0047] The path control module dynamically adjusts the test path based on the predicted failure risk probability.

[0048] Furthermore, the data acquisition module includes: a data retrieval unit, a data filtering unit, and a signal acquisition unit;

[0049] The data retrieval unit periodically retrieves the operating data of each test node of the circuit monitored by the test equipment and generates historical test data records.

[0050] The data filtering unit extracts voltage, current, and temperature data from the historical test data records to form data tuples, filters out target data exceeding the threshold in the data tuples, and identifies the first target test node.

[0051] The signal acquisition unit extracts the signal change monitored by the signal analyzer corresponding to the first target test node, and integrates the target data and the corresponding signal change into a target parameter data group.

[0052] Furthermore, the analysis and calculation module includes: an anomaly frequency calculation unit, a signal bias ratio calculation unit, and a fault impact factor calculation unit;

[0053] The anomaly frequency calculation unit analyzes the target parameter data set according to the time series and calculates the average anomaly frequency of the first target test node;

[0054] The signal bias ratio calculation unit analyzes the difference in signal changes, counts the number of positive and negative offsets, and calculates the signal bias ratio.

[0055] The fault impact factor calculation unit combines the average anomaly frequency and signal bias ratio to calculate the fault impact factor through weighting, and then selects the second target test node.

[0056] Furthermore, the path control module includes: a fault risk probability calculation unit and a test path control unit;

[0057] The fault risk probability calculation unit calculates the fault risk probability of the second target test node based on the historical fault data of the second target test node.

[0058] The test path control unit organizes the test path of the circuit package test system, prioritizes the second target test node according to the probability of failure risk from high to low, and puts the remaining test nodes later, forming a dynamic test path.

[0059] Compared with the prior art, the beneficial effects of the present invention are:

[0060] 1. Targeted testing: By screening test nodes, high-risk test nodes are accurately identified, avoiding indiscriminate testing of all test nodes, enhancing the targeting of testing, and reducing invalid testing steps.

[0061] 2. Optimize test paths: Identify high-risk test nodes in the original test paths and prioritize testing high-risk test nodes to facilitate early detection of potential faults, shorten the fault diagnosis cycle, and improve test efficiency.

[0062] 3. Reduce manpower and time costs: Intelligent computing algorithms automatically complete data filtering, analysis and path control, reducing reliance on manual operation, avoiding repeated debugging by testers in large amounts of data, and reducing manpower input and time consumption. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the method flow of a circuit packaging test system and method based on intelligent computing power algorithm according to the present invention;

[0064] Figure 2 This is a schematic diagram of the system structure of a circuit packaging testing system and method based on intelligent computing power algorithm according to the present invention. Detailed Implementation

[0065] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] Example 1: As Figure 1 As shown, the present invention provides a technical solution: a circuit packaging testing method based on intelligent computing power algorithms, which includes:

[0067] Step S100: Retrieve historical circuit package test data records; filter the historical circuit package test data records, extract target data, and set the test node corresponding to the target data as the first target test node; based on the target data, obtain the target parameter data group of the first target test node;

[0068] Step S100 includes:

[0069] Step S101: The testing equipment periodically monitors the operating status of each test node in the circuit and generates test data records; the testing equipment includes a voltage probe, a current probe, a temperature sensor, and a signal analyzer;

[0070] Step S102: Extract the voltage data monitored by the voltage probe from each of the historical circuit package test data records. Current data monitored by the current probe and temperature data monitored by temperature sensors To form data tuples If the data tuple If a data item in the data tuple exceeds the corresponding data threshold, then the data tuple is set to... The data in the middle is the target data. The target data The corresponding test node is the first target test node; among them, This represents the j-th target data of the i-th first target test node;

[0071] Step S103: Extract the signal change monitored by the signal analyzer from the historical circuit package test data record corresponding to the first target test node. ;in, This represents the signal change corresponding to the j-th target data of the i-th first target test node;

[0072] Step S104: Integrate the target data and corresponding signal changes corresponding to all first target test nodes to obtain the target parameter data set of the first target test nodes. ;

[0073] Step S200: Analyze the target data in the target parameter data group and calculate the average anomaly frequency of the first target test node;

[0074] Step S200 includes:

[0075] Step S201: Extract the target parameter data set of the first target test node. The same signal change is divided into target changes, and all target data corresponding to the target changes are extracted to form a target data sequence:

[0076] ;

[0077] Step S202: Sort the target data in the target data sequence D according to the time series, compare two adjacent target data, and if the difference between two adjacent target data exceeds a preset range, accumulate the number of abnormalities of the first target test node; obtain the total number of abnormalities of the first target test node corresponding to the target change amount, and record the time interval corresponding to each abnormality of the first target test node corresponding to the target change amount, and obtain the total time interval corresponding to the abnormality of the first target test node corresponding to the target change amount;

[0078] Step S203: Calculate the average anomaly frequency of the first target test node:

[0079] ;

[0080] in, This represents the average anomaly frequency of the first target test node. This represents the total number of anomalies corresponding to the j-th type of target change. This represents the weighting factor corresponding to the total number of anomalies. This represents the total time interval corresponding to the occurrence of an anomaly at the first target test node corresponding to the j-th type of target change. This indicates the number of types of target changes;

[0081] Step S300: Analyze the target parameter data set of the first target test node to obtain the signal bias ratio of the first target test node;

[0082] Step S300 includes:

[0083] Step S301: From the target parameter data group of the first target test node In the process, all signal changes of the first target test node are extracted, and the signal changes are numbered according to the time series to obtain the signal change sequence of the first target test node:

[0084] ;

[0085] Step S302: Calculate the difference in change ,in, , Let represent the (j+1)th and (j)th signal changes of the i-th first target test node, respectively;

[0086] Step S303: If the change difference If the signal at the first target test node changes, it is determined that a signal enhancement change has occurred, and the number of positive offsets of the first target test node is accumulated. If the difference in the change If the signal attenuation at the first target test node changes, then the number of reverse offsets of the first target test node is accumulated. ; Calculate the signal bias ratio of the first target test node:

[0087] ;

[0088] in, Indicates the signal bias ratio of the first target test node;

[0089] Step S400: Calculate the fault impact factor of each first target test node based on the average anomaly frequency and signal bias ratio of the first target test node; integrate and analyze the fault impact factors corresponding to all first target test nodes to obtain the second target test node;

[0090] Step S400 includes:

[0091] Step S401: Calculate the fault impact factor of the first target test node:

[0092] ;

[0093] in, This represents the failure impact factor of the first target test node. This represents the average anomaly frequency of the first target test node. This represents the weighting factor corresponding to the average anomaly frequency. This indicates the signal bias ratio of the first target test node. This represents the weighting factor corresponding to the signal bias ratio;

[0094] Step S402: Integrate the fault impact factors of all first target test nodes; if the fault impact factor is greater than the preset fault impact factor threshold, then set the first target test node corresponding to the fault impact factor as the second target test node;

[0095] Step S500: Perform fault risk probability prediction on the second target test node respectively; based on the prediction results, intelligently adjust the test path in the circuit packaging test system to obtain the dynamic test path;

[0096] Step S500 includes:

[0097] Step S501: Retrieve historical fault data for all second target test nodes from the historical database, and calculate the cumulative test duration of the second target test nodes; calculate the fault risk probability of each second target test node:

[0098] ;

[0099] in, This represents the probability of failure for the second target test node. This indicates the cumulative test duration of the second target test node. This indicates the fault-free runtime of the second target test node. Indicates the adjustment factor;

[0100] Step S502: Organize all test paths in the circuit packaging test system, mark the second target test node in the test path corresponding to each circuit, and test the marked second target test node in the test path in order of failure risk probability from large to small. The test order of the remaining test nodes in the test path is correspondingly rearranged to form a dynamic test path.

[0101] Example 2: Figure 2 As shown, in order to better implement the above method, a circuit packaging test system based on intelligent computing power algorithm is also provided. The circuit packaging test system includes: a data acquisition module, an analysis and calculation module, a fault risk prediction module, and a path control module.

[0102] The data acquisition module is used to acquire, filter, and integrate circuit test data, providing data support for the subsequent analysis and calculation module.

[0103] The analysis and calculation module analyzes the target data acquired by the data acquisition module, calculates the average frequency of change and the signal bias ratio, in order to identify high-priority test nodes.

[0104] The fault risk prediction module predicts the fault risk probability of the selected high-priority test nodes.

[0105] The path control module dynamically adjusts the test path based on the failure risk probability prediction results;

[0106] The data acquisition module includes: a data retrieval unit, a data filtering unit, and a signal acquisition unit;

[0107] The data retrieval unit periodically retrieves the operating data of each test node of the circuit monitored by the test equipment and generates historical test data records.

[0108] The data filtering unit extracts voltage, current, and temperature data from the historical test data records to form data tuples, filters out target data exceeding the threshold in the data tuples, and identifies the first target test node.

[0109] The signal acquisition unit extracts the signal change monitored by the signal analyzer corresponding to the first target test node, and integrates the target data and the corresponding signal change into a target parameter data group.

[0110] The analysis and calculation module includes: an anomaly frequency calculation unit, a signal bias ratio calculation unit, and a fault impact factor calculation unit.

[0111] The anomaly frequency calculation unit analyzes the target parameter data set according to the time series and calculates the average anomaly frequency of the first target test node;

[0112] The signal bias ratio calculation unit analyzes the difference in signal changes, counts the number of positive and negative offsets, and calculates the signal bias ratio.

[0113] The fault impact factor calculation unit combines the average anomaly frequency and signal bias ratio to calculate the fault impact factor through weighting and select the second target test node.

[0114] The path control module includes: a fault risk probability calculation unit and a test path control unit;

[0115] The fault risk probability calculation unit calculates the fault risk probability of the second target test node based on the historical fault data of the second target test node.

[0116] The test path control unit organizes the test path of the circuit package test system, prioritizes the second target test node according to the failure risk probability from high to low, and puts the remaining test nodes later to form a dynamic test path.

[0117] In an embodiment of the present invention, a circuit contains three test nodes. , , The testing equipment periodically collects the voltage of these three test nodes. Current ,temperature and signal change The system filters out , test node , , Data exceeding the threshold will trigger a test node. , Set as the first target test node, its target parameter data set is as follows: , ; The same signal change at the node corresponds to three instances where the difference in the target data sequence exceeds the preset range, with a total time interval of 60 minutes, and an average anomaly frequency. times / minute; The node reported two anomalies, with a total time interval of 40 minutes. times / minute (weighting factor set to 1); Difference in signal change in node signal change sequence There were 2 times. There was one instance where the signal bias was greater than... Node B There was one time. There was one instance where the signal bias was greater than... Let the weighting factor be... , , Node failure impact factors ; Node failure impact factors The preset fault impact factor threshold is 0.3, therefore The node is the second target test node; Node cumulative test duration Minutes, trouble-free runtime Minutes, adjustment coefficient Fault risk probability In the test path Nodes are tested first, and the remaining nodes are tested later, forming a dynamic path.

[0118] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A circuit packaging testing method based on intelligent computing power algorithms, characterized in that: The circuit packaging test method includes: Step S100: Retrieve historical circuit package test data records; filter the historical circuit package test data records, extract target data, and set the test node corresponding to the target data as the first target test node; based on the target data, obtain the target parameter data group of the first target test node; Step S200: Analyze the target data in the target parameter data group and calculate the average anomaly frequency of the first target test node; Step S300: Analyze the target parameter data set of the first target test node to obtain the signal bias ratio of the first target test node; Step S400: Calculate the fault impact factor of each first target test node based on the average anomaly frequency and signal bias ratio of the first target test node; integrate and analyze the fault impact factors corresponding to all first target test nodes to obtain the second target test node; Step S500: Perform fault risk probability prediction on the second target test node respectively; based on the prediction results, intelligently adjust the test path in the circuit packaging test system to obtain a dynamic test path.

2. The circuit packaging testing method based on intelligent computing power algorithm according to claim 1, characterized in that: Step S100 includes: Step S101: The testing equipment periodically monitors the operating status of each test node in the circuit and generates test data records; the testing equipment includes a voltage probe, a current probe, a temperature sensor, and a signal analyzer; Step S102: Extract the voltage data monitored by the voltage probe from each of the historical circuit package test data records. Current data monitored by the current probe and temperature data monitored by temperature sensors To form data tuples If the data tuple If a data item in the data tuple exceeds the corresponding data threshold, then the data tuple is set to... The data in the middle is the target data. The target data The corresponding test node is the first target test node; among them, This represents the j-th target data of the i-th first target test node; Step S103: Extract the signal change monitored by the signal analyzer from the historical circuit package test data record corresponding to the first target test node. ;in, This represents the signal change corresponding to the j-th target data of the i-th first target test node; Step S104: Integrate the target data and corresponding signal changes corresponding to all first target test nodes to obtain the target parameter data set of the first target test nodes. .

3. The circuit packaging testing method based on intelligent computing power algorithm according to claim 1, characterized in that: Step S200 includes: Step S201: Extract the target parameter data set of the first target test node. The same signal change is divided into target changes, and all target data corresponding to the target changes are extracted to form a target data sequence: ； Step S202: Sort the target data in the target data sequence D according to the time series, compare two adjacent target data, and if the difference between two adjacent target data exceeds a preset range, accumulate the number of abnormalities of the first target test node; obtain the total number of abnormalities of the first target test node corresponding to the target change amount, and record the time interval corresponding to each abnormality of the first target test node corresponding to the target change amount, and obtain the total time interval corresponding to the abnormality of the first target test node corresponding to the target change amount; Step S203: Calculate the average anomaly frequency of the first target test node: ； in, This represents the average anomaly frequency of the first target test node. This represents the total number of anomalies corresponding to the j-th type of target change. This represents the weighting factor corresponding to the total number of anomalies. This represents the total time interval corresponding to the occurrence of an anomaly at the first target test node corresponding to the j-th type of target change. This indicates the number of types of target changes.

4. The circuit packaging testing method based on intelligent computing power algorithm according to claim 1, characterized in that: Step S300 includes: Step S301: From the target parameter data group of the first target test node In the process, all signal changes of the first target test node are extracted, and the signal changes are numbered according to the time series to obtain the signal change sequence of the first target test node: ； Step S302: Calculate the difference in change ,in, , Let represent the (j+1)th and (j)th signal changes of the i-th first target test node, respectively; Step S303: If the change difference If the signal at the first target test node changes, it is determined that a signal enhancement change has occurred, and the number of positive offsets of the first target test node is accumulated. If the difference in the change If the signal attenuation at the first target test node changes, then the number of reverse offsets of the first target test node is accumulated. ; Calculate the signal bias ratio of the first target test node: ； in, This indicates the signal bias ratio of the first target test node.

5. The circuit packaging testing method based on intelligent computing power algorithm according to claim 1, characterized in that: Step S400 includes: Step S401: Calculate the fault impact factor of the first target test node: ； in, This represents the failure impact factor of the first target test node. This represents the average anomaly frequency of the first target test node. This represents the weighting factor corresponding to the average anomaly frequency. This indicates the signal bias ratio of the first target test node. This represents the weighting factor corresponding to the signal bias ratio; Step S402: Integrate the fault impact factors of all first target test nodes; if the fault impact factor is greater than the preset fault impact factor threshold, then set the first target test node corresponding to the fault impact factor as the second target test node.

6. The circuit packaging testing method based on intelligent computing power algorithm according to claim 1, characterized in that: Step S500 includes: Step S501: Retrieve historical fault data for all second target test nodes from the historical database, and calculate the cumulative test duration of the second target test nodes; calculate the fault risk probability of each second target test node: ； in, This represents the probability of failure for the second target test node. This indicates the cumulative test duration of the second target test node. This indicates the fault-free runtime of the second target test node. Indicates the adjustment factor; Step S502: Organize all test paths in the circuit packaging test system, mark the second target test node in the test path corresponding to each circuit, and test the marked second target test node in the test path in order of failure risk probability from large to small. The test order of the remaining test nodes in the test path is correspondingly rearranged to form a dynamic test path.

7. A circuit packaging test system based on intelligent computing power algorithms, used to execute the circuit packaging test method based on intelligent computing power algorithms according to any one of claims 1-6, characterized in that: The circuit packaging test system includes: a data acquisition module, an analysis and calculation module, a fault risk prediction module, and a path control module; The data acquisition module is used to acquire, filter and integrate circuit test data, providing data support for the subsequent analysis and calculation module. The analysis and calculation module analyzes the target data acquired by the data acquisition module, calculates the average change frequency and signal bias ratio, and identifies high-priority test nodes. The fault risk prediction module predicts the fault risk probability of the selected high-priority test nodes. The path control module dynamically adjusts the test path based on the fault risk probability prediction results.

8. The circuit packaging and testing system based on intelligent computing power algorithm according to claim 7, characterized in that: The data acquisition module includes: a data retrieval unit, a data filtering unit, and a signal acquisition unit; The data retrieval unit periodically retrieves the operating data of each test node of the circuit monitored by the test equipment and generates historical test data records. The data filtering unit extracts voltage, current and temperature data from the historical test data records to form data tuples, filters out target data exceeding the threshold in the data tuples, and identifies the first target test node. The signal acquisition unit extracts the signal change monitored by the signal analyzer corresponding to the first target test node, and integrates the target data and the corresponding signal change into a target parameter data group.

9. A circuit packaging and testing system based on intelligent computing power algorithm according to claim 7, characterized in that: The analysis and calculation module includes: an anomaly frequency calculation unit, a signal bias ratio calculation unit, and a fault impact factor calculation unit; The anomaly frequency calculation unit analyzes the target parameter data group according to the time series and calculates the average anomaly frequency of the first target test node. The signal bias ratio calculation unit analyzes the difference in signal changes, counts the number of positive and negative offsets, and calculates the signal bias ratio. The fault impact factor calculation unit combines the average anomaly frequency and signal bias ratio to calculate the fault impact factor through weighting, and then selects the second target test node.

10. A circuit packaging and testing system based on intelligent computing power algorithm according to claim 7, characterized in that: The path control module includes: a fault risk probability calculation unit and a test path control unit; The fault risk probability calculation unit calculates the fault risk probability of the second target test node based on the historical fault data of the second target test node. The test path control unit organizes the test path of the circuit packaging test system, prioritizes the second target test node according to the probability of failure risk from high to low, and puts the remaining test nodes later, forming a dynamic test path.

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