PFC device control method and device, power supply system, medium and product

Abstract

The invention discloses a PFC device control method and device, a power supply system, a storage medium and a computer program product, and the method comprises the steps: under the operation condition of a PFC device, according to the input voltage of the PFC device, the current of an inductor module, the output voltage of the PFC device, and the given duty ratio of a power switch tube module, carrying out the control of the PFC device according to the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty ratio of the power switch tube module; processing in the voltage loop and the current loop by using an ADRC module, and determining the current duty ratio of the power switch tube module; and outputting a PWM signal to the power switch tube module according to the current duty ratio of the power switch tube module, and controlling on and off of a corresponding power switch tube in the power switch tube module so as to adjust the waveform and / or phase of the input current of the PFC device. According to the scheme, an ADRC control strategy is adopted in a current loop and a voltage loop, and a feed-forward link is arranged in the current loop, so that the anti-interference capability and the response speed of current to voltage tracking are improved.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a control method, device, power supply system, storage medium, and computer program product for a PFC device, and particularly to a control method, device, power supply system, storage medium, and computer program product for a bridgeless PFC circuit. Background Technology

[0002] With the rapid development of modern power electronics technology, the importance of power factor correction (PFC) circuits in power systems is becoming increasingly prominent. The main purpose of PFC circuits is to improve the utilization rate of electrical energy, reduce the waste of reactive power, thereby reducing the burden on the power grid and improving power quality. Traditional PFC circuits typically use bridge rectifiers, but this structure has disadvantages such as many components, large size, and low efficiency, making it difficult to meet the requirements of modern power electronic systems for high efficiency, miniaturization, and high dynamic response.

[0003] To address these issues, bridgeless PFC circuits have emerged as a novel topology. Bridgeless PFC circuits eliminate the bridge rectifier found in traditional PFC circuits, simplifying the circuit structure and improving system efficiency and reliability. However, bridgeless PFC circuits also face some control challenges; for example, their interference immunity is relatively weak, affecting the accuracy of current waveform control.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The purpose of this invention is to provide a control method, device, power supply system, storage medium, and computer program product for a PFC device, in order to solve the problem that the anti-interference capability of bridgeless PFC circuits is weak, which affects the accuracy of current waveform control. The invention achieves the effect of improving anti-interference capability and accuracy of current waveform control by adopting ADRC control strategies in both the current loop and voltage loop to consider system interference through extended states; and by setting a feedforward link in the current loop to use the initial duty cycle of the drive signal of the power switch as a feedforward term, the response speed of current to voltage tracking is improved.

[0006] This invention provides a control method for a Power Factor Correction (PFC) device. The PFC device includes an inductor module and a power switch module. The control system of the PFC device includes a voltage loop and a current loop. A feedforward loop is provided on the output side of the current loop, and ADRC modules are provided in both the voltage loop and the current loop. The control method of the PFC device includes: acquiring the input voltage of the PFC device, acquiring the current of the inductor module, acquiring the output voltage of the PFC device, and acquiring a given duty cycle of the power switch module provided by the feedforward loop, while the PFC device is operating; processing the input voltage, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module using the ADRC modules in the voltage loop and the current loop to determine the current duty cycle of the power switch module; and outputting a PWM signal to the power switch module based on the current duty cycle of the power switch module to control the on and off of the corresponding power switch in the power switch module, thereby adjusting the waveform and / or phase of the input current of the PFC device.

[0007] In some implementations, the current duty cycle of the power switch module is determined by processing data using ADRC modules in the voltage loop and the current loop based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module. This includes: processing the output voltage of the PFC device and a preset reference voltage through the ADRC module in the voltage loop to obtain the intermediate value of the target input current of the PFC device; processing the input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device through the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module; and using the sum of the given duty cycle and the calculated duty cycle of the power switch module as the current duty cycle of the power switch module.

[0008] In some embodiments, the output voltage of the PFC device and a preset reference voltage are processed by the ADRC module in the voltage loop to obtain the intermediate value of the target input current of the PFC device. This includes: processing the output voltage of the PFC device by a preset first A / D module to obtain the digital output voltage of the PFC device; using the digital output voltage of the PFC device as the actual value of the ADRC module in the voltage loop, and using the preset reference voltage as the target value of the ADRC module in the voltage loop; inputting the digital output voltage of the PFC device and the preset reference voltage into the ADRC module in the voltage loop respectively to obtain the output value of the ADRC module in the voltage loop, which is used as the intermediate value of the target input current of the PFC device.

[0009] In some implementations, the input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device are processed by the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module. This includes: determining the effective value of the input voltage of the PFC device based on the input voltage of the PFC device; processing the input voltage of the PFC device through a preset second A / D module to obtain the digital input voltage of the PFC device; and processing the current of the inductor module through a preset second A / D module to obtain the digital current value of the inductor module; and processing the PFC device... The product of the digital input voltage and the intermediate value of the target input current of the PFC device is divided by the effective value of the input voltage of the PFC device to obtain the target input current of the PFC device. The target input current of the PFC device is used as the target value of the ADRC module in the current loop, and the digital current value of the inductor module is used as the actual value of the ADRC module in the current loop. The digital current value of the inductor module and the target input current of the PFC device are respectively input into the ADRC module in the current loop to obtain the output value of the ADRC module in the current loop, which is used as the calculated duty cycle of the power switch module.

[0010] In some implementations, the expression for the given duty cycle of the power switch module provided by the feedforward circuit is as follows:

[0011] d2(n) = K1 - |Uin / Uoref|;

[0012] Wherein, d2(n) represents the given duty cycle of the power switch module provided by the feedforward link, K1 represents the set calculation coefficient, Uin represents the input voltage of the PFC device, and Uoref represents the ideal value of the output voltage of the PFC device.

[0013] In some embodiments, the ADRC module includes a TD (Transient Decision) stage, an NLSEF (Non-Standardized Loss Decision) stage, and an ESO (Electronic Stability Decision) stage. The input side of the ADRC module is used to input actual values ​​and target values, and the output side is used to output the required output value. Processing using the ADRC module includes: based on the target value input to the ADRC module's input side, performing a transition process through the TD stage to obtain a transition value of the target value; based on the actual value input to the ADRC module's input side, performing an estimation process through the ESO stage to package interference factors in the actual value into an extended state, obtaining a first estimated value and a second estimated value of the actual value. The difference between the transitional value of the target value and the second estimated value of the actual value is processed by the NLSEF loop to obtain the nonlinear configuration value of the deviation between the target value and the actual value, which is denoted as the deviation configuration value between the target value and the actual value. The difference between the deviation configuration value between the target value and the actual value and the ratio of the first estimated value of the actual value and the preset control input proportional coefficient is taken as the output value of the ADRC module. The product of the output value of the ADRC module and the preset control input proportional coefficient is taken as the feedback value of the ESO loop and fed back to the ESO loop to realize closed-loop control.

[0014] In some implementations, wherein in the ADRC module:

[0015] The expression for the TD step is as follows:

[0016] V1 = V1 + h * r0 * Π(y - yr, r, h);

[0017] Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, V1 represents the transition value of the target value, r0, h and r all represent preset transition process control parameters, and Π(y-yr,r,h) represents a preset nonlinear function;

[0018] And / or,

[0019] The expression for the NLSEF stage is as follows:

[0020] u1=r1*(Π(V1-Z1,alph3,belta1));

[0021] Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u1 represents the deviation configuration value between the target value and the actual value, r1 represents the preset adjustment parameter, V1 represents the transition value of the target value, Z1 represents the first estimated value of the actual value, alph3 represents the preset nonlinear parameter, belt1 represents the preset weight parameter, and Π(V1-Z1,alph3,belta1) represents the preset nonlinear function;

[0022] And / or,

[0023] The expression for the ESO step is as follows:

[0024] Z1=Z1+h*(Z2+belta1*(Π(y-Z1,alph1,belta1))+b0*u);

[0025] Z2=Z2+belta2*(Π(y-Z1,alph2,belta1));

[0026] Wherein, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u represents the output value of the ADRC module, h represents the preset transition process control parameter, Z1 represents the first estimated value of the actual value, Z2 represents the second estimated value of the actual value, belt2 represents the preset weight parameter, alph1 and alph2 both represent preset nonlinear parameters, and Π(y-Z1,alph1,belta1) and Π(y-Z1,alph2,belta1) both represent preset nonlinear functions.

[0027] In conjunction with the above method, another aspect of the present invention provides a control device for a PFC device, the PFC device having an inductor module and a power switch module; the control system of the PFC device having a voltage loop and a current loop; a feedforward circuit is provided on the output side of the current loop, and ADRC modules are provided in both the voltage loop and the current loop; the control device for the PFC device includes: an acquisition unit configured to acquire, when the PFC device is operating, the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the power supplied by the feedforward circuit. The given duty cycle of the power switching module; the control unit, configured to process the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switching module using an ADRC module in the voltage loop and the current loop to determine the current duty cycle of the power switching module; the control unit is further configured to output a PWM signal to the power switching module based on the current duty cycle of the power switching module, and control the on and off of the corresponding power switching transistors in the power switching module to adjust the waveform and / or phase of the input current of the PFC device.

[0028] In some embodiments, the control unit determines the current duty cycle of the power switch module by processing data in the voltage loop and the current loop using ADRC modules based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module. This includes: processing the output voltage of the PFC device and a preset reference voltage through the ADRC module in the voltage loop to obtain the intermediate value of the target input current of the PFC device; processing the input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device through the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module; and using the sum of the given duty cycle and the calculated duty cycle of the power switch module as the current duty cycle of the power switch module.

[0029] In some embodiments, the control unit processes the output voltage of the PFC device and a preset reference voltage through an ADRC module in the voltage loop to obtain an intermediate value of the target input current of the PFC device. This includes: processing the output voltage of the PFC device through a preset first A / D module to obtain the digital output voltage of the PFC device; using the digital output voltage of the PFC device as the actual value of the ADRC module in the voltage loop, and using the preset reference voltage as the target value of the ADRC module in the voltage loop; and inputting the digital output voltage of the PFC device and the preset reference voltage into the ADRC module in the voltage loop respectively to obtain the output value of the ADRC module in the voltage loop, which is then used as the intermediate value of the target input current of the PFC device.

[0030] In some embodiments, the control unit processes the input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device through the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module. This includes: determining the effective value of the input voltage of the PFC device based on the input voltage of the PFC device; processing the input voltage of the PFC device through a preset second A / D module to obtain the digital input voltage of the PFC device; and processing the current of the inductor module through a preset second A / D module to obtain the digital current value of the inductor module; and processing the PFC device's input voltage through the ADRC module to obtain the digital current value of the inductor module. The product of the digital input voltage of device C and the intermediate value of the target input current of the PFC device is divided by the effective value of the input voltage of the PFC device to obtain the target input current of the PFC device. The target input current of the PFC device is used as the target value of the ADRC module in the current loop, and the digital current value of the inductor module is used as the actual value of the ADRC module in the current loop. The digital current value of the inductor module and the target input current of the PFC device are respectively input into the ADRC module in the current loop to obtain the output value of the ADRC module in the current loop, which is used as the calculated duty cycle of the power switch module.

[0031] In some implementations, the expression for the given duty cycle of the power switch module provided by the feedforward circuit is as follows:

[0032] d2(n) = K1 - |Uin / Uoref|;

[0033] Wherein, d2(n) represents the given duty cycle of the power switch module provided by the feedforward link, K1 represents the set calculation coefficient, Uin represents the input voltage of the PFC device, and Uoref represents the ideal value of the output voltage of the PFC device.

[0034] In some embodiments, the ADRC module includes a TD (Transient Decision) stage, an NLSEF (Non-Standardized Loss Decision) stage, and an ESO (Electronic Stability Decision) stage. The input side of the ADRC module is used to input actual values ​​and target values, and the output side is used to output the required output value. The control unit utilizes the ADRC module for processing, including: based on the target value input from the ADRC module's input side, performing a transition process through the TD stage to obtain a transition value of the target value; based on the actual value input from the ADRC module's input side, performing an estimation process through the ESO stage to package interference factors in the actual value into an extended state, and obtaining a first estimated value and the actual value. The second estimated value of the target value; the difference between the transition value of the target value and the second estimated value of the actual value is processed by the NLSEF loop to obtain the nonlinear configuration value of the deviation between the target value and the actual value, which is denoted as the deviation configuration value between the target value and the actual value; the difference between the deviation configuration value between the target value and the actual value and the ratio of the first estimated value of the actual value and the preset control input proportional coefficient is taken as the output value of the ADRC module; the product of the output value of the ADRC module and the preset control input proportional coefficient is taken as the feedback value of the ESO loop and fed back to the ESO loop to realize closed-loop control.

[0035] In some implementations, wherein in the ADRC module:

[0036] The expression for the TD step is as follows:

[0037] V1 = V1 + h * r0 * Π(y - yr, r, h);

[0038] Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, V1 represents the transition value of the target value, r0, h and r all represent preset transition process control parameters, and Π(y-yr,r,h) represents a preset nonlinear function;

[0039] And / or,

[0040] The expression for the NLSEF stage is as follows:

[0041] u1=r1*(Π(V1-Z1,alph3,belta1));

[0042] Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u1 represents the deviation configuration value between the target value and the actual value, r1 represents the preset adjustment parameter, V1 represents the transition value of the target value, Z1 represents the first estimated value of the actual value, alph3 represents the preset nonlinear parameter, belt1 represents the preset weight parameter, and Π(V1-Z1,alph3,belta1) represents the preset nonlinear function;

[0043] And / or,

[0044] The expression for the ESO step is as follows:

[0045] Z1=Z1+h*(Z2+belta1*(Π(y-Z1,alph1,belta1))+b0*u);

[0046] Z2=Z2+belta2*(Π(y-Z1,alph2,belta1));

[0047] Wherein, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u represents the output value of the ADRC module, h represents the preset transition process control parameter, Z1 represents the first estimated value of the actual value, Z2 represents the second estimated value of the actual value, belt2 represents the preset weight parameter, alph1 and alph2 both represent preset nonlinear parameters, and Π(y-Z1,alph1,belta1) and Π(y-Z1,alph2,belta1) both represent preset nonlinear functions.

[0048] In conjunction with the above-described device, the present invention further provides a power supply system, including: a control device for the PFC device described above.

[0049] In conjunction with the above method, the present invention further provides a storage medium comprising a stored program, wherein, when the program is executed, the device on which the storage medium is located executes the steps of the control method of the PFC device described above.

[0050] In conjunction with the above method, the present invention further provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the control method for the PFC device described above.

[0051] Therefore, the solution of this invention, for PFC devices (such as bridgeless PFC circuits) with power switches (such as MOS switches), and for the current loop and voltage loop in the control system of the PFC device (such as the control system for controlling the turn-on and turn-off of the power switches in a bridgeless PFC circuit), sets a feedforward link in the current loop to use the initial duty cycle of the drive signal of the power switch as the feedforward term, and adopts ADRC control strategy in both the current loop and the voltage loop to improve anti-interference capability by considering system interference through extended state, thereby realizing the control of the turn-on and turn-off of the power switch; thus, by adopting ADRC control strategy in both the current loop and the voltage loop to consider system interference through extended state, the accuracy of current waveform control is improved; and by setting a feedforward link in the current loop to use the initial duty cycle of the drive signal of the power switch as the feedforward term, the response speed of current to voltage tracking is improved.

[0052] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention.

[0053] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0054] Figure 1 This is a schematic flowchart of an embodiment of the control method for the PFC device of the present invention;

[0055] Figure 2 This is a flowchart illustrating an embodiment of the method of the present invention for determining the current duty cycle of the power switch module;

[0056] Figure 3 This is a schematic flowchart of an embodiment of the method of the present invention, processed by the ADRC module in the voltage loop;

[0057] Figure 4 This is a schematic flowchart of an embodiment of the method of the present invention after processing by the ADRC module in the current loop;

[0058] Figure 5 This is a flowchart illustrating an embodiment of the method of the present invention that utilizes the ADRC module for processing;

[0059] Figure 6 This is a schematic diagram of the structure of a control device of the PFC device of the present invention;

[0060] Figure 7 This is a schematic diagram of the topology of a bridgeless PFC circuit;

[0061] Figure 8This is a schematic diagram of the closed-loop control flow of a bridgeless PFC circuit, which can illustrate the direction of the entire closed-loop control flow.

[0062] Figure 9 This is a flowchart illustrating the ADRC control strategy, demonstrating the ADRC algorithms for the voltage and current loops.

[0063] Figure 10 This is a schematic diagram of the digital control flow of a bridgeless PFC circuit.

[0064] Referring to the accompanying drawings, the reference numerals in the embodiments of the present invention are as follows:

[0065] 102 - Acquisition unit; 104 - Control unit. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0067] Considering the weak anti-interference capability of bridgeless PFC circuits, which affects the accuracy of current waveform control, achieving precise current waveform control has become an urgent problem to be solved. Simultaneously, improving the system's dynamic response capability is also a pressing issue. In other words, how to achieve precise current waveform control and improve the system's dynamic response capability—that is, the ability of the input current Iin in the bridgeless PFC circuit to maintain zero phase difference with the input voltage Uin—is crucial.

[0068] Active disturbance rejection control (ADRC), as an advanced control method, can adjust system parameters in real time to cope with various disturbances and uncertainties. Compared with traditional PID control, ADRC has better dynamic response and anti-interference capability. Applying ADRC to bridgeless PFC circuits can not only improve the dynamic response speed of the system, but also enhance the system's anti-interference capability, thereby achieving a higher power factor and a better current waveform.

[0069] Therefore, the present invention proposes a control method for a PFC device, specifically a control method for a bridgeless PFC circuit. This method employs a dual ADRC closed-loop algorithm with feedforward, incorporating system interference through extended states to improve the system's anti-interference capability, thereby achieving more precise current waveform control. Furthermore, the initial duty cycle of the drive signal is included as a feedforward term in the ADRC, enhancing the system's dynamic response and enabling rapid current-voltage tracking.

[0070] According to embodiments of the present invention, a control method for a PFC device is provided, such as... Figure 1 The diagram shows a flowchart of an embodiment of the method of the present invention. The PFC device includes an inductor module and a power switch module, as shown in the diagram. Figure 7 The bridgeless PFC circuit shown has an inductor module as follows: Figure 7 The inductors L1 and L2 shown are used in the power switching module as follows: Figure 7 The MOSFETs Q1 and Q2 in the bridgeless PFC circuit shown; Figure 7 This is a schematic diagram of the topology of a bridgeless PFC circuit. Figure 7 In this design, inductors L1 and L2 are energy storage elements, serving an energy storage function; diodes D1 and D2 are freewheeling diodes, providing a freewheeling circuit and providing reverse protection; power switches such as MOSFET Q1 and Q2 regulate the magnitude and direction of the current; capacitor C1 serves as a voltage regulator and filter; Load is the load. Uin represents single-phase AC power, and this invention is designed for single-phase AC power input. Figure 7 As shown, the bridgeless PFC circuit includes: inductor L1, inductor L2, diodes D1, D2, D3, and D4, capacitor C1, load Load, and MOSFETs Q1 and Q2. The first connection terminal of the single-phase AC current Uin is connected to the anode of diode D1 via inductor L1. The cathode of diode D1 is connected to the cathode of diode D2, and the cathode of diode D2 is connected to the positive terminal of capacitor C1. The cathode of diode D2 is also connected to the first connection terminal of the load Load. The anode of diode D1 is connected to the drain of MOSFET Q1, and the source of MOSFET Q1 is connected to the negative terminal of capacitor C1. The second connection terminal of the single-phase AC current Uin is connected to the drain of MOSFET Q2 via inductor L2. The drain of MOSFET Q2 is connected to the anode of diode D2. The source of MOSFET Q2 is connected to the negative terminal of capacitor C1. The voltage between the first connection terminal and the second connection terminal of the load is Uo. The first connection terminal of the load is connected to the positive terminal of the voltage Uo, and the second connection terminal of the load is connected to the negative terminal of the voltage Uo.

[0071] Figure 7The working principle and flow of the bridgeless PFC circuit shown are as follows: With a single-phase AC input Uin, high-frequency control of power switches such as MOSFETs Q1 and Q2 causes inductors such as L1 and L2 to store and release energy at different time intervals, thereby controlling the waveform and phase of the input current in the designed circuit (i.e., the bridgeless PFC circuit). Ideally, the input current waveform after correction by the bridgeless PFC circuit should be in phase with the input voltage waveform of the single-phase AC Uin and close to a sine wave. This can greatly improve the power factor of the circuit, reduce reactive power, and improve the efficiency of energy utilization.

[0072] Figure 7 The specific working process of the bridgeless PFC circuit shown is as follows:

[0073] During the positive half-cycle: MOSFET Q2 remains continuously on.

[0074] When the AC input voltage Uin of the single-phase AC power supply is in the positive half-cycle, the branch containing inductor L1 and power switch transistor such as MOSFET Q1 is in operation. At this time, the power switch transistor such as MOSFET Q1 performs high-frequency turn-on and turn-off operations according to a certain duty cycle; this duty cycle is... Figure 8 The value d(n) is the result calculated using the ADRC algorithm and is related to the input voltage, current, and output voltage. In this invention, the duty cycle is the final calculated d(n). During the conduction of the power switch, such as MOSFET Q1, the AC input power supply, i.e., single-phase AC Uin, forms a circuit through inductor L1, the conducting MOSFET Q1, and MOSFET Q2. Inductor L1 stores energy, and the current in inductor L1 gradually increases. During this time, diode D1 is in the reverse cutoff state. During the turn-off of the power switch, such as MOSFET Q1, the energy stored in inductor L1 is released to the load Load through diode D1. Simultaneously, it supplies power to the load Load along with the single-phase AC input power supply Uin. The output voltage of the PFC circuit (i.e., the voltage Uo on the load Load) increases, achieving the boost function. Furthermore, due to the current control during the positive half-cycle, the input current can follow the changes in the input voltage, thereby achieving power factor correction.

[0075] Negative half-cycle operation process 1: MOSFET Q1 is always on for freewheeling.

[0076] When the AC input voltage of the single-phase AC power Uin is in the negative half-cycle, the situation is the opposite of the positive half-cycle. At this time, the branch containing inductor L2 and power switching transistors such as MOSFET Q2 starts to work, and MOSFET Q2 performs high-frequency turn-on and turn-off operations. During the conduction period of MOSFET Q2, the AC input power supply, i.e., the single-phase AC power Uin, forms a loop through inductor L2, the conducting MOSFET Q2, and MOSFET Q1, and inductor L2 stores energy. Diode D2 is in the reverse cutoff state. During the turn-off period of MOSFET Q2, the energy stored in inductor L2 is released to the load Load through diode D2, and together with the input power supply of single-phase AC power Uin, it supplies power to the load Load. The output voltage of the PFC circuit continues to be maintained at a high level, and power factor correction is also achieved in the negative half-cycle. The control system of the PFC device has a voltage loop and a current loop; a feedforward link is set on the output side of the current loop, and ADRC modules are set in both the voltage loop and the current loop. The ADRC module is a module that can run the ADRC algorithm. In the scheme of the present invention, as Figure 1 As shown, the control method of the PFC device includes steps S110 to S130.

[0077] In step S110, while the PFC device is operating, the input voltage of the PFC device is acquired, the current of the inductor module is acquired, the output voltage of the PFC device is acquired, and the given duty cycle of the power switch module provided by the feedforward circuit is acquired; wherein, the input voltage of the PFC device is as follows: Figure 8 The input voltage Uin(t) of the single-phase AC power Uin shown is given, and the current of the inductor module is as follows: Figure 8 The sampled value IL(t) of the current lin on the inductor L1 is shown, and the output voltage of the PFC device is as follows. Figure 8 The output voltage Uo(t) of the bridgeless PFC circuit shown is given by the feedforward circuit. The given duty cycle provided by the feedforward circuit is... Figure 8 The given duty cycle feedforward signal d2(n) is shown.

[0078] In step S120, based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module, the ADRC module is used in the voltage loop and the current loop to determine the current duty cycle of the power switch module; wherein, the current duty cycle of the power switch module is as follows: Figure 8 The final duty cycle d(n) can be obtained by adding the duty cycle d1(n) to the duty cycle feedforward signal d2(n).

[0079] In step S130, based on the current duty cycle of the power switching module, a PWM signal is output to the power switching module to control the on and off of the corresponding power switching transistors in the power switching module, thereby adjusting the waveform and / or phase of the input current of the PFC device, so that the input voltage of the PFC device is in phase with the input current of the PFC device, and the waveform of the input current of the PFC device is a preset standard sine wave. The input current of the PFC device is the current of the inductor module (such as inductor L1 and inductor L2).

[0080] To reduce design costs and improve energy efficiency, a bridgeless PFC circuit is used to improve power quality when the controller (i.e., the load) is connected to the grid, which also simplifies the circuit structure. However, controlling the switching frequency of the power transistors to achieve phase-difference-free tracking of the current and input voltage is a challenge when using a bridgeless PFC circuit. Traditional PFC circuits employ a dual PID closed-loop control method with an inner current loop and an outer voltage loop. In contrast, this invention proposes an ADRC control method with feedforward to achieve faster response and stronger noise immunity. This method incorporates system disturbances into the control algorithm through extended states, improving noise immunity and obtaining a better current waveform. Furthermore, to achieve faster dynamic response, the initial duty cycle of the drive signal is incorporated as a feedforward term into the ADRC, enabling the current to track the voltage more quickly.

[0081] In some implementations, the specific process of determining the current duty cycle of the power switch module in step S120 by using an ADRC module in the voltage loop and the current loop based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module is described in the following exemplary description.

[0082] The following is combined Figure 2 The flowchart shown is a schematic diagram of an embodiment of the method of the present invention for determining the current duty cycle of the power switch module. The specific process of determining the current duty cycle of the power switch module in step S120 is further explained, including steps S210 to S230.

[0083] Step S210: The output voltage of the PFC device and the preset reference voltage are processed by the ADRC module in the voltage loop to obtain the intermediate value of the target input current of the PFC device; wherein, the intermediate value of the target input current of the PFC device is as follows: Figure 8 The target input current intermediate value Iv(n) is shown.

[0084] Step S220: The input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device are processed by the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module; wherein, the calculated duty cycle of the power switch module is as follows: Figure 8 The duty cycle d1(n) is shown.

[0085] Step S230: The sum of the given duty cycle of the power switch module and the calculated duty cycle of the power switch module is taken as the current duty cycle of the power switch module.

[0086] In this invention, an ADRC dual-loop algorithm with feedforward is used to improve the system's anti-interference capability, thereby achieving more precise current waveform control. Compared to the dual PID (proportional-integral-derivative) closed-loop control of traditional PFC circuits, the ADRC dual-loop algorithm with feedforward in this invention can also improve the system's dynamic response capability and achieve rapid current-voltage tracking.

[0087] In some embodiments, the specific process of obtaining the target input current intermediate value of the PFC device by processing the output voltage of the PFC device and the preset reference voltage through the ADRC module in the voltage loop in step S210 is described in the following exemplary description.

[0088] The following is combined Figure 3 The flowchart of an embodiment of the method of the present invention, which is processed by the ADRC module in the voltage loop, is shown below. The specific process of processing by the ADRC module in the voltage loop in step S210 is further explained, including steps S310 to S330.

[0089] Step S310: The output voltage of the PFC device is processed by a preset first A / D module to obtain the digital output voltage of the PFC device; wherein, the digital output voltage of the PFC device is as follows: Figure 8 The output voltage Uo(n) is shown.

[0090] Step S320: Use the digital output voltage of the PFC device as the actual value of the ADRC module in the voltage loop, and use the preset reference voltage as the target value of the ADRC module in the voltage loop.

[0091] Step S330: Input the digital output voltage of the PFC device and the preset reference voltage into the ADRC module in the voltage loop respectively to obtain the output value of the ADRC module in the voltage loop, which is used as the intermediate value of the target input current of the PFC device.

[0092] Figure 8 This is a schematic diagram of the closed-loop control flow of a bridgeless PFC circuit, which can illustrate the direction of the entire closed-loop control flow (i.e., the control flow of signals) and serves as the framework for the entire control concept. Figure 8 In this context, Uin(t) is Figure 7 In the context, Uin, IL(t) is Figure 7 The current lin on inductor L1 is represented by the pentagonal component, which indicates the multiplication stage. The adder connects the current loop to the PWM module, and d(t) controls MOSFETs Q1 and Q2. Figure 8 In the example shown, after clarifying how the power switches, such as MOSFETs Q1 and Q2, are turned on and off, the next problem to solve is how to control the on and off frequencies of the power switches, such as MOSFETs Q1 and Q2, so that the input current and voltage are in phase. For example... Figure 8 As shown, the solution of this invention uses a dual ADRC closed-loop control process with feedforward, including: Step 11, sampling the voltage Uo across the load Load to obtain the output voltage Uo(t), processing the output voltage Uo(t) through an A / D module to obtain the output voltage Uo(n), and inputting the output voltage Uo(n) and the reference voltage Vref into the input... Figure 8 The voltage loop shown generates the target input current intermediate value Iv(n) through ADRC calculation in the voltage loop.

[0093] In the solution of this invention, a dual ADRC closed-loop algorithm with feedforward is used to take system disturbances into account through extended states, thereby improving the robustness of the system and achieving a high power factor and current waveform, thus improving the system's anti-interference capability and achieving more precise current waveform control.

[0094] Compared to the dual PID closed-loop control of traditional PFC, the scheme of this invention uses a dual ADRC closed-loop algorithm with feedforward, which incorporates the initial duty cycle of the drive signal as a feedforward term into ADRC, thereby accelerating the dynamic response of current to voltage, improving the dynamic response capability of the system, and realizing rapid tracking of current to voltage.

[0095] In some implementations, the specific process of obtaining the calculated duty cycle of the power switch module after processing the input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device through the ADRC module in the current loop in step S220 is described in the following exemplary description.

[0096] The following is combined Figure 4 The schematic diagram shown is a flowchart of an embodiment of the method of the present invention after processing by the ADRC module in the current loop. It further illustrates the specific process after processing by the ADRC module in the current loop in step S220, including steps S410 to S440.

[0097] Step S410: Determine the effective value of the input voltage of the PFC device based on the input voltage of the PFC device.

[0098] Step S420: The input voltage of the PFC device is processed by a preset second A / D module to obtain the digital input voltage of the PFC device; and the current of the inductor module is processed by a preset second A / D module to obtain the digital current value of the inductor module; wherein, the digital input current of the PFC device is as follows: Figure 8 The inductor current sampling value IL(n) shown; the digital current value of the inductor module, as shown... Figure 8 The sampled value IL(t) of the current lin on the inductor L1 shown is processed by the A / D module to obtain the sampled value IL(n) of the inductor current.

[0099] Step S430: Divide the product of the digital input voltage of the PFC device and the intermediate value of the target input current of the PFC device by the effective value of the input voltage of the PFC device to obtain the target input current of the PFC device; use the target input current of the PFC device as the target value of the ADRC module in the current loop, and use the digital current value of the inductor module as the actual value of the ADRC module in the current loop; wherein, the target input current of the PFC device is as follows: Figure 8 The current reference value Iref is shown.

[0100] Step S440: Input the digital current value of the inductor module and the target input current of the PFC device into the ADRC module in the current loop respectively to obtain the output value of the ADRC module in the current loop, which is used as the calculated duty cycle of the power switch module.

[0101] like Figure 8 As shown, the present invention uses a dual ADRC closed-loop control process with feedforward, and further includes: in step 11, the target input current intermediate value Iv(n) of the voltage loop is multiplied by the instantaneous value Uin(n) of the input voltage Uin(t) of the single-phase AC Uin by a multiplier, and then divided by the effective value of the input voltage to obtain the current reference value Iref. The instantaneous value Uin(n) of the input voltage Uin(t) of the single-phase AC Uin is obtained after processing the input voltage Uin(t) of the single-phase AC Uin by the A / D module, and the effective value of the input voltage is the maximum value Um / √2 of the input voltage Uin(t) of the single-phase AC Uin. The sampled value IL(t) of the current lin on the inductor L1 is processed by the A / D module to obtain the inductor current sampled value IL(n).

[0102] Step 12: After step 11, the obtained current reference value Iref, and Figure 8 The inductor current sampling value IL(n) shown is... Figure 7 The current Iin on the inductor L1 shown is simultaneously input to Figure 8 In the current loop shown, the duty cycle d1(n) can be obtained through ADRC calculation in the current loop. Adding the duty cycle d1(n) to the duty cycle feedforward signal d2(n) yields the final duty cycle d(n). Here, the duty cycle d(n) directly adjusts the on-time of the output control MOSFETs Q1 and Q2 of the PWM module, thereby controlling the bridgeless PFC circuit to ensure that the input and output are in phase and the input current is a standard sine wave. This improves the utilization rate of electrical energy, reduces the waste of reactive power, thereby reducing the burden on the power grid and improving power quality.

[0103] In some implementations, the expression for the given duty cycle of the power switch module provided by the feedforward circuit in step S110 is as follows:

[0104] d2(n) = K1 - |Uin / Uoref|;

[0105] Wherein, d2(n) represents the given duty cycle of the power switch module provided by the feedforward circuit, K1 represents the set calculation coefficient, Uin represents the input voltage of the PFC device, and Uoref represents the ideal value of the output voltage of the PFC device. Preferably, the set calculation coefficient can be set to 1.

[0106] exist Figure 8 In the example shown, the feedforward circuit is used to feed forward the signal d2(n) with a given duty cycle:

[0107] d2(n)=1-|Uin / Uoref| (1).

[0108] Where Uin is the input voltage and Uoref represents the ideal value of the output voltage. d(n) directly adjusts the conduction time of MOSFETs Q1 and Q2 to control PFC, making the input and output in phase and the input current a standard sine wave, thereby improving the utilization rate of electrical energy, reducing the waste of reactive power, reducing the burden on the power grid, and improving power quality.

[0109] In some embodiments, the ADRC module includes a TD stage, an NLSEF stage, and an ESO stage; the input side of the ADRC module is used to input actual and target values, and the output side of the ADRC module is used to output the required output value; wherein, the actual value on the input side of the ADRC module is as follows: Figure 9 As shown in the figure, the target value on the input side of the ADRC module is as follows: Figure 9As shown in the figure, the output value of the ADRC module is as follows: Figure 9 The u shown.

[0110] For details on the processing using the ADRC module in step S120, please refer to the following exemplary description.

[0111] The following is combined Figure 5 The flowchart of an embodiment of the method of the present invention using the ADRC module is shown. The specific process of using the ADRC module in step S120 is further explained, including steps S510 to S550.

[0112] Step S510: Based on the target value input from the input side of the ADRC module, after the transition process is performed by the TD stage, a transition value of the target value is obtained; wherein, the transition value of the target value is as follows: Figure 9 The value V1 is shown as the value of the transition process for the target value yr.

[0113] Step S520: Based on the actual value input to the input side of the ADRC module, after the ESO stage packages the interference factors in the actual value into an extended state for estimation processing, a first estimated value and a second estimated value of the actual value are obtained; wherein, the first estimated value of the actual value is as follows: Figure 9 The ESO step shown represents the first processed value Z1 of the actual value y, and the second estimated value of the actual value is as follows: Figure 9 The ESO step shown represents the second processing value Z2 for the actual value y.

[0114] Step S530: The difference between the transition value of the target value and the second estimated value of the actual value is processed by the NLSEF stage to obtain a nonlinear configuration value of the deviation between the target value and the actual value, which is denoted as the deviation configuration value between the target value and the actual value; wherein, the deviation configuration value between the target value and the actual value is as follows: Figure 9 The difference between V1 and Z2 shown is the processed value u1 after passing through the NLSEF circuit.

[0115] Step S540: The difference between the deviation between the target value and the actual value, and the ratio of the first estimated value of the actual value to the preset control input proportional coefficient, is used as the output value of the ADRC module; wherein, the preset control input proportional coefficient is as follows: Figure 9 The proportional coefficient b0 of the control input shown is the ratio of the first estimated value of the actual value to the preset input proportional coefficient, such as... Figure 9 Z1 / b0 is shown.

[0116] Step S550: The product of the output value of the ADRC module and the preset control input proportional coefficient is used as the feedback value of the ESO loop, and fed back to the ESO loop to achieve closed-loop control. Wherein, the product of the output value of the ADRC module and the preset control input proportional coefficient is as follows: Figure 9 Z1*b0 is shown.

[0117] Figure 9 This is a flowchart illustrating the ADRC control strategy, demonstrating the ADRC algorithm for both the voltage and current loops. Figure 8 Specific details of the control of the current loop and voltage loop in this invention. The solution uses ADRC instead of traditional PID, and adds feedforward to the current loop to improve the response speed and noise immunity of the bridgeless PFC circuit. Figure 9 It can display the internal structure of the voltage loop and current loop. `yr` represents the target value, such as the reference voltage Vref of the voltage loop or the current reference value Iref of the current loop, and `y` represents the actual value, such as Uo(n) of the voltage loop or Iv(n) of the current loop. For example... Figure 9 As shown, in the ADRC control strategy with feedforward, the TD element is used to optimize the contradiction between the "speed" and "overshoot" of PID regulation. The TD element is a transient element (also called a tracking differentiator).

[0118] In some implementations, in the ADRC module:

[0119] The expression for the TD step is as follows:

[0120] V1=V1+h*r0*Π(y-yr,r,h); that is,

[0121] V1 current time = V1 previous time + h*r0*Π(y current time - yr current time, r, h);

[0122] Wherein, = represents assignment (i.e., assigning the value of the right side of the equal sign to the left side of the equal sign according to the calculation result, the same applies below); yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, V1 represents the transition value of the target value, r0, h and r all represent preset transition process control parameters, and Π(y-yr,r,h) represents a preset nonlinear function.

[0123] And / or, the expression for the NLSEF stage is as follows:

[0124] u1=r1*(Π(V1-Z1,alph3,belta1)); that is,

[0125] u1 current time = r1 * (Π(V1 current time - Z1 current time, alph3, belta1));

[0126] Where, = indicates assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u1 represents the deviation configuration value between the target value and the actual value, r1 represents the preset adjustment parameter, V1 represents the transition value of the target value, Z1 represents the first estimated value of the actual value, alph3 represents the preset nonlinear parameter, belt1 represents the preset weight parameter, and Π(V1-Z1,alph3,belta1) represents the preset nonlinear function. Π(V1 current time-Z1 current time,alph3,belta1) represents the preset nonlinear function.

[0127] And / or, the expression for the ESO step is as follows:

[0128] Z1=Z1+h*(Z2+belta1*(Π(y-Z1,alph1,belta1))+b0*u);

[0129] Z2=Z2+belta2*(Π(y-Z1,alph2,belta1)); that is,

[0130] Z1 current time = Z1 previous time + h*(Z2 previous time + belta1*(Π(y current time - Z1 previous time, alph1, belta1)) + b0*u previous time);

[0131] Z2 current time = Z2 previous time + belta2*(Π(y current time - Z1 current time, alph2, belta1));

[0132] Wherein, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u represents the output value of the ADRC module, h represents a preset transient control parameter, Z1 represents the first estimate of the actual value, Z2 represents the second estimate of the actual value, belt2 represents a preset weight parameter, alph1 and alph2 represent preset nonlinear parameters, and Π(y-Z1,alph1,belta1) and Π(y-Z1,alph2,belta1) represent preset nonlinear functions. Π(y current time - Z1 previous time,alph1,belta1) and Π(y current time - Z1 current time,alph2,belta1) also represent preset nonlinear functions.

[0133] exist Figure 9 In the example shown, the target value yr will be transformed into a transition value V1 after passing through the TD stage. The TD stage contains:

[0134] V1 = V1 + h * r0 * Π(y - yr, r, h) (2).

[0135] That is, V1 at the current moment = V1 at the previous moment + h * r0 * Π(y at the current moment - yr at the current moment, r, h).

[0136] Among them, r0, h, and r are parameters; r0 is a parameter used to regulate the speed of the transition process, h is a threshold parameter used to determine whether to enter the linear region, and r is a parameter used to control the strength of the non - linear feedback.

[0137] Π(y - yr, r, h) is a designed non - linear function: when y - yr < h, Π(y - yr, r, h) = (y - yr) / h^(1 - r); otherwise when y - yr ≥ h, Π(y - yr, r, h) = |y - yr|^r * sign(y - yr)). Among them, ^ represents the power, such as the (1 - r)th power of h, the rth power of |y - yr|; sign() represents the sign function.

[0138] Π(y , 当 , 当前时刻 , , 当前时刻 , ,

[0139] , 当前时刻 ,

[0140] , 当前时刻 ,

[0141] , 当前时刻 , , Figure 9 -yr 当前时刻 , r, h) is a designed non - linear function: when y 当前时刻 -yr 当前时刻 < h, Π(y 当前时刻 -yr 当前时刻 , r, h) = (y 当前时刻 -yr 当前时刻 ) / h^(1 - r); otherwise when y 当前时刻 -yr 当前时刻 ≥ h, Π(y 当前时刻 -yr 当前时刻 , r, h) = |y 当前时刻 -yr 当 at the previous moment|^r * sign(y at the current moment - yr at the current moment)). The rth power of |y at the current moment - yr at the current moment|.

[0139] As Figure 9 shown, in the ADRC control strategy with feed - forward, the ESO link is used to pack all disturbances and uncertainties in the actual value y into an extended state for unified estimation. By observing unknown disturbances, feedback is used to cancel the influence of disturbances on the system. The ESO link, that is, the extended observer. In the ESO link:

[0140] Z1 = Z1 + h * (Z2 + belta1 * (Π(y - Z1, alph1, belta1)) + b0 * u) (3);

[0141] Z2 = Z2 + belta2 * (Π(y - Z1, alph2, belta1)) (4). That is, Z1 current time = Z1 previous time + h*(Z2 previous time + belta1*(Π(y current time - Z1 previous time, alph1, belta1)) + b0*u previous time);

[0142] Z2 current time = Z2 previous time + belta2*(Π(y current time - Z1 current time, alph2, belta1));

[0143] In the NLSEF (nonlinear collocation) stage:

[0144] u1=r1*(Π(V1-Z1,alph3, belta1)) (5).

[0145] That is, u1 current time = r1*(Π(V1 current time - Z1 current time, alph3,belta1)).

[0146] Where Z1 represents the first processed value of the actual value y by the ESO stage, Z2 represents the second processed value of the actual value y by the ESO stage, and u1 is the processed value of the difference between V1 and Z2 after passing through the NLSEF stage. belta1 and belta2 are weight parameters, alph1, alph2, and alph3 are nonlinear parameters, and r1 is an adjustable parameter. h is the threshold parameter used to determine whether to enter the linear region. V1 is the value of the transition process from the target value yr to the target value yr after passing through the TD stage. u = u1 - Z1 / b0, where b0 is the proportional coefficient of the control input. Π(y-Z1,alph1,belta1), Π(y-Z1,alph2,belta1), and Π(V1-Z1,alph3,belta1) are all designed nonlinear functions. u1 is the output of the nonlinear configuration stage NLSEF, Z1 is the observed value of the total system disturbance, and Z2 is the observed value of y. Π(y current time - Z1 previous time, alph1,belta1), Π(y current time - Z1 current time, alph2,belta1), and Π(V1 current time - Z1 current time, alph3,belta1) are all designed nonlinear functions. Π(x,y,z) is the expression for the designed composite nonlinear function, where x, y, and z represent the input values, and y current time - Z1 previous time, alph1,belta1, y current time - Z1 current time, alph2, and V1 current time - Z1 current time, alph3 are the values ​​input into the function.

[0147] exist Figure 9In the example shown, the target value yr is processed through the TD stage to obtain the transition value V1 of the target value yr. The actual value y is processed through the ESO stage to obtain the first processed value Z1 and the second processed value Z2. The difference between the transition value V1 of the target value yr and the second processed value Z2 of the actual value y is processed through the NLSEF stage to obtain the processed value u1. The first processed value Z1 of the actual value y is multiplied by 1 / b0 through the 1 / b0 stage to obtain the processed value Z1 / b0. The difference between the processed value u1 and the processed value Z1 / b0 is the processed value u. The processed value u is multiplied by b0 through the b0 stage to obtain the feedback value u*b0. The feedback value u*b0 is fed back to the ESO stage for looping.

[0148] The ADRC algorithm in the voltage loop and current loop is explained in detail below. Since the voltage loop and current loop control use the same model (i.e., the same ADRC algorithm), the following explanation distinguishes the variable suffixes that have similar effects but are not the same quantity, such as Z1v and Z1i, Z2v and Z2i, etc.

[0149] In the voltage loop, if the target voltage Vref replaces yr, and the actual voltage Uo(n) replaces y, the transient process V1v = V1v + hv*r0v*Π(Uo(n) - Vref,rv,hv) can be obtained through TD. That is, V1v 当前时刻 =V1v 上一时刻 +hv*r0v*Π(Uo(n) current time - Vref current time, rv, hv). Where r0v, hv, and rv are parameters, r0v controls the speed of the transition process, hv is a threshold parameter that determines whether to enter the linear region, and rv controls the strength of the nonlinear feedback.

[0150] During the ESO process:

[0151] Z1v=Z1v+hv*(Z2v+belta1v*(Π(Uo(n)-Z1v,alph1v,belta1v))+b0v*uv),

[0152] Z2v=Z2v+belta2v*(Π(Uo(n)-Z1v,alph2v,belta1v)).

[0153] In the NLSEF circuit, u1v = r1v * (Π(V1v - Z1v, alph3v, belt1v)), where belt1v and belt2v are weight parameters, alph1v, alph2v, and alph3v are nonlinear parameters, b0v is the proportional coefficient controlling the input, and r1v is an adjustable parameter. uv = u1v - Z1v / b0v. Here, uv represents Iv(n).

[0154] Next, multiplying Iv(n) by the instantaneous value of the input voltage and then dividing by the effective value of the input voltage yields the current reference value Iref(n). Figure 8 The pentagon in the diagram represents a multiplier. Therefore, in the current loop, the target current value is Iref replacing yr, and the actual current value is IL(n) replacing y. After TD, the transient process V1i = V1i + hi * r0i * Π(IL(n) - Iref,ri,hi) can be obtained. Here, r0i, hi, and ri are parameters; r0i controls the speed of the transient process, hi is a threshold parameter determining whether to enter the linear region, and ri controls the strength of the nonlinear feedback.

[0155] That is, Z1v 当前时刻 =Z1v 当前时刻 +hv*(Z2v 上一时刻 +belta1v*(Π(Uo(n) 当前时刻 -Z1v 上一时 (e.g., alph1v, belta1v))+b0v*uv (previous time),)

[0156] Z2v 当前时刻 =Z2v 上一时刻 +belta2v*(Π(Uo(n) current time - Z1v) 当前时刻 ,alph2v,belta1v)).

[0157] u1v in the NLSEF phase 当前时刻 =r1v*(Π(V1v current time - Z1v) 当前时刻 ,alph3v,delta1v), where belt1v and belt2v are weighting parameters, alph1v, alph2v, and alph3v are nonlinear parameters, b0v is the proportional coefficient controlling the input, and r1v is an adjustable parameter. uv 当前时刻 =u1v 当前时刻 -Z1v 当前时刻 / b0v. Here, uv represents Iv(n) at the current time.

[0158] Next, multiplying Iv(n) by the instantaneous value of the input voltage and then dividing by the effective value of the input voltage yields the current reference value Iref(n). Figure 8 The pentagon in the diagram represents a multiplier. Therefore, in the current loop, the target current value is Iref replacing yr, and the actual current value is IL(n) replacing y. The transient process V1i can be obtained through TD. 当前时刻 =V1i 上一时刻 +hi*r0i*Π(IL(n) 当The previous time step is Iref, the current time step is ri, and hi is ri. Here, r0i, hi, and ri are parameters. r0i controls the speed of the transition process, hi is a threshold parameter that determines whether to enter the linear region, and ri controls the strength of the nonlinear feedback.

[0159] During the ESO process:

[0160] Z1i=Z1i+hi*(Z2i+belta1i*(Π(IL(n)-Z1i,alph1i,belta1i))+b0i*ui),

[0161] Z2i=Z2i+belta2i*(Π(IL(n)-Z1i,alph2i,belta1i)).

[0162] In the NLSEF circuit, u1i = r1i * (Π(V1i - Z1i, alph3i, belt1i)), where belt1i and belt2i are weight parameters, alph1i, alph2i, and alph3i are nonlinear parameters, b0i is the proportional coefficient controlling the input, and r1i is an adjustable parameter. ui = u1i - Z1i / b0i. Here, ui represents d1(n).

[0163] That is, Z1i 当前时刻 =Z1i 上一时刻 +hi*(Z2i 上一时刻 +belta1i*(Π(IL(n) 当前时刻 -Z1i 上一时 (e.g., alph1i,belta1i))+b0i*ui previous time),

[0164] Z2i 当前时刻 =Z2i 上一时刻 +belta2i*(Π(IL(n) 当前时刻 -Z1i 当前时刻 ,alph2i,belta1i)).

[0165] u1i in the NLSEF phase 当前时刻 =r1i*(Π(V1i) 当前时刻 -Z1i 当前时刻 ,alph3i,belta1i), wherebelta1i andbelta2i are weighting parameters,alph1i,alph2i, andalph3i are nonlinear parameters, b0i is the proportional coefficient controlling the input, and r1i is an adjustable parameter. ui 当前时刻 =u1i 当前时刻 -Z1i 当前时刻 / b0i. The UI here... 当前时刻 This represents d1(n).

[0166] The feedforward circuit acquires the initial duty cycle signal d2(n) to improve the control response speed, d2(n) = 1 - |Uin / Vref|, where Uin represents the input voltage and Vref represents... Figure 1 The target voltage value of the output voltage Uo. The final duty cycle signal d(n) = d1(n) + d2(n) controls the PWM, determines the conduction time of Q1 and Q2, and ultimately improves the power factor of the circuit so that the bus voltage Uo(t) and the bus current IL(t) have almost no phase difference.

[0167] Figure 10 This is a schematic diagram of the digital control flow for a bridgeless PFC circuit. Because an A / D converter (microcontroller) is being designed, a digital control flow is used. A / D is analog-to-digital conversion; in engineering, the analog-to-digital conversion pins in the microcontroller are typically used to convert analog signals into digital signals. For example... Figure 10 As shown, the digital control flow of the bridgeless PFC circuit includes:

[0168] Step 21: Acquire the bus output voltage Uo(t) of the bridgeless PFC circuit. After the signal is processed by an A / D converter (microcontroller), obtain Uo(n), and then proceed to step 22. PFC is a general-purpose circuit that optimizes power quality and improves power factor. It can be used in the front end of any electrical equipment, including motor controllers, frequency converters, etc., and is equivalent to an optimized power supply. Here, the bus voltage is the voltage Uo(t) across the load Load.

[0169] Step 22: Input Uo(n) and the reference voltage Vref together into the voltage loop ADRC controller to obtain Iv(n), and then execute step 23.

[0170] Step 23: Input the voltage loop-generated Iv(n) and the input voltage Uin(t) obtained by (A / D) processing into the multiplier to generate the mains current reference value Iref through calculation, and then execute step 24.

[0171] Step 24: Collect the bus inductor current (IL(t) / lin) and convert it to IL(n) through A / D conversion, then proceed to step 25.

[0172] Step 25: Input IL(n) and Iref together into the current loop ADRC controller to obtain the initial duty cycle signal d1(n), and then execute step 26.

[0173] Step 26: In the feedforward circuit, the mains voltage and the output reference voltage are processed by the feedforward unit to obtain the feedforward control signal duty cycle d2(n), and then step 27 is executed.

[0174] Step 27: Add the feedforward control signal d2(n) and the initial duty cycle signal d1(n) to obtain the duty cycle PWM, and use the duty cycle PWM to drive the MOS transistors such as MOS transistor Q1 and MOS transistor Q2 in the bridgeless PFC structure.

[0175] This invention proposes a dual-loop ADRC control method with feedforward based on a bridgeless PFC circuit. For the bridgeless PFC circuit, it employs ADRC closed-loop control with feedforward duty cycle to improve response speed. Compared to a bridged BOOST mode (i.e., boost chopper) PFC circuit, the bridgeless PFC circuit reduces cost and size by eliminating the need for a rectifier, and this change also improves energy efficiency. However, to achieve phase-free input voltage and current to improve the circuit's control power factor, the drive control method is crucial. Although all three methods use model-independent control, the use of a High Order Differential Feedback Controller (HODFC) in the inner current loop of related schemes affects response speed due to the need for high-order derivative and dual-integral single-cycle modules. Considering system interference and the closed-loop response speed of PFC, this invention adopts a dual-loop ADRC control method with feedforward. In the inner current loop, the duty cycle is jointly determined by the feedforward term and the current loop output, improving the system's response speed. Meanwhile, due to the use of ADRC dual closed-loop control, system disturbances are considered in the extended state ESO of ADRC. Compared with the dual PID closed-loop control in related schemes, it has higher dynamic response and anti-interference capability, enabling the circuit to obtain better current waveforms and higher power factor.

[0176] In the solution of this invention, the control of the bridgeless PFC circuit uses an ADRC dual-loop algorithm with feedforward. Compared with the dual PID closed-loop control of the traditional PFC circuit, the advantages of using the ADRC dual-loop algorithm with feedforward are as follows:

[0177] (1) ADRC has stronger robustness: The traditional PFC circuit's dual PID closed-loop control directly takes the difference between the setpoint and the system output when calculating the error, resulting in a contradiction between the "speed" and "overshoot" of PID control. In contrast, the ADRC dual closed-loop algorithm with feedforward arranges a TD module (see...) Figure 9 The transition process optimizes the trade-off between "speed" and "overshoot" in PID control. Simultaneously, the TD stage obtains the differential signal through the "fastest tracking" method, avoiding noise amplification introduced by the PID controller in the derivative stage.

[0178] (2) The dual PID closed-loop control of the traditional PFC circuit is more suitable for the control of linear systems. ADRC can provide more accurate and stable control for the nonlinear characteristics exhibited by PFC.

[0179] (3) ADRC has adaptive characteristics, which can be achieved through the ESO module (see...). Figure 9 This invention packages all disturbances and uncertainties into an extended state for unified estimation. By observing unknown disturbances, feedback is used to offset their impact on the system. In this invention, ADRC has a significant advantage over PID in compensating for unmodeled dynamics (e.g., parasitic parameters of components) and unknown disturbances (e.g., temperature rise) in bridgeless PFC circuits. When a bridgeless PFC circuit operates for extended periods or is exposed to strong electromagnetic interference, the parameters of the components themselves change, leading to a decline in the circuit's performance, such as a decrease in inductance and an increase in equivalent capacitance. ADRC compensates for these potential system disturbances through the extended state observer (ESO), greatly improving the noise immunity of the bridgeless PFC circuit.

[0180] The technical solution of this embodiment, for a PFC device (such as a bridgeless PFC circuit) with a power switch (such as a MOS switch), and for the current loop and voltage loop of the control system of the PFC device (such as the control system for controlling the turn-on and turn-off of the power switch in a bridgeless PFC circuit), a feedforward loop is set in the current loop to use the initial duty cycle of the drive signal of the power switch as the feedforward term. Furthermore, ADRC control strategies are adopted in both the current loop and the voltage loop to improve anti-interference capability by considering system interference through extended states, thereby achieving control over the turn-on and turn-off of the power switch. Thus, by adopting ADRC control strategies in both the current loop and the voltage loop to consider system interference through extended states, the accuracy of current waveform control is improved; and by setting a feedforward loop in the current loop to use the initial duty cycle of the drive signal of the power switch as the feedforward term, the response speed of current to voltage tracking is improved.

[0181] According to an embodiment of the present invention, a control device for a PFC device corresponding to a control method for a PFC device is also provided. See also Figure 6 The diagram shows a structural schematic of an embodiment of the device of the present invention. The PFC device includes an inductor module and a power switch module, as shown in the diagram. Figure 7 The bridgeless PFC circuit shown has an inductor module as follows: Figure 7 The inductors L1 and L2 shown are used in the power switching module as follows: Figure 7The bridgeless PFC circuit shown includes MOSFETs Q1 and Q2; the control system of the PFC device has a voltage loop and a current loop; a feedforward circuit is provided on the output side of the current loop; ADRC modules are provided in both the voltage loop and the current loop, and the ADRC modules are modules capable of running the ADRC algorithm; in the solution of the present invention, as... Figure 6 As shown, the control device of the PFC device includes: an acquisition unit 102 and a control unit 104.

[0182] The acquisition unit 102 is configured to, when the PFC device is operating, acquire the input voltage of the PFC device, acquire the current of the inductor module, acquire the output voltage of the PFC device, and acquire the given duty cycle of the power switch module provided by the feedforward circuit; wherein, the input voltage of the PFC device is as follows: Figure 8 The input voltage Uin(t) of the single-phase AC power Uin shown is given, and the current of the inductor module is as follows: Figure 8 The sampled value IL(t) of the current lin on the inductor L1 is shown, and the output voltage of the PFC device is as follows. Figure 8 The output voltage Uo(t) of the bridgeless PFC circuit shown is given by the feedforward circuit. The given duty cycle provided by the feedforward circuit is... Figure 8 The given duty cycle feedforward signal d2(n) is shown. The specific functions and processing of this acquisition unit 102 are described in step S110.

[0183] The control unit 104 is configured to determine the current duty cycle of the power switch module by processing data in the voltage loop and the current loop using an ADRC module based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module; wherein, the current duty cycle of the power switch module is as follows: Figure 8 The final duty cycle d(n) is obtained by adding the duty cycle d1(n) to the duty cycle feedforward signal d2(n). The specific functions and processing of this control unit 104 are described in step S120.

[0184] The control unit 104 is further configured to output a PWM signal to the power switching module based on the current duty cycle of the power switching module, controlling the on and off of the corresponding power switching transistors in the power switching module, thereby adjusting the waveform and / or phase of the input current of the PFC device, so that the input voltage of the PFC device is in phase with the input current of the PFC device, and the waveform of the input current of the PFC device is a preset standard sine wave. The specific functions and processing of the control unit 104 are further described in step S130.

[0185] To reduce design costs and improve energy efficiency, a bridgeless PFC circuit is used to improve power quality when the controller is connected to the grid, which also simplifies the circuit structure. However, controlling the switching frequency of the power transistors to achieve phase-difference-free tracking of the current and input voltage is a challenge when using a bridgeless PFC circuit. Traditional PFC circuits employ a dual PID closed-loop control method with an inner current loop and an outer voltage loop. In contrast, this invention proposes an ADRC control method with feedforward to achieve faster response and stronger noise immunity. This method incorporates system disturbances into the control algorithm through extended states, improving noise immunity and obtaining a better current waveform. Furthermore, to achieve faster dynamic response, the initial duty cycle of the drive signal is incorporated as a feedforward term into the ADRC, enabling the current to track the voltage more quickly.

[0186] In some embodiments, the control unit 104, based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module, uses an ADRC module in the voltage loop and the current loop to determine the current duty cycle of the power switch module, including:

[0187] The control unit 104 is further configured to process the output voltage of the PFC device and a preset reference voltage through the ADRC module in the voltage loop to obtain the intermediate value of the target input current of the PFC device; wherein, the intermediate value of the target input current of the PFC device is as follows: Figure 8 The target input current intermediate value Iv(n) is shown. For the specific functions and processing of this control unit 104, please refer to step S210.

[0188] The control unit 104 is further configured to process the input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device through the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module; wherein, the calculated duty cycle of the power switch module is as follows: Figure 8 The duty cycle d1(n) is shown. For the specific functions and processing of this control unit 104, please refer to step S220.

[0189] The control unit 104 is further configured to use the sum of the given duty cycle of the power switch module and the calculated duty cycle of the power switch module as the current duty cycle of the power switch module. The specific functions and processing of the control unit 104 are further described in step S230.

[0190] In this invention, an ADRC dual-loop algorithm with feedforward is used to improve the system's anti-interference capability, thereby achieving more precise current waveform control. Compared to the dual PID (proportional-integral-derivative) closed-loop control of traditional PFC circuits, the ADRC dual-loop algorithm with feedforward in this invention can also improve the system's dynamic response capability and achieve rapid current-voltage tracking.

[0191] In some embodiments, the control unit 104 processes the output voltage of the PFC device and a preset reference voltage through the ADRC module in the voltage loop to obtain the intermediate value of the target input current of the PFC device, including:

[0192] The control unit 104 is further configured to process the output voltage of the PFC device through a preset first A / D module to obtain the digital output voltage of the PFC device; wherein, the digital output voltage of the PFC device is as follows: Figure 8 The output voltage Uo(n) is shown. For the specific functions and processing of this control unit 104, please refer to step S310.

[0193] The control unit 104 is further configured to use the digital output voltage of the PFC device as the actual value of the ADRC module in the voltage loop, and to use a preset reference voltage as the target value of the ADRC module in the voltage loop. The specific functions and processing of the control unit 104 are further described in step S320.

[0194] The control unit 104 is further configured to input the digital output voltage of the PFC device and a preset reference voltage into the ADRC module in the voltage loop, respectively, to obtain the output value of the ADRC module in the voltage loop, which serves as the intermediate value of the target input current of the PFC device. The specific functions and processing of this control unit 104 are further described in step S330.

[0195] Figure 8 This is a schematic diagram of the closed-loop control flow of a bridgeless PFC circuit, which can illustrate the direction of the entire closed-loop control flow (i.e., the control flow of signals) and serves as the framework for the entire control concept. Figure 8 In this context, Uin(t) is Figure 7 In the context, Uin, IL(t) is Figure 7 The current lin on inductor L1 is represented by the pentagonal component, which indicates the multiplication stage. The adder connects the current loop to the PWM module, and d(t) controls MOSFETs Q1 and Q2. Figure 8In the example shown, after clarifying how the power switches, such as MOSFETs Q1 and Q2, are turned on and off, the next problem to solve is how to control the on and off frequencies of the power switches, such as MOSFETs Q1 and Q2, so that the input current and voltage are in phase. For example... Figure 8 As shown, the solution of this invention uses a dual ADRC closed-loop control process with feedforward, including: Step 11, sampling the voltage Uo across the load Load to obtain the output voltage Uo(t), processing the output voltage Uo(t) through an A / D module to obtain the output voltage Uo(n), and inputting the output voltage Uo(n) and the reference voltage Vref into the input... Figure 8 The voltage loop shown generates the target input current intermediate value Iv(n) through ADRC calculation in the voltage loop.

[0196] In the solution of this invention, a dual ADRC closed-loop algorithm with feedforward is used to take system disturbances into account through extended states, thereby improving the robustness of the system and achieving a high power factor and current waveform, thus improving the system's anti-interference capability and achieving more precise current waveform control.

[0197] Compared to the dual PID closed-loop control of traditional PFC, the scheme of this invention uses a dual ADRC closed-loop algorithm with feedforward, which incorporates the initial duty cycle of the drive signal as a feedforward term into ADRC, thereby accelerating the dynamic response of current to voltage, improving the dynamic response capability of the system, and realizing rapid tracking of current to voltage.

[0198] In some embodiments, the control unit 104 processes the input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device through the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module, including:

[0199] The control unit 104 is further configured to determine the effective value of the input voltage of the PFC device based on the input voltage of the PFC device. The specific functions and processing of the control unit 104 are further described in step S410.

[0200] The control unit 104 is further configured to process the input voltage of the PFC device through a preset second A / D module to obtain the digital input voltage of the PFC device; and to process the current of the inductor module through a preset second A / D module to obtain the digital current value of the inductor module; wherein, the digital input current of the PFC device is as follows: Figure 8 The inductor current sampling value IL(n) shown; the digital current value of the inductor module, as shown... Figure 8The sampled value IL(t) of the current lin on the inductor L1 shown is processed by the A / D module to obtain the inductor current sampled value IL(n). For the specific functions and processing of the control unit 104, please refer to step S420.

[0201] The control unit 104 is further configured to divide the product of the digital input voltage of the PFC device and the intermediate value of the target input current of the PFC device by the effective value of the input voltage of the PFC device to obtain the target input current of the PFC device; to use the target input current of the PFC device as the target value of the ADRC module in the current loop, and to use the digital current value of the inductor module as the actual value of the ADRC module in the current loop; wherein, the target input current of the PFC device, such as Figure 8 The current reference value Iref is shown. For the specific functions and processing of this control unit 104, please refer to step S430.

[0202] The control unit 104 is further configured to input the digital current value of the inductor module and the target input current of the PFC device into the ADRC module in the current loop, respectively, to obtain the output value of the ADRC module in the current loop, which is used as the calculated duty cycle of the power switch module. The specific functions and processing of this control unit 104 are further described in step S440.

[0203] like Figure 8 As shown, the present invention uses a dual ADRC closed-loop control process with feedforward, and further includes: in step 11, the target input current intermediate value Iv(n) of the voltage loop is multiplied by the instantaneous value Uin(n) of the input voltage Uin(t) of the single-phase AC Uin by a multiplier, and then divided by the effective value of the input voltage to obtain the current reference value Iref. The instantaneous value Uin(n) of the input voltage Uin(t) of the single-phase AC Uin is obtained after processing the input voltage Uin(t) of the single-phase AC Uin by the A / D module, and the effective value of the input voltage is the maximum value Um / √2 of the input voltage Uin(t) of the single-phase AC Uin. The sampled value IL(t) of the current lin on the inductor L1 is processed by the A / D module to obtain the inductor current sampled value IL(n).

[0204] Step 12: After step 11, the obtained current reference value Iref, and Figure 8 The inductor current sampling value IL(n) shown is... Figure 7 The current Iin on the inductor L1 shown is simultaneously input to Figure 8In the current loop shown, the duty cycle d1(n) can be obtained through ADRC calculation in the current loop. Adding the duty cycle d1(n) to the duty cycle feedforward signal d2(n) yields the final duty cycle d(n). Here, the duty cycle d(n) directly adjusts the on-time of the output control MOSFETs Q1 and Q2 of the PWM module, thereby controlling the bridgeless PFC circuit to ensure that the input and output are in phase and the input current is a standard sine wave. This improves the utilization rate of electrical energy, reduces the waste of reactive power, thereby reducing the burden on the power grid and improving power quality.

[0205] In some implementations, the expression for the given duty cycle of the power switch module provided by the feedforward circuit is as follows:

[0206] d2(n) = K1 - |Uin / Uoref|;

[0207] Wherein, d2(n) represents the given duty cycle of the power switch module provided by the feedforward circuit, K1 represents the set calculation coefficient, Uin represents the input voltage of the PFC device, and Uoref represents the ideal value of the output voltage of the PFC device. Preferably, the set calculation coefficient can be set to 1.

[0208] exist Figure 8 In the example shown, the feedforward circuit is used to feed forward the signal d2(n) with a given duty cycle:

[0209] d2(n)=1-|Uin / Uoref| (1).

[0210] Where Uin is the input voltage and Uoref represents the ideal value of the output voltage. d(n) directly adjusts the conduction time of MOSFETs Q1 and Q2 to control PFC, making the input and output in phase and the input current a standard sine wave, thereby improving the utilization rate of electrical energy, reducing the waste of reactive power, reducing the burden on the power grid, and improving power quality.

[0211] In some embodiments, the ADRC module includes a TD stage, an NLSEF stage, and an ESO stage; the input side of the ADRC module is used to input actual and target values, and the output side of the ADRC module is used to output the required output value; wherein, the actual value on the input side of the ADRC module is as follows: Figure 9 As shown in the figure, the target value on the input side of the ADRC module is as follows: Figure 9 As shown in the figure, the output value of the ADRC module is as follows: Figure 9 The u shown.

[0212] The control unit 104 uses an ADRC module for processing, including:

[0213] The control unit 104 is further configured to obtain a transition value of the target value after the transition process is performed by the TD stage based on the target value input from the input side of the ADRC module; wherein, the transition value of the target value is as follows: Figure 9 The value V1 is the value of the transition process of the target value yr shown. For the specific functions and processing of this control unit 104, please refer to step S510.

[0214] The control unit 104 is further configured to, based on the actual value input from the input side of the ADRC module, after the ESO stage packages the interference factors in the actual value into an extended state for estimation processing, obtain a first estimated value and a second estimated value of the actual value; wherein, the first estimated value of the actual value is as follows: Figure 9 The ESO step shown represents the first processed value Z1 of the actual value y, and the second estimated value of the actual value is as follows: Figure 9 The ESO step shown represents the second processed value Z2 of the actual value y. For the specific functions and processing of this control unit 104, please refer to step S520.

[0215] The control unit 104 is further configured to process the difference between the transition value of the target value and the second estimated value of the actual value through the NLSEF circuit, and obtain a nonlinear configuration value representing the deviation between the target value and the actual value, denoted as the deviation configuration value between the target value and the actual value; wherein, the deviation configuration value between the target value and the actual value is as follows: Figure 9 The difference between V1 and Z2 shown is the processed value u1 after passing through the NLSEF circuit. For the specific functions and processing of this control unit 104, please refer to step S530.

[0216] The control unit 104 is further configured to use the difference between the deviation between the target value and the actual value, and the ratio of the first estimated value of the actual value and a preset control input proportional coefficient, as the output value of the ADRC module; wherein the preset control input proportional coefficient is as follows: Figure 9 The proportional coefficient b0 of the control input shown is the ratio of the first estimated value of the actual value to the preset input proportional coefficient, such as... Figure 9 Z1 / b0 is shown. For the specific functions and processing of this control unit 104, please refer to step S540.

[0217] The control unit 104 is further configured to use the product of the output value of the ADRC module and a preset control input proportional coefficient as the feedback value of the ESO loop, thereby achieving closed-loop control. Specifically, the product of the output value of the ADRC module and the preset control input proportional coefficient is as follows: Figure 9 Z1*b0 is shown. For the specific functions and processing of this control unit 104, please refer to step S550.

[0218] Figure 9 This is a flowchart illustrating the ADRC control strategy, demonstrating the ADRC algorithm for both the voltage and current loops. Figure 8 Specific details of the control of the current loop and voltage loop in this invention. The solution uses ADRC instead of traditional PID, and adds feedforward to the current loop to improve the response speed and noise immunity of the bridgeless PFC circuit. Figure 9 It can display the internal structure of the voltage loop and current loop. `yr` represents the target value, such as the reference voltage Vref of the voltage loop or the current reference value Iref of the current loop, and `y` represents the actual value, such as Uo(n) of the voltage loop or Iv(n) of the current loop. For example... Figure 9 As shown, in the ADRC control strategy with feedforward, the TD element is used to optimize the contradiction between the "speed" and "overshoot" of PID regulation.

[0219] In some implementations, in the ADRC module:

[0220] The expression for the TD step is as follows:

[0221] V1 = V1 + h * r0 * Π(y - yr, r, h);

[0222] Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, V1 represents the transition value of the target value, r0, h and r all represent preset transition process control parameters, and Π(y-yr,r,h) represents a preset nonlinear function.

[0223] And / or, the expression for the NLSEF stage is as follows:

[0224] u1=r1*(Π(V1-Z1,alph3,belta1));

[0225] Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u1 represents the deviation configuration value between the target value and the actual value, r1 represents the preset adjustment parameter, V1 represents the transition value of the target value, Z1 represents the first estimated value of the actual value, alph3 represents the preset nonlinear parameter, belt1 represents the preset weight parameter, and Π(V1-Z1,alph3,belta1) represents the preset nonlinear function.

[0226] And / or, the expression for the ESO step is as follows:

[0227] Z1 = Z1 + h * (Z2 + belta1 * Π(y - Z1, alph1, belta1)) + b0 * u;

[0228] Z2 = Z2 + belta2 * Π(y - Z1, alph2, belta1);

[0229] Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u represents the output value of the ADRC module, h represents the preset transition process regulation parameter, Z1 represents the first estimate of the actual value, Z2 represents the second estimate of the actual value, belta2 represents the preset weight parameter, alph1 and alph2 represent the preset nonlinear parameters, and Π(y - Z1, alph1, belta1) and Π(y - Z1, alph2, belta1) represent the preset nonlinear functions.

[0230] In Figure 9 In the example shown, the target value yr passes through the TD link and a transition process value V1 of the target value yr will be obtained. In the TD link:

[0231] V1 = V1 + h * r0 * Π(y - yr, r, h) (2).

[0232] Where, r0, h, and r are parameters; r0 is a parameter for regulating the speed of the transition process, h is a threshold parameter for determining whether to enter the linear region, and r is a parameter for controlling the strength of the nonlinear feedback.

[0233] Π(y - yr, r, h) is the designed nonlinear function: when y - yr < h, Π(y - yr, r, h) = (y - yr) / h ^ (1 - r); otherwise when y - yr ≥ h, Π(y - yr, r, h) = |y - yr| ^ r * sign(y - yr)). Where, ^ represents the power, such as the (1 - r) power of h, the r power of |y - yr|; sign() represents the sign function.

[0234] Such as Figure 9 As shown, in the ADRC control strategy with feedforward, the ESO link is used to package all disturbances and uncertainties in the actual value y into an extended state for unified estimation. By observing unknown disturbances, the feedback is used to cancel the influence of the disturbances on the system. In the ESO link:

[0235] Z1 = Z1 + h * (Z2 + belta1 * Π(y - Z1, alph1, belta1)) + b0 * u (3);

[0236] Z2=Z2+belta2*(Π(y-Z1,alph2,belta1)) (4). In the NLSEF (nonlinear collocation) stage:

[0237] u1=r1*(Π(V1-Z1,alph3, belta1)) (5).

[0238] Where Z1 represents the first processed value of the actual value y by the ESO stage, Z2 represents the second processed value of the actual value y by the ESO stage, and u1 is the processed value of the difference between V1 and Z2 after passing through the NLSEF stage. belta1 and belta2 are weight parameters, alph1, alph2, and alph3 are nonlinear parameters, and r1 is an adjustable parameter. h is the threshold parameter used to determine whether to enter the linear region. V1 is the value of the transition process from the target value yr to the target value yr after passing through the TD stage. u = u1 - Z1 / b0, where b0 is the proportional coefficient controlling the input. Π(y-Z1,alph1,belta1), Π(y-Z1,alph2,belta1), and Π(V1-Z1,alph3,belta1) are all designed nonlinear functions.

[0239] exist Figure 9 In the example shown, the target value yr is processed through the TD stage to obtain the transition value V1 of the target value yr. The actual value y is processed through the ESO stage to obtain the first processed value Z1 and the second processed value Z2. The difference between the transition value V1 of the target value yr and the second processed value Z2 of the actual value y is processed through the NLSEF stage to obtain the processed value u1. The first processed value Z1 of the actual value y is multiplied by 1 / b0 through the 1 / b0 stage to obtain the processed value Z1 / b0. The difference between the processed value u1 and the processed value Z1 / b0 is the processed value u. The processed value u is multiplied by b0 through the b0 stage to obtain the feedback value u*b0. The feedback value u*b0 is fed back to the ESO stage for looping.

[0240] The ADRC algorithm in the voltage loop and current loop is explained in detail below. Since the voltage loop and current loop control use the same model (i.e., the same ADRC algorithm), the following explanation distinguishes the variable suffixes that have similar effects but are not the same quantity, such as Z1v and Z1i, Z2v and Z2i, etc.

[0241] In the voltage loop, if the target voltage Vref replaces yr and the actual voltage Uo(n) replaces y, the transient process V1v = V1v + hv*r0v*Π(Uo(n) - Vref,rv,hv) can be obtained through TD. Here, r0v, hv, and rv are parameters; r0v controls the speed of the transient process, hv is a threshold parameter that determines whether to enter the linear region, and rv controls the strength of the nonlinear feedback.

[0242] During the ESO process:

[0243] Z1v=Z1v+hv*(Z2v+belta1v*(Π(Uo(n)-Z1v,alph1v,belta1v))+b0v*uv),

[0244] Z2v=Z2v+belta2v*(Π(Uo(n)-Z1v,alph2v,belta1v)).

[0245] In the NLSEF circuit, u1v = r1v * (Π(V1v - Z1v, alph3v, belt1v)), where belt1v and belt2v are weight parameters, alph1v, alph2v, and alph3v are nonlinear parameters, b0v is the proportional coefficient controlling the input, and r1v is an adjustable parameter. uv = u1v - Z1v / b0v. Here, uv represents Iv(n).

[0246] Next, multiplying Iv(n) by the instantaneous value of the input voltage and then dividing by the effective value of the input voltage yields the current reference value Iref(n). Figure 8 The pentagon in the diagram represents a multiplier. Therefore, in the current loop, the target current value is Iref replacing yr, and the actual current value is IL(n) replacing y. After TD, the transient process V1i = V1i + hi * r0i * Π(IL(n) - Iref,ri,hi) can be obtained. Here, r0i, hi, and ri are parameters; r0i controls the speed of the transient process, hi is a threshold parameter determining whether to enter the linear region, and ri controls the strength of the nonlinear feedback.

[0247] During the ESO process:

[0248] Z1i=Z1i+hi*(Z2i+belta1i*(Π(IL(n)-Z1i,alph1i,belta1i))+b0i*ui),

[0249] Z2i=Z2i+belta2i*(Π(IL(n)-Z1i,alph2i,belta1i)).

[0250] In the NLSEF circuit, u1i = r1i * (Π(V1i - Z1i, alph3i, belt1i)), where belt1i and belt2i are weight parameters, alph1i, alph2i, and alph3i are nonlinear parameters, b0i is the proportional coefficient controlling the input, and r1i is an adjustable parameter. ui = u1i - Z1i / b0i. Here, ui represents d1(n).

[0251] The feedforward circuit acquires the initial duty cycle signal d2(n) to improve the control response speed, d2(n) = 1 - |Uin / Vref|, where Uin represents the input voltage and Vref represents... Figure 1 The target voltage value of the output voltage Uo. The final duty cycle signal d(n) = d1(n) + d2(n) controls the PWM, determines the conduction time of Q1 and Q2, and ultimately improves the power factor of the circuit so that the bus voltage Uo(t) and the bus current IL(t) have almost no phase difference.

[0252] Figure 10 This is a schematic diagram of the digital control flow of a bridgeless PFC circuit. (Example:) Figure 10 As shown, the digital control flow of the bridgeless PFC circuit includes:

[0253] Step 21: Acquire the bus output voltage Uo(t) of the bridgeless PFC circuit. After the signal is processed by the A / D (microcontroller), obtain Uo(n). Then execute step 22.

[0254] Step 22: Input Uo(n) and the reference voltage Vref together into the voltage loop ADRC controller to obtain Iv(n), and then execute step 23.

[0255] Step 23: Input the voltage loop-generated Iv(n) and the input voltage Uin(t) obtained by (A / D) processing into the multiplier to generate the mains current reference value Iref through calculation, and then execute step 24.

[0256] Step 24: Collect the bus inductor current (IL(t) / lin) and convert it to IL(n) through A / D conversion, then proceed to step 25.

[0257] Step 25: Input IL(n) and Iref together into the current loop ADRC controller to obtain the initial duty cycle signal d1(n), and then execute step 26.

[0258] Step 26: In the feedforward circuit, the mains voltage and the output reference voltage are processed by the feedforward unit to obtain the feedforward control signal duty cycle d2(n), and then step 27 is executed.

[0259] Step 27: Add the feedforward control signal d2(n) and the initial duty cycle signal d1(n) to obtain the duty cycle PWM, and use the duty cycle PWM to drive the MOS transistors such as MOS transistor Q1 and MOS transistor Q2 in the bridgeless PFC structure.

[0260] This invention proposes a dual-loop ADRC control method with feedforward based on a bridgeless PFC circuit. For the bridgeless PFC circuit, it employs ADRC closed-loop control with feedforward duty cycle to improve response speed. Compared to a bridged BOOST mode (i.e., boost chopper) PFC circuit, the bridgeless PFC circuit reduces cost and size by eliminating the need for a rectifier, and this change also improves energy efficiency. However, to achieve phase-free input voltage and current to improve the circuit's control power factor, the drive control method is crucial. Although all three methods use model-independent control, the use of a High Order Differential Feedback Controller (HODFC) in the inner current loop of related schemes affects response speed due to the need for high-order derivative and dual-integral single-cycle modules. Considering system interference and the closed-loop response speed of PFC, this invention adopts a dual-loop ADRC control method with feedforward. In the inner current loop, the duty cycle is jointly determined by the feedforward term and the current loop output, improving the system's response speed. Meanwhile, due to the use of ADRC dual closed-loop control, system disturbances are considered in the extended state ESO of ADRC. Compared with the dual PID closed-loop control in related schemes, it has higher dynamic response and anti-interference capability, enabling the circuit to obtain better current waveforms and higher power factor.

[0261] Since the processing and functions implemented by the device in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned methods, any details not covered in the description of this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0262] According to an embodiment of the present invention, a power supply system corresponding to a control device for a PFC device is also provided. This power supply system may include the control device for the PFC device described above.

[0263] Since the processing and functions implemented by the power system in this embodiment are basically the same as those in the embodiments, principles and examples of the aforementioned device, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0264] According to an embodiment of the present invention, a computer program product corresponding to the control method of a PFC device is also provided, comprising a computer program that, when executed by a processor, implements the steps of the control method of the PFC device described above.

[0265] Since the processing and functions implemented by the product in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned methods, any details not covered in the description of this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0266] According to an embodiment of the present invention, a storage medium corresponding to a control method for a PFC device is also provided, the storage medium comprising a stored program, wherein, when the program is executed, the device where the storage medium is located executes the steps of the control method for the PFC device described above.

[0267] Since the processing and functions implemented by the storage medium in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned methods, any details not covered in the description of this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0268] In summary, it is readily understood by those skilled in the art that, without conflict, the aforementioned advantageous methods can be freely combined and superimposed.

[0269] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A control method for a PFC device, characterized in that, The PFC device has an inductor module and a power switch module; the control system of the PFC device has a voltage loop and a current loop; a feedforward link is provided on the output side of the current loop, and an ADRC module is provided in both the voltage loop and the current loop; The control method for the PFC device includes: When the PFC device is running, the input voltage of the PFC device is obtained, the current of the inductor module is obtained, the output voltage of the PFC device is obtained, and the given duty cycle of the power switch module provided by the feedforward circuit is obtained. Based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module, the ADRC module is used in the voltage loop and the current loop to determine the current duty cycle of the power switch module. Based on the current duty cycle of the power switch module, a PWM signal is output to the power switch module to control the on and off of the corresponding power switch in the power switch module, so as to adjust the waveform and / or phase of the input current of the PFC device.

2. The control method for the PFC device according to claim 1, characterized in that, Based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module, the ADRC module is used in the voltage loop and the current loop to determine the current duty cycle of the power switch module, including: The output voltage of the PFC device and the preset reference voltage are processed by the ADRC module in the voltage loop to obtain the intermediate value of the target input current of the PFC device. The input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device are processed by the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module. The sum of the given duty cycle of the power switch module and the calculated duty cycle of the power switch module is taken as the current duty cycle of the power switch module.

3. The control method for the PFC device according to claim 2, characterized in that, The output voltage of the PFC device and a preset reference voltage are processed by the ADRC module in the voltage loop to obtain the intermediate value of the target input current of the PFC device, including: The output voltage of the PFC device is processed by a preset first A / D module to obtain the digital output voltage of the PFC device; The digital output voltage of the PFC device is used as the actual value of the ADRC module in the voltage loop, and the preset reference voltage is used as the target value of the ADRC module in the voltage loop. The digital output voltage of the PFC device and the preset reference voltage are respectively input to the ADRC module in the voltage loop to obtain the output value of the ADRC module in the voltage loop, which is used as the intermediate value of the target input current of the PFC device.

4. The control method for the PFC device according to claim 2 or 3, characterized in that, The input voltage of the PFC device, the current of the inductor module, and the intermediate value of the target input current of the PFC device are processed by the ADRC module in the current loop to obtain the calculated duty cycle of the power switch module, including: The effective value of the input voltage of the PFC device is determined based on the input voltage of the PFC device. The input voltage of the PFC device is processed by a preset second A / D module to obtain the digital input voltage of the PFC device; and the current of the inductor module is processed by a preset second A / D module to obtain the digital current value of the inductor module. The product of the digital input voltage of the PFC device and the intermediate value of the target input current of the PFC device is divided by the effective value of the input voltage of the PFC device to obtain the target input current of the PFC device; the target input current of the PFC device is used as the target value of the ADRC module in the current loop, and the digital current value of the inductor module is used as the actual value of the ADRC module in the current loop. The digital current value of the inductor module and the target input current of the PFC device are respectively input into the ADRC module in the current loop to obtain the output value of the ADRC module in the current loop, which is used as the calculated duty cycle of the power switch module.

5. The control method for the PFC device according to any one of claims 1 to 4, characterized in that, The expression for the given duty cycle of the power switch module provided by the feedforward circuit is as follows: d2(n) = K1 - |Uin / Uoref|; Wherein, d2(n) represents the given duty cycle of the power switch module provided by the feedforward link, K1 represents the set calculation coefficient, Uin represents the input voltage of the PFC device, and Uoref represents the ideal value of the output voltage of the PFC device.

6. The control method for the PFC device according to any one of claims 1 to 5, characterized in that, The ADRC module has a TD stage, an NLSEF stage, and an ESO stage; the input side of the ADRC module is used to input the actual value and the target value, and the output side of the ADRC module is used to output the required output value. Processing using the ADRC module includes: Based on the target value input from the input side of the ADRC module, the transition value of the target value is obtained after the transition process is performed by the TD link; Based on the actual value input from the input side of the ADRC module, after the ESO step packages the interference factors in the actual value into an extended state for estimation processing, the first estimated value and the second estimated value of the actual value are obtained. The difference between the transition value of the target value and the second estimated value of the actual value is processed by the NLSEF step to obtain the nonlinear configuration value of the deviation between the target value and the actual value, which is denoted as the deviation configuration value between the target value and the actual value. The difference between the deviation between the target value and the actual value, and the ratio of the first estimated value of the actual value to the preset control input proportional coefficient, is used as the output value of the ADRC module. The product of the output value of the ADRC module and the preset control input proportional coefficient is used as the feedback value of the ESO loop, and fed back to the ESO loop to achieve closed-loop control.

7. The control method for the PFC device according to claim 6, characterized in that, in, In the ADRC module: The expression for the TD step is as follows: V1 = V1 + h * r0 * Π(y - yr, r, h); Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, V1 represents the transition value of the target value, r0, h and r all represent preset transition process control parameters, and Π(y-yr,r,h) represents a preset nonlinear function; And / or, The expression for the NLSEF stage is as follows: u1=r1*(Π(V1-Z1,alph3,belta1)); Where, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u1 represents the deviation configuration value between the target value and the actual value, r1 represents the preset adjustment parameter, V1 represents the transition value of the target value, Z1 represents the first estimated value of the actual value, alph3 represents the preset nonlinear parameter, belt1 represents the preset weight parameter, and Π(V1-Z1,alph3,belta1) represents the preset nonlinear function; And / or, The expression for the ESO step is as follows: Z1=Z1+h*(Z2+belta1*(Π(y-Z1,alph1,belta1))+b0*u); Z2=Z2+belta2*(Π(y-Z1,alph2,belta1)); Wherein, = represents assignment, yr represents the target value of the ADRC module, y represents the actual value of the ADRC module, u represents the output value of the ADRC module, h represents the preset transition process control parameter, Z1 represents the first estimated value of the actual value, Z2 represents the second estimated value of the actual value, belt2 represents the preset weight parameter, alph1 and alph2 both represent preset nonlinear parameters, and Π(y-Z1,alph1,belta1) and Π(y-Z1,alph2,belta1) both represent preset nonlinear functions.

8. A control device for a PFC device, characterized in that, The PFC device has an inductor module and a power switch module; the control system of the PFC device has a voltage loop and a current loop; a feedforward link is provided on the output side of the current loop, and an ADRC module is provided in both the voltage loop and the current loop; The control device of the PFC device includes: The acquisition unit is configured to acquire the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module provided by the feedforward circuit when the PFC device is in operation. The control unit is configured to process data in the voltage loop and the current loop using an ADRC module based on the input voltage of the PFC device, the current of the inductor module, the output voltage of the PFC device, and the given duty cycle of the power switch module, to determine the current duty cycle of the power switch module. The control unit is further configured to output a PWM signal to the power switching module according to the current duty cycle of the power switching module, and control the turn-on and turn-off of the corresponding power switching transistor in the power switching module to adjust the waveform and / or phase of the input current of the PFC device.

9. A power supply system, characterized in that, include: The control device for the PFC device as described in claim 8.

10. A storage medium, characterized in that, The storage medium includes a stored program, wherein, when the program is executed, the device containing the storage medium is controlled to perform the control method of the PFC device according to any one of claims 1 to 7.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the control method for the PFC device according to any one of claims 1 to 7.

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