Parallel switched capacitor integrator for oversampling ADC

Abstract

The invention relates to a parallel switch capacitor integrator insensitive to parasitic capacitance, which realizes high-precision signal integration processing through four steps: firstly, controlling switch logic by using a two-phase non-overlapping clock, ensuring that control signals are not overlapped, and reducing charging injection and clock feed-through; secondly, a resistor in the continuous time integrator is replaced by a switched capacitor simulation resistor, and current flow is simulated by utilizing a periodic charging and discharging process so as to control charge quantity transfer; then, a virtual switch is introduced to compensate the influence of charge injection, and the circuit performance is improved. And finally, a shunt capacitor integrator circuit is constructed, and the shunt capacitor integrator circuit is insensitive to parasitic capacitance through a specific circuit layout, so that high precision and linearity of an integrator are ensured.

Description

Technical Field

[0001] This invention provides a parallel switched capacitor integrator that is insensitive to parasitic capacitance, which can be applied to oversampling analog-to-digital converters and belongs to the field of integrated circuits. Background Technology

[0002] Switched-capacitor integrators play a crucial role in analog circuits, primarily responsible for key tasks such as analog signal integration, filtering, and noise shaping. The core function of a switched-capacitor integrator is time integration of the input signal, which is fundamental to various analog signal processing functions. By integrating the input signal, the integrator can alter the signal's spectral characteristics. In oversampling analog-to-digital converters, using an integrator to integrate the signal effectively reconfigures the noise energy distribution in the input signal, concentrating it primarily outside the frequency band, thereby improving the signal-to-noise ratio within a certain frequency band. Furthermore, since the core components of a switched-capacitor integrator are capacitors and switches, they are unaffected by temperature and process variations, thus enabling precise control and good repeatability. Through carefully designed switched-capacitor networks and non-overlapping clock strategies, parasitic effects caused by switching and circuit layout can be minimized, thereby improving the overall circuit accuracy and linearity. Summary of the Invention

[0003] Objective: The objective of this invention is to provide a switched capacitor integrator that is insensitive to parasitic capacitance, thereby increasing the reliability of the design while achieving high-precision signal integration processing, thus improving the performance and accuracy of the system.

[0004] Technical solution: The switch is controlled by a two-phase non-overlapping clock, and the switching element is simulated by a switched capacitor. The switching function is realized by a MOS transmission gate based on charge compensation technology. The input signal is applied to the inverting input of the operational amplifier through multiple capacitors connected in parallel, and finally the integration function is realized.

[0005] The specific steps are as follows: Step 1: Use a two-phase non-overlapping clock to control the switching logic.

[0006] Using clock source ck as the basic clock signal, NAND gates are used to adjust the duty cycle of the clock signal, and an inverter chain is added to copy and delay the clock signal, resulting in two non-overlapping clocks ck1 and ck2, and their delayed clocks ckd1 and ckd2. During the high level of ck1, ck2 remains low, and during the high level of ck2, ck1 remains low. Between the two clock phases, there is a brief time interval in which both ck1 and ck2 are low to ensure they do not overlap.

[0007] Step two: Replace the resistor in the continuous-time integrator with a switched capacitor to simulate a resistor.

[0008] Capacitor C is periodically charged and discharged between two voltage levels via controlled switches φ1 and φ2. This process simulates the current flow in a continuous-time resistor. During each switching cycle, the capacitor charges from one end to the other, transferring a certain amount of charge. By adjusting the switching frequency and the capacitance value, the amount of charge transferred in each cycle can be controlled, thus simulating different resistance values.

[0009] Step 3: Switch charge compensation.

[0010] Add a virtual switch on both sides of the main switch. Set the size of the virtual switch to half the size of the main switch and short-circuit its source and drain to compensate for the impact of the charge injected from the input terminal into the main circuit on the circuit performance.

[0011] Step 4: Establish a parallel capacitor integrator circuit that is insensitive to parasitic capacitance.

[0012] When φ1 is closed, Cp1 is connected in parallel with C, and the two capacitors are charged by the input voltage. When φ2 is closed, the charge held by C is transferred to the output terminal through the feedback capacitor C0. Since both plates of Cp1 are grounded, Cp1 has no effect on the transfer function of the circuit, that is, this integrator is not sensitive to parasitic capacitance.

[0013] Compared with the prior art, the advantages of this invention are: 1) Using non-overlapping clock techniques in circuits can reduce charge injection and clock feedthrough, thereby reducing the impact of parasitic capacitance. Ensuring sufficient time intervals between clock signals for control switches can prevent simultaneous off or on states and reduce parasitic effects.

[0014] 2) Because the capacitance value can be controlled very precisely and is less affected by temperature and manufacturing process variations, switched capacitor technology can achieve high-precision resistance simulation.

[0015] 3) This method allows for flexible adjustment of the analog resistor value by changing the switching frequency, increasing the flexibility of circuit design. Attached Figure Description

[0016] Figure 1 This is a flowchart of the two-phase non-overlapping clock generation process described in this invention; Figure 2 This invention includes a switched capacitor simulating a resistor; Figure 3 The switch used in this invention is a charge compensation switch; Figure 4 Circuit diagram of the parallel capacitor integrator designed for this invention;

[0017] C, C p1C0 switching capacitor, parasitic capacitance, feedback capacitor φ1, φ2 Switch 1, Switch 2 Detailed Implementation

[0018] In step two, within one clock cycle T, the amount of charge flowing from V1 to V2 is:

[0019] Therefore, the average current flowing to V2 in the circuit is:

[0020] The equivalent resistance derived from this can be expressed as:

[0021] In step four, the transfer function of the integrator is:

Claims

1. A parallel switched-capacitor integrator insensitive to parasitic capacitance, suitable for oversampling analog-to-digital converters, characterized in that, It includes a two-phase non-overlapping clock control module, which ensures that there is no overlap between control signals, reducing charge injection and clock feedthrough phenomena.

2. The parallel switched capacitor integrator according to claim 1, characterized in that, A switched capacitor is used to simulate a resistor element. This element simulates the resistance in a continuous-time integrator through a periodic charging and discharging process to control the amount of charge transferred in each switching cycle.

3. The parallel switched capacitor integrator according to claim 2, characterized in that, A charge compensation module is introduced, including a MOS transmission gate based on charge compensation technology and at least one virtual switch for compensating for the effects of charge injection, wherein the size of the virtual switch is configured as part of the size of the main switch and its source and drain are shorted.

4. The parallel switched capacitor integrator according to claim 3, characterized in that, A parallel capacitor integrator circuit is constructed, and a specific circuit layout is adopted to make it insensitive to parasitic capacitance, thereby ensuring the high accuracy and linearity of the integrator.

5. An oversampling analog-to-digital converter using the above-described parallel switched-capacitor integrator, characterized in that, This converter improves system performance and accuracy by reducing charge injection and clock feedthrough, as well as mitigating the effects of parasitic capacitance.

6. The oversampling analog-to-digital converter according to claim 5, characterized in that, This converter achieves precise control and high-precision resistor simulation by adjusting the switching frequency and utilizing switched capacitor technology, increasing the flexibility of circuit design.

7. A method for improving the performance of switched-capacitor integrators in oversampling analog-to-digital converters, characterized by the use of non-overlapping clocking techniques, switched-capacitor analog-resistive elements, and charge-compensated MOS transmission gates to effectively improve signal processing accuracy and system performance.

Images