Netlist data determination method and apparatus, chip, electronic device, storage medium, and computer program product

Abstract

The application provides a netlist data determination method and device, a chip, electronic equipment, a storage medium and a computer program product, and relates to the field of data processing. The method comprises the following steps: obtaining a target frequency and a target number of times of an SHA3 operation unit, the target frequency being a system running frequency, and the target number of times being the number of iterations of a KECCAK-f function in a single clock cycle; the SHA3 operation unit comprises an iteration calculation unit and at least one preprocessing unit, and the iteration calculation unit is used for executing the KECCAK-f function; determining a first maximum delay for executing a single KECCAK-f function according to the target frequency and the target number of times; determining a second maximum delay of at least one critical path in the KECCAK-f function according to the first maximum delay; determining first constraint data of the KECCAK-f function according to the first maximum delay and the second maximum delay; and determining netlist data of the iteration calculation unit according to RTL code of the KECCAK-f function and the first constraint data.

Description

Technical Field

[0001] This application relates to the field of data processing, and in particular to a method, apparatus, chip, electronic device, storage medium, and computer program product for determining netlist data. Background Technology

[0002] SHA-3 (Secure Hash Algorithm 3) is a third-generation secure hash algorithm released by the U.S. National Security Agency, also known as the Keccak algorithm. It is the latest generation of secure hash algorithms. Secure hash algorithms are also called hashing algorithms. The Keccak algorithm can resist attacks with a minimum complexity of 2^N, where N is the hash size. FPGA (Field-Programmable Gate Array) is a highly flexible programmable logic device widely used in electronic design and development. When implementing the SHA-3 algorithm on an FPGA platform, the complex principles of the SHA-3 algorithm and its computational flow (involving permutations, shifts, linear and nonlinear operations on large-width data and multi-dimensional arrays) result in excessively long timing paths. Currently, a common approach is to insert pipelines into the algorithm core operation process to complete complex calculations over multiple clock cycles, thereby improving operating frequency and computing power. However, inserting multi-stage pipelines generates a large number of registers, consumes significant hardware resources, and complicates the design. Furthermore, while multi-stage pipelines can increase the operating frequency, they consume more clock cycles, resulting in lower final performance. Summary of the Invention

[0003] This application provides a method, apparatus, chip, electronic device, storage medium, and computer program product for determining netlist data.

[0004] One embodiment of this application provides a method for determining netlist data, the method comprising:

[0005] The target frequency and target number of iterations of the SHA3 operation unit are obtained. The target frequency is the operating frequency of the system, and the target number of iterations is the number of iterations of the KECCAK-f function in a single clock cycle. The SHA3 operation unit includes an iterative calculation unit and at least one preprocessing unit. The iterative calculation unit is used to execute the KECCAK-f function.

[0006] The first maximum delay for executing the KECCAK-f function once is determined based on the target frequency and the target number of times.

[0007] Determine the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay;

[0008] The first constraint data of the KECCAK-f function is determined based on the first maximum delay and the second maximum delay;

[0009] The netlist data of the iterative calculation unit is determined based on the RTL code of the KECCAK-f function and the first constraint data.

[0010] The step of determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes:

[0011] The second maximum delay of the first sub-function is determined based on the first maximum delay, and the first sub-function is used to perform bit XOR on the input data.

[0012] The step of determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes:

[0013] The second maximum delay of the transmission path between the second sub-function and the third sub-function is determined based on the first maximum delay. The second sub-function is used to perform fixed transposition on the input data, and the third sub-function is used to perform bit combination on the input data.

[0014] The step of determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes:

[0015] The second maximum delay of the fourth sub-function is determined based on the first maximum delay, and the fourth sub-function is used to perform bit modification on the input data.

[0016] The method further includes:

[0017] Obtain the target number of cycles, which is the number of cycles required for data input;

[0018] The number of function execution cycles is determined based on the number of KECCAK-f functions and the target number of times.

[0019] The maximum number of cycles for the at least one preprocessing unit is determined based on the number of function execution cycles and the target number of cycles.

[0020] The method further includes:

[0021] The second constraint data of the at least one preprocessing unit is determined based on the maximum number of cycles;

[0022] The netlist data of the SHA3 operation unit is determined based on the RTL code of the at least one preprocessing unit, the second constraint data, and the netlist data of the iterative calculation unit.

[0023] Another embodiment of this application provides a netlist data determination apparatus, the apparatus comprising:

[0024] The processing module is used to obtain the target frequency and target number of iterations of the SHA3 operation unit. The target frequency is the operating frequency of the system, and the target number of iterations is the number of iterations of the KECCAK-f function in a single clock cycle. The SHA3 operation unit includes an iterative calculation unit and at least one preprocessing unit. The iterative calculation unit is used to execute the KECCAK-f function.

[0025] The calculation module is configured to: determine a first maximum delay for executing the KECCAK-f function once based on the target frequency and target number of times; determine a second maximum delay for at least one critical path within the KECCAK-f function based on the first maximum delay; determine first constraint data for the KECCAK-f function based on the first maximum delay and the second maximum delay; and determine netlist data for the iterative calculation unit based on the RTL code of the KECCAK-f function and the first constraint data.

[0026] Another embodiment of this application provides a chip, the chip including a processor, the processor being capable of executing the netlist data determination method.

[0027] Another aspect of this application provides an electronic device, the electronic device including a chip, the chip including a processor, the processor being capable of executing the netlist data determination method.

[0028] Another embodiment of this application provides a computer-readable storage medium storing a computer program for executing the netlist data determination method.

[0029] Another aspect of this application provides a computer program product, including a computer program or instructions, for inducing a processor to execute and implement the netlist data determination method provided in this application.

[0030] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0031] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0032] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0033] Figure 1 A flowchart of a method for determining netlist data according to an embodiment of this application is shown;

[0034] Figure 2 A schematic diagram of the structure of an SHA3 operation unit according to an embodiment of this application is shown;

[0035] Figure 3 A flowchart of a method for determining netlist data according to another embodiment of this application is shown;

[0036] Figure 4 A flowchart of a method for determining netlist data according to another embodiment of this application is shown;

[0037] Figure 5 A schematic diagram of a netlist data determination apparatus according to an embodiment of this application is shown;

[0038] Figure 6 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0039] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] Currently, when designing netlist files for corresponding hardware circuits, only the overall maximum time limit is constrained, resulting in low running frequency and low computational power for the algorithms described in the netlist files. Therefore, to improve the running frequency and computational power of the algorithms described in the netlist files, one embodiment of this application provides a method for determining netlist data, such as... Figure 1 As shown, the method includes:

[0041] Step 101: Obtain the target frequency and target number of iterations of the SHA3 operation unit. The target frequency is the operating frequency of the system, and the target number of iterations is the number of iterations of the KECCAK-f function within a single clock cycle. The SHA3 operation unit includes an iterative calculation unit and at least one preprocessing unit. The iterative calculation unit is used to execute the KECCAK-f function.

[0042] In a System-on-a-Chip (SoC), the SHA3 arithmetic unit is typically a unit mounted on the system bus or a dedicated bus. It is used to retrieve data from the processor or mass storage and perform arithmetic operations. The data width of the bus interface is typically 32 bits or 64 bits, while the SHA3 algorithm requires input of data of length r (e.g., 1152, 1088, 832, 576, or 1344 bits) each time.

[0043] The target frequency is the operating frequency of the SOC system where the SHA3 computing unit resides. The target number of iterations is the number of times the KECCAK-f function can be iterated within a single clock cycle, i.e., the number of KECCAK-f functions that can be executed within a single clock cycle. The target number of iterations is determined based on the performance requirements of the initial design of the SHA3 computing unit.

[0044] For example, the target frequency of a certain SHA3 operation unit is 100MHz and the target number of operations is 4.

[0045] The SHA3 operation unit includes an iterative calculation unit and at least one preprocessing unit. The iterative calculation unit includes multiple sub-units, each of which is used to execute the first KECCAK-f function on the input data.

[0046] For example, such as Figure 2 As shown, Figure 2 An SHA3 operation unit is shown, which includes three preprocessing units: data packetization, message filling, and logic control, as well as an iterative calculation unit. The iterative calculation unit includes multiple sub-units.

[0047] Data grouping is used to convert 32-bit or 64-bit data from the previous input into data of length r.

[0048] Message padding is used to add extra information to the data input from the previous level, ensuring that the total length of the input data and the added extra information is an integer multiple of r. The specific padding method varies depending on the data length. This step handles large bit widths (such as 1152, 1088, 832, 576, and 1344 bits), resulting in high timing delays and significant hardware resource consumption.

[0049] The logic control is used to output the data after message filling to the iterative operation unit according to the requirements of the next level read / write timing.

[0050] The iterative computation unit is used to iteratively compress the input data using the KECCAK-f function in multiple rounds.

[0051] Step 102: Determine the first maximum delay for executing the KECCAK-f function once based on the target frequency and the target number of times.

[0052] Specifically, the first maximum delay for executing a single KECCAK-f function can be determined based on the following formula. :

[0053]

[0054] in, For the target frequency, The target number of times.

[0055] Continuing with the example above, if the target frequency is 100MHz and the target number of executions is 4, then the first maximum delay for executing the KECCAK-f function once is determined to be 2.25 nanoseconds.

[0056] Step 103: Determine the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay.

[0057] Determine the critical path within the KECCAK-f function, and then determine the corresponding second maximum delay, such as the second maximum delay of the sub-function used to perform bit XOR and bit modification on the input data, and the second maximum delay of the transmission from the sub-function used to perform fixed transposition on the input data to the sub-function used to perform bit combination on the input data.

[0058] The second maximum delay corresponding to the sub-function can be determined based on the preset ratio and the first maximum delay.

[0059] For example, the preset ratio for the sub-function used to perform a bitwise XOR operation on the input data is 0.4. The first maximum delay is 2.25 nanoseconds. Then the second maximum delay of this sub-function is 0.9 nanoseconds.

[0060] The structure of the critical path can also be obtained, and the second maximum delay corresponding to the sub-function can be determined based on the structure of the critical path and the first maximum delay.

[0061] Step 104: Determine the first constraint data of the KECCAK-f function based on the first maximum delay and the second maximum delay.

[0062] The first constraint data must simultaneously include timing constraints on the KECCAK-f function as a whole, i.e., the first maximum delay, and timing constraints on the critical paths within the KECCAK-f function, i.e., the second maximum delay of each critical path. The overall constraint ensures that a single KECCAK-f iteration does not exceed the total allowable delay, while the critical path constraint specifically optimizes the path with the longest delay to avoid local timing violations, ultimately ensuring that the netlist data meets the requirements of the target frequency and target number of iterations.

[0063] For example, if the first maximum delay is 2.25 nanoseconds, then the first constraint data generated based on the first maximum delay is " The second maximum delay of the sub-function used to perform bit XOR on the input data is 0.9 nanoseconds. Therefore, based on the second maximum delay, the generated first constraint data is "". ".

[0064] Step 105: Determine the netlist data of the iterative calculation unit based on the RTL code of the KECCAK-f function and the first constraint data.

[0065] The RTL code of the KECCAK-f function is combined with the first constraint data, and the netlist data of the iterative computation unit is generated through logic synthesis. The synthesis tool will optimize the logic based on the functional logic of the RTL code and the timing requirements in the first constraint data, and finally generate gate-level netlist data that meets the timing constraints.

[0066] In the above scheme, by first obtaining the target frequency and target number of SHA3 operation units, the performance requirement anchor point for algorithm operation is clarified. Then, based on the target frequency and target number of executions, the first maximum delay for executing a single KECCAK-f function is determined, achieving precise control over the total delay of a single KECCAK-f function iteration and avoiding performance waste or timing violations caused by overly loose or tight overall timing constraints. Then, based on the first maximum delay and the proportion corresponding to the sub-functions, the second maximum delay for at least one critical path within the KECCAK-f function is determined, refining and decomposing the overall delay constraint to the critical path level, effectively solving the problem of local critical path timing exceedances that may occur when only constraining the overall system. Furthermore, by combining the first and second maximum delays, first constraint data is generated that simultaneously contains the overall timing constraints of the KECCAK-f function and the timing constraints of the internal critical paths, providing a more accurate optimization basis for logic synthesis, ensuring that a single KECCAK-f iteration does not exceed the total allowable delay, and enabling targeted optimization of the path with the longest delay. Finally, based on the RTL code of the KECCAK-f function and the first constraint data, the netlist data of the iterative computation unit is generated through logic synthesis. This allows the synthesis tool to perform logic optimization based on precise timing constraints, ultimately generating gate-level netlist data that meets the target frequency and target number of iterations. This improves the running frequency and computational power of the algorithm described in the netlist file.

[0067] In one example of this application, a method for determining netlist data is also provided, wherein determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes:

[0068] The second maximum delay of the first sub-function is determined based on the first maximum delay, and the first sub-function is used to perform bit XOR on the input data.

[0069] The first sub-function is This function is used to perform bitwise XOR on the input data.

[0070] The second maximum delay of the first subfunction can be determined in the following two ways:

[0071] The first method involves determining the second maximum delay of the first sub-function based on a preset ratio and the first maximum delay.

[0072] For example, if the preset ratio of the first sub-function is set to 0.4 and the first maximum delay is 2.25 nanoseconds, then the second maximum delay of the first sub-function is 0.9 nanoseconds.

[0073] The second method involves obtaining the structure of the first sub-function and determining the second maximum delay of the first sub-function based on the structure and the first maximum delay.

[0074] For example, the first sub-function needs to XOR 5 bits within a column. Its structure is a 2-layer XOR gate, and its internal path is input data - 2-layer XOR gate - output data. The wiring length from input to output of the first sub-function is approximately 5mm. Extracting the delay data corresponding to the gate type from the technology library: 0.12 nanoseconds for a 2-bit XOR gate, and 0.05 nanoseconds / mm for wiring per unit length. Therefore, the second maximum delay of the first sub-function is: Nanoseconds. The first maximum delay is used to constrain the sum of the second maximum delays of each critical path to not exceed the first maximum delay, after determining the second maximum delays of each critical path.

[0075] In the above scheme, two specific methods are provided for determining the second maximum delay of the first sub-function within the KECCAK-f function, which performs bitwise XOR on the input data. This creates conditions for accurately controlling the timing of this critical path. The first method determines the second maximum delay by combining a preset ratio of the first sub-function with the first maximum delay, offering convenient operation and rapid delay result acquisition. The second method first obtains the structural information of the first sub-function, then combines it with the corresponding gate delay data and unit length wiring delay data from the technology library to calculate the second maximum delay. This method better reflects the actual hardware implementation of the first sub-function, making delay determination more accurate and providing strong support for ultimately generating iterative computing unit netlist data that meets performance requirements.

[0076] In one example of this application, a method for determining netlist data is also provided, wherein determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes:

[0077] The second maximum delay of the transmission path between the second sub-function and the third sub-function is determined based on the first maximum delay. The second sub-function is used to perform fixed transposition on the input data, and the third sub-function is used to perform bit combination on the input data.

[0078] The second sub-function is The function is used to perform a fixed transposition on the input data. The third sub-function is... The function is used to combine bits from the input data. The transmission path between the second and third sub-functions is the critical path.

[0079] The second maximum delay of the transmission path between the second and third sub-functions can be determined in the following two ways:

[0080] The first method involves determining the second maximum delay of the transmission path between the second and third sub-functions based on a preset ratio and the first maximum delay.

[0081] For example, if the preset ratio is set to 0.2 and the first maximum delay is 2.25 nanoseconds, then the second maximum delay of the transmission path between the second sub-function and the third sub-function is 0.45 nanoseconds.

[0082] The second method involves obtaining the structure of the first sub-function and determining the second maximum delay of the first sub-function based on the structure and the first maximum delay.

[0083] For example, the wiring length of the transmission path between the second and third sub-functions is approximately 8mm. The delay data corresponding to the gate type is extracted from the technology library: the unit length wiring delay is 0.05 nanoseconds / mm. Therefore, the second maximum delay of the transmission path between the second and third sub-functions is: Nanoseconds. The first maximum delay is used to constrain the sum of the second maximum delays of each critical path to not exceed the first maximum delay, after determining the second maximum delays of each critical path.

[0084] In the above scheme, for the critical path between the second sub-function (used for fixed transposition of input data) and the third sub-function (used for bit combination of input data) within the KECCAK-f function, two specific methods are provided to determine the second maximum delay, offering a clear and feasible solution for timing control of this critical path. The first method determines the second maximum delay of the transmission path by combining a preset ratio with the first maximum delay; this method is simple to operate and can quickly obtain delay results. The second method first obtains the wiring length of the transmission path and then calculates the second maximum delay by combining it with the unit length wiring delay data from the technology library. This method better reflects the actual hardware implementation of the transmission path, making the delay determination more accurate and providing strong support for the final generation of iterative computing unit netlist data that meets performance requirements.

[0085] In one example of this application, a method for determining netlist data is also provided, wherein determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes:

[0086] The second maximum delay of the fourth sub-function is determined based on the first maximum delay, and the fourth sub-function is used to perform bit modification on the input data.

[0087] The fourth sub-function is A function used to modify the bits of input data.

[0088] The second maximum delay of the fourth subfunction can be determined in the following two ways:

[0089] The first method involves determining the second maximum delay of the fourth sub-function based on a preset ratio and the first maximum delay.

[0090] For example, if the preset ratio of the fourth sub-function is set to 0.05 and the first maximum delay is 2.25 nanoseconds, then the second maximum delay of the fourth sub-function is 0.1125 nanoseconds.

[0091] The second method involves obtaining the structure of the fourth sub-function and determining the second maximum delay of the fourth sub-function based on the structure and the first maximum delay.

[0092] For example, the fourth sub-function has a 2-bit XOR gate structure, and its internal path is round constant - 2-bit XOR gate - output data. The wiring length from the round constant to the output of the fourth sub-function is approximately 2 mm. Extracting the delay data corresponding to the gate type from the technology library: 0.12 nanoseconds for the 2-bit XOR gate, and 0.05 nanoseconds / mm for the unit length wiring delay. Therefore, the second maximum delay of the fourth sub-function is: Nanoseconds. The first maximum delay is used to constrain the sum of the second maximum delays of each critical path to not exceed the first maximum delay, after determining the second maximum delays of each critical path.

[0093] In the above scheme, two specific methods are provided for determining the second maximum delay of the fourth sub-function within the KECCAK-f function, which is used to modify the input data bits. This provides a feasible solution for timing control of this critical path. The first method determines the second maximum delay by combining a preset ratio of the fourth sub-function with the first maximum delay, offering convenient operation and quick delay results. The second method first obtains the structure of the fourth sub-function, then calculates its second maximum delay by combining 2-bit XOR gate delay data and unit-length wiring delay data from the technology library. This method better reflects the actual hardware implementation of the fourth sub-function, making delay determination more accurate and supporting the final generation of iterative computing unit netlist data that meets performance requirements.

[0094] This application also provides a method for determining netlist data in one example, such as Figure 3 As shown, the method further includes:

[0095] Step 201: Obtain the target number of cycles, which is the number of cycles required for data input.

[0096] Step 202: Determine the number of function execution cycles based on the number of KECCAK-f functions and the target number of times.

[0097] Because the iterative computation unit comprises multiple sub-units, each operating independently, the next set of data does not need to wait for the previous set of data to be processed by all sub-units before being input into the iterative computation unit. It only needs to be input into the iterative computation unit after a target number of clock cycles. To improve performance, all pre-processing units within the SHA3 computation unit must complete the preparation of the next set of data within the cycle in which the current set of data completes its iterative computation. Generally, the data input bandwidth is high (no complex calculations involved, only transmission), therefore only a small number of clock cycles are required. The number of clock cycles required to acquire the data input is denoted as... That is, the target number of cycles.

[0098] For example, the SHA3 operation unit includes data packetization, message stuffing, logic control, and iterative computation units. The iterative computation unit includes 24 sub-units, with a target number of iterations of 4. Therefore, it takes 6 clock cycles for a set of data to complete 24 rounds of iterative computation within the iterative computation unit. Within these 6 clock cycles of the current set of data undergoing 24 rounds of iterative computation within the iterative computation unit, the data input and non-critical path (pre-processing unit) processing for the next set of data need to be completed, namely data packetization, message stuffing, and logic control.

[0099] However, considering the complexity of non-critical path processes and the lengthy and complex timing paths, setting this process as a multi-cycle constraint can increase the execution frequency without affecting performance. When setting the constraint, the number of function execution cycles can be determined first using the following formula based on the number of KECCAK-f functions and the target number of iterations. :

[0100]

[0101] in, The number of KECCAK-f functions, The target number is the number of iterations of the KECCAK-f function within a single clock cycle.

[0102] For example, if the number of KECCAK-f functions is 24 and the target number of times is 4, then the number of function execution cycles is 6, meaning that it takes 6 clock cycles to complete all rounds of the KECCAK-f function for each batch of input data.

[0103] Step 203: Determine the maximum number of cycles for the at least one preprocessing unit based on the function execution cycle number and the target cycle number.

[0104] Specifically, the maximum number of cycles for the non-critical path can be determined using the following formula based on the function execution cycle number and the target cycle number. :

[0105]

[0106] in, This represents the number of function execution cycles. The number of clock cycles for data input.

[0107] Continuing with the example above, if the function execution cycle count is 6 and the data input clock cycle count is 2, then the maximum number of cycles for the non-critical path is 3.

[0108] In the above scheme, the target number of cycles required for data input is first obtained, and then the number of function execution cycles is determined based on the number of KECCAK-f functions and the target number of cycles. Since multiple sub-units within the iterative computation unit can run independently, the next round of data does not need to wait for the previous round of data to go through all sub-unit operations; it only needs to be input into the iterative computation unit for processing after the target number of cycles. Next, combining the number of function execution cycles and the target number of cycles, the maximum number of cycles for at least one pre-processing unit is determined. This ensures that the pre-processing unit is ready for the next set of data within the cycle in which the current set of data completes its iterative computation. At the same time, for cases where non-critical paths have complex and long time sequences, they are set as multi-cycle constraints, which effectively improves the running frequency of the SHA3 computation unit without affecting performance, thus providing stronger support for generating netlist data for the SHA3 computation unit that meets performance requirements.

[0109] This application also provides a method for determining netlist data in one example, such as Figure 4 As shown, the method further includes:

[0110] Step 301: Determine the second constraint data of the at least one preprocessing unit based on the maximum number of cycles.

[0111] After determining the maximum number of cycles for non-critical paths, second constraint data for at least one preprocessing unit is determined based on the maximum number of cycles.

[0112] For example, if the maximum number of cycles on a non-critical path is 3, then the second constraint data generated based on the maximum number of cycles is " ".

[0113] Step 302: Determine the netlist data of the SHA3 operation unit based on the RTL code of the at least one preprocessing unit, the second constraint data, and the netlist data of the iterative calculation unit.

[0114] The RTL code of all preprocessing units, the second constraint data, and the netlist data of the iterative computation unit are synthesized into the netlist data of the SHA3 computation unit through logic synthesis. The synthesis tool will perform logic optimization based on the functional logic of the RTL code and the timing requirements in the first constraint data, and finally generate gate-level netlist data that meets the timing constraints.

[0115] In the above scheme, firstly, based on the determined maximum number of cycles, the second constraint data for at least one preprocessing unit is determined, providing a clear basis for the timing constraints of the preprocessing unit. Then, the RTL code of at least one preprocessing unit, the second constraint data, and the netlist data of the previously determined iterative computation unit are combined, and the netlist data of the SHA3 computation unit is generated through logic synthesis. The synthesis tool will perform logic optimization according to the functional logic of the RTL code and in accordance with relevant timing requirements, and finally generate gate-level netlist data that meets the timing constraints. This not only improves the generation process of the SHA3 computation unit netlist data, but also ensures that the generated netlist data better meets the overall performance requirements.

[0116] To implement the above method for determining netlist data, such as Figure 5 As shown, an example of this application provides a netlist data determination apparatus, including:

[0117] Processing module 401 is used to obtain the target frequency and target number of iterations of the SHA3 operation unit. The target frequency is the operating frequency of the system, and the target number of iterations is the number of iterations of the KECCAK-f function in a single clock cycle. The SHA3 operation unit includes an iterative calculation unit and at least one preprocessing unit. The iterative calculation unit is used to execute the KECCAK-f function.

[0118] The calculation module 402 is configured to determine a first maximum delay for executing the KECCAK-f function once based on the target frequency and the target number of times; determine a second maximum delay for at least one critical path within the KECCAK-f function based on the first maximum delay; determine first constraint data for the KECCAK-f function based on the first maximum delay and the second maximum delay; and determine netlist data for the iterative calculation unit based on the RTL code of the KECCAK-f function and the first constraint data.

[0119] The calculation module 402 is further configured to determine the second maximum delay of the first sub-function based on the first maximum delay, wherein the first sub-function is configured to perform bit XOR on the input data.

[0120] The calculation module 402 is further configured to determine the second maximum delay of the transmission path between the second sub-function and the third sub-function based on the first maximum delay. The second sub-function is configured to perform fixed transposition on the input data, and the third sub-function is configured to perform bit combination on the input data.

[0121] The calculation module 402 is further configured to determine the second maximum delay of the fourth sub-function based on the first maximum delay, wherein the fourth sub-function is used to perform bit modification on the input data.

[0122] The processing module 401 is further configured to obtain a target number of cycles, wherein the target number of cycles is the number of cycles required for data input;

[0123] The calculation module 402 is further configured to determine the number of function execution cycles based on the number of KECCAK-f functions and the target number of cycles; and to determine the maximum number of cycles for the at least one preprocessing unit based on the number of function execution cycles and the target number of cycles.

[0124] The calculation module 402 is further configured to determine the second constraint data of the at least one preprocessing unit based on the maximum number of cycles; and to determine the netlist data of the SHA3 operation unit based on the RTL code of the at least one preprocessing unit, the second constraint data, and the netlist data of the iterative calculation unit.

[0125] This application also provides a chip, which includes a processor capable of executing the netlist data determination method provided in this application.

[0126] This application also provides an electronic device.

[0127] Figure 6 A schematic block diagram of an example electronic device 500 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0128] like Figure 6As shown, the electronic device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. The RAM 503 may also store various programs and data required for the operation of the electronic device 500. The computing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0129] Multiple components in electronic device 500 are connected to I / O interface 505, including: input unit 506, such as keyboard, mouse, etc.; output unit 507, such as various types of monitors, speakers, etc.; storage unit 508, such as disk, optical disk, etc.; and communication unit 509, such as network card, modem, wireless transceiver, etc. Communication unit 509 allows electronic device 500 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0130] The computing unit 501 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the various methods and processes described above, such as the netlist data determination method. For example, in some embodiments, the netlist data determination method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by the computing unit 501, one or more steps of the netlist data determination method described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the netlist data determination method by any other suitable means (e.g., by means of firmware).

[0131] This application provides a computer-readable storage medium storing executable instructions, wherein a computer program is stored, the computer program being used to execute the netlist data determination method provided in this application.

[0132] This application provides a computer program product, which includes a computer program or instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or instructions from the computer-readable storage medium and executes the computer program or instructions, causing the computer device to perform the netlist data determination method described above in this application.

[0133] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0134] In some embodiments, a computer program may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0135] As an example, a computer program may be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0136] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0137] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0138] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0139] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0140] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0141] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0142] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0143] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0144] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for determining netlist data, characterized in that, The method includes: The target frequency and target number of iterations of the SHA3 operation unit are obtained. The target frequency is the operating frequency of the system, and the target number of iterations is the number of iterations of the KECCAK-f function in a single clock cycle. The SHA3 operation unit includes an iterative calculation unit and at least one preprocessing unit. The iterative calculation unit is used to execute the KECCAK-f function. The first maximum delay for executing the KECCAK-f function once is determined based on the target frequency and the target number of times. Determine the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay; The first constraint data of the KECCAK-f function is determined based on the first maximum delay and the second maximum delay; The netlist data of the iterative calculation unit is determined based on the RTL code of the KECCAK-f function and the first constraint data.

2. The method according to claim 1, characterized in that, The step of determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes: The second maximum delay of the first sub-function is determined based on the first maximum delay, and the first sub-function is used to perform bit XOR on the input data.

3. The method according to claim 1, characterized in that, The step of determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes: The second maximum delay of the transmission path between the second sub-function and the third sub-function is determined based on the first maximum delay. The second sub-function is used to perform fixed transposition on the input data, and the third sub-function is used to perform bit combination on the input data.

4. The method according to claim 1, characterized in that, The step of determining the second maximum delay of at least one critical path within the KECCAK-f function based on the first maximum delay includes: The second maximum delay of the fourth sub-function is determined based on the first maximum delay, and the fourth sub-function is used to perform bit modification on the input data.

5. The method according to claim 1, characterized in that, The method further includes: Obtain the target number of cycles, which is the number of cycles required for data input; The number of function execution cycles is determined based on the number of KECCAK-f functions and the target number of times. The maximum number of cycles for the at least one preprocessing unit is determined based on the number of function execution cycles and the target number of cycles.

6. The method according to claim 5, characterized in that, The method further includes: The second constraint data of the at least one preprocessing unit is determined based on the maximum number of cycles; The netlist data of the SHA3 operation unit is determined based on the RTL code of the at least one preprocessing unit, the second constraint data, and the netlist data of the iterative calculation unit.

7. A netlist data determination device, characterized in that, The device includes: The processing module is used to obtain the target frequency and target number of iterations of the SHA3 operation unit. The target frequency is the operating frequency of the system, and the target number of iterations is the number of iterations of the KECCAK-f function in a single clock cycle. The SHA3 operation unit includes an iterative calculation unit and at least one preprocessing unit. The iterative calculation unit is used to execute the KECCAK-f function. The calculation module is configured to: determine a first maximum delay for executing the KECCAK-f function once based on the target frequency and target number of times; determine a second maximum delay for at least one critical path within the KECCAK-f function based on the first maximum delay; determine first constraint data for the KECCAK-f function based on the first maximum delay and the second maximum delay; and determine netlist data for the iterative calculation unit based on the RTL code of the KECCAK-f function and the first constraint data.

8. The apparatus according to claim 7, characterized in that, include: The calculation module is further configured to determine the second maximum delay of the first sub-function based on the first maximum delay, wherein the first sub-function is configured to perform bit XOR on the input data.

9. The apparatus according to claim 7, characterized in that, include: The calculation module is further configured to determine a second maximum delay from the output of the second sub-function to the input of the third sub-function based on the first maximum delay. The second sub-function is configured to perform fixed transposition on the input data, and the third sub-function is configured to perform bit combination on the input data.

10. The apparatus according to claim 7, characterized in that, include: The calculation module is further configured to determine the second maximum delay of the fourth sub-function based on the first maximum delay, wherein the fourth sub-function is used to perform bit modification on the input data.

11. The apparatus according to claim 7, characterized in that, include: The processing module is also used to obtain a target number of cycles, which is the number of cycles between the previous round of input data and the next round of input data; The calculation module is further configured to determine the number of function execution cycles based on the number of KECCAK-f functions and the target number of cycles; and to determine the third maximum delay of the at least one preprocessing unit based on the number of function execution cycles and the target number of cycles.

12. A chip, characterized in that, The chip includes a processor capable of executing the netlist data determination method according to any one of claims 1 to 6.

13. An electronic device, characterized in that, The electronic device includes a chip, the chip includes a processor, and the processor is capable of executing the netlist data determination method according to any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that, The storage medium stores a computer program for executing the netlist data determination method according to any one of claims 1 to 6.

15. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, they implement the netlist data determination method according to any one of claims 1 to 6.

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