Wafer test data transmission method and device, computer equipment and storage medium

Abstract

The invention relates to the technical field of chip testing, and discloses a wafer test data transmission method and device, computer equipment and a storage medium, and the wafer test data transmission method comprises the steps: obtaining a to-be-transmitted data volume and an expected transmission block data volume of each wafer; obtaining a division divisor according to the to-be-transmitted data volume and the expected transmission block data volume; carrying out block division on the wafer according to the division divisor and obtaining the number of blocks needing to be transmitted; and obtaining test data of one crystal grain on the block needing to be transmitted and sending the test data to the design technology collaborative optimization system for analysis. According to the invention, the wafer can be automatically divided into blocks, and only the measured values of the crystal grains representing the blocks in the wafer are sent to the design technology collaborative optimization system for data analysis, so that the processing burden of the design technology collaborative optimization system can be reduced while the detection of the feature distribution of the wafer is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, and particularly relates to a wafer test data transmission method and device, computer equipment and a storage medium. BACKGROUND

[0002] In the process of chip design and process manufacturing, integrated optimization is often sought through a design-technology co-optimization (DTCO) approach to improve performance, power efficiency, transistor density, and cost. The dies on the wafer / silicon wafer are measured by an automatic test equipment (ATE) to obtain relevant parameters, which are transmitted to a DTCO system for data analysis, and then an improvement direction is obtained.

[0003] However, the DTCO requires a large number of measurement items, and the data generated by one lot (a batch of wafers processed by the same processing step) can reach tens of millions or even hundreds of millions. The existing method usually transmits the measurement values of each die to the system, and such a large amount of data will cause the processing burden of the DTCO system to be too large.

[0004] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0005] In view of the above problems of the prior art, the present application aims to provide a wafer test data transmission method, device, computer equipment and storage medium to solve the problem that the processing burden of the DTCO system is too large due to too large data flow when the wafer data is tested.

[0006] The technical scheme of the present application is as follows: In a first aspect, the present application provides a wafer test data transmission method, which comprises: obtaining the amount of data to be transmitted and the expected amount of data to be transmitted for each wafer; square rooting the ratio of the amount of data to be transmitted and the expected amount of data to be transmitted; obtaining a division divisor by taking the square root value obtained after square rooting and taking the upper value; dividing the wafer according to the division divisor and obtaining the number of blocks to be transmitted; obtaining the test data of one die on the block to be transmitted and sending it to a design-technology co-optimization system for analysis.

[0007] Further provided in the present application, the step of obtaining a division divisor according to the amount of data to be transmitted and the expected amount of data to be transmitted comprises: square root of the ratio of the amount of data to be transmitted and the expected amount of data to be transmitted; obtaining the division divisor by rounding up the square root value.

[0008] Further provided in the present application, the step of dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted comprises: dividing the wafer into blocks along the transverse direction and the longitudinal direction of the wafer with the division divisor; wherein the division divisor represents the number of cells to be divided on the wafer.

[0009] Further provided in the present application, the step of obtaining the test data of one of the dies on the block to be transmitted and sending the test data to the design-technology collaborative optimization system for analysis comprises: obtaining the measurement value of the die at the same position of each block to be transmitted, and taking the coordinates of the die and the measurement value as the representative value and the representative coordinates of the block to be transmitted; sending the measurement value of the die at the same position of each block to be transmitted to the design-technology collaborative optimization system.

[0010] Further provided in the present application, the step of obtaining the test data of one of the dies on the block to be transmitted and sending the test data to the design-technology collaborative optimization system for analysis comprises: obtaining the measurement value of the die on the block to be transmitted and performing average processing to obtain a measurement average value; assigning the measurement average value to the coordinates of the die at the center of the block to be transmitted, and taking the coordinates of the center die and the measurement value as the representative value and the representative coordinates of the block to be transmitted.

[0011] Further provided in the present application, the step of obtaining the test data of one of the dies on the block to be transmitted and sending the test data to the design-technology collaborative optimization system for analysis further comprises: screening the dies on each block to be transmitted to screen out effective dies; if the dies in the block to be transmitted are all abnormal dies, the test data of the block with all abnormal dies is not transmitted to the design-technology collaborative optimization system.

[0012] Further provided in the present application, the expression of the division divisor is: .

[0013] In a second aspect, the present application further provides a wafer test data transmission device, which comprises: an acquisition unit configured to acquire the amount of data to be transmitted and the expected amount of data to be transmitted for each wafer; a calculation unit configured to square root a ratio of the to-be-transmitted data amount to the expected transmission block data amount, and obtain a division divisor by rounding up the square root value; a block division unit configured to divide the wafer into blocks according to the division divisor and obtain a number of blocks to be transmitted; a data sending unit configured to obtain test data of one die on the block to be transmitted and send the test data to a design technology collaborative optimization system for analysis.

[0014] In a third aspect, the present application also provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the computer program is used to implement the steps of the wafer test data transmission method when executed by the processor.

[0015] In a fourth aspect, the present application also provides a storage medium storing a computer program, and the computer program is used to implement the steps of the wafer test data transmission method when executed by a processor.

[0016] The wafer test data transmission method, device, computer device and storage medium provided by the present application can automatically calculate a suitable block division divisor to automatically implement block division of the wafer, and greatly improve the efficiency of block division, compared with a traditional scheme in which a work staff manually plans a block division divisor on the wafer (the work staff needs to repeatedly try multiple division manners to calculate corresponding block data amounts, so as to find a block division divisor close to an expected transmission block data amount, and the efficiency is extremely low). In this way, the present application only sends measurement values of dies representing blocks in the wafer to the design technology collaborative optimization system for analysis, so that the processing burden of the design technology collaborative optimization system can be reduced while ensuring detection of characteristic distribution of the wafer. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to make the technical solutions of the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only need to explain the present application, and those skilled in the art can also obtain other drawings according to the structures shown in the drawings without any creative effort.

[0018] Figure 1 is a flowchart of the wafer test data transmission method in the present application.

[0019] Figure 2 is a schematic diagram of automatically dividing blocks in an embodiment of the present application.

[0020] Figure 3 is a schematic diagram of obtaining representative values and representative coordinates of blocks after automatically dividing blocks in an embodiment of the present application.

[0021] Figure 4 is a schematic diagram of obtaining representative values and representative coordinates of blocks in the case of missing dies in blocks in an embodiment of the present application.

[0022] Figure 5 is a schematic diagram of obtaining representative values and representative coordinates of blocks in an embodiment of the present application.

[0023] Figure 6 is a schematic diagram of obtaining representative values and representative coordinates of blocks in the case of abnormal dies in blocks in an embodiment of the present application.

[0024] Figure 7 is a schematic diagram of obtaining representative values and representative coordinates of blocks in the case of all abnormal dies in blocks in an embodiment of the present application.

[0025] Figure 8 is a schematic diagram of obtaining representative values and representative coordinates of blocks in the case of all abnormal dies in blocks in an embodiment of the present application. Specific embodiments

[0026] The present application provides a wafer test data transmission method, device, computer equipment and storage medium. In order to make the purpose, technical solutions and effects of the present application clearer and more explicit, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0027] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0028] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any of the units and all combinations thereof of one or more associatedly listed items.

[0029] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0030] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0031] The inventors discovered that DTCO requires numerous measurements, with a single lot (a batch of wafers undergoing the same processing steps) generating tens or even hundreds of millions of data points. Current practices typically transmit the measurement values ​​of each die to the system, but such a massive data volume places an excessive burden on the DCTO system. Furthermore, existing methods do not filter out abnormal data before it is transmitted to the system; instead, the DCTO system filters and selects data one by one, which can easily degrade system performance.

[0032] In view of the above technical problems, the present application provides a wafer test data transmission method, device, computer equipment and storage medium, which can automatically implement block division processing on the wafer, and only sends the measurement value of the die representing the block in the wafer to the design technology collaborative optimization system for analysis, so as to reduce the processing burden of the design technology collaborative optimization system while ensuring the detection of the wafer feature distribution. In addition, before testing, the effective die of the wafer is screened, so that the measurement value of the abnormal die will not be input to the design technology collaborative optimization system for analysis, and the design technology collaborative optimization system does not need to detect the abnormal state of the die, which can further reduce the processing burden of the design technology collaborative optimization system.

[0033] Please refer to Figures 1 to 7 The present application provides a preferred embodiment of a wafer test data transmission method.

[0034] In some embodiments, as shown in Figure 1 The present application provides a wafer test data transmission method, which includes the following steps: S100, obtaining the amount of data to be transmitted and the amount of data of the expected transmission block for each wafer; Specifically, the wafer (or silicon wafer) is composed of a plurality of arranged dies, each die has its own coordinate value and measurement value. The expected transmission block data amount refers to theoretically dividing the dies on the wafer into blocks, and analyzing the feature distribution of the wafer in the design technology collaborative optimization system in units of blocks, so that the analysis result obtained is accurate.

[0035] S200, obtaining a division divisor according to the amount of data to be transmitted and the amount of data of the expected transmission block; Specifically, the division divisor refers to the number of dies that need to be divided in the horizontal direction (X-axis direction) and the vertical direction (Y-axis direction) of the wafer. The division divisor is calculated by the amount of data to be transmitted and the amount of data of the expected transmission block.

[0036] S300, dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted; Specifically, please refer to Figure 2 and Figure 3 , in Figure 3In the embodiment, the origin represents the selected grain, for example, when the division divisor calculation is 3, then every 3 grids are divided on the X-axis and Y-axis of the wafer to obtain the actual number of blocks to be transmitted. It should be noted that there may be a small error between the actual block data amount transmitted from the wafer according to the division divisor and the expected block data amount to be transmitted, for example, the expected block data amount to be transmitted is 90, the division divisor is 3, and every 3 grids are divided on the X-axis and Y-axis, and the actual block data amount is calculated to be 86. The actual block data amount transmitted is close to the expected block data amount to be transmitted, and does not affect the analysis result.

[0037] S400, obtaining the test data of one of the grains on the block to be transmitted and sending the test data to the design technology collaborative optimization system for analysis.

[0038] Specifically, the design technology collaborative optimization system is a system capable of performing data analysis on the measurement data of the input wafer. By analyzing the feature distribution of each region on the wafer, the improvement direction of the wafer can be obtained. After the block division of the wafer is completed, the coordinate values and measurement values of the grains on each block to be transmitted are taken as the representative coordinate values and measurement values of the corresponding block to be transmitted and sent to the design technology collaborative optimization system for data analysis to complete the test of the wafer.

[0039] In the above technical solution, the present application can automatically calculate a suitable block division divisor to automatically realize the block division of the wafer. Compared with the traditional scheme of manually planning the division divisor on the wafer (the working staff needs to plan the division divisor on the wafer by himself, that is, the working staff needs to repeatedly try multiple division methods to calculate the corresponding block data amount to find the division divisor close to the expected block data amount to be transmitted, which is extremely low in efficiency), the efficiency of block division is greatly improved. In this way, the present application only sends the measurement values of the grains representing the blocks in the wafer to the design technology collaborative optimization system for analysis, which can reduce the data transmission amount and the operation processing burden of the design technology collaborative optimization system while ensuring the detection of the feature distribution of the wafer.

[0040] In some embodiments, the step of obtaining the division divisor according to the to-be-transmitted data amount and the expected block data amount to be transmitted comprises: S210, square root of the ratio of the to-be-transmitted data amount and the expected block data amount to be transmitted; S220, obtaining the division divisor by taking the value obtained after the square root as an upper value.

[0041] In the embodiment, when the division divisor is calculated, the expression of the division divisor is: .

[0042] wherein, ROUNDUP means rounding up, for example, when the value obtained by squaring the ratio of the amount of data to be transmitted to the expected amount of data to be transmitted is between 2 and 3, the value is 2.31, then rounding up to 3, so that the block data obtained by division is closer to the expected amount of data to be transmitted, that is, the block data obtained after rounding up is more than that without rounding up, so that the detection of wafer feature distribution in the design technology collaborative optimization system is more accurate.

[0043] In some embodiments, the step of dividing the wafer according to the division divisor to obtain the number of blocks to be transmitted comprises: S310, dividing the wafer along the transverse direction and the longitudinal direction of the wafer with the division divisor; wherein the division divisor represents the number of grids to be divided on the wafer.

[0044] In this embodiment, the X-axis direction and the Y-axis direction of the wafer are taken as the transverse direction and the longitudinal direction of the wafer, for example, when the division divisor is calculated to be 4, then divide every 4 grids on the X-axis and Y-axis of the wafer to obtain the number of blocks to be actually transmitted.

[0045] In some embodiments, the step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis comprises: S410, obtaining the measurement value of the die at the same position of each block to be transmitted, and taking the coordinates of the die and the measurement value as the representative value and the representative coordinates of the block to be transmitted; S420, sending the measurement value of the die at the same position of each block to be transmitted to the design technology collaborative optimization system.

[0046] In this embodiment, after completing the block division of the wafer, the measurement value of the die at the same position of each block is directly taken, and then the measurement value of each block is sent to the design technology collaborative system. In this embodiment, the die at the same position of each block is directly taken, without any calculation, which can reduce the computing power and power consumption. It should be noted that for the blocks at the edge of the wafer, if there is no die at the same position as other wafers on the wafer, the measurement value of the die at the same position is taken as close as possible, as shown in Figure 4 .

[0047] In some embodiments, the step of obtaining the test data of one of the dies on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis comprises: S410, obtaining the measurement value of the die on the block to be transmitted and performing average processing to obtain the average measurement value; S420, assign the measurement average value to the coordinates of the grain in the center of the block to be transmitted, and take the coordinates of the center grain and the measurement value as the representative value and representative coordinates of the block to be transmitted.

[0048] In the present embodiment, please combine Figure 5 , sum the measurement data of the grains of all the divided blocks, and then calculate the measurement average value. Assign the calculated measurement average value to the coordinates of the grain in the center, and take the coordinates of the center grain and the measurement value as the representative value of the coordinates and measurement value of the corresponding block. In this way, the test data sent to the design technology collaborative optimization system is more accurate in analyzing the feature distribution of the wafer.

[0049] In some embodiments, the step of obtaining the test data of one of the grains on the block to be transmitted and sending the test data to the design technology collaborative optimization system for analysis further comprises: S430, screen the grains on each block to be transmitted to screen out valid grains; S440, if the grains in the block to be transmitted are all abnormal grains, the test data of the block with all abnormal grains is not transmitted to the design technology collaborative optimization system.

[0050] In the present embodiment, please combine Figure 6 with Figure 7 , in Figure 6 with Figure 7 , the origin represents the selected grain, and the rectangle represents the abnormal grain. Before testing the wafer, the integrated circuit automatic test machine detects the grains on the wafer and distinguishes valid grains and abnormal grains one by one. After dividing the wafer into blocks, the validity of the grains on each block is detected. When a certain grain is directly selected for detection, if the selected grain is an abnormal grain, a nearby grain is selected as the representative grain of the corresponding block. If all the grains of all the blocks are abnormal, the corresponding block is not included in the detection range. When the measurement value of the grain is averaged and then assigned to the center grain of the block, the abnormal grain is excluded before the average calculation of the measurement value, and then the coordinates of the center grain of the block are assigned as the representative value and representative coordinates of the corresponding block.

[0051] In some embodiments, as Figure 8 shown, the present application also provides a wafer test data transmission device, which comprises: An acquisition unit is configured to acquire the amount of data to be transmitted for each wafer and the amount of data to be transmitted for each block. Details are described in an embodiment of a wafer test data transmission method, which will not be described here.

[0052] A computing unit is configured to obtain a division divisor according to the to-be-transmitted data amount and the expected transmission block data amount. Details are described in the embodiments of the wafer test data transmission method, which are not described herein again.

[0053] A block division unit is configured to divide the wafer into blocks according to the division divisor and obtain the number of blocks to be transmitted. Details are described in the embodiments of the wafer test data transmission method, which are not described herein again.

[0054] A data sending unit is configured to obtain test data of one die on the block to be transmitted and send the test data to a design technology collaborative optimization system for analysis. Details are described in the embodiments of the wafer test data transmission method, which are not described herein again.

[0055] In some embodiments, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is used to implement the steps in the following method when executed by the processor. S100, obtaining a to-be-transmitted data amount and an expected transmission block data amount of each wafer; S200, obtaining a division divisor according to the to-be-transmitted data amount and the expected transmission block data amount; S300, dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted; S400, obtaining test data of one die on the block to be transmitted and sending the test data to a design technology collaborative optimization system for analysis.

[0056] In some embodiments, the present application further provides a storage medium storing a computer program, and the computer program is used to implement the steps in the following method when executed by a processor. S100, obtaining a to-be-transmitted data amount and an expected transmission block data amount of each wafer; S200, obtaining a division divisor according to the to-be-transmitted data amount and the expected transmission block data amount; S300, dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted; S400, obtaining test data of one die on the block to be transmitted and sending the test data to a design technology collaborative optimization system for analysis.

[0057] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, database or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0058] In summary, the wafer test data transmission method and device, computer equipment and storage medium provided by the present application have the following beneficial effects: The wafer can be automatically divided and processed, and only the measurement value of the die representing the block in the wafer is sent to the design technology collaborative optimization system for analysis, so that the detection of the wafer feature distribution can be ensured while the processing burden of the design technology collaborative optimization system is reduced. Before testing, the effective die of the wafer is screened, so that the measurement value of the abnormal die will not be input to the design technology collaborative optimization system for analysis, and the design technology collaborative optimization system does not need to detect the abnormal state of the die, which can further reduce the processing burden of the design technology collaborative optimization system.

[0059] It should be understood that the application of the present application is not limited to the above examples, and those skilled in the art can make improvements or changes according to the above description, and all these improvements and changes shall belong to the protection scope of the appended claims of the present application.

Claims

1. A wafer test data transmission method, characterized in that, include: Obtain the amount of data to be transmitted for each wafer and the expected amount of data in the block to be transmitted; Take the square root of the ratio of the amount of data to be transmitted to the amount of data in the block to be transmitted. The divisor is obtained by taking the square root and rounding it up. The wafer is divided into blocks according to the division divisor to obtain the number of blocks that need to be transmitted; The test data of one of the chips on the block to be transmitted is obtained and sent to the design technology collaborative optimization system for analysis.

2. The wafer test data transmission method according to claim 1, characterized in that, The step of dividing the wafer into blocks according to the division divisor and obtaining the number of blocks to be transmitted includes: The wafer is divided into blocks along the transverse and longitudinal directions using the division divisor; wherein the division divisor represents the number of grids to be divided on the wafer.

3. The wafer test data transmission method according to claim 1, characterized in that, The steps of acquiring test data of one of the chips on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis include: Obtain the measurement value of the die at the same location in each block that needs to be transmitted, and use the coordinates of the die and the measurement value as the representative value and representative coordinates of the block that needs to be transmitted. The measurement values ​​of the same location of the die in each block that needs to be transmitted are sent to the design technology collaborative optimization system.

4. The wafer test data transmission method according to claim 1, characterized in that, The steps of acquiring test data of one of the chips on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis include: Obtain the measurement values ​​of the dies on the block to be transmitted and perform averaging to obtain the average measurement value; The average measurement value is assigned to the coordinates of the center grain of the block to be transmitted, and the coordinates of the center grain and the measurement value are used as the representative value and representative coordinates of the block to be transmitted.

5. The wafer test data transmission method according to claim 1, characterized in that, The step of acquiring test data of one of the chips on the block to be transmitted and sending it to the design technology collaborative optimization system for analysis also includes: The dies on each block that needs to be transmitted are screened to select the valid dies; If all the dies in the block to be transmitted are abnormal dies, the test data of the block containing all abnormal dies will not be transmitted to the design technology collaborative optimization system.

6. The wafer test data transmission method according to claim 1, characterized in that, The expression for the divisor is: 。 7. A wafer testing data transmission device, characterized in that, include: The acquisition unit is used to acquire the amount of data to be transmitted for each wafer and the amount of data in the expected block to be transmitted. The calculation unit is used to take the square root of the ratio of the amount of data to be transmitted to the amount of data in the block to be transmitted, and then take the value of the square root upward to obtain the partition divisor. A block partitioning unit is used to partition the wafer into blocks according to the partitioning divisor and obtain the number of blocks to be transmitted. The data transmission unit is used to acquire test data of one of the chips on the block to be transmitted and send it to the design technology collaborative optimization system for analysis.

8. A computer device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program, which, when executed by the processor, is used to implement the steps in the wafer test data transmission method as described in any one of claims 1-6.

9. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it is used to implement the steps in the wafer test data transmission method as described in any one of claims 1-6.

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