Semiconductor device

Abstract

The present disclosure provides a semiconductor device, relates to the technical field of semiconductor chip, and aims to solve the problem of uneven electric field distribution of the semiconductor device; the semiconductor device comprises a substrate, an epitaxial layer, a source, a drain, a gate and an electric field modulation region; the epitaxial layer is arranged on the substrate; the source, the drain and the gate are embedded in the epitaxial layer; the electric field modulation region is arranged on the side of the epitaxial layer away from the substrate and embedded in the epitaxial layer; the electric field modulation region comprises a first electric field modulation sub-region and a second electric field modulation sub-region connected with each other, the second electric field modulation sub-region comprises a first part and a second part; the first part is located on the side of the first electric field modulation sub-region away from the substrate, and the second part is located on the side of the first electric field modulation sub-region away from the drain; the first part and the second part are connected, the doping type of the first electric field modulation sub-region is the same as the doping type of the epitaxial layer, and the doping type of the second electric field modulation sub-region is different from the doping type of the epitaxial layer; the doping type is P-type doping and N-type doping.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor device. BACKGROUND

[0002] In a semiconductor device, uneven electric field distribution can cause local electric field to be too high, thereby causing problems such as breakdown or performance degradation of the semiconductor device. SUMMARY

[0003] Embodiments of the present disclosure provide a semiconductor device, aiming at solving the problem of uneven electric field distribution of the semiconductor device.

[0004] To achieve the above object, embodiments of the present disclosure adopt the following technical solutions:

[0005] A semiconductor device is provided. The semiconductor device comprises a substrate, an epitaxial layer, a source, a drain, a gate and an electric field modulation region.

[0006] The epitaxial layer is arranged on the substrate. The source, the drain and the gate are arranged on a side of the epitaxial layer away from the substrate. The source and the drain are embedded in the epitaxial layer, and the gate is located between the source and the drain.

[0007] The electric field modulation region is arranged on a side of the epitaxial layer away from the substrate and embedded in the epitaxial layer. The electric field modulation region comprises a first electric field modulation sub-region and a second electric field modulation sub-region. The second electric field modulation sub-region comprises a first part and a second part. The first part is located on a side of the first electric field modulation sub-region away from the substrate, and the second part is located on a side of the first electric field modulation sub-region away from the drain. The first part and the second part are connected. The doping type of the first electric field modulation sub-region is the same as the doping type of the epitaxial layer, and the doping type of the second electric field modulation sub-region is different from the doping type of the epitaxial layer. The doping type is P-type doping and N-type doping.

[0008] The semiconductor device provided by the above embodiments of the present disclosure forms an alternating arrangement of charge interfaces with different doping characteristics in the channel region by arranging the second electric field modulation sub-region to cover the surface of the first electric field modulation sub-region away from the substrate and arranging the second electric field modulation sub-region to have a doping type different from that of the epitaxial layer, so that a space charge region (interface potential difference) is formed at the interface, such as a PN junction, and a built-in electric field is generated at the charge interface, thereby introducing a new electric field distribution at the surface of the electric field modulation region to adjust the surface electric field distribution of the semiconductor device, so that the electric field lines are bent at the interface to avoid the concentration of the electric field on the surface of the region of the drain and the region of the source, thereby achieving uniform distribution of the entire surface electric field of the semiconductor device and significantly improving the breakdown voltage capability of the semiconductor device. Moreover, the first electric field modulation sub-region has the same doping type as the epitaxial layer (for example, both are N-type or P-type), which can ensure the electrical continuity between the first electric field modulation sub-region, the second electric field modulation sub-region and the epitaxial layer, optimize the flow of carriers in the semiconductor device, increase the effective carrier density of the overall epitaxial layer, and reduce the on-resistance of the semiconductor device. Moreover, the first part is located on the side of the first electric field modulation sub-region away from the substrate, i.e., closer to the gate; and the second part is located on the side of the first electric field modulation sub-region away from the drain, i.e., closer to the region of the source, which can improve the electric field gradient between the drain region and the electric field modulation region and optimize the electric field distribution between the drain region and the electric field modulation region, thereby reducing the risk of breakdown caused by a higher electric field.

[0009] In some embodiments, the ion doping concentration of the second electric field modulation sub-region is greater than the ion doping concentration of the first electric field modulation sub-region.

[0010] In some embodiments, the ion doping concentration of the first electric field modulation sub-region is greater than the ion doping concentration of the epitaxial layer.

[0011] In some embodiments, the semiconductor device includes a plurality of electric field modulation regions arranged along a first direction, the first direction being a direction from the source to the drain. In any two adjacent electric field modulation regions, the electric field modulation region closer to the source is the first electric field modulation region, and the electric field modulation region closer to the drain is the second electric field modulation region. The first part of the first electric field modulation region and the second part of the second electric field modulation region are shared.

[0012] In some embodiments, the distance from the surface of the plurality of first electric field modulation sub-regions away from the substrate to the surface of the second electric field modulation sub-region gradually decreases along the first direction.

[0013] In some embodiments, the distance from the surface of the plurality of first electric field modulation sub-regions close to the substrate to the surface of the second electric field modulation sub-region gradually decreases along the first direction.

[0014] In some embodiments, the interface between the plurality of first electric field modulation sub-regions and the second electric field modulation sub-region has a stepped morphology.

[0015] In some embodiments, the interface between the plurality of first electric field modulation sub-regions and the epitaxial layer has a stepped morphology.

[0016] In some embodiments, the ion doping concentration of the plurality of first electric field modulation sub-regions gradually increases along the first direction.

[0017] In some embodiments, the second electric field modulation sub-region further comprises a third part, the third part is located on the side of the first electric field modulation sub-region close to the drain, and the third part has a spacing with the drain; the third part is connected with the first part.

[0018] In some embodiments, the semiconductor device comprises a plurality of electric field modulation regions, the plurality of electric field modulation regions are arranged along a first direction, the first direction is a direction from the source to the drain. In any two adjacent electric field modulation regions, the electric field modulation region closer to the source is a first electric field modulation region, and the electric field modulation region closer to the drain is a second electric field modulation region; a third part of the first electric field modulation region is shared with a second part of the second electric field modulation region.

[0019] In some embodiments, the ion doping concentration of the plurality of first electric field modulation sub-regions gradually increases along the first direction.

[0020] In some embodiments, the size of the plurality of first electric field modulation sub-regions gradually increases along the first direction.

[0021] In some embodiments, the number of the first electric field modulation sub-regions is one; the ratio of the size of the first electric field modulation sub-region along the first direction to the size of the electric field modulation region along the first direction ranges from 0.1 to 0.9; the first direction is a direction from the source to the drain.

[0022] In some embodiments, the number of the first electric field modulation sub-regions is a plurality, and the plurality of first electric field modulation sub-regions are arranged along the first direction; the ratio of the sum of the sizes of the plurality of first electric field modulation sub-regions along the first direction to the size of the electric field modulation region along the first direction ranges from 0.1 to 0.9. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size of the product, the actual flow of the method, the actual time sequence of the signal, etc. involved in the embodiments of the present disclosure.

[0024] Figure 1 A structural schematic diagram of an electronic device according to some embodiments of the present disclosure;

[0025] Figure 2 A structural schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0026] Figure 3 A structural schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0027] Figure 4 A structural schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0028] Figure 5 A structural schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0029] Figure 6 A structural schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0030] Figure 7 A structural schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 8 A structural schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0032] Figure 9 A structural schematic diagram corresponding to each step in a preparation method of a composite substrate according to Embodiment 1 of the present disclosure;

[0033] Figure 10 A structural schematic diagram corresponding to each step in a preparation method of a composite substrate according to Embodiment 2 of the present disclosure;

[0034] Figure 11 A structural schematic diagram corresponding to each step in a preparation method of a composite substrate according to Embodiment 3 of the present disclosure. DETAILED DESCRIPTION

[0035] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present disclosure.

[0036] In the description of the present disclosure, it needs to be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0037] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise", "comprising", and the like are to be construed in an open, inclusive and a non-exclusive sense; that is, as "comprising, but not limited to." In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary", or "some examples" are intended to mean that a particular feature, structure, material, or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily indicate a reference to the same embodiment or example. In addition, a particular feature, structure, material or characteristic can be included in any suitable manner in any one or more embodiments or examples.

[0038] Hereinafter, in the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0039] In addition, the use of "based on" means open and inclusive, as a process, step, calculation or other action that is "based on" one or more conditions or values can be based on additional conditions or values in practice.

[0040] As used herein, "about", "approximately" or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, wherein the acceptable range of deviation is determined by a person of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0041] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized exemplary illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the precise shapes illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded characteristics. Thus, the regions illustrated in the drawings are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0042] As used herein, the term "substrate" refers to a material on which a subsequent layer of material can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire substrate.

[0043] The following explains the technical terms in the embodiments of the present application as follows:

[0044] Semiconductor: Semiconductor is a material whose electrical conductivity at room temperature is intermediate between that of a conductor and an insulator; wherein semiconductor includes intrinsic semiconductor and impurity semiconductor. Pure semiconductor without impurities and defects, whose internal electron and hole concentration are equal, is called intrinsic semiconductor. Semiconductor doped with a certain amount of impurities is called impurity semiconductor or extrinsic semiconductor. Among them, the impurities doped in the impurity semiconductor can improve the conductivity of the intrinsic semiconductor when a certain concentration of carriers (such as holes or electrons, wherein the impurity semiconductor doped with impurities that provide electrons (such as pentavalent phosphorus element) is also called electron-type semiconductor or N (negative) type semiconductor, and the impurity semiconductor doped with impurities that provide holes (such as trivalent boron element) is also called hole-type semiconductor or P (positive) type semiconductor) is provided. Generally, the greater the carrier concentration, the lower the resistivity of the semiconductor, and the better the conductivity. In the embodiments of the present application, this type of impurity semiconductor is also called conductive type semiconductor, for example, conductive silicon carbide material, doped impurities are nitrogen N, boron B, aluminum Al, etc. In addition, when the impurities doped in the impurity semiconductor can impurity compensate the impurity semiconductor, the donor electrons just fill the acceptor energy level, but cannot provide electrons and holes to the conduction band and valence band, so that the semiconductor material with a wide band gap has a resistivity similar to that of an insulator. For example, in the embodiments of the present application, transition metals are doped into silicon carbide material to realize impurity compensation of silicon carbide material, thereby improving the resistivity of silicon carbide material. This type of impurity semiconductor is also called semi-insulating semiconductor or semi-insulating body, or has semi-insulating body characteristics.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, "first", "second", and the like do not limit the quantity and order.

[0046] In addition, in the present application, the orientation terms such as "upper", "lower", and the like are defined with respect to the orientation in which the components in the drawings are placed, and it should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can change accordingly according to the change of the orientation in which the components are placed in the drawings.

[0047] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present relevant concepts in a concrete manner.

[0048] The technical solutions of the present application can be applied to electronic devices, which are different types of user devices or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and vehicle-mounted devices; the electronic devices can also be network devices such as base stations. The electronic device can also be a device such as a power amplifier used in the above electronic devices. The embodiments of the present application do not specially limit the specific form of the above electronic devices.

[0049] As shown in Figure 1 The present application provides an electronic device 1000. The electronic device 1000 can be a fast charging, uninterruptible power supply (UPS), power motor, and the like.

[0050] With reference to Figure 1The electronic device 1000 includes a chip 1001 and a circuit board 1002, the chip 1001 and the circuit board 1002 are electrically connected, and the circuit board 1002 converts an external power supply into a voltage or a current required for the chip 1001 to work.

[0051] Exemplarily, the circuit board 1002 can include a printed circuit board (PCB) or the like.

[0052] Exemplarily, the circuit board 1002 can include a plurality of conductive layers. The plurality of conductive layers in the circuit board 1002 can be separated from each other by a dielectric layer.

[0053] Embodiments of the present disclosure provide a chip 1001. The chip 1001 includes a semiconductor device.

[0054] It can be understood that the chip 1001 is a part of an electronic device and is a carrier of an integrated circuit. The semiconductor device is a device with electrical conductivity between a conductor and an insulator, which can be used to make rectifiers, diodes, transistors, integrated circuits, and the like.

[0055] Embodiments of the present disclosure provide a semiconductor device 300. As shown in Figure 2 the semiconductor device 300 includes a substrate 301, an epitaxial layer 303, a source 306, a drain 307, a gate 311, and an electric field modulation region 390.

[0056] The epitaxial layer 303 is disposed on the substrate 301.

[0057] The source 306, the drain 307, and the gate 311 are disposed on a side of the epitaxial layer 303 away from the substrate 301. The source 306 and the drain 307 are embedded in the epitaxial layer 303, and the gate 311 is located between the source 306 and the drain 307.

[0058] The substrate 301 serves as a base layer of the semiconductor device 300 and provides a support structure.

[0059] Exemplarily, the material of the substrate 301 can be silicon carbide.

[0060] The epitaxial layer 303 is a semiconductor layer grown on the substrate 301 and is used to form an active region of the semiconductor device 300. The epitaxial layer 303 can provide a semiconductor material with excellent crystal quality and is used to form the source 306, the drain 307, and the gate 311 region to control the current flow path and adjust the performance of the semiconductor device 300.

[0061] Exemplarily, as Figure 3As shown, an epitaxial sublayer 302 can be disposed between the substrate 301 and the epitaxial layer 303. The conductivity type of the epitaxial sublayer 302 is opposite to that of the substrate 301; the conductivity type of the epitaxial layer 303 is opposite to that of the epitaxial sublayer 302. The doping type is P-type doping and N-type doping. For example, the substrate 301 is N-type doped, the epitaxial sublayer 302 is P-type doped, and the epitaxial layer 303 is N-type doped. Alternatively, the substrate 301 is P-type doped, the epitaxial sublayer 302 is N-type doped, and the epitaxial layer 303 is P-type doped.

[0062] The source 306 serves as the current input terminal, introducing charge carriers into the semiconductor device 300 and embedding them in the epitaxial layer 303, which helps to form good electrical contact.

[0063] The drain 307 serves as the current output terminal, allowing charge carriers to flow to the external circuit through the epitaxial layer. Embedded in the epitaxial layer, it facilitates the flow of charge carriers.

[0064] In some examples, such as Figure 3 As shown, the semiconductor device 300 further includes a well region 304 and a body region 305, embedded in the epitaxial layer 303. The well region 304 covers the surface of the body region 305 near the substrate 301, the surface of the source 306 near the substrate 301, and the surface of the source 306 near the drain 307. The body region 305 is located on the side of the source 306 away from the drain 307 and is in contact with the source 306.

[0065] Well region 304 is used to control the carrier type and concentration, forming a shallow channel (N-type or P-type), with the opposite conductivity type to that of epitaxial layer 303. Body region 305 can adjust and control the threshold voltage of semiconductor device 300, and the conductivity type of body region 305 is the same as that of well region 304.

[0066] The gate 311 is located between the source 306 and the drain 307. By applying voltage, the formation and disconnection of the channel are controlled, the carrier flow across the source 306 and the drain 307 is adjusted, and the conduction and cutoff of the channel are controlled to achieve switching or amplification.

[0067] In some examples, such as Figure 3 As shown, the gate oxide layer 310 is located between the gate 311 and the epitaxial layer 303. The gate oxide layer 310 serves as an insulating layer between the gate 311 and the channel, preventing current from directly entering the channel through the gate 311.

[0068] The semiconductor device 300 is a laterally diffused metal-oxide-semiconductor (LDMOS). Unlike the vertical structure of a typical MOSFET, LDMOS employs a lateral double-diffusion structure. This structure results in a lower drain current density (307) and thus allows it to withstand higher voltages and power. LDMOS devices consist of N-type and P-type materials, with the N-type material sandwiched between two P-type materials. Electrons move within the N-type region, enabling conductivity. However, this process suffers from uneven electric field distribution. For example, differences in channel and drift region lengths lead to varying local electric fields, resulting in uneven electric field gradients. Furthermore, variations in doping concentration and incomplete diffusion during the double-diffusion process can cause concentrated electric fields, forming localized electric field spikes.

[0069] Based on this, embodiments of the present disclosure provide a semiconductor device 300. For example... Figure 2 As shown, the semiconductor device 300 further includes an electric field modulation region 390. The electric field modulation region 390 is disposed on the side of the epitaxial layer 303 away from the substrate 301 and is embedded in the epitaxial layer 303. The electric field modulation region 390 includes a first electric field modulation sub-region 391 and a second electric field modulation sub-region 392. The second electric field modulation sub-region 392 includes a first portion 392A and a second portion 392B. The first portion 392A is located on the side of the first electric field modulation sub-region 391 away from the substrate 301, and the second portion 392B is located on the side of the first electric field modulation sub-region 391 away from the drain 307. The first portion 392A and the second portion 392B are connected.

[0070] The first electric field modulation sub-region 391 has the same doping type as the epitaxial layer 303, while the second electric field modulation sub-region 392 has a different doping type than the epitaxial layer 303. The doping types are P-type and N-type doping.

[0071] For example, if the epitaxial layer 303 is N-type doped and the first electric field modulation sub-region 391 is N-type doped, then the second electric field modulation sub-region 392 is P-type doped. Similarly, if the epitaxial layer 303 is P-type doped and the first electric field modulation sub-region 391 is P-type doped, then the second electric field modulation sub-region 392 is N-type doped.

[0072] The electric field modulation region 390 is used to adjust the surface electric field distribution in the semiconductor device 300. By setting the second electric field modulation sub-region 392 to cover the surface of the first electric field modulation sub-region 391 away from the substrate 301, and the second electric field modulation sub-region 392 is doped with a type different from the type of the epitaxial layer 303, so that the semiconductor device 300 forms an alternating arrangement of charge interfaces with different doping characteristics in the channel region, and the interface forms a space charge region (interface potential difference), such as a PN junction, and the charge interface generates a built-in electric field, thereby introducing a new electric field distribution on the surface of the electric field modulation region 390, adjusting the surface electric field distribution of the semiconductor device 300, bending the electric field lines at the interface, avoiding the concentration of electric field on the surface of the region of the drain 307 and the region of the source 306, thereby achieving uniform distribution of the entire surface electric field of the semiconductor device 300, and significantly improving the breakdown voltage capability of the semiconductor device 300; and the doping type of the first electric field modulation sub-region 391 is the same as that of the epitaxial layer 303 (for example, both are N-type or P-type), which can ensure the electrical continuity between the first electric field modulation sub-region 391, the second electric field modulation sub-region 392 and the epitaxial layer 303, optimize the flow of carriers in the semiconductor device 300, increase the effective carrier density of the overall epitaxial layer 303, and reduce the on-resistance of the semiconductor device 300.

[0073] Furthermore, the first part 392A is located on the side of the first electric field modulation sub-region 391 away from the substrate 301, i.e. closer to the gate 311; the second part 392B is located on the side of the first electric field modulation sub-region 391 away from the drain 307, closer to the region of the source 306, which can improve the electric field gradient between the region of the drain 307 and the electric field modulation region 390, and optimize the electric field distribution between the region of the drain 307 and the electric field modulation region 390, thereby reducing the risk of breakdown caused by high electric field.

[0074] In some embodiments, the ion doping concentration of the second electric field modulation sub-region 392 is greater than the ion doping concentration of the first electric field modulation sub-region 391.

[0075] It can be understood that the ion doping concentration of the second electric field modulation sub-region 392 is greater than that of the first electric field modulation sub-region 391, so that the second electric field modulation sub-region 392 generates a greater space charge density, and a stronger built-in electric field is formed at the interface between the first electric field modulation sub-region 391 and the second electric field modulation sub-region 392, which can more effectively adjust the electric field distribution, slow down or adjust the transmission of external voltage in the semiconductor device 300, reduce the local electric field peak value, and avoid forming a sharp peak in the local area, thereby improving the breakdown voltage of the semiconductor device 300. Furthermore, the higher doping concentration in the second electric field modulation sub-region 392 can increase the carrier concentration and the number of activated carriers, making it easier for current to pass through, thereby reducing the specific on-resistance of the semiconductor device 300.

[0076] In some embodiments, the ion doping concentration of the first electric field modulation sub-region 391 is greater than the ion doping concentration of the epitaxial layer 303.

[0077] It can be understood that, on the one hand, the ion doping concentration of the first electric field modulation sub-region 391 is higher than the ion doping concentration of the epitaxial layer 303, so that the first electric field modulation sub-region 391 can strengthen the electric field regulation effect, improve the electric field distribution, and make the carrier injection and collection smoother, thereby reducing the specific on-resistance of the semiconductor device 300; on the other hand, in the preparation process of the semiconductor device 300, the first electric field modulation sub-region 391 with a higher ion doping concentration is ion implanted after the higher epitaxial layer 303 with a lower ion doping concentration is ion implanted, which is more feasible in the preparation process, thereby simplifying the process and improving the reliability of the preparation of the semiconductor device 300.

[0078] In some embodiments, the electric field modulation region 390 and the drain 307 have a spacing therebetween.

[0079] It can be understood that, by setting a spacing between the electric field modulation region 390 and the drain 307, unnecessary current leakage or stray current can be reduced, the voltage withstanding performance of the semiconductor device 300 can be improved, and uncontrolled electric field interference can be prevented; the electric field distribution inside the semiconductor device 300 can also be adjusted to avoid the electric field from concentrating in a local area, reduce the risk of breakdown, reduce the stress concentration of the semiconductor device 300 in a high-voltage working state, and improve the reliability and life of the semiconductor device 300.

[0080] In some embodiments, the second part 392B of the second electric field modulation sub-region 392 is coplanar with the surface of the substrate 301 and the surface of the first electric field modulation sub-region 391 close to the surface of the substrate 301.

[0081] It can be understood that, on the one hand, the second electric field modulation sub-region 392 and the first electric field modulation sub-region 391 of the electric field modulation region 390 can be arranged on the same plane close to the surface of the substrate 301 without height difference, which helps to form continuous and smooth electric field lines between the electric field modulation regions 390 and avoid local peaks; on the other hand, the coplanar structure is conducive to the control of flatness in the preparation process of the semiconductor device 300, helps to realize the consistency of the thin layer process, and improves the matching of the electric field and the structure of the semiconductor device 300.

[0082] In some embodiments, the first part 392A of the second electric field modulation sub-region 392 is coplanar with the surface of the drain 307 and the surface of the first electric field modulation sub-region 391 close to the surface of the drain 307.

[0083] It can be appreciated that the above arrangement can make the first portion 392A of the second electric field modulation sub-region 392 close to the surface of the drain 307 in the same plane as the surface of the drain 307 close to the first electric field modulation sub-region 391, which is helpful to achieve uniform electric field between the drain 307 and the electric field modulation region 390, to make the electric field lines smoothly transition between the drain 307 and the electric field modulation region 390, and to make the electric field intensity change gently from the drain 307 to the electric field modulation region 390, which is helpful to achieve consistent charge regulation in the entire modulation region 390.

[0084] In some embodiments, as shown in FIG. 3, the semiconductor device 300 includes a plurality of electric field modulation regions 390, and the plurality of electric field modulation regions 390 are arranged along a first direction X, where the first direction X is a direction in which the source 306 points to the drain 307. Figure 4

[0085] For example, the semiconductor device 300 can include 2, 3, 4, or 5 electric field modulation regions 390, in which case the first electric field modulation sub-region 391 can be 2, 3, 4, or 5, and the second electric field modulation sub-region 392 can be 2, 3, 4, or 5, for example, as shown in FIG. 3. Figure 4 For example, as shown in one example in which the semiconductor device 300 includes 3 electric field modulation regions 390, the first electric field modulation sub-region 391 can include a first sub-region 3911, a second sub-region 3912, and a third sub-region 3913.

[0086] In any two adjacent electric field modulation regions 390, the electric field modulation region 390 closer to the source 306 is the first electric field modulation region 3901, and the electric field modulation region 390 closer to the drain 307 is the second electric field modulation region 3902. The first portion 392A of the first electric field modulation region 3901 is shared with the second portion 390B of the second electric field modulation region 3902.

[0087] For example, as shown in FIG. 3, the semiconductor device 300 includes a plurality of electric field modulation regions 390, and the plurality of electric field modulation regions 390 are arranged along a first direction X, where the first direction X is a direction in which the source 306 points to the drain 307. Figure 4 ​As shown, in two adjacent electric field modulation regions 390, for example, the first electric field modulation sub-region 391 in the first electric field modulation region 3901 is the first sub-region 3911, and the first electric field modulation sub-region 391 in the second electric field modulation region 3902 is the second sub-region 3912; the first part 392A of the second electric field modulation sub-region 392 located on the side of the first sub-region 3911 away from the substrate 301 is shared with the second part 392B of the second electric field modulation sub-region 392 located on the side of the second sub-region 3912 away from the drain 307. For example, the first electric field modulation sub-region 391 in the second electric field modulation region 3902 is the second sub-region 3912; the first electric field modulation sub-region 391 in the third electric field modulation region 3903 is the third sub-region 3913; the first part 392A of the second electric field modulation sub-region 392 located on the side of the second sub-region 3912 away from the substrate 301 is shared with the second part 392B of the second electric field modulation sub-region 392 located on the side of the second sub-region 3912 away from the drain 307.

[0088] Understandably, the multiple first electric field modulation sub-regions 391 can achieve the superposition of local modulations, and the multiple first electric field modulation sub-regions 391 are arranged along the direction from the source 306 to the drain 307, which helps to gradually guide the transport of charge carriers, reduce electric field abrupt changes, and smooth the flow of charge carriers; and, through the position setting of the multiple first electric field modulation sub-regions 391 and the second electric field modulation sub-regions 392, a gentler electric field gradient can be formed in the epitaxial layer 303 surface region far away from the substrate 301, reducing electric field distortion and local sharp electric fields, and further making the electric field distribution more uniform.

[0089] In some embodiments, the distance between the surface of the plurality of first electric field modulator regions 391 away from the substrate 301 and the surface of the second electric field modulator region 392 away from the substrate 301 gradually decreases along the first direction X.

[0090] For example, such as Figure 4 As shown, when there are three first electric field modulation sub-regions 391, the distance from the surface of the first sub-region 3911 away from the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L1; the distance from the surface of the second sub-region 3912 away from the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L2; ​​the distance from the surface of the third sub-region 3913 away from the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L3; and L1 > L2 > L3.

[0091] Alternatively, in some embodiments, the distance between the surface of the plurality of first electric field modulator regions 391 near the substrate 301 and the surface of the second electric field modulator region 392 away from the substrate 301 gradually decreases along the first direction X.

[0092] For example, such asFigure 5 As shown, when the plurality of first electric field modulation sub-regions 391 is 3, the distance from the surface of the substrate 301 to the surface of the second electric field modulation sub-region 392 of the first sub-region 3911 is L1 * ; the distance from the surface of the substrate 301 to the surface of the second electric field modulation sub-region 392 of the second sub-region 3912 is L2 * ; the distance from the surface of the substrate 301 to the surface of the second electric field modulation sub-region 392 of the third sub-region 3913 is L3 * ; and L1 * > L2 * > L3 * .

[0093] It can be understood that the above arrangement can make the electric field gradually transition between the plurality of first electric field modulation sub-regions 391 along the first direction X, ensure smooth transmission of carriers along the first direction X, reduce reverse drift and stagnation, avoid electric field mutation or distortion, form smooth electric field change, realize multi-level modulation, and further make the electric field distribution more uniform.

[0094] In some embodiments, the plurality of first electric field modulation sub-regions 391 and the interface of the first electric field modulation sub-region 391 have a stepped morphology.

[0095] In other words, in some embodiments, the plurality of first electric field modulation sub-regions 391 and the interface of the epitaxial layer 303 have a stepped morphology.

[0096] It can be understood that the above arrangement can make the plurality of first electric field modulation sub-regions 391 further realize multi-level regulation and more smooth electric field distribution.

[0097] In some embodiments, the first part 392A of the second electric field modulation sub-region 392 is close to the surface of the drain 307, and is coplanar with the surface of the first electric field modulation sub-region 391 closest to the drain 307 in the plurality of first electric field modulation sub-regions 391.

[0098] For example, Figure 5 As shown, when the plurality of first electric field modulation sub-regions 391 is 3, the first electric field modulation sub-region 391 closest to the drain 307 in the plurality of first electric field modulation sub-regions 391 is the third sub-region 3913, i.e., the first part 392A of the second electric field modulation sub-region 392 is coplanar with the surface of the third sub-region 3913 close to the drain 307.

[0099] It can be understood that the above arrangement can make the electric field of the semiconductor device 300 in the region close to the drain 307 transition smoothly, avoid the concentration of electric field caused by surface deviation, thereby reducing the risk of breakdown of the semiconductor device 300 and improving the reliability of the semiconductor device 300.

[0100] In some embodiments, the second part 392B of the second electric field modulation sub-region 392 is coplanar with the surface of the substrate 301 close to the first electric field modulation sub-region 391 farthest from the drain 307 in the plurality of first electric field modulation sub-regions 391.

[0101] For example, as shown in FIG. 4, when the plurality of first electric field modulation sub-regions 391 is 3, the first electric field modulation sub-region 391 farthest from the drain 307 in the plurality of first electric field modulation sub-regions 391 is the first sub-region 3911, and the second part 392B of the second electric field modulation sub-region 392 is coplanar with the surface of the substrate 301 close to the first sub-region 3911. Figure 5

[0102] It can be understood that the above arrangement can make the electric field of the semiconductor device 300 in the region close to the substrate 301, help to form a uniform electric field distribution, reduce partial discharge, and achieve gradual regulation of the electric field, reduce sudden changes, and increase the withstand voltage performance of the semiconductor device 300.

[0103] In some embodiments, the ion doping concentration of the plurality of first electric field modulation sub-regions 391 gradually increases along the first direction X.

[0104] For example, as shown in FIG. 4, when the plurality of first electric field modulation sub-regions 391 is 3, the ion doping concentration of the first sub-region 3911 < the ion doping concentration of the second sub-region 3912 < the ion doping concentration of the third sub-region 3913. Figure 5 It can be understood that along the first direction X, the ion doping concentration of the plurality of first electric field modulation sub-regions 391 gradually increases, the conductivity of the semiconductor device 300 is enhanced, and the specific on-resistance of the semiconductor device 300 is reduced.

[0105] In some embodiments, as shown in FIG. 4, the second electric field modulation sub-region 392 further includes a third part 392C. The third part 392C is located on the side of the first electric field modulation sub-region 391 close to the drain 307, and the third part 392C has a spacing from the drain 307. The third part 392C is connected to the first part 392A.

[0106] Figure 6

[0107] ​​​It can be understood that the third part 392C can reduce the electric field peak between the first electric field modulation sub-region 391 and the drain 307, thereby reducing the leakage current, the electric field is more uniform, and the local electric field is not too high; and the third part 392C keeps a distance from the drain 307, which helps to reduce the electric field strength in this area, reduce the risk of breakdown caused by local electric field distortion and high electric field, and improve the voltage withstand capability of the device.

[0108] In some embodiments, the second part 392B of the second electric field modulation sub-region 392 is close to the surface of the substrate 301, the surface of the first electric field modulation sub-region 391 is close to the surface of the substrate 301, and the third part 392C of the second electric field modulation sub-region 392 is close to the surface of the substrate 301 are coplanar.

[0109] It can be understood that the above arrangement can make the second part 392B close to the surface of the substrate 301, the surface of the first electric field modulation sub-region 391 close to the surface of the substrate 301, and the third part 392C of the second electric field modulation sub-region 392 close to the surface of the substrate 301 in the same plane, forming a continuous interface, which helps to form a continuous and smooth electric field distribution, and further makes the electric field distribution more uniform.

[0110] In some embodiments, the semiconductor device 300 includes a plurality of electric field modulation regions 390, and the plurality of electric field modulation regions 390 are arranged along a first direction X, and the first direction X is a direction in which the source 306 points to the drain 307.

[0111] For example, the semiconductor device 300 can include 2, 3, 4, or 5 electric field modulation regions 390, and at this time, the first electric field modulation sub-region 391 can be 2, 3, 4, or 5, and the second electric field modulation sub-region 392 can be 2, 3, 4, or 5, for example, as shown in Figure 7 In one example shown, when including 2 electric field modulation regions 390, the first electric field modulation sub-region 391 includes a first sub-region 3911 and a second sub-region 3912.

[0112] In any two adjacent electric field modulation regions 390, the electric field modulation region 390 closer to the source 306 is the first electric field modulation region 3901, and the electric field modulation region 390 closer to the drain 307 is the second electric field modulation region 3902; the third part 392C of the first electric field modulation region 3901 is shared with the second part 392B of the second electric field modulation region 3902.

[0113] For example, as shown in Figure 7As shown, in two adjacent electric field modulation regions 390, for example, the first electric field modulation sub-region 391 in the first electric field modulation region 3901 is the first sub-region 3911, and the first electric field modulation sub-region 391 in the second electric field modulation region 3902 is the second sub-region 3912; the third part 392C of the second electric field modulation sub-region 392 located on the side of the first sub-region 3911 near the drain 307 is shared with the second part 392B of the second electric field modulation sub-region 392 located on the side of the second sub-region 3912 away from the drain 307.

[0114] Understandably, multiple first electric field modulation sub-regions 391 can achieve the superposition of local modulations, and the multiple first electric field modulation sub-regions 391 are arranged along the direction from the source 306 to the drain 307. That is, multiple third parts 392C are arranged along the direction from the source 306 to the drain 307, which further reduces the electric field spike in the region between the first electric field modulation sub-regions 391 and the drain 307, thereby reducing the leakage current, making the electric field more uniform, avoiding excessively high or low local electric fields, and further making the electric field distribution more uniform.

[0115] In some embodiments, the ion doping concentration of the plurality of first electric field modulator subregions 391 gradually increases along the first direction X.

[0116] For example, such as Figure 7 As shown, when there are two first electric field modulation sub-regions 391, the ion doping concentration of the first sub-region 3911 is less than the ion doping concentration of the second sub-region 3912.

[0117] Understandably, along the first direction X, as the ion doping concentration of the multiple first electric field modulator regions 391 gradually increases, the conductivity of the semiconductor device 300 is enhanced, resulting in a decrease in the specific on-resistance of the semiconductor device 300.

[0118] In some embodiments, the size of a plurality of first electric field modulator subregions 391 gradually increases along a first direction X.

[0119] For example, such as Figure 7 As shown, when there are two first electric field modulation sub-regions 391, the first sub-region 3911 has a dimension of D1 along the first direction X, and the second sub-region 3912 has a dimension of D2 along the first direction X, then D1 < D2.

[0120] Understandably, the above configuration allows the gradually increasing first electric field modulator region 391 to act as a buffer, effectively alleviating electric field concentration and making the electric field distribution in the semiconductor device 300 along the direction from the source 306 to the drain 307 smoother, avoiding abrupt changes, thereby reducing electric field distortion and further making the electric field distribution more uniform.

[0121] In some embodiments, the number of the first electric field modulation sub-regions 391 is one. The ratio of the size of the first electric field modulation sub-region 391 along the first direction X to the size of the electric field modulation region 390 along the first direction X ranges from 0.1 to 0.9. The first direction X is the direction in which the source electrode 306 points to the drain electrode 307.

[0122] As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9. Figure 3 As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9.

[0123] Figure 6 As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9.

[0124] As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9.

[0125] As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9.

[0126] In some embodiments, the number of the first electric field modulation sub-regions 391 is multiple. The multiple first electric field modulation sub-regions 391 are arranged along the first direction X. The ratio of the sum of the sizes of the multiple first electric field modulation sub-regions 391 along the first direction X to the size of the electric field modulation region 390 along the first direction X ranges from 0.1 to 0.9.

[0127] As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9. Figure 4 As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9.

[0128] Figure 7 As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9.

[0129] As shown in FIG. 3, the size D of the first electric field modulation sub-region 391 along the first direction X, and the size d of the electric field modulation region 390 along the first direction X, the ratio of D to d ranges from 0.1 to 0.9.​​

[0130] It can be understood that the above setting can optimize the electric field change of the plurality of first electric field modulation sub-regions 391, adjust the electric field gradient of the semiconductor device 300, reduce the potential peak and enhance the withstand voltage, and further make the electric field distribution uniform.

[0131] In some embodiments, in the orthographic projection onto the substrate 301, the second electric field modulation sub-region 392 overlaps with the gate 311 close to the boundary of the drain 307.

[0132] It can be understood that the setting that the second electric field modulation sub-region 392 overlaps with the gate 311 close to the boundary of the drain 307 in the orthographic projection onto the substrate 301 can make the gate 311 and the second electric field modulation sub-region 392 contact and couple with each other, which is beneficial for more accurate regulation and control in the on state. Moreover, in the preparation process of the semiconductor device 300, the overlap of the second electric field modulation sub-region 392 and the gate 311 close to the boundary of the drain 307 is more conducive to the implementation of the process and improves the feasibility of the process.

[0133] In some other embodiments, in the orthographic projection onto the substrate 301, the second electric field modulation sub-region 392 can also partially overlap with the gate 311, or the second electric field modulation sub-region 392 has a spacing with the gate 311.

[0134] In some embodiments, in the orthographic projection onto the substrate 301, the first electric field modulation sub-region 391 has a spacing between the boundary away from the drain 307 and the boundary of the gate 311 close to the drain 307.

[0135] It can be understood that the setting that the first electric field modulation sub-region 391 has a spacing between the boundary away from the drain 307 and the boundary of the gate 311 close to the drain 307 in the orthographic projection onto the substrate 301 is helpful for regulating and controlling the effective carrier density of the epitaxial layer 303, and further reduces the on-resistance of the semiconductor device 300.

[0136] In some other embodiments, in the orthographic projection onto the substrate 301, the first electric field modulation sub-region 391 has no spacing between the boundary away from the drain 307 and the boundary of the gate 311 close to the drain 307.

[0137] Embodiments of the present disclosure provide a preparation method of a semiconductor device 300. As shown in FIG. 8, the preparation method of the semiconductor device 300 includes S1-S3. Figure 8 S1-S3.

[0138] S1: Forming an epitaxial layer 303 on a substrate 301.

[0139] S2: forming a source 306, a drain 307 and a gate 311 on a side of the epitaxial layer 303 away from the substrate 301; the source 306 and the drain 307 are embedded in the epitaxial layer 303, and the gate 311 is between the source 306 and the drain 307.

[0140] S3: forming an electric field modulation region 390 on a side of the epitaxial layer 303 away from the substrate 301. The electric field modulation region 390 is embedded in the epitaxial layer 303, and the electric field modulation region 390 comprises a first electric field modulation sub-region 391 and a second electric field modulation sub-region 392 connected to each other, the second electric field modulation sub-region 392 covers a surface of the first electric field modulation sub-region 391 away from the substrate 301, the first electric field modulation sub-region 391 has a same doping type as the epitaxial layer 303, and the second electric field modulation sub-region 392 has a different doping type from the epitaxial layer 303.

[0141] The semiconductor device 300 can be prepared by the preparation method of one of the above embodiments. The preparation method of the semiconductor device 300 of the present disclosure will be further described below by a specific preparation method.

[0142] In some embodiments, a semiconductor device 300 is provided. As shown in Figure 9 The preparation method of the semiconductor device 300 comprises T1-T6.

[0143] Step T1: forming an epitaxial sub-layer 302 on a substrate 301.

[0144] For example, a second conductive type epitaxial sub-layer 302 is epitaxially grown on a first conductive type bulk substrate 301 by a suitable epitaxial growth process such as chemical vapor deposition (CVD). The substrate 301 is made of silicon carbide. For example, the first conductive type is P type, and the second conductive type is N type.

[0145] Step T2: epitaxially growing a first conductive type epitaxial layer 303 on a side of the epitaxial sub-layer 302 away from the substrate 301.

[0146] Step T3: forming a well region 304.

[0147] For example, a well region 304 pattern is defined on the first conductive type epitaxial layer 303 by a photolithography process. The well region 304 is formed by ion implantation of a second conductive type ion.

[0148] Step T4: Forming active region. Injecting second conductive type ions into the second conductive type (e.g. P-type) well region 304 far from the substrate 301 to form a body region 305, and injecting first conductive type ions into the well region 304 far from the substrate 301 and contacting the body region 305 to form a source region 306. Injecting first conductive type ions into the pre-formed drain region 307 to form a drain region 307. Depositing multi-layer metal (including but not limited to Ti / Ni / Ag) by electron beam evaporation process to form the source region 306 and the drain region 307.

[0149] Step T5: Forming electric field modulation region 390.

[0150] For example, injecting first conductive type ions into the epitaxial layer 303 far from the substrate 301 to form a first electric field modulation sub-region 391, adjusting the photoetch mask, and injecting second conductive type ions into the surface of the first electric field modulation sub-region 391 to form a second electric field modulation sub-region 392.

[0151] Step T6: Forming gate 311.

[0152] For example, growing a gate oxide layer 310 with a thickness of 20-80 nm on the surface of the epitaxial layer 303 far from the substrate 301, depositing a polysilicon layer with a thickness of 200-700 nm by a deposition process (e.g. Low-Pressure Chemical Vapor Deposition, LPCVD, etc.), forming a gate region 311 by photoetching and dry etching, and depositing multi-layer metal (including but not limited to Ti / Ni / Ag) by electron beam evaporation process to form the gate 311.

[0153] In some embodiments, a semiconductor device 300 is provided. As shown, the method for manufacturing the semiconductor device 300 includes N1-N6. Figure 10

[0154] Step N1: Forming an epitaxial sub-layer 302 on a substrate 301.

[0155] For example, using a suitable epitaxial growth process such as chemical vapor deposition (CVD), an epitaxial sub-layer 302 of a second conductive type is epitaxially grown on a body substrate 301 of a first conductive type. The material of the substrate 301 is silicon carbide. For example, the first conductive type is P-type and the second conductive type is N-type.

[0156] Step N2: Epitaxially growing an epitaxial layer 303 of the first conductive type on the side of the epitaxial sub-layer 302 far from the substrate 301.

[0157] Step N3: Forming a well region 304.

[0158] ​For example, a photoetching process is used to define the pattern of the well region 304 on the epitaxial layer 303 of the first conductive type. An ion implantation process is used to implant ions of the second conductive type to form the well region 304.

[0159] Step N4: Forming the active region. Ions of the second conductive type are implanted to form the body region 305 in the well region 304 away from the substrate 301. Ions of the first conductive type are implanted to form the source region 306 in the well region 304 away from the substrate 301 and contacting the body region 305. Ions of the first conductive type are implanted to form the drain region 307 in the pre-formed drain region 307. A multi-layer metal including but not limited to Ti / Ni / Ag is deposited by an electron beam evaporation process to form the source region 306 and the drain region 307.

[0160] Step N5: Forming the electric field modulation region 390.

[0161] For example, ions of the first conductive type are implanted to form the first electric field modulation sub-region 391 in the epitaxial layer 303 away from the substrate 301. The photoetching mask is adjusted so that the second electric field modulation sub-region 392 covers the surface of the first electric field modulation sub-region 391 away from the substrate 301. Ions of the second conductive type are implanted to form the second electric field modulation sub-region 392. The first electric field modulation sub-region 391 includes a first sub-region 3911, a second sub-region 3912, and a third sub-region 3913.

[0162] Step N6: Forming the gate 311.

[0163] For example, a gate oxide layer 310 with a thickness of 20-80 nm is grown on the surface of the epitaxial layer 303 away from the substrate 301. A polysilicon layer with a thickness of 200-700 nm is deposited by a deposition process such as low pressure chemical vapor deposition (LPCVD) or the like. The gate region 311 is formed by photoetching and dry etching. A multi-layer metal including but not limited to Ti / Ni / Ag is deposited by an electron beam evaporation process to form the gate 311.

[0164] In some embodiments, a semiconductor device 300 is provided. As shown in Figure 11 the preparation method of the semiconductor device 300 includes M1-M6.

[0165] Step M1: Forming the epitaxial sub-layer 302 on the substrate 301.

[0166] For example, a chemical vapor deposition (CVD) or other suitable epitaxial growth process is used to epitaxially grow the epitaxial sub-layer 302 of the second conductive type on the bulk substrate 301 of the first conductive type. The substrate 301 is made of silicon carbide. For example, the first conductive type is P-type and the second conductive type is N-type.

[0167] Step M2: epitaxially growing a first-conductivity-type epitaxial layer 303 on the side of the epitaxial sub-layer 302 away from the substrate 301.

[0168] Step M3: forming a well region 304.

[0169] For example, the well region 304 pattern is defined on the first-conductivity-type epitaxial layer 303 by a photolithography process. The well region 304 is formed by implanting ions of a second conductivity type using an ion implantation process.

[0170] Step M4: forming an active region. A body region 305 is formed by implanting ions of the second conductivity type on the side of the well region 304 away from the substrate 301. A source region 306 is formed by implanting ions of the first conductivity type on the side of the well region 304 away from the substrate 301 and contacting the body region 305. A drain region 307 is formed by implanting ions of the first conductivity type on a pre-formed drain region 307. A multi-layer metal (including but not limited to Ti / Ni / Ag) is deposited by an electron beam evaporation process to form the source region 306 and the drain region 307.

[0171] Step M5: forming an electric field modulation region 390.

[0172] For example, a first electric field modulation sub-region 391 is formed by implanting ions of the first conductivity type on the side of the epitaxial layer 303 away from the substrate 301. A second electric field modulation sub-region 392 is formed by implanting ions of the second conductivity type on the surface of the first electric field modulation sub-region 391 away from the substrate 301 using a photomask to cover the first electric field modulation sub-region 391. The first electric field modulation sub-region 391 includes a first sub-region 3911 and a second sub-region 3912.

[0173] Step M6: forming a gate 311.

[0174] For example, a gate oxide layer 310 with a thickness of 20-80 nm is grown on the surface of the epitaxial layer 303 away from the substrate 301. A polysilicon layer with a thickness of 200-700 nm is deposited by a deposition process (such as low pressure chemical vapor deposition (LPCVD), etc.). The gate 311 region is formed by photolithography and dry etching. A multi-layer metal (including but not limited to Ti / Ni / Ag) is deposited by an electron beam evaporation process to form the gate 311.

[0175] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily conceived by those skilled in the art, and should be encompassed within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; an epitaxial layer disposed on the substrate; a source, a drain and a gate disposed on a side of the epitaxial layer away from the substrate, the source and the drain being embedded in the epitaxial layer, and the gate being located between the source and the drain; an electric field modulation region disposed on a side of the epitaxial layer away from the substrate and embedded in the epitaxial layer, and disposed between the drain and the gate, the electric field modulation region comprising a first electric field modulation sub-region and a second electric field modulation sub-region, the second electric field modulation sub-region comprising a first part and a second part, the first part being located on a side of the first electric field modulation sub-region away from the substrate and in contact with the first electric field modulation sub-region, the second part being located on a side of the first electric field modulation sub-region away from the drain and in contact with the first electric field modulation sub-region, and the first part and the second part being connected; the first electric field modulation sub-region and the second electric field modulation sub-region have different doping types from the epitaxial layer, and the doping type is P-type doping or N-type doping.

2. The semiconductor device according to claim 1, wherein The ion doping concentration of the second electric field modulation sub-region is greater than the ion doping concentration of the first electric field modulation sub-region. The ion doping concentration of the first electric field modulation sub-region is greater than the ion doping concentration of the epitaxial layer.

3. The semiconductor device of claim 1, wherein The electric field modulation region comprises a plurality of electric field modulation regions arranged along a first direction, and the first direction is the direction in which the source points to the drain. In any two adjacent electric field modulation regions, the electric field modulation region closer to the source is a first electric field modulation region, and the electric field modulation region closer to the drain is a second electric field modulation region. The first part of the first electric field modulation region and the second part of the second electric field modulation region are shared.

4. The semiconductor device according to claim 3, wherein The distance from the surface of the first electric field modulation sub-region away from the substrate to the surface of the second electric field modulation sub-region away from the substrate gradually decreases along the first direction; and / or The distance from the surface of the first electric field modulation sub-region close to the substrate to the surface of the second electric field modulation sub-region away from the substrate gradually decreases along the first direction.

5. The semiconductor device of claim 4, wherein the interface between the first electric field modulation sub-region and the second electric field modulation sub-region has a stepped morphology; and / or the interface between the first electric field modulation sub-region and the epitaxial layer has a stepped morphology.

6. The semiconductor device of claim 4, wherein, The ion doping concentration of the first electric field modulation sub-region gradually increases along the first direction.

7. The semiconductor device of claim 1, wherein The second electric field modulation sub-region further comprises a third part, the third part being located on a side of the first electric field modulation sub-region close to the drain, and the third part and the drain have a spacing therebetween and are in contact with the first electric field modulation sub-region, and the third part and the first part are connected.

8. The semiconductor device of claim 7, wherein, The electric field modulation region comprises a plurality of electric field modulation regions arranged along a first direction, and the first direction is the direction in which the source points to the drain. In any two adjacent electric field modulation regions, the electric field modulation region closer to the source is a first electric field modulation region, and the electric field modulation region closer to the drain is a second electric field modulation region; The third part of the first electric field modulation region shares the second part of the second electric field modulation region.

9. The semiconductor device of claim 8, wherein, The ion doping concentration of the plurality of first electric field modulation sub-regions gradually increases along the first direction; and / or, The size of the plurality of first electric field modulation sub-regions gradually increases along the first direction.

10. The semiconductor device according to any one of Claims 1 to 9, wherein The number of the first electric field modulation sub-regions is one; the ratio of the size of the first electric field modulation sub-region along the first direction to the size of the electric field modulation region along the first direction ranges from 0.1 to 0.9; the first direction is the direction from the source to the drain; Or, The number of the first electric field modulation sub-regions is multiple, and the plurality of first electric field modulation sub-regions are arranged along the first direction; the ratio of the sum of the size of the plurality of first electric field modulation sub-regions along the first direction to the size of the electric field modulation region along the first direction ranges from 0.1 to 0.9.

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