Hybrid back contact n-type crystalline silicon solar cell and preparation method thereof

Abstract

The invention discloses a mixed back contact n-type crystalline silicon solar cell and a preparation method thereof, and the cell comprises the components of crystalline silicon which is provided with a light receiving surface and a backlight surface; an anti-reflection passivation layer; the electron collection assemblies and the hole collection assemblies are distributed on the backlight face at intervals, and an insulation gap is formed between the adjacent electron collection assembly and hole collection assembly; and the conductive component comprises a positive conductive layer and a negative conductive layer, one surface of the positive conductive layer back to the crystalline silicon is connected with a positive electrode, and one surface of the negative conductive layer back to the crystalline silicon is connected with a negative electrode. According to the mixed back contact n-type crystalline silicon solar cell and the preparation method thereof, anti-reflection of a light receiving surface and interface defect suppression of a backlight surface are considered, isolation between the electron collection assembly and the hole collection assembly is realized through the insulation gap, the passivation quality is ensured, the cell piece is simple in structure, the process cost is reduced, and the production efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of back contact cells, in particular to a hybrid back contact n-type crystalline silicon solar cell and a preparation method thereof. BACKGROUND

[0002] The back contact cell removes the shading loss on the front surface by moving all electrodes to the back surface, and becomes an important development direction of high-efficiency crystalline silicon cells. The current back contact cell generally includes IBC, HBC and TBC.

[0003] In the manufacturing of the traditional IBC cell, the photoetching and mask process is the core technology for realizing the patterning of the back surface interdigitated electrode. However, the photoetching and mask process has defects of complex process and high equipment cost. The single-process cost accounts for 15%-20% of the total cell manufacturing cost, and the production capacity is limited by the photoetching speed (about 50-100 pieces / hour). The HBC cell combines the heterojunction passivation advantage, but is limited by the low-temperature process and the high cost of amorphous silicon / TCO layer. This is because the amorphous silicon deposition and TCO of HTJ need to be completed in a low-temperature environment of 200-250℃ to avoid amorphous silicon crystallization and silicon wafer thermal damage. Although this feature simplifies the process and reduces energy consumption, it directly conflicts with the high-temperature doping process (such as phosphorus diffusion at 800-900℃) of the traditional IBC cell. In order to solve the problem of high-temperature process, the HBC needs to use low-temperature technologies such as laser doping or ion implantation. The low-temperature doping technology needs multiple photoetching or laser alignment, which requires high assembly precision, increases the process steps, reduces the production efficiency, and also reduces the yield. The TBC is compatible with high-temperature process, but the doping uniformity of the single-polysilicon passivation layer and the damage to the passivation structure caused by laser grooving cannot be effectively solved. During deposition, uneven gas diffusion easily leads to fluctuations in film thickness and doping concentration. When laser grooving, too high laser pulse energy density will cause local temperature to rise sharply, causing thermal stress damage and lattice distortion of the silicon substrate. Too low energy density will cause the passivation layer to be unable to be removed.

[0004] In summary, the IBC cell and its production process of the prior art generally have the following core contradictions: first, the process complexity and cost are difficult to balance, such as multiple masking, low laser patterning precision, which leads to yield loss; second, the trade-off between passivation effect and contact resistance, such as the Voc loss caused by the polysilicon grain boundary defects in TBC, and the light absorption and cost disadvantage of TCO layer in HBC; third, the adjustment of material system compatibility, such as the poor thermal stability of amorphous silicon layer limiting the integration of high-temperature process, and the matching problem of metallization paste and bipolar contact area.

[0005] Therefore, it is necessary to improve the back contact cell and its production process in the prior art. SUMMARY

[0006] The present application aims to overcome the defects in the prior art, and provide a hybrid back contact n-type crystalline silicon solar cell and a preparation method thereof, which can reduce production cost, improve production efficiency, realize high and low temperature compatibility and ensure product quality.

[0007] To solve the above technical problems, the present application provides a hybrid back contact n-type crystalline silicon solar cell, comprising: crystalline silicon, having a light-receiving surface and a back surface distributed along the thickness direction of the crystalline silicon; an anti-reflection passivation layer, laminated on the light-receiving surface; an electron collection assembly and a hole collection assembly, spacedly distributed on the back surface, and an insulating gap is arranged between adjacent electron collection assemblies and hole collection assemblies; a conductive assembly, comprising a negative conductive layer and a positive conductive layer laminated on the electron collection assembly and the hole collection assembly respectively and processed from the same conductive film, and a positive electrode is connected to the side of the positive conductive layer opposite to the crystalline silicon, and a negative electrode is connected to the side of the negative conductive layer opposite to the crystalline silicon.

[0008] Preferably, to simplify the structure while ensuring the power generation efficiency, simplify the production process, reduce the production cost and improve the efficiency, the electron collection assembly comprises an electron tunneling layer and an n-type semiconductor layer laminated, the hole collection assembly comprises a hole passivation layer and a p-type semiconductor layer laminated, and the electron tunneling layer and the hole passivation layer are both connected to the back surface.

[0009] Preferably, to enhance the interface bonding force, improve the purity and density, ensure the thickness uniformity, increase the process compatibility and ensure the long-term reliability of the photovoltaic cell, the electron tunneling layer is an electron tunneling layer formed by thermal oxidation.

[0010] To solve the above technical problems, the present application also provides a preparation method of a hybrid back contact n-type crystalline silicon solar cell, comprising the following steps: S100, pretreatment: removing the damage layer after double-sided polishing of the crystalline silicon, the two surfaces of the crystalline silicon distributed along the thickness direction of the crystalline silicon are a light-receiving surface and a back surface respectively, and the back surface is divided into an electron zone, an insulating zone and a hole zone spacedly distributed in sequence; S200, preparing an electron collection assembly, a hole collection assembly and an anti-reflection passivation layer: depositing an anti-reflection passivation layer on the light-receiving surface, and preparing an electron collection assembly and a hole collection assembly in the electron zone and the hole zone respectively in sequence, so that an insulating gap opposite to the insulating zone is formed between adjacent electron collection assemblies and hole collection assemblies; S300, preparing the conductive assembly: forming a positive conductive layer and a negative conductive layer on the side of the electron collection assembly and the side of the hole collection assembly away from the crystalline silicon respectively, and forming a positive electrode and a negative electrode on the side of the positive conductive layer and the negative conductive layer away from the crystalline silicon respectively.

[0011] Preferably, in order to simplify the structure, simplify the production process, reduce the production cost, and improve the efficiency while ensuring power generation, in step S200, the electron collection assembly comprises a stacked electron tunneling layer and an n-type semiconductor layer, the hole collection assembly comprises a stacked hole passivation layer and a p-type semiconductor layer, and the electron tunneling layer and the hole passivation layer are stacked on the electron region and the hole region respectively.

[0012] Preferably, in order to enhance the interface bonding force, improve the purity and density, ensure the thickness uniformity, increase the process compatibility, and ensure the long-term reliability of the photovoltaic cell, in step S200, the electron tunneling layer is an oxidized electron tunneling layer.

[0013] Preferably, in order to save energy in production, the temperature difference in forming is fully utilized, in step S200, the electron collection assembly is formed first, then the anti-reflection passivation layer is formed, and finally the hole collection assembly is formed.

[0014] Preferably, in order to ensure the production quality of the cell sheet, step S200 comprises the following steps: S210, thermal oxidation: thermally oxidizing the crystalline silicon obtained in S100 to form an electron tunneling cover on the surface, the electron tunneling cover comprising an electron tunneling film stacked on the back light surface and an electron tunneling cover enclosing a wrapping cavity, the cavity wall of the wrapping cavity being sealingly and fixedly connected to the outer surface of the crystalline silicon; S220, depositing an n-type semiconductor film: depositing an n-type semiconductor film on the side of the electron tunneling film away from the crystalline silicon obtained in S210, and forming PSG on the outer surface of the n-type semiconductor film and the outer surface of the electron tunneling cover during deposition; S230, removing the around plating: removing the PSG corresponding to the electron tunneling cover and the light receiving surface and the circumferential outer edge of the crystalline silicon to retain the PSG corresponding to the n-type semiconductor film as a sacrificial layer; S240, laser slotting: irradiating laser light on the back light surface side of the crystalline silicon to expose the insulating region and the hole region; S250, depositing a pre-treatment: removing the sacrificial layer to expose the n-type semiconductor layer; S260, depositing an anti-reflection passivation layer: depositing an anti-reflection passivation layer on the light receiving surface; S270, depositing a hole recombination film: sequentially depositing a hole passivation film and a p-type semiconductor film on the back light surface side of the crystalline silicon; S280, laser cutting: irradiating laser on the back side of the crystalline silicon to expose the n-type semiconductor layer and the insulating region.

[0015] Preferably, in order to improve photoelectric efficiency and enhance interface bonding force, in the step S230, alkali solution is used to remove the corresponding electron tunneling cover and PSG, so that the light receiving surface, the hole region and the insulating region form a rough structure.

[0016] Preferably, in order to ensure the insulation of the electron collection assembly and the hole collection assembly and reduce damage to the crystalline silicon, the step S300 comprises the following steps: S310, depositing a conductive film: depositing a conductive film on the back side of the crystalline silicon; S320, removing excess film: printing etching paste on the position opposite to the conductive film and the insulating region, so that the conductive film is etched and divided into a positive conductive layer and a negative conductive layer which are spaced apart and respectively correspond to the n-type semiconductor layer and the p-type semiconductor layer and are stacked and connected one by one; S330, preparing electrodes: printing metal electrodes on the positive conductive layer and the negative conductive layer respectively to form a positive electrode connected with the positive conductive layer and a negative electrode connected with the negative conductive layer.

[0017] In summary, compared with the prior art, the hybrid back contact n-type crystalline silicon solar cell and the preparation method have the advantages that the light receiving surface is anti-reflection and the interface defects on the back side are inhibited, the isolation between the electron collection assembly and the hole collection assembly is realized through the insulating gap, the passivation quality is ensured, the battery piece structure is simple, the process cost is reduced, and the production efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a structural schematic diagram of the first embodiment of the hybrid back contact n-type crystalline silicon solar cell; Figure 2 is a schematic diagram of depositing an n-type semiconductor film in the production process of the first embodiment; Figure 3 is a schematic diagram of preparing an electron collection assembly in the production process of the first embodiment; Figure 4 is a schematic diagram of preparing an electron collection assembly and a conductive assembly in the production process of the first embodiment; Figure 5 is a production process schematic diagram of the first embodiment; Figure 6 is Figure 5 is a total production process schematic diagram of the step S200 in the first embodiment; Figure 7 is Figure 5 is a specific production process schematic diagram of the step S200 in the first embodiment; Figure 8This is a schematic diagram of the structure of the hybrid back-contact n-type crystalline silicon solar cell of the second embodiment; Figure 9 This is a schematic diagram of the structure of the hybrid back-contact n-type crystalline silicon solar cell in the third embodiment; Figure 10 This is a performance data table based on the first embodiment; Figure 11 This is a performance data table based on the second embodiment; Figure 12 This is a performance data table based on the third embodiment; In the diagram: 1. Crystalline silicon; 11. Light-receiving surface; 12. Backlight-receiving surface; 2. Anti-reflection passivation layer; 21. Alumina layer; 22. Silicon nitride layer; 3. Electron collecting component; 31. Electron tunneling layer; 310. Electron tunneling sleeve; 311. Electron tunneling cover; 312. Electron tunneling film; 32. n-type semiconductor layer; 320. n-type semiconductor film; 33. PSG; 331. Sacrificial layer; 4. Hole collecting component; 41. Hole passivation layer; 410. Hole passivation film; 42. p-type semiconductor layer; 420. p-type semiconductor film; 5. Insulating gap; 6. Conductive component; 61. Positive conductive layer; 62. Negative conductive layer; 63. Positive electrode; 64. Negative electrode; 65. Conductive film. Detailed Implementation

[0019] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solutions of the present invention and should not be construed as limiting the scope of protection of the present invention.

[0020] First Embodiment

[0021] like Figure 1 As shown, a hybrid back-contact n-type crystalline silicon solar cell according to a first embodiment of the present invention includes: Crystalline silicon 1 has a light-receiving surface 11 and a backlighting surface 12 distributed along its own thickness direction; Anti-reflective passivation layer 2 is stacked on the light-receiving surface 11; Electron collecting component 3 and hole collecting component 4 are spaced apart on backlight surface 12. An insulating gap 5 is provided between adjacent electron collecting component 3 and hole collecting component 4. The insulating gap 5 and the backlight surface 12 enclose an insulating groove with the opening facing away from the crystal silicon 1. The conductive component 6 includes a negative conductive layer 62 and a positive conductive layer 61, which are respectively stacked on the electron collecting component 3 and the hole collecting component 4 and formed by the same conductive film 65. A positive electrode 63 is connected to the side of the positive conductive layer 61 that faces away from the crystalline silicon 1, and a negative electrode 64 is connected to the side of the negative conductive layer 62 that faces away from the crystalline silicon 1.

[0022] The back contact n-type crystalline silicon solar cell of the embodiment has the anti-reflection and passivation layer 2 laminated and connected to the front surface of the crystalline silicon 1, so that the reflection amount of the light receiving surface 11 of the crystalline silicon 1 can be reduced, the light absorption amount is increased, the photovoltaic power generation amount per unit time is improved, and the electron collecting component 3 and the hole collecting component 4 can be distributed at intervals on the back surface 12. The back surface defects of the crystalline silicon 1 are inhibited, the passivation quality is ensured, the insulation gap 5 is used to realize the isolation between the electron collecting component 3 and the hole collecting component 4, and the power generation amount is ensured. Moreover, the back cell has a simple structure, so that the process cost is reduced and the production efficiency is improved.

[0023] Specifically, in the embodiment, the crystalline silicon 1 is an n-type crystalline silicon 1 with a thickness of 110 um. Compared with a p-type, the n-type crystalline silicon 1 has the advantages of short minority carrier lifetime, high photoelectric efficiency, good temperature characteristics, and high bifacial rate, and is suitable for scenes with high power generation efficiency and high stability.

[0024] The anti-reflection and passivation layer 2 preferably adopts a silicon nitride layer with a thickness of 80 nm. As the anti-reflection and passivation layer 2, the silicon nitride layer mainly plays a role in reducing reflection and passivation. Specifically, the silicon nitride can reduce the reflection of sunlight on the light receiving surface 11 side, so that more sunlight enters the inside of the cell. In addition, it can also be chemically passivated to reduce the surface load, thereby improving the carrier lifetime.

[0025] After the sunlight transmits through the above-mentioned film layer, it enters the crystalline silicon 1, the photon energy is absorbed by the silicon, the electrons in the silicon atoms are excited, and the electron-hole pairs (i.e. photo-generated carriers) are generated. After the hole-electron pairs are separated by the built-in electric field, the electrons in the photo-generated carriers gather to the electron collecting component 3, and the holes gather to the hole collecting component 4. The insulation gap 5 is used to isolate the electron collecting component 3 and the hole collecting component 4, and the output is achieved through the conductive component 6, so that the electrons are collected to the negative electrode 64 through the negative conductive layer 62, and the holes are collected to the positive electrode 63 through the positive conductive layer 61. The output power is output, and the photoelectric conversion is realized.

[0026] Further improvement is that the electron collecting component 3 includes a laminated electron tunneling layer 31 and an n-type semiconductor layer 32, and the hole collecting component 4 includes a laminated hole passivation layer 41 and a p-type semiconductor layer 42. The electron tunneling layer 31 and the hole passivation layer 41 are both connected to the back surface 12.

[0027] After the above structure is adopted, the structure of the electron collecting component 3 and the hole collecting component 4 is further simplified, so that the production cost is reduced.

[0028] Further improvement is that the electron tunneling layer 31 is an electron tunneling layer 31 formed by thermal oxidation.

[0029] Compared with the electron tunneling layer 31 formed by deposition, the electron tunneling layer formed by thermal oxidation is grown from the inside by chemical reaction with the crystalline silicon 1 and an oxidizing agent, and an atomically close interface (such as the interface between silicon and silicon dioxide) can be formed between the oxide film and the back surface 12 of the crystalline silicon 1. Moreover, during the process of thermal oxidation, the high-purity oxide film can act as a passivation layer, effectively inhibiting the defects of the back surface 12 of the crystalline silicon 1, and the dense structure can also block the diffusion of metal ions, avoiding reliability problems in long-term use of the battery. Furthermore, during thermal oxidation, the oxide film can be precisely controlled in terms of time, temperature, and oxidizing agent concentration, achieving uniform distribution of the electron tunneling layer 31 on the large-area back surface 12 of the crystalline silicon 1. In addition, compared with the deposition process, the thermal oxidation process can be completed simultaneously with the diffusion and annealing steps of the silicon wafer, without the need for additional equipment or time, thereby improving production efficiency and reducing the cost of the oxidation furnace compared with the deposition furnace, further reducing the production cost of the battery wafer. In addition, the electron tunneling layer 31 formed by thermal oxidation has a dense structure, higher chemical stability and thermal stability, stronger moisture resistance and ultraviolet aging resistance, thereby prolonging the service life of the battery wafer.

[0030] In this embodiment, the contact part of the back surface 12 with the electron collection assembly 3 is the electron collection area of the back surface 12, the contact part of the back surface 12 with the hole collection assembly 4 is the hole collection area of the back surface 12, and the remaining part is the insulating area of the back surface 12, which is opposite the insulating gap 5. In this way, a pn junction is formed.

[0031] Further specifically, the electron tunneling layer 31 is a silicon oxide layer with a thickness of 2 nm, the n-type semiconductor layer 32 is an n-type polysilicon layer with a thickness of 20 nm, the hole passivation layer 41 is a hydrogenated intrinsic amorphous silicon layer with a thickness of 10 nm, and the p-type semiconductor layer 42 is a hydrogenated p-type amorphous silicon layer with a thickness of 12 nm.

[0032] After adopting the above structure, the built-in electric field formed by the pn junction drives the photogenerated carriers to separate, and the electrons are pushed to the electron collection assembly 3, while the holes are pushed to the hole collection assembly 4.

[0033] The positive conductive layer 61 and the negative conductive layer 62 are both ITO conductive layers with a thickness of 100 nm, and the positive electrode 63 and the negative electrode 64 are both silver electrodes.

[0034] After the separated electrons pass through the electron tunneling layer 31, the n-type semiconductor layer 32, and the negative conductive layer 62 in turn, they finally reach the negative electrode 64. After the holes pass through the hole passivation layer 41, the p-type semiconductor layer 42, and the positive conductive layer 61 in turn, they finally reach the positive electrode 63. During the above process, the insulating gap 5 plays an insulating isolation role, avoiding crosstalk of carriers in different regions, thereby ensuring the orderly transmission of the carriers.

[0035] The electrons and the holes reach the negative electrode 64 and the positive electrode 63 respectively, so that a potential difference is formed between the positive electrode 63 and the negative electrode 64, and after the external circuit is connected, the electrons flow from the negative electrode 64 to the positive electrode 63 through the external circuit, forming an electric current, realizing the conversion of light energy into electric energy, and outputting the electric energy.

[0036] Based on the hybrid back contact n-type crystalline silicon solar cell of the embodiment, the application further discloses a preparation method of the hybrid back contact n-type crystalline silicon solar cell, comprising the following steps: S100, pretreatment: removing a damage layer after double-sided polishing of the crystalline silicon 1, the two surfaces of the crystalline silicon 1 distributed along the thickness direction of the crystalline silicon 1 are a light-receiving surface 11 and a back light surface 12 respectively, and the back light surface 12 is divided into an electron area, an insulation area and a hole area distributed in sequence and at intervals; S200, preparing an electron collection assembly 3, a hole collection assembly 4 and an anti-reflection and passivation layer 2: depositing the anti-reflection and passivation layer 2 on the light-receiving surface 11, and preparing the electron collection assembly 3 and the hole collection assembly 4 in the electron area and the hole area respectively in sequence, so that an insulation gap 5 opposite to the insulation area is formed between the adjacent electron collection assembly 3 and hole collection assembly 4; S300, preparing a conductive assembly 6: forming a positive conductive layer 61 and a negative conductive layer 62 processed from the same conductive film 65 on the side of the electron collection assembly 3 away from the crystalline silicon 1 and the side of the hole collection assembly 4 away from the crystalline silicon 1 respectively, and forming a positive electrode 63 and a negative electrode 64 on the side of the positive conductive layer 61 away from the crystalline silicon 1 and the side of the negative conductive layer 62 away from the crystalline silicon 1 respectively.

[0037] The preparation method is simple in process, is conducive to improving the production efficiency of the back cell, and reduces the production cost, and the back contact cell produced by the preparation method takes into account the anti-reflection of the light-receiving surface 11 and the inhibition of interface defects of the back light surface 12, separates the electron collection assembly 3 and the hole collection assembly 4 through the insulation gap 5, improves the passivation quality, and ensures the photoelectric conversion efficiency of the cell sheet.

[0038] Further improvement is that in step S200, the electron collection assembly 3 comprises a layer-stacked electron tunneling layer 31 and an n-type semiconductor layer 32, and the hole collection assembly 4 comprises a layer-stacked hole passivation layer 41 and a p-type semiconductor layer 42, and the electron tunneling layer 31 and the hole passivation layer 41 are respectively layer-stacked in the electron area and the hole area.

[0039] Specifically, the electron tunneling layer 31 is a silicon oxide layer, the n-type semiconductor layer 32 is an n-type polycrystalline silicon layer, the hole passivation layer 41 is a hydrogenated intrinsic amorphous silicon layer, and the p-type semiconductor layer 42 is a hydrogenated p-type amorphous silicon layer. In this way, while ensuring the separation of the electrons and the holes of the photo-generated carriers, the amorphous silicon / polycrystalline silicon hybrid passivation structure is adopted, and the product quality of the cell sheet is further ensured.

[0040] In step S200, the electron tunneling layer 31 is an oxidized electron tunneling layer 31. Through oxidation, the forming quality of the electron tunneling layer 31 is improved, the photoelectric conversion efficiency is ensured, and the use of an oxidation furnace for forming can reduce the process cost.

[0041] Further improvement is that, in step S200, the electron collection assembly 3 is first formed, then the anti-reflection and passivation layer 2 is formed, and finally the hole collection assembly 4 is formed. Specifically, step S200 includes the following steps: S210, thermal oxidation: thermally oxidizing the crystalline silicon 1 obtained in S100 to form an electron tunneling sleeve 310 on the surface thereof, the electron tunneling sleeve 310 including an electron tunneling layer 31 laminated on the back light surface 12 and an electron tunneling cover 311 formed by surrounding the electron tunneling layer 31, the cavity wall of the wrapped cavity being sealingly and fixedly connected with the outer surface of the crystalline silicon 1; S220, depositing an n-type semiconductor film 320: depositing an n-type semiconductor film 320 on the side of the electron tunneling layer 31 obtained in S210 opposite to the crystalline silicon 1, and forming a PSG 33 on the outer surface of the n-type semiconductor film 320 and the outer surface of the electron tunneling cover 311 during the deposition; S230, removing the around plating: removing the PSG 33 corresponding to the electron tunneling cover 311 and the light-receiving surface 11 and the circumferential outer edge of the crystalline silicon 1, so as to retain the PSG 33 corresponding to the n-type semiconductor film 320 as a sacrificial layer 331; S240, laser slotting: irradiating laser light on the back light surface 12 side of the crystalline silicon 1 to expose the insulating region and the hole region; S250, deposition pre-treatment: removing the sacrificial layer 331 to expose the n-type semiconductor layer 32; S260, depositing an anti-reflection and passivation layer 2: depositing an anti-reflection and passivation layer 2 on the light-receiving surface 11; S270, depositing a hole recombination film: sequentially depositing a hole passivation film 410 and a p-type semiconductor film 420 on the back light surface 12 side of the crystalline silicon 1; S280, laser cutting: irradiating laser light on the back light surface 12 side of the crystalline silicon 1 to expose the n-type semiconductor layer 32 and the insulating region.

[0042] In the above steps, the material of the antireflection passivation layer 2 is silicon nitride, and the hole recombination film in step S270 is formed by laminating a hydrogenated intrinsic amorphous silicon film and a hydrogenated p-type amorphous silicon film, wherein the hydrogenated intrinsic amorphous silicon film is located on the side of the hydrogenated p-type amorphous silicon film close to the crystalline silicon 1. Generally, the oxidation forming temperature of the silicon oxide in step S210 is 900-1200°C, the chemical vapor deposition temperature of the n-type semiconductor film 320 in step S220 is 570-880°C, the chemical vapor deposition temperature of the antireflection passivation layer 2, i.e., silicon nitride, in step S260 is 300-550°C, and the vapor deposition temperature of the hydrogenated intrinsic amorphous silicon film and the hydrogenated p-type amorphous silicon film in step S270 is 180-250°C. Therefore, in the above production process, the processing temperature gradually decreases, so that the production process has good compatibility, is suitable for high-temperature / low-temperature processes, and specifically, the silicon oxide and the n-type semiconductor film 320 are formed at high temperature, and the hydrogenated intrinsic amorphous silicon film and the hydrogenated p-type amorphous silicon film are formed at low temperature. In the low-temperature processing process, the electron tunneling layer 31 and the n-type semiconductor film 320 are not affected, the forming quality and photoelectric conversion efficiency of the battery piece are ensured, the process cost is reduced, and the production process is suitable for large-scale mass production.

[0043] Further specifically, in step S230, the corresponding electron tunneling mask 311 and PSG 33 are removed using an alkali solution, so that the light receiving surface 11, the hole region, and the insulating region form a textured structure.

[0044] With the above design, the roughness of the light receiving surface 11 and the back surface 12 of the crystalline silicon 1 can be increased, so that the light reflectivity of the light receiving surface 11 is reduced, the amount of light absorption is increased, the power generation is improved, and the bonding strength between the light receiving surface 11 and the back surface 12 of the crystalline silicon 1 and other film layers is ensured. Moreover, the step combines the removal of plating and texturing together, so that the step has the functions of removing impurities and texturing, which is beneficial to improving the production efficiency.

[0045] Further improvement is that step S300 includes the following steps: S310, depositing a conductive film 65: depositing a conductive film 65 on the back surface 12 side of the crystalline silicon 1; S320, removing excess film: printing etching paste at the positions opposite to the conductive film 65 and the insulating region, so that the conductive film 65 is etched and divided into a positive conductive layer 61 and a negative conductive layer 62 which are spaced apart and respectively correspond to the n-type semiconductor layer 32 and the p-type semiconductor layer 42; S330, preparing electrodes: printing metal electrodes on the positive conductive layer 61 and the negative conductive layer 62 respectively to form a positive electrode 63 connected with the positive conductive layer 61 and a negative electrode 64 connected with the negative conductive layer 62.

[0046] The conductive assembly 6 is prepared by the above method, the excess part of the conductive film 65 deposited on the back light surface 12 of the crystalline silicon 1 is removed by printing the etching slurry, so that the conductive film 65 is divided into the positive conductive layer 61 and the negative conductive layer 62 which are distributed at intervals, and then the electrodes are printed on the positive conductive layer 61 and the negative conductive layer 62 respectively to form the positive electrode 63 and the negative electrode 64, compared with the method using laser, the damage to the battery piece can be avoided and the production quality of the battery piece can be ensured.

[0047] Further specifically, in the above steps: In step S210, the temperature of the thermal oxidation is 950℃, the compact electron tunneling cover 310 is formed on the outer surface (including the side surface, the light receiving surface 11 and the back light surface 12) of the crystalline silicon 1 by the thermal oxidation, the material of the electron tunneling cover 310 is silicon oxide, and the electron tunneling cover 310 is divided into two parts, one part is the electron tunneling film 312 which is stacked on the back light surface 12, and the other part is the electron tunneling cover 311 which is irradiated from the front surface and connected with the electron tunneling film 312; In step S220, the n-type semiconductor film 320 is deposited on the outer surface of the electron tunneling cover 310 which is adjacent to the back light surface 12, that is, the surface of the electron tunneling layer 31 which is opposite to the crystalline silicon 1 by the vapor deposition method, the deposition temperature is 650℃, and the n-type semiconductor film 320 is formed, preferably, the n-type semiconductor film 320 is prepared by using a tube diffusion furnace, in the deposition process, the process gas is wound to the surface of the crystalline silicon 1 which does not need to be deposited by the edge of the crystalline silicon 1 and the carrier plate, the silicon oxide film is formed in the edge area, that is, the silicon dioxide is deposited on the edge, in addition, the phosphorus, oxygen and silicon elements react to form the PSG 33, that is, the phosphor silicon glass; In step S230, the winding is needed to be removed, the chain machine is usually used to react with the impurities, at the same time, a part of the PSG 33 which is stacked on the n-type semiconductor film 320 is reserved, the part of the PSG 33 can protect the n-type semiconductor film 320 in the subsequent processing process, for the convenience of description, the part of the layered PSG 33 is called the sacrificial layer 331, after the step, the circumferential outer edge and the light receiving surface 11 of the crystalline silicon 1 are exposed; In step S240, the laser is irradiated on the back light surface 12 of the crystalline silicon 1, the electron tunneling film 312 and the n-type semiconductor film 320 corresponding to the insulating area and the hole area are removed by the laser, so that the insulating area and the hole area of the back light surface 12 of the crystalline silicon 1 are exposed, and the electron tunneling film 312 and the n-type semiconductor film 320 are processed by the laser to form the electron tunneling layer 31 and the n-type semiconductor layer 32 which are stacked on the electron area in turn, and the electron tunneling layer 31 and the n-type semiconductor layer 32 combine to form the electron collection assembly 3; In step S250, while removing the sacrificial part with an alkaline solution, the crystalline silicon 1 is texturized so that the insulating and hole regions of the light-receiving surface 11 and the back-light surface 12 form a textured structure, which helps to reduce reflectivity and increase light absorption. In step S260, a silicon nitride layer is deposited on the light-receiving surface 11 by chemical vapor deposition at a deposition temperature of 450°C. In step S70, hydrogenated intrinsic amorphous silicon film and hydrogenated p-type amorphous silicon film are sequentially deposited on the backlight surface 12 by low-temperature chemical vapor deposition. The hydrogenated intrinsic amorphous silicon film and the hydrogenated p-type amorphous silicon film form a composite film that covers the exposed insulating region, hole region and n-type semiconductor layer 32. In step S80, laser is irradiated on the back surface 12 side of the crystalline silicon 1 by laser grooving, exposing the n-type semiconductor layer 32 and the insulating region. Thus, the hydrogenated intrinsic amorphous silicon film and the hydrogenated p-type amorphous silicon film are simultaneously cut by laser into hydrogenated intrinsic amorphous silicon layer and hydrogenated p-type amorphous silicon layer, respectively, which are then stacked sequentially on the hole passivation layer 41 and the p-type semiconductor layer 42 in the hole region. The two are combined to form the hole collection component 4.

[0048] In this embodiment, the conductive film 65 is preferably an ITO conductive film 65.

[0049] Based on the above production process, produce a batch of such... Figure 10 The solar back-contact cells shown were tested, and their photoelectric conversion efficiency (Eff, in %), open-circuit voltage (Voc, in V), short-circuit voltage (Isc, in A), and fill factor (FF, in %) were measured. To ensure testing accuracy, five solar cells from the same production batch were selected for performance testing. These five back-contact cells were designated as samples A1 to A5. The results are as follows: Figure 10 The data shown.

[0050] Second Embodiment

[0051] like Figure 8 As shown, a hybrid back-contact n-type crystalline silicon solar cell according to the second embodiment of the present invention is based on the first embodiment, except that: the anti-reflection passivation layer 2 is a composite layer, including an aluminum oxide layer 21 and a silicon nitride layer 22 stacked and connected, wherein the aluminum oxide layer 21 is connected to the light-receiving surface 11 and has a thickness of 12nm, and the silicon nitride layer 22 has a thickness of 70nm.

[0052] The method for fabricating a hybrid back-contact n-type crystalline silicon solar cell in this embodiment differs from the method in the above embodiment in that, in step S260, an aluminum oxide layer 21 and a silicon nitride layer 22 are deposited sequentially.

[0053] According to the preparation method of the mixed back contact n-type crystalline silicon solar cell in the embodiment, according to the above production process, a batch of solar back contact cells as shown in Figure 11 are manufactured, and 5 solar cells in the same production batch are selected for relevant performance testing, and the 5 back contact cells are the second sample B1 to the second sample B5, and data as shown in Figure 11 are obtained.

[0054] Taking the average value as the representative, compared with the first embodiment, the open circuit voltage of the heterojunction cell in the embodiment is basically unchanged, the short circuit current is increased by about 0.63%, the fill factor is increased by about 0.073%, and the photoelectric conversion efficiency is increased by 0.197%, which is mainly due to the fact that the composite structure is adopted for the anti-reflection and passivation layer 2 deposited on the light-receiving surface 11, the light reflectivity is further reduced, the light absorption amount of the cell sheet is increased, the photo-generated carriers are increased, and the internal loss of the cell is reduced, so that the short circuit current, the fill factor and the photoelectric conversion efficiency and other parameters are increased.

[0055] Third embodiment

[0056] As shown in Figure 9 , a mixed back contact n-type crystalline silicon solar cell of the third embodiment of the application is based on the second embodiment, and the difference lies in that the light-receiving surface 11 and the back light surface 12 are both completely textured structures.

[0057] The preparation method of the mixed back contact n-type crystalline silicon solar cell in the embodiment is different from the method mentioned in the second embodiment, and further comprises the step S101 of pre-texturing between the step S100 and the step S200, and the textured crystal silicon 1 after the pretreatment is textured, so that the light-receiving surface 11 and the back light surface 12 are both completely textured structures.

[0058] According to the preparation method of the mixed back contact n-type crystalline silicon solar cell in the embodiment, according to the above production process, a batch of solar back contact cells as shown in Figure 12 are manufactured, and 5 solar cells in the same production batch are selected for relevant performance testing, and the 5 back contact cells are the second sample B1 to the second sample B5, and data as shown in Figure 12 are obtained.

[0059] Taking the average value as the representative, compared with the second embodiment, although the fill factor of the heterojunction cell in the embodiment is decreased by 0.031%, the back light surface 12 adopts a completely textured structure, which helps to increase the light absorption amount, so that the amount of photo-generated carriers is increased, and therefore the open circuit voltage of the cell sheet is increased by 0.132%, the short circuit current is increased by 0.148%, the beneficial effect brought by the increase is much greater than the adverse effect caused by the decrease of the fill factor, and finally the photoelectric conversion efficiency of the cell sheet in the embodiment is increased by 0.02%, and the comprehensive performance is better than that of the cell sheet in the second embodiment.

[0060] In summary, the mixed back contact n-type cell and the preparation method thereof simplify the patterning step and reduce the cost of the production equipment by replacing ion implantation with the preparation of the n-type semiconductor film 320 by a tube diffusion furnace, combining laser step processing with selective removal technology of etching slurry, and innovatively adopting a laminated passivation and amorphous silicon / polycrystalline silicon mixed passivation structure to balance the anti-reflection of the light-receiving surface 11 and the inhibition of interface defects of the back light surface 12. The heat damage is reduced by optimizing the laser timing control, and the ITO etching and laser insulation groove process is designed to realize efficient isolation between the electron collection assembly 3 and the hole collection assembly 4, so that the technical solution of the present application is expected to break through the limitations of the prior art back cell in process cost, passivation quality and high-low temperature compatibility.

[0061] The above only describes the preferred embodiments of the present application, and it should be noted that those skilled in the art can make several improvements and refinements without departing from the technical principles of the present application, and these improvements and refinements should also be considered within the protection scope of the present application.

Claims

1. A hybrid back-contact n-type crystalline silicon solar cell, characterized in that, include: Crystalline silicon has a light-receiving surface and a back-lighting surface distributed along its thickness direction; An anti-reflection passivation layer is stacked on the light-receiving surface; Electron collecting components and hole collecting components are spaced apart on the backlight surface, and an insulating gap is provided between adjacent electron collecting components and hole collecting components. A conductive component includes a negative conductive layer and a positive conductive layer, which are respectively stacked on the electron collecting component and the hole collecting component and are formed by the same conductive film. A positive electrode is connected to the side of the positive conductive layer facing away from the crystalline silicon, and a negative electrode is connected to the side of the negative conductive layer facing away from the crystalline silicon.

2. The hybrid back-contact n-type crystalline silicon solar cell according to claim 1, characterized in that: The electron collecting component includes a stacked electron tunneling layer and an n-type semiconductor layer, and the hole collecting component includes a stacked hole passivation layer and a p-type semiconductor layer. Both the electron tunneling layer and the hole passivation layer are connected to the backlight surface.

3. The hybrid back-contact n-type crystalline silicon solar cell according to claim 2, characterized in that: The electron tunneling layer is formed by thermal oxidation.

4. A method for fabricating a hybrid back-contact n-type crystalline silicon solar cell, characterized in that, Includes the following steps: S100, Pre-treatment: After double-sided polishing of the crystalline silicon, the damaged layer is removed. The two sides of the crystalline silicon distributed along its own thickness direction are the light-receiving surface and the back-light surface, respectively. The back-light surface is divided into electron regions, insulating regions and hole regions that are distributed in sequence. S200, Preparation of electron collecting components, hole collecting components and anti-reflection passivation layer: Deposit an anti-reflection passivation layer on the light-receiving surface, and prepare electron collecting components and hole collecting components in the electron region and hole region respectively, so that an insulating gap is formed between adjacent electron collecting components and hole collecting components, which is directly opposite to the insulating region. S300, Fabrication of conductive components: A positive conductive layer and a negative conductive layer, processed from the same conductive film, are formed on the side of the electron collecting component facing away from the crystalline silicon and the side of the hole collecting component facing away from the crystalline silicon, respectively. A positive electrode and a negative electrode are formed on the side of the positive conductive layer and the negative conductive layer facing away from the crystalline silicon, respectively.

5. The method for preparing a hybrid back-contact n-type crystalline silicon solar cell according to claim 4, characterized in that: In step S200, the electron collecting component includes a stacked electron tunneling layer and an n-type semiconductor layer, and the hole collecting component includes a stacked hole passivation layer and a p-type semiconductor layer. The electron tunneling layer and the hole passivation layer are respectively stacked on the electron region and the hole region.

6. The method for fabricating a hybrid back-contact n-type crystalline silicon solar cell according to claim 5, characterized in that: In step S200, the electron tunneling layer is an oxidized electron tunneling layer.

7. The method for fabricating a hybrid back-contact n-type crystalline silicon solar cell according to claim 6, characterized in that: In step S200, an electron collection component is first formed, an anti-reflection passivation layer is then formed, and finally a hole collection component is formed.

8. The method for preparing a hybrid back-contact n-type crystalline silicon solar cell according to claim 7, characterized in that: Step S200 includes the following steps: S210, Thermal oxidation: The crystalline silicon obtained in S100 is thermally oxidized to form an electron tunneling sleeve on its surface. The electron tunneling sleeve includes an electron tunneling film stacked on the backlight surface and an electron tunneling cover that surrounds the electron tunneling film to form a cavity. The cavity wall of the cavity is sealed and fixedly connected to the outer surface of the crystalline silicon. S220, Deposit an n-type semiconductor film: Deposit an n-type semiconductor film on the side of the electron tunneling film obtained in S210 that is opposite to the crystalline silicon. During deposition, a PSG is formed on the outer surface of the n-type semiconductor film and the outer surface of the electron tunneling shield. S230, Removal of the coating: Remove the electron tunneling mask and the PSG corresponding to the light-receiving surface and circumferential outer edge of the crystalline silicon to retain the PSG corresponding to the n-type semiconductor film as a sacrificial layer. S240, Laser grooving: A laser is irradiated on the back side of the crystalline silicon to expose the insulating and hole regions. S250, Pre-deposition treatment: Remove the sacrificial layer to expose the n-type semiconductor layer; S260, Deposition of anti-reflection passivation layer: Deposition of anti-reflection passivation layer on the light-receiving surface; S270, Deposited Hole Composite Film: A hole passivation film and a p-type semiconductor film are sequentially deposited on one side of the backlight surface of crystalline silicon; S280, Laser Removal: A laser is irradiated on the back side of the crystalline silicon to expose the n-type semiconductor layer and the insulating region.

9. The method for fabricating a hybrid back-contact n-type crystalline silicon solar cell according to claim 8, characterized in that: In step S230, an alkaline solution is used to remove the corresponding electron tunneling shield and PSG, so that the light-receiving surface, the hole region and the insulating region form a velvety structure.

10. The method for preparing a hybrid back-contact n-type crystalline silicon solar cell according to claim 8, characterized in that: Step S300 includes the following steps: S310, Depositing a conductive film: Depositing a conductive film on the back side of crystalline silicon; S320, Remove excess film: Print etching paste at the position where the conductive film is directly opposite the insulating area, so that the conductive film is etched and divided into positive conductive layer and negative conductive layer that are spaced apart and stacked one-to-one with the n-type semiconductor layer and the p-type semiconductor layer, respectively. S330. Electrode fabrication: Metal electrodes are printed on the positive conductive layer and the negative conductive layer respectively to form a positive electrode connected to the positive conductive layer and a negative electrode connected to the negative conductive layer.

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