Voltage isolation integrated circuit package with backside transformer

Abstract

Aspects of the present disclosure include systems, structures, circuits, and methods of providing an integrated circuit (chip) package or module having a transformer disposed or mounted on an opposite side of a lead frame from an associated semiconductor die of the chip package. The transformer may be placed on the PCB structure. In some examples, an insulating coating may be disposed on the package to increase the isolation capability of the final package. The packages and modules may include various types of circuitry; in some examples, a chip package or module may include an electrically isolated gate driver or other high voltage circuit.

Description

BACKGROUND

[0001] Solid state switches typically include a transistor structure and are generally either fully on or fully off. The control electrode, often referred to as the gate (or base) of the switch, is typically controlled (driven) by a switch drive circuit (sometimes also referred to as a gate drive circuit). Such solid state switches are typically voltage controlled, turning on when the gate voltage exceeds a manufacturer-specific threshold voltage by a certain margin, and turning off when the gate voltage remains below the threshold voltage by a certain margin.

[0002] Switch drive circuits typically receive their control instructions from a controller, such as a pulse width modulation (PWM) controller, via one or more switch driver inputs. The switch drive circuit delivers its drive signals directly (or indirectly via a network of active and passive components) to the respective terminals (gate and source) of the switch.

[0003] Some electronic systems, including those having solid state switches, have employed electrical isolation to prevent unwanted DC current from flowing from one side of the isolation barrier to the other. Such electrical isolation can be used to separate circuits to protect users from direct contact with hazardous voltages.

[0004] Various transmission techniques can be used to send signals across an electrical isolation barrier, including optical, capacitive, and magnetic coupling techniques. Magnetic coupling typically relies on the use of a transformer (or variator) to magnetically couple circuits on different sides of the transformer (typically referred to as the primary side and the secondary side), while also providing electrical separation of the circuits.

[0005] Transformers used for magnetically coupling isolation barriers typically utilize a magnetic core (or magnetic core) to provide a magnetic path to direct flux generated by currents flowing in the primary and secondary sides of the transformer. Due to the inclusion of the magnetic core, magnetically coupled isolation barriers have proven to have various deficiencies, including manufacturing issues, for integrated circuit (IC) packages. SUMMARY

[0006] One aspect of the present disclosure includes a chip package for electrically isolating an integrated circuit (IC). The chip package can include a leadframe having a first side and a second side; first and second semiconductor dies (also referred to as IC dies) can be disposed on the first side of the leadframe; a molding material can be configured to cover a portion of the leadframe forming a package body; a ferromagnetic core can be disposed in the package body adjacent the second side of the leadframe; and first and second coils can be disposed in the package body configured around the ferromagnetic core in a transformer (or variator) configuration, each coil including a plurality of windings; wherein the first and second coils and the ferromagnetic core are disposed within the package body on the second side of the leadframe opposite the first side.

[0007] Implementations can include one or more of the following features. The chip package can include first and second die conductive portions (which can be referred to as die pads or die paddles) configured to receive / support the first and second dies, respectively, with the first and second semiconductor dies disposed on the first and second die pads, respectively. The first and / or second dies can include an integrated circuit (IC). The integrated circuit can include a gate driver circuit. The chip package can include an insulator material disposed between the first and second coils.

[0008] One general aspect includes a chip package comprising: a leadframe having a first side and a second side and configured to receive first and second semiconductor dies on the first side; a package body comprising a molding material and configured to cover a portion of the leadframe; a transformer core disposed in the package body on the second side of the leadframe; and first and second coils having windings disposed around the transformer core in a transformer configuration and disposed in the package body; wherein the first and second coils and the transformer core are disposable on the second side of the leadframe opposite the first side.

[0009] Implementations can include one or more of the following features. The chip package can include first and second semiconductor dies disposed on a first side of the leadframe. The first and second coils can be configured to magnetically couple the first and second semiconductor dies. The first and second semiconductor dies can each include a first and second integrated circuit (IC). The first or second integrated circuit (IC) can include a gate driver. The gate driver can be configured to receive power from the transformer. The gate driver can be configured to receive a control signal from the transformer. The first or second integrated circuit can include a gate driver. The chip package can include first and second die pads disposed on the first side of the leadframe and configured to receive / support the first and second semiconductor dies, respectively. The chip package can include a plurality of first wire bonds connecting the leadframe to the first semiconductor die. The chip package can include a plurality of second wire bonds connecting the leadframe to the second semiconductor die. A shortest distance between the plurality of first and second wire bonds (or, between the plurality of first wire bonds and the plurality of second wire bonds) can be at least 1 mm. The shortest distance between the plurality of first and second wire bonds can be at least 1.2 mm. The shortest distance between the plurality of first and second wire bonds can be at least 1.5 mm. The shortest distance between the plurality of first and second wire bonds can be at least 3 mm. The shortest distance between the plurality of first and second wire bonds can be at least 5.5 mm. The shortest distance between the plurality of first and second wire bonds can be at least 7.2 mm. The shortest distance between the plurality of first and second wire bonds can be at least 8 mm. The leadframe can include a partially etched leadframe portion / region. A shortest distance between the leadframe and a conductive portion of the transformer can be at least 1 mm. The shortest distance between the leadframe and the conductive portion of the transformer can be at least 1.2 mm. A shortest distance between first and second conductive portions of the leadframe can be at least 1.5 mm. The shortest distance between the first and second conductive portions of the leadframe can be at least 3 mm. The shortest distance between the first and second conductive portions of the leadframe can be at least 5.5 mm. The shortest distance between the first and second conductive portions of the leadframe can be at least 7.2 mm. The shortest distance between the first and second conductive portions of the leadframe can be at least 8 mm.

[0010] Another general aspect of the present disclosure includes a method of manufacturing an electrically isolated (voltage isolated) integrated circuit (IC) package. The method can include providing a leadframe having first and second sides and configured to receive first and second semiconductor dies; connecting the first and second semiconductor dies to the first side of the leadframe; disposing a transformer core on the second side of the leadframe; providing first and second coils disposed around the transformer core; and forming a package body covering the first and second semiconductor dies and the first and second coils disposed on the transformer core.

[0011] Implementations can include one or more of the following features. Forming the package body can include applying a molding material to cover the first and second semiconductor dies. Applying the molding material to cover the first and second semiconductor dies can include a first molding step, and can include applying the molding material to cover the first and second coils disposed on the transformer core as a second molding step. Forming the package body can include applying a molding material to cover the first and second coils disposed on the transformer core. The leadframe can include first and second die pads configured to receive the first and second semiconductor dies, respectively. The first and / or second semiconductor dies can include gate drivers for solid state devices. The solid state devices can include solid state power devices / switches. The solid state power devices / switches can include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), GaNFETs (Gallium Nitride Field Effect Transistors), SiCFETs (Silicon Carbide Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and / or the like. The first and second coils can be disposed about the transformer core and configured as a transformer that magnetically couples the first and second semiconductor dies while providing electrical separation between the semiconductor dies and any integrated circuits (ICs) included in either or both of the dies.

[0012] The features and advantages described herein are not all-inclusive; many additional features and advantages will be apparent to one of ordinary skill in the art in view of the following drawings, descriptions, and claims. Moreover, it should be noted that the language used in the specification is principally intended to be read in a context of readability and guidance rather than in a manner of limitation (which can have many embodiments). The following is an exemplary description of the scope of the disclosure, not an exhaustive list. BRIEF DESCRIPTION OF DRAWINGS

[0013] The manner and process (or processes) of making and using the disclosed embodiments can be understood by reference to the figures, each of which is referenced by figures. In the appended figures, the same components have the same numbers. However, similar components, elements, and steps / actions can have different numbers in different figures. It is to be understood that the components and structures shown in the figures are not necessarily drawn to scale, but rather emphasis is placed upon illustrating the principles of the concepts described herein. Moreover, the embodiments are shown by way of example, and not by way of limitation, in the figures, in which:

[0014] Figure 1A is a graphic showing a top view of an example voltage isolation integrated circuit package having a backside (or backside) transformer in accordance with the present disclosure;

[0015] Figure 1B is a side view of the integrated circuit package of Figure 1A ​

[0016] Figure 2 FIG. 1 is a diagram illustrating a side view of an example voltage isolation integrated circuit package having a backside transformer according to the present disclosure;

[0017] Figure 3 FIG. 2 is a diagram illustrating a side view of an example voltage isolation integrated circuit package having a backside transformer according to the present disclosure;

[0018] Figure 4 FIG. 3 is a diagram illustrating a side view of an example transformer and substrate structure according to the present disclosure; and

[0019] Figure 5 FIG. 4 is a block diagram illustrating steps in an example manufacturing method for a voltage isolation integrated circuit package having a backside transformer according to the present disclosure. DETAILED DESCRIPTION

[0020] The features and advantages described herein are not all-inclusive; numerous additional features and advantages will be readily apparent to one of ordinary skill in the art upon review of the drawings, description and claims. Moreover, it should be noted that the language used in the specification is principally intended for readability and guidance in understanding the subject technology and is not intended to limit the scope of the inventive subject matter. The subject technology can have many embodiments. The following is an exemplification of the subject technology and is not intended to limit the scope thereof in any way.

[0021] Aspects of the present disclosure relate to and include systems, structures, circuits, and methods of providing integrated circuit (IC) packages or modules having voltage isolation transformers implemented on a leadframe on opposite sides relative to an associated IC. The IC packages and modules can include various types of circuitry; in some examples, the IC packages or modules can include electrically isolated gate drivers or other high voltage circuitry, etc. First and second semiconductor dies (also referred to as "IC dies") having one or more integrated circuits can be included in the packages. Such integrated circuits can include, for example, but are not limited to, high voltage circuitry such as electrically isolated gate drivers configured to drive an external gate on a solid state switch (e.g., MOSFET, GaN FET, SiC FET, IGBT) or other load. Windings can be made up of or include a combination of pre-formed (or pre-shaped) metal components (e.g., leadframe, etc.) held by a suitable insulating material (e.g., a molded and / or potted compound). In some examples / embodiments, the transformer can be or include a printed circuit board (PCB) having metal vias and wire bonds over the core. In some examples / embodiments, the windings can be or include a combination of PCB traces and vias, with or without a top connection (part of the winding) as a wire bond; in other examples / embodiments, the top connection (part of the coil) can be made by similar PCB-like techniques and include PCB structures such as vias, traces, etc.

[0022] In some examples, the leadframe and / or circuit board can have additional polymer or insulating layers, for example, to meet given isolation requirements. In some examples, a printed circuit board (PCB) can be utilized instead with a substrate (e.g., alumina substrate). In examples, the primary and secondary (also referred to as first and second sides) of the transformer winding can be on opposite sides of the PCB or alumina substrate to increase voltage isolation. In some examples, wire bonds can be used to connect the windings to the dies. In some instances, one or more dies (dices) can be connected to the leadframe, circuit board (e.g., alumina or PCB), or flexible substrate such as polyimide or polyamide, for example, in a flip-chip manner. The dies or winding substrate can then be connected to the pins of the package by wire bonds or other suitable methods. In some examples, a solder bump or stud bump process can be used. If the dies are also connected to the board using a similar method, it can be preferable to select a solder or bump material such that the reflow process used to connect the winding substrate and the dies to the leads of the leadframe does not cause the dies to fall off the substrate.

[0023] In some examples, the final package or module can be coated with an insulator, or a strip of material can be added to the module or package to hold the core in place (or in position). A second molding (or a third molding, if the core is molded) of insulating material can also be used to secure the core and / or provide increased distance between the first and second sides of the ICs in the package (e.g., the high and low sides of the package). If a second or third molding is used, locking features can be made (formed) in the first molding to help secure the second (or third) molding.

[0024] Figure 1A is a graphic showing a top view of an example electrically isolated (voltage isolated) integrated circuit (chip) package 100 having a back transformer, in accordance with the present disclosure. A leadframe 101 includes regions or areas of electrically conductive material, such as 104 and 105, which can also be referred to as die pads or paddles. First and second semiconductor dies (also referred to as dies or die chips) 102 and 103 can be included in the package 100, such as mounted directly or indirectly on the die pads 104 and 105, respectively. The package 100 includes a body 110, which can be formed of or include an insulating and / or protective material 112, such as a molding material such as an epoxy molding material. The body 110 can include a transformer 120, which includes a core 122 and first and second coils (shown as 124, 126), respectively. The leadframe 101 can include first and second sets of leads (lead sets) 116 and 118, each set of leads including a plurality of leads that protrude from the package body 110. In some examples, the chip package (module) 100 can include or house, for example, an isolated gate driver or other high voltage application / integrated circuit (IC). In some examples, the core 122 can include a high permeability material, such as ferrite. In this graphic, the molding or insulating material is removed for visibility of the structures inside the package body 110. Figure 1B

[0025] As noted above, the package 100 can include a transformer 120. The transformer 120 can include a core 122 (e.g., a ferromagnetic core) and a plurality of coils (shown as 124, 126 in Figure 1B

[0026] Figure 1B ​​is a drawing showing a side view of the package 100 of Figure 1. The coils 124, 126 can include electrical connections (not shown) to the dies 102 and 103 and / or one or more ICs included in the dies 102, 103. The core 122 is shown in cross-section, with cross-sections 122a, 122b indicated. The coils 124, 126 are shown as configured on the core 122, wrapped around the cross-sections 122a, 122b.

[0027] Figure 2 is a drawing showing a side view of another example electrically isolated (voltage isolated) integrated circuit (IC, also referred to as a chip) package 200 having a backside transformer, in accordance with the present disclosure. The package 200 can include a leadframe 201 and first and second semiconductor dies 202, 203. The dies 202, 203 can be disposed on die pads 204, 205 (conductive portions) on one side of the leadframe 201 (directly or indirectly). A transformer 220 having a core 222 and first and second coils 224, 226 can be disposed on or connected to the leadframe on a side opposite the IC dies 202, 203. The coils 224, 226 can each have one or more windings made of a conductive material (e.g., wire) configured (e.g., wound or wrapped) around a portion of the core 222. The package 200 can include a body 206, which can be composed of or include a molding material, e.g., having first and second regions of molding material 207, 208 applied by one or more molding processes, respectively. The leadframe 201 can include first and second sets of leads (lead sets) 216, 218 extending from the body 206 (e.g., electrically connected to other circuitry, components, and / or systems external to the package 200).

[0028] DIEs 202, 203 can be connected to leads 216, 218, respectively, by electrical connections (e.g., wire bonds 251, 254). DIEs 202, 203 can also be connected to conductive portions (dies pads or "paddles") 204, 205 of lead frame 201 by electrical connections (e.g., wire bonds 252, 252). Alternatively, DIEs (chips) 202, 203 can be connected to lead frame 201 by solder bumps, copper pillars, or other electrical connections used in / for flip-chip or flip-chip-like processes. Conductive lead frame portions 204, 205, in turn, can be connected to coils 224, 226, respectively, by conductive pads 232, 234, as shown. In some examples, ICs configured or disposed in DIEs 202, 203 can function as primary and secondary circuits, respectively, having low and high voltage levels on different sides of an (electrical) isolation barrier provided by transformer 220, for example. In some examples and / or embodiments, the different sides of the (electrical) isolation barrier provided by transformer 220 can be referred to as the input (or primary) side and the secondary (or output) side, respectively.

[0029] In some examples and / or embodiments, other conductive features of the primary and secondary sides of transformer 220 in body 206 or integrated circuits (ICs) in DIEs 202, 203 can be fabricated or configured to have a desired separation distance (d) between certain portions or features, for example, to meet internal creepage or external clearance requirements for a given pollution level defined by certain safety standard organizations such as Underwriters Laboratories (UL) and the International Electrotechnical Commission (IEC). For example, the separation distance can be between the closest (voltage) points of the respective circuits, e.g., low voltage (primary) side and high voltage (secondary) side). For further examples, such separation distance can be the distance between any two voltage points between the primary and secondary sides, e.g., the distance dl between conductive lead frame portions (dies pads or paddles) 204 and 205, or the distance between DIE 202 and DIE 203 in Figure 2 The distance between DIE 202 and DIE 203 in 200, in respective examples, can be at least 1.2 mm, 1.4 mm, 1.5 mm, 3.0 mm, 4.0 mm, 5.5 mm, 7.2 mm, 8.0 mm, 10 mm, or 10+ mm. This distance between the conductive portions of the DIEs can include any insulator covering the conductors, e.g., the plastic coating of the wires / leads. Other distances (e.g., d2, d3, and / or d4) between components, assemblies, and / or features of package 200 can also be designed and implemented, for example, to meet desired internal voltage creepage or external clearance requirements.

[0030] As noted above, in some embodiments, the package 200 can include regions of first and second molding materials 207, 208, and each material can be applied by a separate (mold) molding process / step, thereby forming respective molded packages or bodies 207', 208' that together form the package 200. The first molded body 207' (including the dies 202, 203 and the die paddles 204, 205) can be formed such that the die paddles 204, 205 are not exposed at the edges / boundaries of the first molded body 207', and only the conductive pads 232, 234 of the back (exposed) face of the molded body 207' are exposed for connection to the transformer 220 included in the second molded body 208'. When the two molded bodies 207', 208' are connected (mated), the transformer 220 is connected to the dies 202, 203. The conductive pads 232, 234 can be selected / designed to have a desired shape and / or size, e.g., to facilitate obtaining a particular standoff distance. In some embodiments, the conductive pads 232, 234 can be fabricated to have a desired size and shape by selectively partially etching the leadframe 201.

[0031] A dielectric material (e.g., a gel) can be used to pot and / or protect a PCB system assembly, such as a power semiconductor package or module, to protect the dies and / or interconnects from environmental conditions and / or to provide dielectric insulation. In some examples, the dielectric material can include, but is not limited to, one or more of the following materials: DOWSIL TM DOWSIL EG-3810 dielectric gel (available from The Dow Chemical Corporation, also known as “Dow”) and DOWSIL EG-3896 dielectric gel (available from Dow) can be used to provide dielectric insulation for a PCB system assembly, such as a power semiconductor package or module. The DOWSIL EG-3810 dielectric gel is designed for a temperature range of -60°C to 200°C, while the DOWSIL EG-3896 dielectric gel is designed for a temperature range of -40°C to +185°C; both can be used to meet typical temperature ranges for automotive applications. TM DOWSIL EG-3896 dielectric gel (available from Dow) has the ability to provide isolation greater than 20 kV / mm. Other suitable gel materials can also or instead be used, e.g., to meet or facilitate meeting voltage isolation specifications required for a given package design. The DOWSIL EG-3810 dielectric gel is designed for a temperature range of -60°C to 200°C, while the DOWSIL EG-3896 dielectric gel is designed for a temperature range of -40°C to +185°C; both can be used to meet typical temperature ranges for automotive applications. TM DOWSIL EG-3810 dielectric gel is designed for a temperature range of -60°C to 200°C, while the DOWSIL EG-3896 dielectric gel is designed for a temperature range of -40°C to +185°C; both can be used to meet typical temperature ranges for automotive applications. TM DOWSIL EG-3810 dielectric gel is designed for a temperature range of -60°C to 200°C, while the DOWSIL EG-3896 dielectric gel is designed for a temperature range of -40°C to +185°C; both can be used to meet typical temperature ranges for automotive applications.

[0032] Figure 3is a graphic showing a side view of an example electrically isolated (voltage isolated) integrated circuit (IC) package 300 having a backside transformer utilizing a substrate in accordance with the present disclosure. Package 300 can include a leadframe 301 and a plurality of integrated circuits (ICs), also referred to as semiconductors, dies 302, 303. Dies 302, 303 can be disposed on die pads or paddles (electrically conductive portions) 304, 305 on one side of leadframe 301 (directly or indirectly). As shown, a transformer 320 having a core 322 and first and second coils 324, 326 can be disposed on or connected to leadframe 301 on a side opposite dies 302, 303. Coils 324, 326 can each have one or more windings made of an electrically conductive material (e.g., wire) configured around (e.g., wound around) a portion of core 322. Package 300 can include a body 306, which can be composed of or include a molding material, e.g., having regions of first and second molding materials 307, 308 applied by one or more molding processes, respectively. Leadframe 301 can include first and second sets of leads (lead sets) 316, 318 extending from body 306 (e.g., electrically connected to other circuits, components, and / or systems external to package 300).

[0033] As previously mentioned, in some embodiments, package 300 can include regions of first and second molding materials 307, 308, and each material can be applied by a separate (mold) molding process / step, thereby forming respective molded packages or bodies 307', 308', which together form package 300. First molded body 307' (including dies 302, 303 and die paddles 304, 305) can be formed such that die paddles 304, 305 are not exposed at the edges / boundaries of first molded body 307', and only electrically conductive pads 332, 334 of the back (exposed) face of molded body 307' are exposed for connection to transformer 320, which is included in second molded body 308'. When the two molded bodies 307', 308' are connected (mated), transformer 320 is connected to dies 302, 303. Electrically conductive pads 332, 334 can be selected / designed to have a desired shape and / or size, e.g., to facilitate obtaining a particular standoff distance. In some embodiments, electrically conductive pads 332, 334 can be fabricated to have a desired size and shape by selectively partially etching leadframe 301.

[0034] Dies 302 and 303 can be connected to leads 316 and 318 via electrical connectors 351 and 354, respectively. Dies 302 and 303 can also be connected, for example, to conductive portions 304 and 305 of leadframe 301 via wire bonds 253 and 353, which in turn can be connected to coils 324 and 326 via conductive structures described below for substrate 350. In some examples, the IC configured or disposed in IC dies 302 and 303 can be used as, for example, primary and secondary circuits having low and high voltage levels respectively on different sides of a (magnetic) isolation barrier provided by transformer 320.

[0035] As shown in the figure, the package 300 may include a substrate 350 to facilitate mounting or connecting the transformer 320 to the lead frame 301. In some examples, the substrate 350 may include a printed circuit board (PCB) or an alumina substrate. The transformer core 322 may use insulating materials 366, 368 (e.g., made of...) Insulating strips made of other polyimide materials, or non-conductive epoxy resin, etc., and conductive traces / regions 362, 364 are mounted to the substrate 350. In some examples (e.g., embodiments utilizing flip-chip mounting), the substrate 350 may be mounted to the lead frame 301 using solder bumps (or copper pillars) 382, ​​384, for example, at raised regions 332, 334 of conductive portions 304, 305 of the lead frame 301. Coils 324, 326 may include portions formed by conductive traces 362, 364, respectively, and other portions comprising, or consisting of, wires 363, 365 (or composed of wires 363, 365), respectively. Optional dielectric gel and / or potting material 372, 374 may be used to protect and / or insulate the transformer structure. In other examples and embodiments, the transformer may be fabricated in a PCB or flexible circuit board, except in, for example... Figure 4 Apart from the windings fabricated in the PCB or flexible substrate shown, there are no other windings.

[0036] Figure 4 This is a drawing showing a side view of an example transformer and substrate structure 400 according to the present disclosure. Structure 400 may include a substrate 401 to which a transformer 420 is mounted. The transformer 420 may include a core 422 and coils 424, 426. The substrate 401 may include conductive regions or traces 402, 403 on or near a first side and separate conductive regions or traces 404, 405, 406 and 407 on or near a second side. Vias (e.g., conductive pillars) 410, 411, 412 and 413 within the substrate 401 may connect the conductive regions / traces on different sides of the substrate 401. Although dual (two-layer) vias are shown, other examples / embodiments may include one or more single-layer vias or vias having more than two layers.

[0037] As shown, the coils 424, 426 can include or be composed of multiple components / elements. For example, the coil 424 can include a wire (winding) portion 425, a conductive trace 404, a via 410, a conductive trace 402, a via 411, and a conductive trace 405. Similarly, the coil 426 can include a wire (winding) portion 427, a conductive trace 406, a via 412, a conductive trace 403, a via 413, and a conductive trace 407. Thus, in operation of the transformer 420, the structure 400 can be used to provide an electrical isolation barrier, and the magnetic coupling and electrical isolation are connected to two circuits (e.g., ICs residing in the dies 302, 303 in Figure 3

[0038] Figure 5 is a block diagram illustrating steps in an example method 500 for a voltage isolation (electrical isolation) integrated circuit (chip) package with a backside transformer, in accordance with the present disclosure. For the method 500, a leadframe can be provided having a first side and a second side and configured to receive first and second semiconductor dies, as described at 502. The first and second semiconductor dies can be connected to the first side of the leadframe, as described at 504.

[0039] Continuing the description of the method 500, a transformer (ferromagnetic) core can be disposed (connected) to the second side of the leadframe, as described at 506. First and second coils can be disposed around the transformer core, with the coils and core configured as a transformer, as described at 508. In some examples, the transformer core and coils can be mounted on or implemented with a substrate, such as a PCB or an alumina substrate, mounted to the leadframe. In some examples, one or more portions of each coil can be composed of or include conductive traces of the substrate. A package body can be formed to cover the first and second semiconductor dies and the first and second coils disposed on the ferromagnetic core, as described at 510.

[0040] ​In some embodiments, forming the package body (e.g., by step 510) can include a multi-step molding process. For example, the first and second molding materials for the package body can each be applied by separate (mold) molding processes / steps, thereby forming respective molded packages or moldings, which together can form the package body. For example, a first molding can be formed from the first molding material (including the die and die paddle), such that the die paddle is not exposed at the edges / boundaries of the first molding, with only the conductive pads exposed at the back of the first molding for connection to the transformer included in the second molding. When the two moldings are connected (mated), the transformer is electrically connected to the semiconductor die in the first molding. The conductive pads can be selected / designed to have a desired shape and / or size, e.g., to facilitate obtaining a particular standoff distance. In some embodiments, the conductive pads can be manufactured to have a desired size and shape by selectively partially etching the leadframe of the first molding.

[0041] Accordingly, embodiments of the inventive subject matter can provide various advantages over prior art. For example, embodiments and examples of the present disclosure can enable or facilitate the use of smaller size packages for a given power or voltage level. Embodiments and examples of the present disclosure can enable or facilitate lower cost and higher scalability of manufacturing IC packages / modules having voltage-isolated IC dies and transformers.

[0042] Various embodiments of the claimed concepts, systems, devices, structures, and techniques are described above with reference to the associated drawings. Alternative embodiments can be devised without departing from the scope of the claimed concepts, systems, devices, structures, and techniques. For example, while some examples are described herein as having transformer cores arranged in a direction perpendicular to the epitaxial direction of the die (i.e., parallel to the substrate direction), other examples and embodiments can have cores arranged parallel to the epitaxial direction (i.e., perpendicular to the substrate direction). For further example, while embodiments and examples are described herein as generally including two transformer windings (coils), examples and embodiments of the present disclosure can include different numbers of transformer windings, including but not limited to: one, three, four, five, etc.; further, the windings (coils) themselves can each have an integer or fractional number of turns (loops around the associated core or structure intended for receiving the core), e.g., 1.5, 2.5, 1.75, 1.8, 2.25, etc.

[0043] Note that various connections and positional relationships (e.g., above, below, left, right, left of, right of, side, behind, in front of, into, and / or the like) can be described in the specification and in the drawings. These connections and / or positional relationships can be direct or indirect, and the described

[0044] As an example of an indirect positional relationship, a component "A" positioned above component "B" can include instances where one or more intermediate components (e.g., component "C") are positioned between component "A" and component "B" such that the relative position of component "A" to component "B" is not changed by the presence of the intermediate components "C".

[0045] Furthermore, the following clauses apply to the claims and the specification. The terms "comprise," "comprising," "include," "including," "have," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0046] In addition, the term "exemplary" means "serving as an example, instance, or illustration." Any implementation or design described as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations or designs. The terms "one or more" and "at least one" indicate that any integer of 1 or more, i.e., one, two, three, four, etc. The term "plurality" indicates any integer of more than one. The term "connected" can include "indirectly connected" and "directly connected."

[0047] References in the specification to "an embodiment," "one embodiment,” "a(n) embodiment,” "example embodiment,” "exemplary embodiment,” "example,” "instance,” “aspect,” or the like, indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the purview of one of ordinary skill in the art to effect such feature, structure, or characteristic in connection with other

[0048] Relative or positional terms such as“upper,”“lower,”“right,”“left,”“vertical,”“horizontal,”“top,”“bottom,” and derivatives of these terms, including their derivatives, relate to the described structures and methods as oriented in the drawings. The terms“overlying,”“on top of,”“on,” “positioned on” or“positioned on top of” mean that a first element is present on top of a second element, where intervening elements can be present between the first element and the second element. The term“direct contact” means that a first element and a second element are connected without any intermediary elements.

[0049] The use of ordinal terms such as“first,”“second,”“third,” etc. in the claims to modify a claim element does not imply any priority, precedence or sequence of one claim element over another claim element, or of a temporal sequence of acts of a method, but is used merely as labels to identify elements of the claims with particular names. Unless otherwise indicated, the use of relational terms such as“associated with,”“associated therewith,” etc., are taken to mean a causal relationship, a spatial relationship, a temporal relationship, or any combination of these or other types of relationships.

[0050] The terms“about” and“approximately” can be used to indicate that in some embodiments, the value is within ±20% of the target value, in some embodiments, within ±10% of the target value, in some embodiments, within ±5% of the target value, and in some embodiments, even within ±2% of the target value. The terms“about” and“approximately” can encompass the target value. The term“substantially equal to” can be used to indicate that in some embodiments, the values are within ±20% of each other, in some embodiments, within ±10% of each other, in some embodiments, within ±5% of each other, and in some embodiments, even within ±2% of each other.

[0051] The term“substantially” can be used to indicate that in some embodiments, the value is within ±20% of the comparison measurement (value), in some embodiments, within ±10%, in some embodiments, within ±5%, and in some embodiments, even within ±2%. For example, a first direction that is“substantially perpendicular” to a second direction can indicate that in some embodiments, the first direction is within ±20% of a 90° angle to the second direction, in some embodiments, within ±10% of a 90° angle to the second direction, in some embodiments, within ±5% of a 90° angle to the second direction, and in some embodiments, even within ±2% of a 90° angle to the second direction.

[0052] The disclosed subject matter is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways.

[0053] Furthermore, the phraseology and terminology used by the present disclosure are for the purpose of description and should not be regarded as limiting. Thus, the concepts underlying the present disclosure can be readily employed as a basis for the design and construction of other structures, methods and systems for carrying out the several purposes of the disclosed subject matter. Accordingly, the claims should be regarded as including such equivalent constructions insofar they do not depart from the spirit and scope of the disclosed subject matter.

[0054] While the disclosed subject matter has been described and illustrated in the foregoing illustrative embodiments, it is understood that the present disclosure is by way of example only and that numerous changes in the details of embodiments of the disclosed subject matter can be made without departing from the spirit and scope of the disclosed subject matter.

[0055] The scope of the present patent should therefore not be limited to the described embodiments, but should only be limited by the spirit and scope of the claims that follow.

[0056] All publications and references cited in this patent are expressly incorporated herein by reference in their entirety.

Claims

1. A chip package for electrically isolated integrated circuits (ICs), the chip package comprising: A lead frame having a first side and a second side; A first semiconductor die and a second semiconductor die are disposed on the first side of the lead frame; Molding material configured to cover a portion of the lead frame and form the package body; A ferromagnetic core is disposed in the package body on the second side adjacent to the lead frame; as well as A first coil and a second coil are arranged in the package body around the ferromagnetic core in a transformer configuration, each coil including multiple windings; The first coil, the second coil, and the ferromagnetic core are disposed on the second side of the lead frame opposite to the first side within the package body.

2. The chip package according to claim 1 further includes a first die pad and a second die pad, wherein the first semiconductor die and the second semiconductor die are respectively disposed on the first die pad and the second die pad.

3. The chip package according to claim 2, wherein, The first and / or second die includes an integrated circuit.

4. The chip package according to claim 3, wherein, The integrated circuit includes a gate driver circuit.

5. The chip package according to claim 1 further includes an insulating material disposed between the first coil and the second coil.

6. A chip package comprising: A lead frame having a first side and a second side and configured to receive a first semiconductor die and a second semiconductor die on the first side; A package body comprising molding material and configured to cover a portion of the lead frame; A transformer core is disposed on the second side of the lead frame within the package body; as well as A first coil and a second coil having windings are arranged in a transformer configuration around the transformer core and disposed within the package body; The first coil, the second coil, and the transformer core are disposed on the second side of the lead frame opposite to the first side.

7. The chip package according to claim 6 further includes a first semiconductor die and a second semiconductor die disposed on the first side of the lead frame.

8. The chip package according to claim 7, wherein, The first coil and the second coil are configured to magnetically couple the first semiconductor die and the second semiconductor die.

9. The chip package according to claim 8, wherein, The first semiconductor die and the second semiconductor die respectively include a first integrated circuit and a second integrated circuit.

10. The chip package according to claim 9, wherein, The first integrated circuit or the second integrated circuit includes a gate driver.

11. The chip package according to claim 10, wherein, The gate driver is configured to receive power from the transformer.

12. The chip package according to claim 10, wherein, The gate driver is configured to receive control signals from the transformer.

13. The chip package of claim 7, further comprising a first die pad and a second die pad disposed on a first side of the lead frame and configured to receive the first semiconductor die and the second semiconductor die, respectively.

14. The chip package according to claim 6, wherein, The lead frame includes a partially etched lead frame.

15. The chip package according to claim 6, wherein, The shortest distance between the lead frame and the conductive part of the transformer is at least 1 mm.

16. The chip package according to claim 6, wherein, The shortest distance between the lead frame and the conductive part of the transformer is at least 1.2 mm.

17. The chip package according to claim 6, wherein, The shortest distance between the first conductive portion and the second conductive portion of the lead frame is at least 1.5 mm.

18. The chip package according to claim 6, wherein, The shortest distance between the first conductive portion and the second conductive portion of the lead frame is at least 3 mm.

19. The chip package according to claim 6, wherein, The shortest distance between the first conductive portion and the second conductive portion of the lead frame is at least 5.5 mm.

20. The chip package according to claim 6, wherein, The shortest distance between the first conductive portion and the second conductive portion of the lead frame is at least 7.2 mm.

21. The chip package according to claim 6, wherein, The shortest distance between the first conductive portion and the second conductive portion of the lead frame is at least 8 mm.

22. The chip package of claim 7, further comprising a plurality of first wire bonding members connecting the lead frame to the first semiconductor die.

23. The chip package of claim 22, further comprising a plurality of second wire bonding members connecting the lead frame to the second semiconductor die.

24. The chip package according to claim 23, wherein, The shortest distance between the plurality of first wire bonding members and the plurality of second wire bonding members is at least 1 mm.

25. The chip package according to claim 23, wherein, The shortest distance between the plurality of first wire bonds and the plurality of second wire bonds is at least 1.2 mm.

26. The chip package according to claim 23, wherein, The shortest distance between the plurality of first wire bonding members and the plurality of second wire bonding members is at least 1.5 mm.

27. The chip package according to claim 23, wherein, The shortest distance between the plurality of first wire bond members and the plurality of second wire bond members is at least 3 mm.

28. The chip package according to claim 23, wherein, The shortest distance between the plurality of first wire bond members and the plurality of second wire bond members is at least 5.5 mm.

29. The chip package according to claim 23, wherein, The shortest distance between the plurality of first wire bonds and the plurality of second wire bonds is at least 7.2 mm.

30. The chip package according to claim 23, wherein, The shortest distance between the plurality of first wire bonding members and the plurality of second wire bonding members is at least 8 mm.

31. The chip package according to claim 9, wherein, The first integrated circuit or the second integrated circuit includes a gate driver.

32. A method for manufacturing an electrically isolated integrated circuit (IC) package, the method comprising: A lead frame having a first side and a second side and configured to receive a first semiconductor die and a second semiconductor die is provided; Connect the first semiconductor die and the second semiconductor die to the first side of the lead frame; A transformer core is disposed on the second side of the lead frame; Provides a first coil and a second coil arranged around the transformer core; and A package body is formed, the package body covering the first semiconductor die and the second semiconductor die, as well as the first coil and the second coil disposed on the transformer core.

33. The method according to claim 32, wherein, Forming the package body includes applying a molding material to cover the first semiconductor die and the second semiconductor die.

34. The method according to claim 32, wherein, Forming the package body includes applying molding material to cover the first coil and the second coil disposed on the transformer core.

35. The method according to claim 33, wherein, Applying molding material to cover the first semiconductor die and the second semiconductor die includes applying a first molding material as a first molding step, and the method further includes applying a second molding material as a second molding step to cover the first coil and the second coil disposed on the transformer core.

36. The method according to claim 32, wherein, The lead frame includes a first die pad and a second die pad configured to receive the first semiconductor die and the second semiconductor die, respectively.

37. The method according to claim 32, wherein, The first semiconductor die and / or the second semiconductor die include a gate driver for a solid-state device.

38. The method according to claim 37, wherein, The solid-state devices include solid-state power devices.

39. The method according to claim 38, wherein, The solid-state power devices include MOSFETs, GaNFETs, SiCFETs, or IGBTs.

40. The method according to claim 32, wherein, The first coil and the second coil arranged around the transformer core are configured as a transformer that magnetically couples the first semiconductor die and the second semiconductor die.

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