High-integration low-power consumption system-level industrial 5GAIoT chip

Abstract

The invention relates to the technical field of integrated circuit design and Internet of Things, in particular to a high-integration-level low-power-consumption system-level industry 5G AIoT chip which comprises a multi-core heterogeneous computing module, a high-integration-level radio frequency front-end module, a low-power-consumption storage and data management module and a power management and dynamic power consumption optimization module. The multi-core heterogeneous computing module comprises a reduced instruction set-V (RISC-V) core which is used as a main control core, adopts a 64-bit architecture and is used for task scheduling and system management; a dedicated AI acceleration core is based on in-memory computing (CIM) technology. According to the high-integration-level low-power-consumption system-level industry 5G AIoT chip, miniaturization, low power consumption and function diversification of industry terminal equipment are achieved by integrating a multi-core calculation module, a high-integration radio frequency module, a low-power-consumption storage module and an intelligent power management module, and the high-integration-level low-power-consumption system-level industry 5G AIoT chip is particularly suitable for 5G Internet of Things terminals of industry scenes such as industrial monitoring, intelligent power grids and intelligent cities; and the integrated functions of communication, calculation, storage and power management can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design and Internet of Things technology, and particularly relates to a high-integration low-power system-level industry 5G AIoT chip. BACKGROUND

[0002] With the deep integration of 5G technology and Internet of Things (AIoT), industry terminal devices have higher requirements for the integration, power consumption and functional adaptability of chips. The prior art has the following shortcomings: 1. Function dispersion: 5G communication, AI calculation, and radio frequency processing functions need to be implemented by multiple chips, resulting in large terminal device size, high hardware cost, and difficulty in adapting to small-scale scenarios such as industrial sensors; 2. Insufficient power consumption control: general-purpose chips do not optimize power management for industry scenarios, resulting in high power consumption in idle state and short battery life of battery-powered devices; 3. Poor scene adaptability: the AI acceleration unit architecture is fixed and cannot flexibly adapt to different industry model operation requirements; the radio frequency front-end and antenna design are independent, resulting in large link loss and affecting communication distance and stability; To solve the above problems, the present application provides a high-integration low-power system-level industry 5G AIoT chip. SUMMARY

[0003] The main purpose of the present application is to provide a high-integration low-power system-level industry 5G AIoT chip, which can effectively solve the problems in the background art.

[0004] To achieve the above purpose, the technical solution adopted by the present application is as follows: A high-integration low-power system-level industry 5G AIoT chip, comprising a multi-core heterogeneous computing module, a high-integration radio frequency front-end module, a low-power storage and data management module, and a power management and dynamic power consumption optimization module, The multi-core heterogeneous computing module comprises: A reduced instruction set (RISC-V) core as a main control core, adopting a 64-bit architecture for task scheduling and system management; A special AI acceleration core based on in-memory computing (CIM) technology, adopting a mixed analog-digital circuit design with a 22nm process, supporting sparse matrix operation for accelerating edge AI tasks; A 5G baseband processing core supporting Sub-6GHz frequency bands, adopting filter bank multi-carrier (FBMC) technology for 5G signal processing; The high-integration radio frequency front-end module comprises: Power amplifier (PA), low noise amplifier (LNA), switch and filter integrated on a single chip; Envelope tracking (ET) circuit for dynamically adjusting the supply voltage of the PA according to the signal envelope; On-chip antenna (AiP) operating in the 600MHz-6GHz frequency band; The low-power storage and data management module includes a multi-level storage architecture including a cache (SRAM) and an embedded flash memory (eFlash); The storage compression and cache prefetch unit is used for data compression and cache optimization; Hardware data encryption engine supporting national encryption SM4 and AES-256 encryption algorithms; The power management and dynamic power optimization module includes a multi-power domain circuit that divides the chip into independent power domains for computing, radio frequency, and storage, and supports individual switching control; Adaptive dynamic voltage and frequency scaling (DVFS) circuit for adjusting core voltage and frequency according to task load; Energy harvesting interface supporting thermoelectric and photovoltaic energy harvesting methods.

[0005] Preferably, the RISC-V core supports dynamic instruction cache management, including: Hardware prefetcher for analyzing spatial and temporal locality of instruction streams and dynamically adjusting prefetch depth to 2-8 instructions; Adaptive replacement policy (ARC) unit for maintaining cache block priority; Instruction compression decoder for 2:1 compression storage of high-frequency instructions (accounting for ≥60%).

[0006] Preferably, the AI acceleration core adopts a reconfigurable computing architecture, including: A two-dimensional array composed of 128 basic computing units (PEs), each PE supporting integer / floating point mixed operations (INT8 / FP16), and realizing data routing between PEs through a configurable interconnection network, with a reconfiguration granularity supporting 4x4, 8x8, and 16x16 operation blocks; Dynamic computing power scheduler for dividing the PE array into 1-4 independent computing clusters according to the real-time load of AI tasks to realize multi-task parallel processing; Model compression engine supporting weight quantization (4bit / 2bit) and channel pruning (pruning rate dynamically configurable 0-50%), and optimizing data paths through hardware-accelerated model reconstruction graph.

[0007] Preferably, the 5G baseband processing core supports multi-band carrier aggregation (3CC) and high-order modulation (256QAM / 1024QAM), including: A channel estimation and equalization unit based on deep learning, which internally contains a lightweight neural network with 256 neurons; A dynamic spectrum sensing module for identifying idle spectrum resources with a bandwidth ≥ 5MHz and implementing fast switching (switching time ≤ 5ms).

[0008] Preferably, the filters of the radio frequency front-end module adopt a hybrid design of surface acoustic wave (SAW) and bulk acoustic wave (BAW): SAW structure for frequency bands below 3GHz, and BAW structure for frequency bands above 3GHz; the PA adopts a multi-mode configurable architecture, supporting low power (5~15dBm), medium power (15~23dBm), and high power (23~26dBm) switching; the LNA integrates a dynamic bias circuit for adjusting the bias current (1mA~5mA) according to the input signal strength (-110dBm~-50dBm).

[0009] Preferably, the SRAM of the low-power storage and data management module adopts a unit circuit containing a dual-threshold voltage transistor (VT) and a polysilicon resistance load; the eFlash adopts a charge trap type (CTF) storage unit, supporting page-based operations (256B per page).

[0010] Preferably, it also includes an edge intelligence collaboration module for distributed computing with peripheral devices, implementing task offloading and result feedback through the 5G network.

[0011] Preferably, the power management module integrates an on-chip temperature sensor for adjusting the cooling strategy according to the chip temperature.

[0012] Preferably, the chip is manufactured using a 22nm FD-SOI process, with a chip area ≤ 10mm 2 , which is 30% smaller than similar functional chips.

[0013] Preferably, the cache (SRAM) capacity is 2MB, and the embedded flash memory (eFlash) capacity is 8MB.

[0014] Compared with the prior art, the present application has the following beneficial effects: 1. High integration: integrating computing, communication, radio frequency, storage, and other functions on a single chip, reducing dependence on external components, and reducing the size and hardware cost of terminal devices; 2. Low power consumption characteristics: through multi-power domain management, adaptive DVFS and energy collection technology, reduce the power consumption of the chip under different loads, prolong the endurance time of the battery powered device; 3. Strong functional adaptability: AI acceleration core supports reconfigurable computing, 5G baseband supports multi-band processing, can meet the functional requirements of different industry scenarios such as industry and agriculture; 4. Improve communication reliability: integrate RF front-end and on-chip antenna, shorten signal link, reduce loss, improve communication stability. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 The overall module composition diagram of the high-integration and low-power system-level industry 5G AIoT chip; Figure 2 The internal flow chart of the multi-core heterogeneous computing module of the high-integration and low-power system-level industry 5G AIoT chip; Figure 3 The RF front-end and storage management flow chart of the high-integration and low-power system-level industry 5G AIoT chip. DETAILED DESCRIPTION

[0016] In order to make the technical means, creative features, purposes and effects realized by the present application easy to understand, the following will further describe the present application in combination with the drawings and specific embodiments.

[0017] A high-integration and low-power system-level industry 5G AIoT chip, comprising the following modules: 1. Multi-core heterogeneous computing module RISC-V main control core: adopting 64-bit architecture, as the main controller of the chip, responsible for task scheduling, system management and peripheral control, supporting data interaction with other modules; AI acceleration core: based on in-memory computing (CIM) technology, adopting 22nm analog-digital hybrid circuit design, containing computing unit and storage array integrated structure, supporting sparse matrix operation, which can accelerate edge AI tasks (such as feature extraction, pattern recognition); 5G baseband processing core: supporting Sub-6GHz frequency band, adopting filter bank multi-carrier (FBMC) technology, used for 5G signal modulation and demodulation, channel coding and data transmission processing.

[0018] 2. High-integration RF front-end module Integrated RF components: single-chip built-in power amplifier (PA), low-noise amplifier (LNA), RF switch and filter, forming a complete RF signal link; Envelope tracking circuit: connected to the PA power supply terminal, can dynamically adjust the supply voltage of the PA according to the envelope of the input radio frequency signal; Antenna-in-package (AiP): operating frequency range covers 600MHz~6GHz, connected to the radio frequency front-end through internal wiring on the chip, used for the transmission and reception of radio frequency signals.

[0019] 3. Low-power storage and data management module Multi-level storage architecture: including 2MB cache (SRAM) and 8MB embedded flash (eFlash), SRAM for temporary data caching, eFlash for program and fixed data storage; Storage optimization unit: contains storage compression module and cache prefetch module, storage compression module for compression processing of written data, cache prefetch module for loading data in advance according to data access regularity; Hardware encryption engine: supports SM4 algorithm and AES-256 algorithm, used for encryption processing of storage data and transmission data.

[0020] 4. Power management and dynamic power optimization module Multi-power domain circuit: divides the chip into computing domain (including RISC-V core, AI acceleration core), radio frequency domain (including radio frequency front-end), storage domain (including storage module), each power domain is independently configured with power switch; Adaptive DVFS circuit: connected to the power supply terminal of each core, can adjust the working voltage and clock frequency according to the running load of the core; Energy harvesting interface: contains rectifier circuit and energy management unit, supports external energy input such as thermoelectricity and photovoltaic, provides auxiliary power supply for the chip.

[0021] 5. Auxiliary function module Edge intelligence collaboration module: connected to 5G baseband and main control core through internal bus, used for establishing data interaction with external devices, realizing task offloading and result feedback; Temperature sensing and protection module: contains on-chip temperature sensor and control logic, can monitor the chip temperature and trigger corresponding heat dissipation control instructions (such as core frequency reduction).

[0022] Industry application examples: In the industrial monitoring scene, the chip receives sensor data through the on-chip antenna, the 5G baseband processing core transmits the data to the RISC-V core, the core calls the AI acceleration core for anomaly detection, and the detection result is uploaded to the monitoring platform through the 5G network after encryption; when the chip temperature exceeds 80℃, the temperature sensing module triggers the AI acceleration core to reduce the frequency, ensuring stable operation.

[0023] In summary, the high-integration low-power system-level industry 5G AIoT chip of the application, the chip includes a multi-core heterogeneous computing module (including a RISC-V main core, an AI acceleration core, and a 5G baseband), a high-integration radio frequency front-end module (including an integrated radio frequency component, an envelope tracking circuit, and an on-chip antenna), a low-power storage and data management module (including a multi-level storage, an encryption engine), and a power management module (including a multi-power domain, a DVFS circuit, and an energy harvesting interface). The application realizes the integration of 5G communication, edge AI calculation, data storage, and low-power management through high-integration design, is suitable for industrial monitoring and other industry scenarios, and can reduce the size and power consumption of terminal equipment.

[0024] The above shows and describes the basic principles and main features of the application and the advantages of the application. Those skilled in the art should understand that the application is not limited to the above examples, and the above examples and descriptions in the specification are only to illustrate the principles of the application. Without departing from the spirit and scope of the application, various changes and improvements can be made to the application, and these changes and improvements all fall within the scope of the claimed application. The scope of protection of the application is defined by the appended claims and their equivalents.

Claims

1. A high-integration low-power system-level industry 5G AIoT chip, comprising a multi-core heterogeneous computing module, a high-integration radio frequency front-end module, a low-power storage and data management module, and a power management and dynamic power optimization module, characterized in that: the multi-core heterogeneous computing module comprises: a reduced instruction set (RISC-V) core as a main control core, adopting a 64-bit architecture, for task scheduling and system management; a special AI acceleration core based on compute-in-memory (CIM) technology, adopting a mixed analog-digital circuit design of 22 nm process, supporting sparse matrix operation, for accelerating edge AI tasks; a 5G baseband processing core supporting Sub-6GHz frequency bands, adopting filter bank multi-carrier (FBMC) technology, for 5G signal processing; the high-integration radio frequency front-end module comprises: power amplifiers (PAs), low-noise amplifiers (LNAs), switches, and filters integrated in a single chip; an envelope tracking (ET) circuit for dynamically adjusting the supply voltage of the PA according to the signal envelope; an antenna-in-package (AiP) operating at 600MHz-6GHz frequency bands; the low-power storage and data management module comprises a multi-level storage architecture including cache memory (SRAM) and embedded flash memory (eFlash); a storage compression and cache prefetch unit for data compression and cache optimization; a hardware data encryption engine supporting national encryption SM4 and AES-256 encryption algorithms; the power management and dynamic power optimization module comprises a multi-power domain circuit dividing the chip into computing, radio frequency, and storage independent power domains, supporting individual switching control; an adaptive dynamic voltage and frequency scaling (DVFS) circuit for adjusting core voltage and frequency according to task load; an energy harvesting interface supporting thermoelectric and photovoltaic energy harvesting methods. 2.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: The RISC-V core supports dynamic instruction cache management, including: a hardware prefetcher for analyzing the spatial and temporal locality of instruction streams and dynamically adjusting the prefetch depth to 2-8 instructions; an adaptive replacement policy (ARC) unit for maintaining cache block priorities; an instruction compression decoder for 2:1 compression storage of high-frequency instructions. 3.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: The AI acceleration core adopts a reconfigurable computing architecture, including: a two-dimensional array composed of 128 basic computing units (PEs), each PE supporting integer / floating-point mixed operations (INT8 / FP16) and realizing data routing between PEs through a configurable interconnection network, with a reconfiguration granularity supporting 4x4, 8x8, and 16x16 operation blocks; a dynamic computing power scheduler for dividing the PE array into 1-4 independent computing clusters according to the real-time load of AI tasks, realizing multi-task parallel processing; a model compression engine supporting weight quantization (4bit / 2bit) and channel pruning, and optimizing data paths through hardware-accelerated model reconstruction graph. 4.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: The 5G baseband processing core supports multi-band carrier aggregation (3CC) and high-order modulation (256QAM / 1024QAM), including: Channel estimation and equalization unit based on deep learning, with a built-in lightweight neural network containing 256 neurons; Dynamic spectrum sensing module for identifying idle spectrum resources with a bandwidth ≥ 5MHz and enabling fast switching. 5.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: The filter of the radio frequency front-end module adopts a hybrid design of surface acoustic wave (SAW) and bulk acoustic wave (BAW): SAW structure for frequency bands below 3GHz, and BAW structure for frequency bands above 3GHz; The PA adopts a multi-mode configurable architecture, supporting low, medium, and high power switching; The LNA integrates a dynamic bias circuit for adjusting the bias current according to the input signal strength. 6.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: The SRAM of the low-power storage and data management module adopts a unit circuit containing dual-threshold voltage transistors (VT) and polysilicon resistance load; The eFlash adopts a charge trap type (CTF) storage unit, supporting page operation. 7.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: It also includes an edge intelligence collaboration module for distributed computing with surrounding devices, task offloading and result feedback through the 5G network. 8.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: The power management module integrates an on-chip temperature sensor for adjusting the cooling strategy according to the chip temperature. 9.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: The chip is manufactured by 22nm FD-SOI process, and the chip area is ≤10mm 2 . 10.The high-integration and low-power consumption system-level industry 5G AIoT chip of claim 1, wherein: The cache (SRAM) capacity is 2MB, and the embedded flash memory (eFlash) capacity is 8MB.

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