A multimodal large model driven circuit diagram generation spice netlist method

Abstract

The application discloses a kind of multi-modal large model driven circuit diagram generation SPICE netlist method, comprising: complete from circuit image to the construction of SPICE netlist dataset;Supervision fine-tuning is carried out to circuit conversion netlist model;Trajectory-guided reinforcement learning phase's step-by-step inference paradigm;Trajectory-guided reinforcement learning phase's multilevel reward mechanism respectively from inference quality, the accuracy of generated netlist and logic consistency aspect to the performance of circuit conversion netlist model is evaluated;Trajectory-guided reinforcement learning phase's reflective learning mechanism;Trajectory-guided reinforcement learning phase's overall optimization is carried out.The present application utilizes trajectory-guided reinforcement learning paradigm, through integration step-by-step inference, multilevel reward mechanism and reflective learning mechanism, can improve the precision and inference consistency of circuit image to SPICE netlist conversion.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, specifically to a method for generating SPICE netlists from circuit diagrams driven by a multimodal large model. Background Technology

[0002] Applications of Artificial Intelligence Technology in Circuit Image to SPICE Netlist Conversion: Circuit images typically contain component layouts and connection structures, while SPICE netlists provide a more structured description of the circuit. Circuit images are usually composed of different components, lines, and connection points, which are laid out and connected according to certain rules and constraints. SPICE netlists, on the other hand, describe the behavior of the circuit through mathematical models, providing the electrical connections between components and their characteristics (such as resistance, current, and voltage), making circuit analysis and simulation more efficient and accurate. With the rapid development of deep learning, more and more research is dedicated to converting circuit images into SPICE netlists for further analysis. For example, the method proposed in "From Schematics to Netlists–Electrical Circuit Analysis Using Deep-Learning Methods" successfully converts this image information into SPICE netlists by decomposing the circuit image into multiple steps, including component detection, wiring detection, and text recognition. "Amsnet: Netlist dataset for ams circuits" uses a data-driven approach, training a deep learning model to directly map circuit images to SPICE netlists. These studies demonstrate the immense potential of deep learning technology in circuit image transformation, effectively enhancing the automated analysis capabilities of circuit images. However, despite these advancements, existing models still face several challenges, particularly when processing highly complex and interconnected circuit images. Circuit diagrams often contain multiple interwoven elements, complex wiring, and connections at different levels, making it difficult for traditional visual language models and deep learning methods to accurately understand the circuit diagram's topology. Especially in cases involving complex symbols, dynamically changing electrical connections, and multi-layered circuit designs, models may fail to effectively capture the interrelationships between components, leading to inference errors or omissions. Furthermore, existing methods often rely on standardized and simplified circuit diagram inputs, making it difficult to handle real-world circuit diagrams with irregular layouts and diverse symbols. These limitations significantly restrict the inference capabilities of deep learning models, especially when facing higher accuracy requirements and complex circuit designs, often failing to meet the demands of practical applications. Therefore, improving the performance of existing models in complex circuit image analysis, particularly in accurately understanding and inferring the circuit's topology, remains a pressing technical challenge.

[0003] Visual language models for circuit image analysis: Visual language models have demonstrated excellent multimodal understanding and reasoning capabilities in image analysis tasks, particularly in processing circuit images. These models, by combining image and textual information, can effectively resolve complex components, connections, and symbols in circuit images. By combining visual perception with language understanding, visual language models can more accurately identify elements and their functional relationships in circuit diagrams, thereby improving the efficiency and accuracy of image analysis. For example, the MAPS paper combines physical perception models with the simulation process, enhancing the modeling and reasoning capabilities of visual language models in the field of circuit physics through supervised fine-tuning techniques. This approach not only improves the understanding of complex components in circuit images but also facilitates the simulation and optimization of circuit designs. The Auto-SPICE paper significantly improves the accuracy of analog circuit netlist generation by introducing techniques such as circuit labeling, cue tuning, and netlist verification. These advances demonstrate the great potential of visual language models in circuit image analysis, effectively improving the efficiency of automated circuit design and simulation. However, current visual language model-based methods mainly rely on surface image information, typically focusing on the explicit features of circuit images while neglecting the deep-seated implicit logic and structural patterns within them. Circuit diagrams are not merely composed of simple components and connections; they also contain various underlying logical relationships and complex electrical functions, which are crucial for netlist generation. Existing models, lacking effective reasoning mechanisms, often fail to delve deeply into this implicit information, leading to inaccuracies and inconsistencies in netlist generation results. Therefore, improving the reasoning ability of visual language models to better understand the complex structures and logical relationships in circuit diagrams is a significant challenge in current research. Summary of the Invention

[0004] The purpose of this invention is to provide a method for generating SPICE netlists from circuit diagrams driven by multimodal large models, so as to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for generating SPICE netlists from circuit diagrams driven by a multimodal large model includes:

[0007] Step 1: Complete the construction of the SPICE netlist dataset from the circuit diagram;

[0008] Step 2: Perform supervised fine-tuning of the circuit-to-netlist model;

[0009] Step 3, the step-by-step reasoning paradigm of the trajectory-guided reinforcement learning stage, simulates the reasoning process of humans when analyzing circuit diagrams through step-by-step decision-making. The reasoning process includes identifying ports, components and their connection relationships.

[0010] Step 4: The multi-level reward mechanism in the trajectory-guided reinforcement learning stage evaluates the performance of the circuit-to-netlist model in terms of inference quality, accuracy of generated netlists, and logical consistency.

[0011] Step 5: The reflective learning mechanism in the trajectory-guided reinforcement learning stage. When the circuit-to-netlist model encounters sparse rewards or incorrect inference paths, the reference answer helps the circuit-to-netlist model adjust its inference trajectory, thereby avoiding the circuit-to-netlist model from getting stuck in local optima or producing incorrect inference results.

[0012] Step 6: Perform overall optimization of the trajectory-guided reinforcement learning stage. The circuit-to-netlist model gradually identifies ports, components and their connections in the circuit diagram, and finally generates a complete SPICE netlist.

[0013] Further, step 1 includes:

[0014] High-quality circuit image data is constructed. Subsequently, the components in these circuit images are accurately labeled, and a target detection model is trained on the labeled circuit image data for automatic detection of components and bounding box annotations.

[0015] Finally, human experts were brought in to review the data again to ensure accuracy.

[0016] Further, step 2 includes:

[0017] The circuit-to-netlist model, through supervised fine-tuning training, enables the model to extract key circuit elements, ports, and their electrical connections from circuit images and corresponding SPICE netlists.

[0018] Further, step 3 includes:

[0019] Use a circuit-to-netlist model to identify the names, types, and relative coordinates of ports and devices;

[0020] Based on the identified port and device names, types and relative coordinates, the circuit-to-netlist model establishes the electrical connections between devices and ports.

[0021] The following dynamic reasoning mechanism is set: if the reward score obtained is lower than a predefined threshold, no reward will be obtained for subsequent reasoning steps;

[0022] This dynamic reasoning mechanism is represented as follows:

[0023]

[0024] in, Let t be the reasoning state at reasoning step t∈{0,1,2,3}. Let i be the reasoning state at reasoning step i. and Let be the reasoning state update and reward function for reasoning step t. The threshold that changes with the training steps. , These are the reward scores for reasoning steps t and t-1, respectively.

[0025] Further, step 4 includes:

[0026] A multi-level reward mechanism is proposed, which decomposes the global reward signal into three fine-grained rewards in "reasoning-answer-logic". The multi-level reward score is defined as follows:

[0027]

[0028] Where α, β, γ, and δ are four hyperparameters, R total R provides multi-tiered reward scores. think For progressive reasoning rewards, R answer As a reward for netlist accuracy, R logic Rewards are given for graph consistency.

[0029] Furthermore, step 4 also includes:

[0030] The step-by-step reasoning reward is set as follows: Based on the step-by-step reasoning paradigm, a structured metric is used to score the three reasoning steps to quantify the compliance of the reasoning chain. In the port and device identification stage, a unified format "name (type) [[bbox]]" is adopted, with dual rewards for semantic and geometric spaces. The semantic reward is a certain number of points for matching the same "name (type)," and the geometric reward is a certain number of points for calculating the average intersection of the normalized bounding boxes, with each reward totaling 1 point. In the connection verification stage, "node" is used as the basis for the reward. <id>Describe the connection in the format "[device name]"; design a list reward mechanism to obtain a number of points by matching the list length and aligning elements; all scores range from 0 to 1.

[0031] Furthermore, step 4 also includes:

[0032] Netlist accuracy reward setting: A continuous reward function based on set matching is constructed. This function applies regularization constraints to map the SPICE netlist list to the connection set between devices and ports. The netlist accuracy reward is calculated by comparing the actual SPICE netlist set C. gt With the generated SPICE netlist set C pred The reward score for the correct set of nodes in the generated SPICE netlist is derived from the proportion of equivalent connections between nodes; the reward score for netlist accuracy is expressed as:

[0033]

[0034] in, The intersection represents the point of contact.

[0035] Furthermore, step 4 also includes:

[0036] The graph consistency reward is defined as follows: A depth-first search algorithm is used to extract the SPICE network list and the inference connection graph, and the adjacency of nodes is compared to determine their equivalence. In the constructed graph, each endpoint represents a port or device in the circuit diagram, and edges represent the connectivity between endpoints. The similarity is calculated and a graph consistency reward is provided by comparing the overlapping parts of corresponding edges in the inference connection graph G and the SPICE network list graph G. The graph consistency reward score is expressed as:

[0037]

[0038] in, and These are graphs. and Graph The i-th edge and the j-th edge, This is an indicator function that determines whether two edges are equal.

[0039] Formatting Rewards: Formatting rewards encourage circuit-to-netlist models to employ structured reasoning processes, requiring them to... <think>and< / think> The reasoning steps should be output within the tags, and the reasoning content should explicitly include... <port> and< / port> , <device> and< / device> ,as well as <connection> and< / connection> Tags; the final answer is located at <answer> and< / answer> Between tags; the formula for the format reward score is:

[0040]

[0041] Here, "Format Correct" indicates that the output answer of the circuit-to-netlist model is in the correct format, and "Otherwise" indicates otherwise.

[0042] Further, step 5 includes:

[0043] A reflective learning approach is proposed, which proactively provides reference answers as hints of low-reward samples when all reward values ​​are below a preset specific reward threshold. This encourages the circuit-to-netlist model to perform reverse correction engineering on the inference trajectory based on the connection relationships and electrical properties in the SPICE network list.

[0044] Based on the improved reward results, the final score is adjusted by calculating the difference between the reflective reward and the original reward, and additional rewards are only given when there is positive improvement.

[0045] If no positive improvements are made, a relative penalty is introduced to guide the circuit-to-netlist model to further optimize the inference process;

[0046] Final reward score Represented as:

[0047]

[0048] in, Reward points for reflecting on the reference answer. For reference reward weight parameters, ε1 is a stability constant. For a specific score threshold, max indicates taking the maximum value.

[0049] Further, step 6 includes:

[0050] The trajectory-guided reinforcement learning training paradigm optimizes the accuracy of inference trajectories and generated SPICE netlist answers based on the differences within groups;

[0051] Given a query From the old strategy Generated in Sample ,in Representing a single generated sample, the trajectory-guided reinforcement learning objective is:

[0052]

[0053] in, Let be the objective function. Let be the expected value of the objective function. For the calculation of KL divergence, The output distribution of the current circuit-to-netlist model, For the output distribution of the reference model, the loss function It can be defined as:

[0054]

[0055] Where min means taking the minimum value, and clip means clipping;

[0056] Standardization advantages Defined as:

[0057]

[0058] in, ε is the score of the i-th generated sample. β and ε2 are default hyperparameters. mean represents the calculation of the mean, and std represents the calculation of the standard deviation.

[0059] Compared with the prior art, the beneficial effects of the present invention are:

[0060] This invention proposes a multimodal large-scale model-based inference framework for the automatic conversion of circuit netlists. Utilizing the TGRL (Trajectory-Guided Reinforcement Learning) paradigm, this framework integrates step-by-step inference, a multi-level reward mechanism, and a reflective learning mechanism to improve the accuracy and inference consistency of circuit diagram-to-SPICE netlist conversion. First, the framework decomposes the complex circuit diagram conversion task into multiple steps of identifying ports, devices, and connections through step-by-step inference, effectively reducing errors and inconsistencies in the inference process. Next, a multi-level reward mechanism evaluates not only the accuracy of netlist generation but also the logical consistency of the inference process, ensuring that the generated netlist is not only accurate but also conforms to the actual circuit structure. Finally, a reflective learning mechanism is introduced, using back feedback and reference answers to guide the model in correcting inference biases, preventing the model from getting trapped in local optima, and improving the stability and reliability of the inference process.

[0061] This invention surpasses existing methods in terms of netlist generation accuracy and inference consistency. Compared to traditional methods, this invention demonstrates higher accuracy and better generalization ability when processing complex circuit diagrams. Future work will focus on further improving the versatility and adaptability of this framework, enabling it to adapt to a wider range of circuit types and application scenarios, promoting its widespread application in circuit design, optimization, and fault diagnosis, and ultimately enhancing the intelligence level of electronic design automation (EDA). Attached Figure Description

[0062] Figure 1 This is a flowchart of a method for generating SPICE netlists from circuit diagrams driven by a multimodal large model according to the present invention.

[0063] Figure 2 This is a trend graph of the training steps and the reward scores for generating the SPICE netlist in the embodiment. Figure 2 In Figure A, the trend of inference accuracy score increases with the number of training steps; in Figure B, the trend of netlist accuracy score increases with the number of training steps. Detailed Implementation

[0064] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0065] Please see Figure 1 A method for generating SPICE netlists from circuit diagrams driven by a multimodal large model, including the following corrections:

[0066] Step 1 involves constructing the SPICE netlist dataset from the circuit diagram, specifically including:

[0067] In the circuit image to SPICE netlist dataset construction step, this invention systematically constructs 3,100 high-quality circuit image datasets from public resources, covering analog, digital, and mixed-signal designs ranging from simple to complex systems. Subsequently, components in these images are precisely labeled, and an object detection model, preferably a YOLO11 model, is trained on the labeled circuit image data for automatic component and bounding box annotation. Considering the complexity of circuit topology and connections, this invention incorporates human expert intervention to ensure accuracy. Specifically, domain experts establish correct connection relationships based on electrical principles and generate the corresponding SPICE netlist. Each data entry follows a standardized JSON structure, contains three main inference steps, and undergoes rigorous quality control for the circuit image to SPICE netlist conversion process.

[0068] Step 2 involves supervised fine-tuning of the circuit-to-netlist model, specifically including:

[0069] In the Supervised Fine-Tuning (SFT) step, the circuit-to-netlist model is trained under supervised fine-tuning, enabling it to extract key circuit components, ports, and their electrical connections from the circuit image and the corresponding SPICE netlist. The goal is to help the circuit-to-netlist model gain a preliminary understanding of the circuit's structure and composition, improving its ability to identify circuit components and their connections. This process lays the foundation for subsequent inference and analysis, ensuring that the circuit-to-netlist model can effectively handle complex circuit image information.

[0070] Step 3, the step-by-step reasoning paradigm of the trajectory-guided reinforcement learning stage, simulates the human reasoning process when analyzing circuit diagrams through step-by-step decision-making. This reasoning process includes identifying ports, components, and their connections, specifically:

[0071] In the stepwise inference paradigm of Trajectory-Guided Reinforcement Learning (TGRL), a circuit-to-netlist model is used to identify the names, types, and relative coordinates of ports and devices. Based on the identified port and device names, types, and relative coordinates, the circuit-to-netlist model establishes the electrical connections between device ports. To prevent the continuation of erroneous inference paths, if the reward score obtained at any step falls below a predefined threshold, subsequent inference steps will not receive any reward. This dynamic inference mechanism can be represented as:

[0072]

[0073] in, Let t be the reasoning state at reasoning step t∈{0,1,2,3}. Let i be the reasoning state at reasoning step i. and Let be the reasoning state update and reward function for reasoning step t. The threshold that changes with the training steps. , These are the reward scores for reasoning steps t and t-1, respectively.

[0074] Step 4, a multi-level reward mechanism for the trajectory-guided reinforcement learning stage, evaluates the performance of the circuit-to-netlist model in terms of inference quality, accuracy of generated netlists, and logical consistency. Specifically, this includes:

[0075] In the stepwise inference paradigm of Trajectory-Guided Reinforcement Learning (TGRL), traditional single-reward mechanisms typically focus only on the quality of the final SPICE netlist, neglecting inference quality and logical consistency. This can lead to "stochastic optimization" strategies, where the circuit-to-netlist model improves the quality of the SPICE netlist through stochastic simplification rather than stable optimization, thereby compromising the learning of the circuit's physical and electrical characteristics and reducing the interpretability of the inference process. Given that the inference chain may be logically inconsistent with the hints or the final SPICE netlist, this bias exacerbates the accumulation of errors. Therefore, this invention proposes a multi-level reward mechanism that decomposes the global reward signal into three fine-grained rewards in the "inference-answer-logic" process. This invention defines the multi-level reward score as follows:

[0076]

[0077] Here, α, β, γ, and δ are four hyperparameters, set to 0.4, 0.2, 0.2, and 0.2, respectively. R total R provides multi-tiered reward scores. think For progressive reasoning rewards, R answer As a reward for netlist accuracy, R logic Rewards are given for graph consistency.

[0078] Step 4.1, Stepwise Reasoning Reward (R) think Based on a step-by-step reasoning paradigm, this invention uses structured metrics to score the three reasoning steps to quantify the compliance of the reasoning chain. In the port and device identification stage, a unified format "name (type) [[bbox]]" is used, with dual rewards for semantic and geometric spaces. A semantic reward of 0.5 points is given for matching the same "name (type)," and a geometric reward of 0.5 points is given for calculating the average intersection (mIoU ≥ 0.5) of the normalized bounding boxes, for a total of 1 point for each. In the connectivity verification stage, "node" is used... <id>The connection is described in the format "[Device Name-Port]", which is treated as a list of device and port pairs. This invention designs a list reward mechanism, awarding 1 point for matching the list length and aligning elements. All scores range from 0 to 1. This reward enhances the spatial understanding of the visual-language circuit-to-netlist model and evaluates the correctness of the inference chain.

[0079] Step 4.2, Netlist Accuracy Bonus (R) answer To constrain the topological accuracy of the generated SPICE netlist and provide a more stable reward signal for small-scale sets, this invention constructs a continuous reward function based on set matching. This method applies regularization constraints to map the SPICE netlist (e.g., "[VDD node1], [Vb node2], [R1 node1 node2 resistor]") to a set of connections between devices and ports (e.g., "(VDD, R1), (Vb, R1)"). The reward is derived by comparing the proportion of equivalent connections between the actual SPICE netlist set Cgt and the generated SPICE netlist set Cpred, thus rewarding the correctly matched node sets in the generated SPICE netlist. The reward score for netlist accuracy can be expressed as:

[0080]

[0081] in, The intersection represents the point of contact.

[0082] Step 4.3, Graph Consistency Reward (R logic Since the generated inference chains differ in format from the SPICE netlist, they cannot be directly evaluated. Therefore, this invention uses a unified graph structure to quantify their similarity, thereby enhancing the logical consistency between inference and the answer. Specifically, this invention employs a depth-first search (DFS) algorithm to extract the SPICE netlist and the inference connection graph. To eliminate differences in node naming (e.g., mapping "node1" in the SPICE netlist to "node5" in the inference graph as an equivalent node), this invention compares the adjacency relationships of nodes to determine their equivalence. Even if the node names are different, they are considered equivalent as long as they are connected to the same node type and share the same connection pattern. In the graph, each endpoint represents a port or device in the circuit diagram, and edges represent the connectivity between endpoints. By comparing the overlapping portions of corresponding edges in the inference connection graph G and the SPICE netlist graph G, this invention calculates similarity and provides a reward. The reward score can be expressed as:

[0083]

[0084] in, and These are graphs. and Graph The i-th edge and the j-th edge, This represents an indicator function that determines whether two edges are equal.

[0085] Step 4.4, Formatted Rewards (R) format The format rewards encourage circuit-to-netlist models to adopt a structured reasoning process, requiring them to... <think> and< / think> The reasoning steps should be output within the tags, and the reasoning content should explicitly include... <port> and< / port> , <device> and< / device> ,as well as <connection> and< / connection> Tags. The final answer is located at <answer> and< / answer> Between tags. The formula for the format reward score is:

[0086]

[0087] Here, "Format Correct" indicates that the output answer of the circuit-to-netlist model is in the correct format, and "Otherwise" indicates otherwise.

[0088] Step 5, the reflective learning mechanism in the trajectory-guided reinforcement learning stage, when the circuit-to-netlist model encounters sparse rewards or inference path errors, helps the circuit-to-netlist model adjust its inference trajectory through hints from the reference answer, thereby avoiding the circuit-to-netlist model getting trapped in local optima or producing incorrect inference results. Specifically, this includes:

[0089] In the reflective learning mechanism of Trajectory-Guided Reinforcement Learning (TGRL), in the circuit-to-netlist conversion task, it can be observed that the circuit-to-netlist model obtains very low inference rewards in the initial exploration phase. Due to the sparsity of reward feedback and the accumulation of errors, the circuit-to-netlist model struggles to obtain sufficient positive feedback, easily getting trapped in local optima or stopping learning. To address this issue, this invention proposes a reflective learning approach. When all reward values ​​fall below a preset reward threshold, a reference answer is proactively provided as a low-reward sample as a hint, encouraging the circuit-to-netlist model to perform reverse correction engineering on the inference trajectory based on the connectivity and electrical properties in the SPICE network list. Based on the improved reward results, this invention adjusts the final score by calculating the difference between the reflective reward and the original reward, awarding additional rewards only when positive improvement occurs. If no positive improvement is made, a relative penalty is introduced to guide the circuit-to-netlist model to further optimize the inference process. Final reward score. It can be represented as:

[0090]

[0091] in, Reward points for reflecting on the reference answer. The reference reward weight parameter is set to 0.6, and ε1 is the stability constant, set to 1e-6. The specific score threshold is set to 0.7.

[0092] Step 6: Perform overall optimization of the trajectory-guided reinforcement learning stage. The circuit-to-netlist model gradually identifies ports, components, and their connections in the circuit diagram, ultimately generating a complete SPICE netlist, which includes:

[0093] In the overall optimization step of Trajectory-Guided Reinforcement Learning (TGRL), the TGRL training paradigm in this invention optimizes inference trajectories and answer accuracy based on intra-group discrepancies. Given a query... From the old strategy Generated in Sample ,in Representing a single generated sample, the objective of the TGRL in this invention is:

[0094]

[0095] in, Let be the objective function. Let be the expected value of the objective function. For the calculation of KL divergence, The output distribution of the current circuit-to-netlist model, For the output distribution of the reference model, the loss function It can be defined as:

[0096]

[0097] Where min means taking the minimum value and clip means clipping.

[0098] Standardization advantages It can be defined as:

[0099]

[0100] in, ε is the score of the i-th generated sample. β and ε2 are default hyperparameters. mean represents the calculation of the mean and std represents the calculation of the standard deviation.

[0101] Example

[0102] 1. Experimental Dataset: This invention uses the Circuit Image-SPICE Netlist dataset for two-stage model training, including 2,500 training pairs and 600 test pairs. During training, the supervised fine-tuning phase is performed on a 1,000-sample subset, while TGRL uses the full training set. This invention evaluates the accuracy of the SPICE netlist on the aforementioned test set and the publicly available AMSNet dataset, and evaluates the accuracy of downstream circuit question answering performance on the publicly available AMSBench dataset.

[0103] 2. Experimental Details: This invention uses Qwen2.5-VL-7B as the base fine-tuning model, starting with the first stage of fully parameter-supervised fine-tuning, followed by 200 steps of TGRL fine-tuning on the supervised model. During the two-stage training process, the batch size was set to 16, with 8 samples per training step, an initial learning rate of 1e-6, and a weight decay of 0.01. Training was performed on eight NVIDIA A100 GPUs.

[0104] 3. Experimental Evaluation Metrics: This invention evaluates the conversion accuracy from circuit diagrams to SPICE netlists from two dimensions: answer accuracy is calculated using the Jaccard similarity between the predicted and actual SPICE netlists, while logical consistency is measured by comparing the predicted SPICE netlists with intermediate connection inferences using Jaccard similarity. For the circuit diagram quality assurance task, this invention uses accuracy as the evaluation metric.

[0105] 4. Experimental Results:

[0106] (1) Results of the TGRL learning paradigm:

[0107] Table 1 compares the results of using different fine-tuning paradigms on Qwen2.5-VL 7B. This invention compares the accuracy of SPICE netlists within 200 steps. The results show that at 200 steps, the TGRL paradigm improves the accuracy by 25.39% compared to traditional supervised fine-tuning, but supervised fine-tuning exhibits overfitting in subsequent steps. Furthermore, TGRL's accuracy is 19.94% higher than that of the reinforcement learning-based Group Relative Policy Optimization (GRPO) technique. The results demonstrate that in complex circuit-to-netlist conversion tasks, TGRL steadily improves model performance and significantly enhances the model's generalization and robustness. Figure 2 The inference steps for 200 steps in TGRL and the reward scores for generating the SPICE netlist are shown. The results indicate that there is a steady improvement in all aspects as training progresses.

[0108] Table 1 shows the performance of Qwen2.5-VL 7B on the dataset constructed in this invention using TGRL and other tuning methods.

[0109]

[0110] (2) Results of the question and answer regarding the circuit diagram:

[0111] This invention evaluates the question-answering accuracy of the model in multiple circuit image question-answering scenarios on the AMSBench dataset to assess its performance on downstream tasks. The invention compares the results using only circuit images and using both circuit images and SPICE netlists. As shown in Table 2, in the connection recognition scenario, Gemini2.5-pro achieves an improvement of 10.97%, while Qwen2.5-VL 72B achieves an improvement of 9.2%. Furthermore, the results demonstrate that integrating SPICE netlist information significantly improves the performance in multiple circuit image question-answering scenarios, validating the auxiliary role of SPICE netlists in this task and further confirming the effectiveness of the SPICE netlist generation method in supporting inference and improving question-answering accuracy.

[0112] Table 2. Comparison of the accuracy of visual language models in answering multiple downstream tasks on the AMSBench dataset.

[0113]

[0114] (3) Ablation experiment:

[0115] This invention conducts ablation studies to verify the effectiveness of reward functions and reflective learning mechanisms.

[0116] ① Soft Rewards vs. Hard Rewards: This invention employs three levels of format constraints (w / o: no format constraints, soft: only constraints on thinks and responses, strict: constraints on thinks, ports, devices, connections, and responses together) to evaluate their impact on the accuracy and logical consistency of SPICE netlist transformations. As shown in Table 3, removing constraints reduces accuracy to 39.21%, while stricter constraints significantly improve both metrics. This demonstrates that the step-by-step reasoning paradigm effectively modulates the reasoning trajectory and improves task performance.

[0117] Table 3 Ablation experiments of format rewards under different constraint types.

[0118]

[0119] ② Design of Stepwise Inference Rewards: This invention evaluates the effectiveness of stepwise inference rewards in three key steps: port identification, device identification, and connection inference. Port and device identification includes type classification and location identification. As shown in Table 4, combining port and device identification improves the accuracy of the SPICE netlist from 45.76% to 48.13% and increases logical consistency by approximately 22%. Adding connection inference significantly improves both metrics. The results highlight the crucial role of stepwise constraints in improving SPICE netlist quality while maintaining logical consistency.

[0120] Table 4 Ablation experiments for the three steps in the reasoning process.

[0121]

[0122] ③ Bbox and Type Design: Table 5 evaluates the impact of type classification and location identification on accuracy. When port and device type classifications (with or without port / device type) are removed, the SPICE netlist accuracy drops to 47%, and logical consistency cannot be maintained. This indicates that identifying component types and port attributes is fundamental to understanding circuit structure and determining functional relationships during reasoning. When location identification (with or without port / device bbox) is removed, the SPICE netlist accuracy drops to 49%. This result shows that type classification and location identification play different but complementary roles in circuit image interpretation; type information is more critical for constructing the overall structural framework, while spatial information ensures accurate inference of positional relationships.

[0123] Table 5. Ablation experiments performed independently.

[0124]

[0125] ④ Design of Inference Logic Strategy: To evaluate the impact of the stepwise inference paradigm and logical consistency constraints, Table 5 reports the ablation results. Removing the "port-device-connection" trajectory (without stepwise inference) reduced the accuracy of the SPICE netlist to 35.38%, indicating that the lack of structured inference disrupted the inference chain and impaired the generation of the SPICE netlist. Ignoring the logical consistency reward (without...) This also reduces accuracy, highlighting the importance of maintaining consistency between the inference process and the SPICE netlist output to obtain reliable results.

[0126] ⑤ Design of reflective learning mechanism strategy: As shown in Table 5, after removing reflective learning, the accuracy of SPICE netlist decreased from 73.27% to 65.76%, and the logical consistency decreased from 85.76% to 70.10%. Figure 2 This further illustrates its impact on reward scores. The results show that the reflective learning mechanism effectively reduces early inference errors and improves score performance. Later, it ensures consistency between the inference trajectory and the SPICE netlist output, prevents error accumulation, and ensures stable, logical SPICE netlist generation.

[0127] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.< / id> < / id>

Claims

1. A multi-modal large model driven circuit diagram generation SPICE netlist method, characterized in that, Comprising: Step 1, completing the construction from the circuit image to the SPICE netlist dataset; Step 2, supervised fine-tuning of the circuit-to-netlist model; Step 3, a step-by-step reasoning paradigm for the trajectory-guided reinforcement learning stage, simulating the reasoning process of humans when analyzing circuit diagrams through step-by-step decision-making, which includes identifying ports, components, and their connection relationships; Step 4, a multi-level reward mechanism for the trajectory-guided reinforcement learning stage, evaluating the performance of the circuit-to-netlist model from the aspects of reasoning quality, accuracy of generated netlist, and logical consistency; Step 5, a reflection learning mechanism for the trajectory-guided reinforcement learning stage, helping the circuit-to-netlist model adjust the reasoning trajectory when encountering sparse rewards or incorrect reasoning paths, thereby avoiding the circuit-to-netlist model falling into local optimal solutions or producing incorrect reasoning results; Step 6, overall optimization of the trajectory-guided reinforcement learning stage, the circuit-to-netlist model identifies ports, components, and their connection relationships in the circuit diagram step by step, and finally generates a complete SPICE netlist, including: The trajectory-guided reinforcement learning training paradigm optimizes the reasoning trajectory and the accuracy of the generated SPICE netlist answer based on the difference relationship within the group; Given query From old policy Generate Samples Where Representing generated individual samples, the trajectory-guided reinforcement learning objective is to: ， where, is the objective function, is the expected value of the objective function, is the computation of the KL divergence, is the output distribution of the current circuit netlist model, is the output distribution of the reference model, the loss function can be defined as: ， Where min represents the minimum value, and clip represents clipping; Standardized advantage is defined as: ， where, is the score of the ith generated sample, β and ε2are default hyperparameters, mean represents the calculation of the mean, and std represents the calculation of the standard deviation.

2. The multi-modal large model driven circuit diagram generation SPICE netlist method of claim 1, wherein, The step 1 includes: Constructing high-quality circuit image data, then accurately labeling the components in these circuit images, and training a target detection model on the labeled circuit image data for automatic detection of components and bounding box labeling; Finally, human experts recheck the data to ensure accuracy.

3. The multi-modal large model driven circuit diagram generation SPICE netlist method of claim 1, wherein, The step 2 includes: The circuit-to-netlist model is trained through supervised fine-tuning, enabling the circuit-to-netlist model to extract key circuit components, ports, and their electrical connections from circuit images and corresponding SPICE netlists.

4. The multi-modal large model driven circuit diagram generation SPICE netlist method of claim 1, wherein, The step 3 includes: Using the circuit-to-netlist model to identify the names, types, and relative coordinates of ports and devices; Based on the results of identifying the names, types, and relative coordinates of ports and devices, the circuit-to-netlist model establishes electrical connections between devices and ports; Setting the following dynamic reasoning mechanism: if the obtained reward score is lower than the pre-defined threshold, the subsequent reasoning steps will not receive any reward; The dynamic reasoning mechanism is represented as: ， wherein, is the inference state at inference step t e {0, 1, 2, 3}, is the inference state at inference step i, and is the inference state update and reward function at inference step t, is a threshold value that varies with training step, , are the reward scores for inference steps t, t-1, respectively.

5. The multi-modal large model driven circuit diagram generation SPICE netlist method of claim 1, wherein, The step 4 includes: Proposing a multi-level reward mechanism, which decomposes the global reward signal into three fine-grained rewards in "reasoning-answer-logic", and defines the multi-level reward score as: ， wherein, α, β, γ, δ are four hyperparameters, R total is the multi-level reward score, R think is the step-by-step reasoning reward, R answer is the netlist accuracy reward, R logic is the Graph consistency reward.

6. The multi-modal large model driven circuit diagram generation SPICE netlist method of claim 5, wherein, The step 4 also includes: Setting of step-by-step reasoning reward: based on the step-by-step reasoning paradigm, three reasoning steps are scored using structured metrics to quantify the compliance of the reasoning chain; in the identification stage of the port and device, a unified format "name (type) [[bbox]]" is adopted to give double rewards to the semantic space and the geometric space; the semantic reward is obtained by matching the same "name (type)" for several scores, and the geometric reward is obtained by calculating the average intersection of the normalized bounding box for several scores, and each total score is 1 point; in the connection relationship verification stage, "node <id>The format of the connection is described as "[device name]"; a list reward mechanism is designed to obtain scores by matching list lengths and aligning elements; all scores range from 0 to 1.< / id> 7. The multi-modal large model driven circuit diagram generation SPICE netlist method of claim 5, wherein, The step 4 also includes: Setting of netlist accuracy reward: construct a set-matching based continuous reward function that applies regularization constraints to map the SPICE netlist list to the connection set between devices and ports; the netlist accuracy reward is derived by comparing the equivalent connections between the real SPICE netlist set C gt and the generated SPICE netlist set C pred , thus rewarding the correctly matched node set in the generated SPICE netlist; the reward score of the netlist accuracy reward is represented as: ， wherein represent the intersection.

8. The multi-modal large model driven circuit diagram generation SPICE netlist method of claim 5, wherein, The step 4 also includes: Setting of Graph consistency reward: the deep-first search algorithm is used to extract the SPICE netlist and the inference connection graph, and the equivalence of nodes is determined by comparing the adjacency relationship of the nodes; in the constructed Graph graph, each endpoint represents a port or device in the circuit image, and the edge represents the connectivity between the endpoints; by comparing the overlapping part of the corresponding edges in the inference connection Graph graph G and the SPICE netlist Graph graph G, the similarity is calculated and the Graph consistency reward is provided, and the Graph consistency reward score is represented as: ， wherein, and are the i-th edge and the j-th edge of the Graph graph and Graph graph respectively, denotes an indicator function that judges whether the two edges are equal or not. Setting of format reward: the format reward encourages the circuit conversion netlist model to adopt a structured reasoning process, requiring it to output the reasoning steps in the content in the form of <think>and< / think> tags, which need to explicitly include <port>and< / port> , <device>and< / device> , and <connection>and< / connection> tags; the final answer is located between <answer>and< / answer> tags; the score formula of the format reward is: ， wherein Format Correct represents that the format of the circuit-to-netlist model output answer is correct, and Otherwise represents otherwise.

9. The multi-modal large model driven circuit diagram generation SPICE netlist method of claim 1, wherein, The step 5 comprises: A reflective learning is proposed, when all reward values are lower than a preset specific reward threshold, a reference answer is actively provided as a prompt for the low reward sample, and the circuit-to-netlist model is encouraged to perform reverse correction engineering on the inference trajectory according to the connection relationship and electrical properties in the SPICE netlist; Based on the improved reward result, the difference between the reflective reward and the original reward is calculated to adjust the final score, and only when positive improvement occurs, additional reward is given; If no positive improvement is made, a relative penalty is introduced to guide the circuit-to-netlist model to further optimize the inference process; Final reward score is represented as: ， wherein, is the reflection reward score for the answer of reference, is the reference reward weight parameter, and ε1is a stability constant, is the specific score threshold, and max denotes the maximum.

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