An offset automatic calibration method for defect root cause analysis

Abstract

The application discloses an offset automatic calibration method for defect source analysis, relates to the technical field of wafer detection and defect source analysis, and comprises the following steps: determining a wafer geometric center position according to a theoretical coordinate matrix and an actual coordinate matrix of chip units in a wafer detection image and extracting candidate chip units; calculating a comprehensive stability score of the candidate chip units, screening out an optimal reference chip unit, and calculating a coordinate deviation value of the optimal reference chip unit in the actual coordinate matrix and the theoretical coordinate matrix; performing weighted average on the coordinate deviation value through a symmetry constraint condition, obtaining a local calibration offset, and extending the local calibration offset into a global offset calibration parameter; applying the global offset calibration parameter to defect positioning calculation in an AOI detection process, comparing and analyzing calibration precision through a detection result and a preset verification chip unit, and completing offset automatic calibration. The application improves the consistency and reproduction precision of defect positioning.

Description

Technical Field

[0001] This invention relates to the field of wafer inspection and defect source analysis technology, and in particular to an automatic offset calibration method for defect source analysis. Background Technology

[0002] As semiconductor integrated circuit manufacturing processes continue to evolve towards nanometer-scale feature sizes, wafer inspection and defect source analysis have gradually become key links in improving yield and optimizing production processes. Among these, AOI (Automatic Optical Inspection) technology is widely used due to its efficient defect capture capabilities. However, in actual inspection processes, limitations such as wafer geometric deformation, equipment stage accuracy drift, and positional errors during image acquisition often lead to defect location deviations in the inspection results, increasing the difficulty of defect re-inspection and repair in subsequent processes. Existing defect identification methods mostly focus on image recognition and classification model optimization, but lack automated and high-precision global correction mechanisms for coordinate offset calibration. Especially when tracing source defects, if the offset is not accurately calibrated, systematic deviations in defect location will occur, not only reducing the traceability of defect reproduction but also potentially causing batch misjudgments, thus constraining yield management and process optimization. Therefore, there is an urgent need for an automatic offset calibration method that combines reference chip cell stability analysis, local offset weighting, and global parameter expansion to improve the accuracy and stability of the defect source analysis process.

[0003] CN116363567B discloses a wafer defect identification method and system based on AOI visual inspection. This method utilizes video stream feature extraction and defect database construction, achieving efficient wafer defect identification through an intelligent model, thus solving the problems of low detection efficiency and high false detection rate. However, it primarily focuses on improving the extraction and recognition accuracy of defect features, without addressing the offset calibration problem caused by equipment misalignment or wafer geometric center positioning errors during the inspection process. Therefore, it still has shortcomings in terms of defect location consistency and reproducibility.

[0004] CN110034034B, a method for compensating for the precision offset of a wafer stage in a defect observation device, proposes to compensate for the precision offset of the wafer stage by constructing a defect database and an offset vector monitoring area to ensure the effectiveness of the detection window. This scheme achieves dynamic correction of positional offset to a certain extent, but it relies on the stage offset vector database, and the calibration range is limited to the mechanical compensation of the device itself. It lacks the ability to automatically calibrate the global offset based on image features, making it difficult to meet the needs of defect source analysis in complex inspection environments.

[0005] In summary, existing wafer defect detection and calibration methods mainly focus on local feature recognition or device-level accuracy compensation, exhibiting two significant shortcomings: First, the acquisition of calibration offsets often relies on observations of single defect points or local areas, leading to spatial propagation and amplification of errors, resulting in systematic cumulative bias. Second, the lack of a reference unit selection mechanism based on image statistical stability makes them susceptible to bias drift due to individual noise points or low-quality image fragments, weakening the reliability of defect source analysis. To address these issues, this invention proposes an automatic offset calibration method for defect source analysis, improving the consistency and reproducibility of defect localization, providing a highly stable coordinate benchmark for defect source analysis, and resolving the lack of globality and automation in existing offset calibration technologies. Summary of the Invention

[0006] The purpose of this section is to outline some aspects of the embodiments of the present invention and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section, as well as in the abstract and title of the present application, to avoid obscuring the purpose of this section, the abstract and title of the invention. Such simplifications or omissions shall not be used to limit the scope of the present invention.

[0007] In view of the common problems of offset error accumulation, lack of global automatic correction mechanism and unstable reference cell selection in existing wafer defect detection and calibration methods, this invention is proposed.

[0008] Therefore, the problem to be solved by this invention is how to achieve high-precision automatic calibration of offset during defect source analysis to ensure the consistency of defect location and the accuracy of reproduction.

[0009] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0010] In a first aspect, embodiments of the present invention provide an automatic offset calibration method for defect source analysis, comprising,

[0011] Based on the theoretical and actual coordinate matrices of the chip units in the wafer inspection image, the geometric center position of the wafer is determined, and multiple candidate chip units are extracted.

[0012] Calculate the comprehensive stability score of the candidate chip units, select the optimal reference chip unit, and calculate the coordinate deviation value of the optimal reference chip unit in the actual coordinate matrix and the theoretical coordinate matrix;

[0013] The coordinate deviation values ​​are weighted and averaged using symmetry constraints to obtain the local calibration offset, which is then extended into a global offset calibration parameter.

[0014] The global offset calibration parameters are applied to defect location calculation during AOI inspection, and the calibration accuracy is analyzed by comparing the inspection results with the preset verification chip unit to complete automatic offset calibration.

[0015] As a preferred embodiment of the automatic offset calibration method for defect source analysis described in this invention, the calibration accuracy is analyzed by comparing the detection results with a preset verification chip unit, including:

[0016] Chip cells located in different radial regions and angular sectors of the wafer are selected from the actual coordinate matrix as preset verification chip cells to construct a set of verification chip cells;

[0017] Based on the set of verification chip units, all defect records belonging to each verification chip unit are queried from the defect attribution mapping table, the calibrated coordinates of each defect are extracted, and the local coordinates of the calibrated coordinates relative to the theoretical center coordinates of the verification chip unit are calculated.

[0018] Recurrent neural networks are used to analyze the local coordinate distribution patterns of defects within each verification chip unit and identify the spatial clustering characteristics of defects.

[0019] The local coordinates of the defect spatial clustering features are spatially matched with the standard pattern data of the corresponding verification chip unit to determine whether the defect is located in a preset defect sensitive area or the distance from the design pattern is less than the process tolerance threshold.

[0020] Count the number of correctly assigned defects and the number of incorrectly assigned defects for each verification chip unit, and calculate the assignment accuracy of this verification chip unit;

[0021] The global assignment accuracy is obtained by averaging the assignment accuracy of all verification chip units in the verification chip unit set, and it is determined whether the global assignment accuracy is higher than a preset qualified threshold.

[0022] If the global attribution accuracy is greater than or equal to the preset qualified threshold, the global offset calibration parameter table is stored in the calibration parameter database of the AOI detection system, and automatic offset calibration is completed; if the global attribution accuracy is less than the preset qualified threshold, the radial offset gradient coefficient is adjusted or the number of chip units in the optimal reference chip unit set is increased, and then the symmetry constraint weighting and global expansion are re-executed.

[0023] As a preferred embodiment of the automatic offset calibration method for defect source analysis described in this invention, the method for obtaining the global offset calibration parameter table is as follows:

[0024] Based on the angular position in the spatial position coding, the coordinate deviation value is projected to the radial direction, and the radial offset component of each optimal reference chip unit is calculated.

[0025] Linear regression fitting was performed on the radial distance and radial offset components, and the fitting parameters were iteratively optimized using the gradient descent method to obtain the radial offset gradient coefficient and radial offset intercept that describe the trend of radial offset with radial distance.

[0026] Based on the local calibration offset, the radial offset gradient coefficient, and the radial offset intercept, a global offset spatial distribution function is established to obtain the offset calibration vector;

[0027] The wafer region is divided into grids according to the chip cells of the theoretical coordinate matrix. For each grid node, the global offset spatial distribution function is called to calculate the offset calibration vector of that grid node, forming a global offset calibration parameter table.

[0028] As a preferred embodiment of the automatic offset calibration method for defect source analysis described in this invention, the method for generating the local calibration offset is as follows:

[0029] Using the geometric center of the wafer as the center of symmetry, we search for pairs of chip cells that satisfy the symmetry relationship in the optimal set of reference chip cells to form a symmetric pairing set.

[0030] Based on the symmetrical pairing set, the coordinate deviation values ​​of the two chip units in the x and y directions are extracted respectively, and the deviation consistency coefficient is calculated.

[0031] For each optimal reference chip unit, the number of times it appears as a pairing element in the symmetric pairing set is counted, the average value of the deviation consistency coefficient is calculated, and the symmetry constraint weights are constructed.

[0032] The coordinate deviation values ​​of each optimal reference chip unit are weighted and averaged using the symmetry constraint weights to obtain the local calibration offset.

[0033] As a preferred embodiment of the automatic offset calibration method for defect source analysis described in this invention, the method for extracting the optimal reference chip cell is as follows:

[0034] The candidate chip units in the candidate chip unit set are sorted in descending order according to their comprehensive stability scores. The top-ranked number of candidate chip units with the highest comprehensive stability scores are selected to form the optimal reference chip unit set.

[0035] Based on the optimal reference chip unit index table, the actual center coordinates and theoretical center coordinates of each chip unit in the optimal reference chip unit set are extracted, and the coordinate deviation components of each optimal reference chip unit in the x and y directions are calculated.

[0036] As a preferred embodiment of the automatic offset calibration method for defect source analysis described in this invention, the method for obtaining the comprehensive stability score is as follows:

[0037] Convolutional neural networks are used to extract features from image feature vectors. Local texture features and global structural features are captured by multi-scale convolutional kernels. The extracted features are input into a feature fusion layer for weighted fusion to generate stability evaluation features.

[0038] Based on the stability evaluation features, an image quality evaluation model is constructed to calculate the basic stability score of each candidate chip unit;

[0039] Extract the spatial location code of each candidate chip cell from the candidate chip cell database, and calculate the spatial distribution weight of each candidate chip cell relative to the geometric center of the wafer.

[0040] The basic stability score and the spatial distribution weight are weighted and multiplied to obtain the comprehensive stability score of each candidate chip unit.

[0041] As a preferred embodiment of the automatic offset calibration method for defect source analysis described in this invention, wherein: the method for obtaining the image feature vector,

[0042] With the geometric center of the wafer as the center, a candidate region circle is constructed with a set radius. All chip units located within the candidate region circle in the actual coordinate matrix are selected, and the selected chip units are marked as the initial candidate chip unit set.

[0043] A polar coordinate grid is established within the candidate region circle, dividing the candidate region circle into equal sections according to angles. Each sector is divided into sectors along the radial direction. A ring band;

[0044] The sector-ring grid cells to which each candidate chip cell belongs in the initial candidate chip cell set are counted. Within each grid cell, the chip cell closest to the grid center is selected as the representative chip cell to form a candidate chip cell set.

[0045] Based on the candidate chip unit set, calculate the radial distance and angular position of the actual center coordinates of the candidate chip unit relative to the geometric center position of the wafer, and assign spatial position codes;

[0046] Image sub-regions corresponding to each candidate chip unit are cropped from the wafer inspection image and then subjected to grayscale normalization processing;

[0047] Based on the processed image sub-regions, the grayscale standard deviation, edge gradient intensity, and texture complexity are calculated to form the image feature vector of the candidate chip unit.

[0048] As a preferred embodiment of the automatic offset calibration method for defect source analysis described in this invention, the method for determining the wafer geometric center position is as follows:

[0049] Read the design layout file corresponding to the wafer inspection image from the AOI inspection system and generate a theoretical coordinate matrix;

[0050] The wafer inspection image is used to perform chip unit boundary detection by image recognition algorithm, the actual contour region of each chip unit is extracted, the centroid coordinates of each contour region are calculated as the actual center coordinates, and the actual coordinate matrix is ​​constructed.

[0051] Calculate the centroids of the actual coordinate matrix and the theoretical coordinate matrix respectively, and determine the midpoint of the two centroids as the geometric center of the wafer.

[0052] Secondly, embodiments of the present invention provide a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement any step of the above-described automatic offset calibration method for defect source analysis.

[0053] Thirdly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the above-described automatic offset calibration method for defect source analysis.

[0054] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0055] By establishing a dual coordinate system of theoretical and actual coordinate matrices and determining the position of the wafer's geometric center, a precise quantitative basis for the spatial distribution deviation of chip cells is realized, thereby eliminating the problem of systematic deviation accumulation caused by the inconsistency of coordinate systems in traditional methods and significantly improving the initial accuracy of offset calibration.

[0056] By introducing a comprehensive stability scoring mechanism to screen the optimal reference chip unit and calculate its coordinate deviation value, intelligent identification and screening of wafer surface quality heterogeneity is realized. This effectively eliminates the interference of unstable chip units caused by process defects, edge effects or local contamination on the calibration results, thereby ensuring the high reliability of the calibration reference sample and avoiding the propagation of calibration error introduced by poor reference point quality in the traditional random point selection method.

[0057] The local calibration offset is obtained by weighting the coordinate deviation values ​​under symmetry constraints, and then extended to a global offset calibration parameter by combining the radial offset gradient model. This realizes the mathematical modeling transformation from discrete sampling points to continuous spatial distribution functions. It fully considers the nonlinear influence of physical factors such as stress distribution, thermal expansion effect and radial gradient of process parameters on coordinate offset during wafer manufacturing. Thus, a parameterized model that accurately describes the spatial variation trend of offset across the entire wafer is constructed. This solves the technical bottleneck of traditional methods that can only provide a single fixed offset and cannot adapt to the differentiated offset characteristics of different areas of the wafer. It enables personalized high-precision calibration of chip units at various locations on the entire wafer.

[0058] By applying global offset calibration parameters to defect location calculations in the AOI inspection process, and employing a multi-region verification chip unit set combined with a recurrent neural network to intelligently analyze defect spatial aggregation features and quantitatively evaluate the accuracy of assignment, comprehensive verification and closed-loop optimization of calibration effects are achieved. This not only enables real-time monitoring of the application performance of calibration parameters in actual inspection scenarios and identification of potential calibration deviation areas, but also allows for dynamic optimization of radial offset gradient coefficients or expansion of the reference sample set through an adaptive adjustment mechanism. This ensures high accuracy in defect assignment, enabling defects to be precisely located to their actual chip unit and design pattern position. This solves the technical problems of low efficiency, strong subjectivity, and difficulty in adapting to the needs of mass production in traditional manual calibration methods. Attached Figure Description

[0059] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0060] Figure 1 The flowchart shows the automatic offset calibration method for defect source analysis. Detailed Implementation

[0061] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0062] Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort should fall within the scope of protection of this invention.

[0063] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0064] As mentioned in the background section, existing wafer defect detection and calibration methods mainly focus on local feature recognition or device-level accuracy compensation, which has two significant shortcomings: First, the acquisition of calibration offset often relies on the observation results of a single defect point or local area, leading to the spatial propagation and amplification of errors, thus forming a systematic cumulative bias; second, the lack of a reference unit screening mechanism based on image statistical stability makes it prone to bias drift due to individual noise points or low-quality image fragments, weakening the reliability of defect source analysis. To address these problems, this invention provides an automatic offset calibration method for defect source analysis.

[0065] Reference Figure 1 , Figure 1 This is a flowchart of an automatic offset calibration method for defect source analysis according to an embodiment of the present invention. Figure 1 As shown, an automatic offset calibration method for defect source analysis includes:

[0066] S1: Determine the geometric center position of the wafer based on the theoretical and actual coordinate matrices of the chip units in the wafer inspection image, and extract multiple candidate chip units;

[0067] S1.1: Read the design layout file corresponding to the wafer inspection image from the AOI inspection system and generate a theoretical coordinate matrix;

[0068] S1.2: The chip unit boundary is detected by the wafer inspection image through the image recognition algorithm, the actual contour area of ​​each chip unit is extracted, the centroid coordinates of each contour area are calculated as the actual center coordinates, and the actual coordinate matrix is ​​constructed.

[0069] Preferably, the relevant formulas for the theoretical coordinate matrix and the actual coordinate matrix are as follows:

[0070]

[0071] ;

[0072] in, This is the theoretical coordinate matrix; This represents the actual coordinate matrix; N is the total number of chip units. Let be the theoretical center coordinates of the i-th chip unit; The actual center coordinates of the i-th chip unit; and The mean of the theoretical coordinate matrix; and The standard deviation of the theoretical coordinate matrix; The radial distance is the theoretical coordinate. The angle is the theoretical coordinate. The radial distance is the actual coordinate. The angle is the actual coordinate.

[0073] Specifically, the normalized coordinate range is (-∞,+∞), but it is usually concentrated in [-3,3], the radial distance r∈(0,+∞), and the angle θ∈(0,2π).

[0074] It should be noted that the design layout file includes the ideal arrangement information of the chip cells; the theoretical coordinate matrix records the standard position information of each chip cell in the design coordinate system, including the row index, column index and corresponding theoretical center coordinates of each chip cell; the actual coordinate matrix includes the actual center coordinates and detection status identifier of the corresponding chip cell.

[0075] S1.3: Calculate the centroids of the actual coordinate matrix and the theoretical coordinate matrix respectively, and determine the midpoint of the two centroids as the geometric center of the wafer.

[0076] It should be noted that the theoretical geometric center coordinates are obtained by arithmetically averaging the theoretical center coordinates of all valid chip cells in the theoretical coordinate matrix; the actual geometric center coordinates are obtained by arithmetically averaging the actual center coordinates of all valid chip cells in the actual coordinate matrix; the midpoint between the theoretical geometric center coordinates and the actual centroid is taken as the wafer geometric center position, where the coordinates of the wafer geometric center position are... .

[0077] S1.4: Construct a candidate region circle with the wafer geometric center as the center and set the radius, filter all chip units in the actual coordinate matrix that are located within the candidate region circle, and mark the filtered chip units as the initial candidate chip unit set;

[0078] Preferably, each chip unit in the initial candidate chip unit set is traversed, and chip units with obvious defect marks, grayscale abnormalities or blurred boundaries in the wafer inspection image are removed, while chip units with qualified image quality are retained.

[0079] S1.5: Establish a polar coordinate grid within the candidate region circle, dividing the candidate region circle into equal parts according to angles. Each sector is divided into sectors along the radial direction. A ring band;

[0080] It should be noted that the radius is taken as 20% to 40% of the wafer radius; The value ranges from 8 to 16; The value ranges from 3 to 5.

[0081] S1.6: Statistically determine the sector-ring grid cells to which each chip cell belongs in the initial candidate chip cell set, and select the chip cell closest to the grid center in each grid cell as the representative chip cell to form the candidate chip cell set;

[0082] S1.7: Based on the candidate chip cell set, calculate the radial distance and angular position of the actual center coordinates of the candidate chip cell relative to the geometric center of the wafer, and assign spatial position codes;

[0083] S1.8: Crops out the image sub-regions corresponding to each candidate chip unit from the wafer inspection image and performs grayscale normalization processing;

[0084] It should be noted that spatial location encoding is used for calculating symmetry constraints in subsequent steps; the image feature vector serves as the input parameter for subsequent stability score calculation.

[0085] S1.9: Based on the processed image sub-regions, calculate the grayscale standard deviation, edge gradient intensity, and texture complexity to form the image feature vector of the candidate chip unit;

[0086] Specifically, the formula for image feature vectors is as follows:

[0087] ;

[0088] in, Let be the image feature vector of the j-th candidate chip unit; Principal component analysis function; , and Use a Gaussian convolution kernel; U represents the image sub-region of the j-th chip unit; U and V represent the image dimensions. This is the image information entropy function.

[0089] It should be noted that the value range of each dimension of the image feature vector is (0,+∞), and the specific range depends on the image content. The entropy value is ∈[0,log(256)]=[0,8].

[0090] Preferably, the actual center coordinates, corresponding theoretical center coordinates, spatial position codes, and image feature vectors of each chip unit in the candidate chip unit set are uniformly stored in the candidate chip unit database; each data item in the candidate chip unit database is associated through index number j.

[0091] For example, after reading the design layout from the AOI system to generate the theoretical coordinate matrix, the actual contour of each chip unit in the wafer inspection image is extracted using an image recognition algorithm, and the centroid coordinates are calculated to form the actual coordinate matrix. After eliminating the influence of dimensions through normalization, the centroid of the two matrices is calculated and the midpoint is taken as the wafer geometric center. A candidate region circle is drawn with this center as the center, such as a radius of 30% of the wafer size. After excluding units with obvious defects or abnormal image quality, the remaining units are divided into polar coordinate grids (such as 12 sectors and 4 rings). The unit closest to the center in each grid is selected as the representative, and finally a candidate set with uniform spatial distribution is formed. The spatial encoding and image features (such as grayscale standard deviation and texture complexity) of these units are stored uniformly.

[0092] S2: Calculate the comprehensive stability score of the candidate chip unit, select the optimal reference chip unit, and calculate the coordinate deviation value of the optimal reference chip unit in the actual coordinate matrix and the theoretical coordinate matrix.

[0093] S2.1: A convolutional neural network is used to extract features from the image feature vector. Local texture features and global structural features are captured by multi-scale convolutional kernels. The extracted features are input into the feature fusion layer for weighted fusion to generate stability evaluation features.

[0094] It should be noted that the multi-scale convolution kernels include three sizes: 3×3, 5×5, and 7×7, which are used to extract image detail information at different scales.

[0095] S2.2: Based on stability evaluation features, construct an image quality evaluation model and calculate the basic stability score of each candidate chip unit;

[0096] In an optional embodiment, a multi-layer neural network model with a fully connected layer at its core is constructed as an image quality assessment model based on stability evaluation features. The input of this model is a stability evaluation feature vector, which undergoes a nonlinear transformation through two hidden layers. The first hidden layer uses the ReLU activation function to enhance the model's expressive power, while the second hidden layer uses the Sigmoid activation function to compress the output value to the range of 0 to 1. The model output is a basic stability score for each candidate chip unit, which directly reflects the stability of the chip unit's image quality. During the model training phase, a chip unit image quality level dataset containing expert annotations is used as a supervision signal, and the mean squared error loss function and Adam optimizer are used for parameter optimization. An early stopping mechanism is introduced during training to prevent overfitting, and training is automatically terminated when the validation set loss no longer decreases for several consecutive epochs. During the model deployment phase, the trained image quality assessment model is integrated into the calibration system to perform batch scoring calculations on each chip unit in the candidate chip unit database.

[0097] S2.3: Extract the spatial location code of each candidate chip cell from the candidate chip cell database, and calculate the spatial distribution weight of each candidate chip cell relative to the geometric center of the wafer;

[0098] It should be noted that the image quality assessment model maps the stability assessment features to values ​​between 0 and 1 through a fully connected layer, serving as a basic stability score that reflects the stability of the chip unit's image quality. The spatial distribution weight is quantified by analyzing the distribution density and radial distance of candidate chip units in the sector-ring grid unit, prioritizing chip units with uniform spatial distribution and appropriate distance from the wafer center.

[0099] S2.4: Perform a weighted product operation between the basic stability score and the spatial distribution weight to obtain the comprehensive stability score of each candidate chip unit;

[0100] Furthermore, the specific formula for the comprehensive stability score is as follows:

[0101] ;

[0102] in, The overall stability score for the j-th candidate chip unit; Based on the stability score; α and β are spatially distributed weights; γ and δ are adaptive weight coefficients; γ and δ are adjustment parameters. The mean of the spatial distribution weights; It is the hyperbolic tangent function.

[0103] It should be noted that the overall stability score The closer the value is to 1, the higher the stability.

[0104] Preferably, an adaptive weight allocation algorithm is used to dynamically adjust the weight ratio of the basic stability score and the spatial distribution weight according to the overall image quality level of the current wafer.

[0105] S2.5: Sort each candidate chip unit in the candidate chip unit set in descending order according to the comprehensive stability score, and select the top-ranked candidate chip units by the comprehensive stability score to form the optimal reference chip unit set;

[0106] Specifically, an optimal reference chip cell index table is established to record the index number j of each chip cell in the optimal reference chip cell set in the candidate chip cell database.

[0107] S2.6: Based on the optimal reference chip cell index table, extract the actual center coordinates and theoretical center coordinates of each chip cell in the optimal reference chip cell set, and calculate the coordinate deviation components of each optimal reference chip cell in the x and y directions;

[0108] Furthermore, the specific formulas for the coordinate deviation components in the x and y directions are as follows:

[0109]

[0110] ;

[0111] in, Let x be the coordinate deviation component of the j-th optimal reference chip unit in the x-direction; Let y be the coordinate deviation component of the j-th optimal reference chip unit in the y direction; The radial distance is the theoretical coordinate. The angle is the theoretical coordinate. The radial distance is the actual coordinate. The angle is the actual coordinate.

[0112] It should be noted that the value range is specified as follows: However, it is usually concentrated in [-1,1] due to normalization.

[0113] S2.7: Verify the validity of the coordinate deviation components in the x and y directions. By comparing the deviation range with historical calibration data, confirm the rationality of the coordinate deviation value and complete the calculation of the coordinate deviation value of the optimal reference chip unit.

[0114] For example, image features of candidate units are extracted using a multi-scale convolutional neural network, fused, and input into a fully connected layer to generate a basic stability score (0-1 points). Simultaneously, spatial distribution weights are calculated based on the distribution density and radial distance of units in the polar coordinate grid (e.g., units in the central region have higher weights). The scores and weights are adaptively weighted to obtain a comprehensive stability score, and the top 5% of units are selected as the optimal reference set. For these units, the deviation components between their theoretical and actual coordinates in the x and y directions are calculated, and the rationality of the deviation is verified by comparing with historical data.

[0115] S3: The coordinate deviation values ​​are weighted and averaged using symmetry constraints to obtain the local calibration offset, and the local calibration offset is then extended to the global offset calibration parameter.

[0116] S3.1: Based on the geometric center position of the wafer Using the center of symmetry, search for pairs of chip cells that satisfy the symmetry relationship in the optimal reference chip cell set to form a symmetric pairing set;

[0117] Specifically, the spatial position codes of each optimal reference chip cell in the optimal reference chip cell set are read. For any optimal reference chip cell j, its symmetric chip cell k must satisfy the radial distance proximity condition. and angular symmetry conditions ,in, For radial distance tolerance, the value is the radial distance. 10%, The angle tolerance is 15° to 25°.

[0118] It should be noted that the symmetric pairing set includes F groups of symmetric chip unit pairs, with each pairing record being (a, b).

[0119] S3.2: Based on the symmetric pairing set, extract the coordinate deviation values ​​of the two chip units in the x and y directions respectively, and calculate the deviation consistency coefficient;

[0120] It should be noted that the deviation consistency coefficient ranges from 0 to 1, and the larger the value, the more consistent the coordinate deviation of the symmetrical pairing.

[0121] S3.3: For each optimal reference chip unit, count the number of times it appears as a pairing element in the symmetric pairing set, calculate the average value of the deviation consistency coefficient, and construct the symmetry constraint weights;

[0122] Specifically, the formula for the symmetry constraint weights is as follows:

[0123] ;

[0124] in, The symmetry constraint weights for the j-th optimal reference chip cell; The number of symmetric units paired with chip unit j; This is the deviation consistency coefficient; The actual radial distance of the j-th optimal reference chip cell; For the first The actual radial distance of each optimal reference chip cell; It is a distance-sensitive parameter.

[0125] It should be noted that, The closer it is to 1, the stronger the symmetry constraint.

[0126] S3.4: The coordinate deviation values ​​of each optimal reference chip unit are weighted by using symmetry constraint weights to obtain the local calibration offset;

[0127] Furthermore, the specific formula for the local calibration offset is as follows:

[0128] ;

[0129] in, The local calibration offset is a two-dimensional vector. The optimal number of reference chip units; Weights are constrained by symmetry. and These are the coordinate deviation components in the x and y directions; η is the Mahalanobis distance of the j-th optimal reference chip cell; η is the Gaussian kernel bandwidth.

[0130] It should be noted that the local calibration offset L∈(-∞,+∞) has a specific range that depends on the deviation component.

[0131] S3.5: Based on the angular position in the spatial position encoding, project the coordinate deviation value to the radial direction and calculate the radial offset component of each optimal reference chip unit;

[0132] S3.6: Perform linear regression fitting on the radial distance and radial offset components, and use the gradient descent method to iteratively optimize the fitting parameters to obtain the radial offset gradient coefficient and radial offset intercept, which describe the trend of radial offset with radial distance.

[0133] S3.7: Based on the local calibration offset, radial offset gradient coefficient, and radial offset intercept, establish a global offset spatial distribution function to obtain the offset calibration vector;

[0134] Furthermore, the specific formula for the offset calibration vector is as follows:

[0135] ;

[0136] in, This is the offset calibration vector at coordinates (x, y); This is the local calibration offset; Radial offset gradient coefficient; This is the radial offset intercept; For angle modulation amplitude; Radial distance; For angular position; It is a nonlinear decay factor; This is the phase shift.

[0137] It should be noted that, ∈(-∞,+∞), the specific value depends on the input coordinates; for any coordinate on the wafer, calculate the radial distance and angular position of that position relative to the geometric center of the wafer; the global offset spatial distribution function outputs the offset calibration vector of that position.

[0138] S3.8: Divide the wafer region into grids according to the chip cells of the theoretical coordinate matrix. For each grid node, call the global offset spatial distribution function to calculate the offset calibration vector of that grid node, and form a global offset calibration parameter table.

[0139] Preferably, the coordinates of all grid nodes and their corresponding offset calibration vectors are organized into a global offset calibration parameter table, wherein each record in the global offset calibration parameter table contains the grid node coordinates, the offset calibration parameter in the x-direction, and the offset calibration parameter in the y-direction; for the defect detection coordinates of any chip unit in the actual coordinate matrix M_actual, the corresponding offset calibration vector is queried in the global offset calibration parameter table using the bilinear interpolation method.

[0140] For example, with the wafer center as the symmetry point, a cell pair that satisfies the radial distance tolerance (±10%) and angular symmetry (tolerance 20°) is searched in the optimal reference set, and its deviation consistency coefficient is calculated. Based on the number of times the cell participates in symmetric pairing and the average consistency coefficient, a symmetry constraint weight is constructed (e.g., cells with frequent symmetry and consistent deviation have higher weights). The deviation value is weighted and averaged using this weight to obtain the local calibration offset. At the same time, the trend of radial offset with distance is analyzed by linear regression to obtain the gradient coefficient and intercept. A global offset spatial distribution function is established to generate a calibration parameter table covering the entire wafer. For example, for coordinates (x, y), its calibration vector contains a nonlinear compensation term modulated by radial distance and angle.

[0141] S4: Apply the global offset calibration parameters to the defect location calculation during the AOI inspection process, and analyze the calibration accuracy by comparing the inspection results with the preset verification chip unit to complete the automatic offset calibration.

[0142] Specifically, based on the original detection coordinates, the four adjacent grid nodes surrounding the coordinates are found in the global offset calibration parameter table, denoted as grid node a, grid node b, grid node c, and grid node d; the coordinates of the four grid nodes and their corresponding offset calibration vectors are extracted; the interpolated offset calibration vector at the original detection coordinates is calculated using a bilinear interpolation algorithm; the interpolated offset calibration vector is obtained by weighting the offset calibration vectors of the four grid nodes according to distance weights.

[0143] It should be noted that each defect record in the original defect dataset contains the defect number, original detection coordinates, defect type, and defect size;

[0144] Furthermore, the original detection coordinates and the interpolated offset calibration vector are added together to obtain the calibrated coordinates; the defect number ID_defect, the original detection coordinates, the calibrated coordinates, the defect type, and the defect size are organized into a calibrated defect dataset.

[0145] Furthermore, the theoretical center coordinates and boundary range of each chip unit are read from the theoretical coordinate matrix. For each defect in the calibrated defect dataset, the chip unit to which the defect belongs is determined based on its calibrated coordinates. For each defect, the chip units in the theoretical coordinate matrix are traversed, and the distance between the calibrated coordinates and the theoretical center coordinates of each chip unit is calculated. It is then determined whether the distance between the calibrated coordinates and the theoretical center coordinates of the chip unit is less than half the length of the chip unit's diagonal. If the distance is less than half the length of the chip unit's diagonal, the defect is assigned to that chip unit, and a defect attribution mapping table is established.

[0146] It should be noted that each record in the defect attribution mapping table includes the defect number ID_defect, the chip cell number ID_die, the calibrated coordinates, and the local coordinates relative to the center of the chip cell.

[0147] S4.1: Select chip cells located in different radial regions and angular sectors of the wafer from the actual coordinate matrix as preset verification chip cells, and construct a set of verification chip cells;

[0148] Preferably, for each verification chip unit in the verification chip unit set, the standard pattern data of that chip unit is extracted from the wafer design layout.

[0149] It should be noted that the verification chip cell set includes representative chip cells from the inner, middle and outer rings of the wafer, with a total number that is 2 to 3 times the number of the optimal reference chip cell set; the standard pattern data includes the design graphics, key dimension annotations and preset defect-sensitive areas of each layer within the chip cell; the preset defect-sensitive areas are the known process weaknesses in the design phase, including high-density interconnect areas, sharp bend wiring areas and narrow-pitch structure areas.

[0150] S4.2: Based on the set of verification chip units, query all defect records belonging to each verification chip unit from the defect attribution mapping table, extract the calibrated coordinates of each defect, and calculate the local coordinates of the calibrated coordinates relative to the theoretical center coordinates of the verification chip unit.

[0151] S4.3: Recurrent neural networks are used to analyze the local coordinate distribution pattern of defects within each verification chip unit and identify the spatial clustering characteristics of defects;

[0152] S4.4: Spatial matching of the local coordinates of the defect spatial clustering features with the standard pattern data of the corresponding verification chip unit to determine whether the defect is located in the preset defect sensitive area or the distance from the design pattern is less than the process tolerance threshold.

[0153] In optional embodiments, if the coordinate system used for the local coordinates of the defect differs from the coordinate system of the standard pattern data due to translation or rotation, a rigid body transformation is performed on the local coordinates of the defect based on the transformation relationship between the theoretical center coordinates of the verification chip unit and the origin of the design layout to ensure that it is in the same coordinate system as the standard pattern data. If the standard pattern data contains multiple process layers, it is mapped to the most relevant target layer according to the defect type attributes (such as short circuit, open circuit, particle defect). If the local coordinates of the defect are located inside the boundary of any design pattern on the target layer (i.e., "point-in-polygon" detection is performed), the defect is determined to fall directly on the design pattern, and the match is successful. If the local coordinates of the defect do not fall inside any design pattern, the shortest distance from the coordinates to the boundaries of all surrounding design patterns is calculated. If the shortest distance calculated in the previous step is less than a preset process tolerance threshold, the defect is determined to be spatially close enough to the design pattern, and the match is successful. If the distance is greater than or equal to the process tolerance threshold, the defect is determined to be an isolated point with no clear association with the design pattern, and the match fails.

[0154] It should be noted that the process tolerance threshold is determined comprehensively based on the capability limits of chip manufacturing processes, design rule requirements, and the actual impact of defects on circuit functionality.

[0155] S4.5: Count the number of correctly assigned defects and the number of incorrectly assigned defects for each verification chip unit, and calculate the assignment accuracy of this verification chip unit;

[0156] S4.6: Take the average of the assignment accuracy of all verification chip units in the verification chip unit set to obtain the global assignment accuracy, and determine whether the global assignment accuracy is higher than the preset qualified threshold.

[0157] Furthermore, the specific formula for global attribution accuracy is as follows:

[0158] ;

[0159] in, b represents the global attribution accuracy; b represents the number of verification chip units. Let be the accuracy of assigning the k-th verification chip unit; Radial weight; is the error function; c is the confidence parameter.

[0160] It should be noted that the global attribution accuracy The closer the value is to 1, the higher the calibration accuracy.

[0161] In an optional embodiment, if the global attribution accuracy is greater than or equal to a preset qualified threshold, the global offset calibration parameter table is stored in the calibration parameter database of the AOI detection system, and automatic offset calibration is completed; if the global attribution accuracy is less than the preset qualified threshold, the radial offset gradient coefficient is adjusted or the number of chip units in the optimal reference chip unit set is increased, and then the symmetry constraint weighting and global expansion are re-executed.

[0162] Preferably, the preset pass threshold is determined by comprehensively considering the industry standard requirements for the final calibration accuracy of the AOI inspection system, the yield control target of the current production batch, and the statistical analysis results of historical calibration verification data.

[0163] For example, a global parameter table is integrated into AOI inspection. The calibration vector of the defect coordinates is calculated by bilinear interpolation to correct the original coordinates. Representative chip cells from the inner, middle, and outer rings of the actual matrix are selected as a verification set. The calibrated defect coordinates are spatially matched with sensitive areas (such as high-density interconnect areas) in the design layout. If the defect falls within the sensitive area or is less than the process tolerance (such as 50nm) from the design pattern, the assignment is considered correct. The accuracy of all verification cells is calculated. If the global average exceeds a preset threshold (such as 95%), the calibration is successful and the parameters are stored. Otherwise, the gradient coefficient is adjusted or the reference cells are expanded and iterated again until the accuracy requirements are met.

[0164] In summary, this invention establishes a dual coordinate system to determine the wafer's geometric center, achieving a precise quantitative basis for spatial deviation and eliminating the problem of systematic deviation accumulation. By selecting the optimal reference chip unit through comprehensive stability scoring, it effectively eliminates unstable factors such as process defects and edge effects, avoiding error propagation associated with traditional random point selection. By establishing global offset parameters through symmetry constraint weighting and a radial gradient model, it achieves the transformation from discrete sampling to continuous spatial distribution modeling, solving the technical bottleneck that traditional single fixed offset cannot adapt to the differentiated characteristics of different regions. Through multi-region verification sets combined with neural networks for attribution accuracy evaluation and closed-loop optimization, it achieves intelligent verification and adaptive adjustment of calibration effects, ensuring that defects are accurately located to their true positions, solving the technical problems of low efficiency, strong subjectivity, and difficulty in meeting the needs of mass production in traditional manual calibration.

[0165] This embodiment also provides a computer device applicable to the automatic offset calibration method for defect source analysis, including a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the automatic offset calibration method for defect source analysis as proposed in the above embodiment.

[0166] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0167] This embodiment also provides a storage medium storing a computer program that, when executed by a processor, implements the automatic offset calibration method for defect source analysis as proposed in the above embodiments.

[0168] The storage medium proposed in this embodiment and the data storage method proposed in the above embodiments belong to the same inventive concept. Technical details not described in detail in this embodiment can be found in the above embodiments, and this embodiment has the same beneficial effects as the above embodiments.

[0169] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An automatic offset calibration method for defect source analysis, characterized in that: include, Based on the theoretical and actual coordinate matrices of the chip units in the wafer inspection image, the geometric center position of the wafer is determined, and multiple candidate chip units are extracted. Calculate the comprehensive stability score of the candidate chip units, select the optimal reference chip unit, and calculate the coordinate deviation value of the optimal reference chip unit in the actual coordinate matrix and the theoretical coordinate matrix; The coordinate deviation values ​​are weighted and averaged using symmetry constraints to obtain the local calibration offset, which is then extended into a global offset calibration parameter. The global offset calibration parameters are applied to defect location calculation during AOI inspection, and the calibration accuracy is analyzed by comparing the inspection results with the preset verification chip unit to complete automatic offset calibration. The method for obtaining the comprehensive stability score is as follows: Convolutional neural networks are used to extract features from image feature vectors. Local texture features and global structural features are captured by multi-scale convolutional kernels. The extracted features are input into a feature fusion layer for weighted fusion to generate stability evaluation features. Based on the stability evaluation features, an image quality evaluation model is constructed to calculate the basic stability score of each candidate chip unit; Extract the spatial location code of each candidate chip cell from the candidate chip cell database, and calculate the spatial distribution weight of each candidate chip cell relative to the geometric center of the wafer. The basic stability score and the spatial distribution weight are weighted and multiplied to obtain the comprehensive stability score of each candidate chip unit. The method for obtaining image feature vectors, With the geometric center of the wafer as the center, a candidate region circle is constructed with a set radius. All chip units located within the candidate region circle in the actual coordinate matrix are selected, and the selected chip units are marked as the initial candidate chip unit set. A polar coordinate grid is established within the candidate region circle, dividing the candidate region circle into equal sections according to angles. Each sector is divided into sectors along the radial direction. A ring band; The sector-ring grid cells to which each candidate chip cell belongs in the initial candidate chip cell set are counted. Within each grid cell, the chip cell closest to the grid center is selected as the representative chip cell to form a candidate chip cell set. Based on the candidate chip unit set, calculate the radial distance and angular position of the actual center coordinates of the candidate chip unit relative to the geometric center position of the wafer, and assign spatial position codes; Image sub-regions corresponding to each candidate chip unit are cropped from the wafer inspection image and then subjected to grayscale normalization processing; Based on the processed image sub-regions, the grayscale standard deviation, edge gradient intensity, and texture complexity are calculated to form the image feature vector of the candidate chip unit.

2. The automatic offset calibration method for defect source analysis as described in claim 1, characterized in that: The calibration accuracy is analyzed by comparing the test results with those of the preset verification chip unit, including: Chip cells located in different radial regions and angular sectors of the wafer are selected from the actual coordinate matrix as preset verification chip cells to construct a set of verification chip cells; Based on the set of verification chip units, all defect records belonging to each verification chip unit are queried from the defect attribution mapping table, the calibrated coordinates of each defect are extracted, and the local coordinates of the calibrated coordinates relative to the theoretical center coordinates of the verification chip unit are calculated. Recurrent neural networks are used to analyze the local coordinate distribution patterns of defects within each verification chip unit and identify the spatial clustering characteristics of defects. The local coordinates of the defect spatial clustering features are spatially matched with the standard pattern data of the corresponding verification chip unit to determine whether the defect is located in a preset defect sensitive area or the distance from the design pattern is less than the process tolerance threshold. Count the number of correctly assigned defects and the number of incorrectly assigned defects for each verification chip unit, and calculate the assignment accuracy of this verification chip unit; The global assignment accuracy is obtained by averaging the assignment accuracy of all verification chip units in the verification chip unit set, and it is determined whether the global assignment accuracy is higher than a preset qualified threshold. If the global attribution accuracy is greater than or equal to the preset qualified threshold, the global offset calibration parameter table is stored in the calibration parameter database of the AOI detection system, and automatic offset calibration is completed; if the global attribution accuracy is less than the preset qualified threshold, the radial offset gradient coefficient is adjusted or the number of chip units in the optimal reference chip unit set is increased, and then the symmetry constraint weighting and global expansion are re-executed.

3. The automatic offset calibration method for defect source analysis as described in claim 2, characterized in that: The method for obtaining the global offset calibration parameter table is as follows: Based on the angular position in the spatial position encoding, the coordinate deviation value is projected to the radial direction, and the radial offset component of each optimal reference chip unit is calculated. Linear regression fitting was performed on the radial distance and radial offset components, and the fitting parameters were iteratively optimized using the gradient descent method to obtain the radial offset gradient coefficient and radial offset intercept that describe the trend of radial offset with radial distance. Based on the local calibration offset, the radial offset gradient coefficient, and the radial offset intercept, a global offset spatial distribution function is established to obtain the offset calibration vector; The wafer region is divided into grids according to the chip cells of the theoretical coordinate matrix. For each grid node, the global offset spatial distribution function is called to calculate the offset calibration vector of that grid node, forming a global offset calibration parameter table.

4. The automatic offset calibration method for defect source analysis as described in claim 3, characterized in that: The method for generating the local calibration offset is as follows: Using the geometric center of the wafer as the center of symmetry, we search for pairs of chip cells that satisfy the symmetry relationship in the optimal set of reference chip cells to form a symmetric pairing set. Based on the symmetrical pairing set, the coordinate deviation values ​​of the two chip units in the x and y directions are extracted respectively, and the deviation consistency coefficient is calculated. For each optimal reference chip unit, the number of times it appears as a pairing element in the symmetric pairing set is counted, the average value of the deviation consistency coefficient is calculated, and the symmetry constraint weights are constructed. The coordinate deviation values ​​of each optimal reference chip unit are weighted and averaged using the symmetry constraint weights to obtain the local calibration offset.

5. The automatic offset calibration method for defect source analysis as described in claim 4, characterized in that: The method for extracting the optimal reference chip unit is as follows: The candidate chip units in the candidate chip unit set are sorted in descending order according to their comprehensive stability scores. The top-ranked number of candidate chip units with the highest comprehensive stability scores are selected to form the optimal reference chip unit set. Based on the optimal reference chip unit index table, the actual center coordinates and theoretical center coordinates of each chip unit in the optimal reference chip unit set are extracted, and the coordinate deviation components of each optimal reference chip unit in the x and y directions are calculated.

6. The automatic offset calibration method for defect source analysis as described in claim 4, characterized in that: The method for determining the geometric center position of the wafer is as follows: Read the design layout file corresponding to the wafer inspection image from the AOI inspection system and generate a theoretical coordinate matrix; The wafer inspection image is used to perform chip unit boundary detection by image recognition algorithm, the actual contour region of each chip unit is extracted, the centroid coordinates of each contour region are calculated as the actual center coordinates, and the actual coordinate matrix is ​​constructed. Calculate the centroids of the actual coordinate matrix and the theoretical coordinate matrix respectively, and determine the midpoint of the two centroids as the geometric center of the wafer.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the automatic offset calibration method for defect source analysis as described in any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the automatic offset calibration method for defect source analysis as described in any one of claims 1 to 6.

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