Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes: a display area including pixels emitting light and a scan driver configured to supply a scan signal to the pixels; and a non-display area surrounding the display area and including a clock line configured to supply a clock signal to the scan driver, the clock line extending in a first direction. The scan driver includes: a first gate driver configured to supply a first gate signal to the pixel; a second gate driver configured to supply a second gate signal and a third gate signal to the pixels; and a light emission control driver configured to supply a light emission signal to the pixels. The clock line is closest to the first gate driver among the first gate driver, the second gate driver, and the light emission control driver.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0065973 filed on May 21, 2024, as well as all the benefits accruing therefrom, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The disclosure relates to a display device and an electronic device. BACKGROUND

[0004] As the information society develops, the demand for display devices for displaying images increases in various forms. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart televisions. A display panel of a display device can include pixels including light emitting elements, wherein each of the pixels of the display panel can emit light by itself, thereby displaying an image without a backlight unit that supplies light to the display panel.

[0005] A display device includes a plurality of pixels, a data line and a gate line connected to the plurality of pixels, a data driver that supplies a data voltage to the data line, and a scan driver that supplies a scan signal to the gate line. The data driver and the scan driver can drive the plurality of pixels according to a predetermined frequency. SUMMARY

[0006] Aspects of the disclosure provide a display device capable of reducing an area of a non-display area.

[0007] However, aspects of the disclosure are not limited to the aspects described herein. The above and other aspects of the disclosure will become more apparent by describing in detail the disclosure given below.

[0008] According to an embodiment of the disclosure, a display device includes a display area including pixels that emit light and a scan driver configured to supply a scan signal to the pixels, and a non-display area surrounding the display area, and the non-display area includes a clock line configured to supply a clock signal to the scan driver, the clock line extending in a first direction. The scan driver includes a first gate driver configured to supply a first gate signal to the pixels, a second gate driver configured to supply a second gate signal and a third gate signal to the pixels, and a light emission control driver configured to supply a light emission signal to the pixels. The clock line is closest to the first gate driver among the first gate driver, the second gate driver, and the light emission control driver.

[0009] The length of each of the first gate driver, the second gate driver, and the light-emitting control driver in a second direction intersecting the first direction may be greater than the width of the corresponding one of the first gate driver, the second gate driver, and the light-emitting control driver in the first direction.

[0010] The width of the second gate driver in the first direction and the width of the light-emitting control driver in the first direction may each be greater than the width of the first gate driver in the first direction.

[0011] The display device may further include: a connecting line extending in a second direction intersecting the first direction, and the connecting line electrically connecting the clock line and the scan driver.

[0012] The clock line may include: a write clock line configured to supply a first clock signal to the first gate driver; a control clock line configured to supply a second clock signal to the second gate driver; and a light emission clock line configured to supply a third clock signal to the light emission control driver.

[0013] Among the write clock line, the control clock line, and the light emission clock line, the write clock line can be closest to the display area.

[0014] The connection lines may include: a first connection line electrically connecting the write clock line and the first gate driver; a second connection line electrically connecting the control clock line and the second gate driver; and a third connection line electrically connecting the light emission clock line and the light emission control driver.

[0015] The first gate driver may include a plurality of stages arranged in the first direction. The second connection line may pass between stages of the first gate driver that are adjacent to each other in the first direction.

[0016] The second gate driver may include a plurality of stages arranged in the first direction. The third connection line may pass between stages adjacent to each other in the first direction among the plurality of stages of the first gate driver and between stages adjacent to each other in the first direction among the plurality of stages of the second gate driver.

[0017] The display device may further include: a start connection line disposed in the non-display area to supply a start signal; and a start line disposed in the display area, wherein the start line is connected to the start connection line to supply the start signal to the scan driver.

[0018] The start line may include: a first start line configured to supply a first start signal to the first gate driver; a second start line configured to supply a second start signal to the second gate driver; and a third start line configured to supply a third start signal to the light-emitting control driver. The start connection line may include: a first start connection line configured to supply the first start signal to the first start line; a second start connection line configured to supply the second start signal to the second start line; and a third start connection line configured to supply the third start signal to the third start line.

[0019] Each of the first starting connection line, the second starting connection line, and the third starting connection line may include: a first portion disposed on a first side of the non-display area including the clock line, and the first portion extending in a first direction; a second portion connected to the first portion, and the second portion extending from a second side of the non-display area adjacent to the first side in a second direction intersecting the first direction; and a third portion connected to the second portion, and the third portion extending into the display area.

[0020] The scan driver may further include a scan transistor disposed in a first active layer comprising a first material. The pixel may include a transistor disposed in a second active layer comprising a second material different from the first material.

[0021] The pixel may include: a light-emitting element; a first transistor supplying a driving current to the light-emitting element; a second transistor supplying a data voltage to a first electrode of the first transistor; a third transistor electrically connecting a second electrode of the first transistor and a gate electrode of the first transistor; a fourth transistor configured to supply an initialization voltage to the gate electrode of the first transistor; a fifth transistor configured to supply a driving voltage to the first electrode of the first transistor; and a sixth transistor electrically connecting a second electrode of the first transistor and a first electrode of the light-emitting element.

[0022] The first gate driver can be configured to supply the first gate signal to the gate electrode of the second transistor. The second gate driver can be configured to supply the second gate signal to the gate electrode of the third transistor and the third gate signal to the gate electrode of the fourth transistor. The light emission control driver is configured to supply the light emission signal to the gate electrode of each of the fifth and sixth transistors.

[0023] According to embodiments of this disclosure, a display device includes: a display area including pixels and a scan driver, the pixels including transistors to emit light, the scan driver including scan transistors to supply scan signals to the pixels; a non-display area surrounding the display area, and the non-display area including a clock line supplying clock signals to the scan driver, the clock line extending in a first direction; a first active layer including a semiconductor region of the scan transistor; a first gate layer disposed on the first active layer, and the first gate layer including a gate electrode of the scan transistor; a second gate layer disposed on the first gate layer; a first interconnect metal layer disposed on the second gate layer, and the first interconnect metal layer including a gate low voltage line; a second interconnect metal layer disposed on the first interconnect metal layer, and the second interconnect metal layer including a metal layer; a second active layer disposed on the second interconnect metal layer, and the second active layer including a semiconductor region of the transistor overlapping the metal layer; a third gate layer disposed on the second active layer, and the third gate layer including a gate electrode of the transistor; and a first source metal layer disposed on the third gate layer, and the first source metal layer including the clock line.

[0024] The scanning transistor and the transistor can overlap in the thickness direction.

[0025] The display device may further include: a connecting line disposed in the first connecting metal layer and electrically connecting the clock line and the scanning transistor.

[0026] The second gate layer may include a scan capacitor electrode, overlapping the gate electrode of the scan transistor to form a scan capacitor for the scan driver. The first interconnect metal layer may further include a first capacitor electrode, overlapping the metal layer to form a first capacitor for the pixel. The first source metal layer may further include a second capacitor electrode, overlapping the gate electrode of the transistor to form a second capacitor for the pixel.

[0027] The display device may further include: a second source metal layer disposed on the first source metal layer and including an anode connection electrode electrically connected to the transistor; and a pixel electrode layer disposed on the second source metal layer and including a pixel electrode connected to the anode connection electrode.

[0028] According to one or more embodiments, the clock line is located in the non-display area and the scan driver is located in the display area and adjacent to the clock line, thereby reducing the area of ​​the non-display area and reducing power consumption.

[0029] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent to those skilled in the art based on the following description. Attached Figure Description

[0030] The above and other features of the present invention will become more apparent from the detailed description of embodiments of the invention with reference to the accompanying drawings.

[0031] Figure 1 This is a perspective view showing a display device according to an embodiment.

[0032] Figure 2 This is a block diagram illustrating a display device according to an embodiment.

[0033] Figure 3 This is a circuit diagram illustrating the pixels of a display device according to an embodiment.

[0034] Figure 4 This is a plan view showing the light-emitting area, gate driver, and clock line of a display device according to an embodiment.

[0035] Figure 5 This is a plan view illustrating the connection relationship between the gate driver and the clock line of a display device according to an embodiment.

[0036] Figure 6 This is a block diagram illustrating a first gate driver of a display device according to an embodiment.

[0037] Figure 7 This is a block diagram illustrating a second gate driver of a display device according to an embodiment.

[0038] Figure 8 This is a block diagram illustrating a light-emitting control driver for a display device according to an embodiment.

[0039] Figure 9 This is a cross-sectional view showing a display device according to an embodiment. Detailed Implementation

[0040] The embodiments of this disclosure address the problem of parasitic capacitance occurring between the touch line and the data fan-out line or between the touch line and the scan fan-out line in any of the plurality of touch lines that overlap with a data fan-out line or a scan fan-out line. Due to the parasitic capacitance, the touch signal of the touch line may be affected by the data voltage of the data fan-out line or the scan control signal of the scan fan-out line, and thus touch sensing errors may occur.

[0041] Embodiments of this disclosure provide a display device that can prevent the touch signal of the touch line from being affected by the data voltage of the data fan-out line or the scan control signal of the scan fan-out line.

[0042] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals throughout refer to the same elements.

[0043] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or an intermediary layer may be present. Conversely, when an element is referred to as being "directly on" another element, no intermediary element is present.

[0044] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, or parts, these elements, components, areas, layers, or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings herein, the terms “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second part.”

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

[0046] As used in this article, the word “or” means logical “or”, so unless the context otherwise indicates, the expression “A, B or C” means “A and B and C”, “A and B but no C”, “A and C but no B”, “B and C but no A”, “A but no B and C”, “B but no A and C”, and “C but no A and B”.

[0047] As used herein, the terms “comprising,” “including,” “having,” and “possessing” mean that the stated feature, area, integer, step, operation, element, or component is present, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, or groups thereof.

[0048] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if the device is flipped in a drawing, an element described as being “below” the other element will subsequently be oriented to be “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can cover both “below” and “above” orientations. Similarly, if the device is flipped in a drawing, an element described as being “below” or “under” the other element will subsequently be oriented to be “above” the other element. Thus, the terms “below” or “under” can cover both “above” and “below” orientations.

[0049] Given the measurements discussed and the errors associated with a particular number of measurements (i.e., the limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated values ​​and indicate an acceptable deviation from the particular values ​​as determined by one of ordinary skill in the art.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their context in the relevant field and in this disclosure, and should not be interpreted in an idealized or overly formal sense.

[0051] Embodiments are described herein with reference to cross-sectional views as schematic representations of idealized embodiments. Thus, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but will include deviations in shape caused, for example, by manufacturing processes. For instance, areas shown or described as flat may generally have rough or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0052] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 This is a perspective view showing the display device 10 according to an embodiment.

[0054] Reference Figure 1The display device 10 is a device for displaying moving or still images and can be used as a display screen for each of various products such as televisions, laptops, monitors, billboards and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices and ultra-mobile PCs (UMPCs).

[0055] The display device 10 may include a display panel 100, a data driver 200, a timing controller 300, a power supply unit 400, a data circuit board 500, a control circuit board 600, and a scan driver 800.

[0056] The display panel 100 may have a rectangular planar shape, having a long side in the X-axis direction and a short side in the Y-axis direction intersecting the X-axis direction. The corners where the long side in the X-axis direction and the short side in the Y-axis direction intersect may be rounded to have a predetermined curvature or may be formed at right angles. The planar shape of the display panel 100 is not limited to a quadrilateral shape and may be formed in other polygonal, circular, or elliptical shapes. The display panel 100 may be formed as flat, but is not limited to this. For example, the display panel 100 may include curved surface portions formed at the left and right ends of the display panel 100 and having a constant or variable curvature. The display panel 100 may be flexibly formed as curved, bent, folded, or rolled.

[0057] Display panel 100 may include a display area DA for displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may occupy most of the area of ​​display panel 100. The display area DA may be located at the center of display panel 100. The display area DA may include multiple pixels of the displayed image and a scan driver 800.

[0058] Each of the plurality of pixels may include a light-emitting element that emits light. The light-emitting element may include, but is not limited to, at least one of an organic light-emitting diode containing an organic light-emitting layer, a quantum dot light-emitting diode containing a quantum dot light-emitting layer, an inorganic light-emitting diode containing an inorganic semiconductor, and a micro light-emitting diode (micro LED).

[0059] The scan driver 800 can supply scan signals to the gate lines of the display area DA. The scan driver 800 can be located at the left and right edges of the display area DA, but is not limited thereto.

[0060] The non-display area NDA can be set to be adjacent to the display area DA. The non-display area NDA can also be an area outside the display area DA. The non-display area NDA can be set to surround the display area DA. The non-display area NDA can be an edge area of ​​the display panel 100.

[0061] The non-display area NDA may include fan-out lines and pads. The fan-out lines can electrically connect the data lines of the data driver 200 and the display area DA. The pads can be electrically connected to the data circuit board 500. The pads may be located at the lower edge of the display panel 100, but are not limited thereto.

[0062] The data driver 200 can output signals and voltages for driving the display panel 100. The data driver 200 can supply data voltage to data lines. The data driver 200 can supply power voltage to power supply lines and can supply scan control signals to the scan driver 800. The data driver 200 can be formed as an integrated circuit (IC) and mounted on the data circuit board 500 using a film-on-fly (COF) method. As another example, the data driver 200 can be mounted in the non-display area NDA of the display panel 100 using a glass-on-gold (COG) method, a plastic-on-ply (COP) method, or an ultrasonic bonding method.

[0063] The timing controller 300 can be mounted on the control circuit board 600 and can receive digital video data and timing synchronization signals supplied from the display driving system or graphics device via a user connector provided on the control circuit board 600. The timing controller 300 can align the digital video data to a suitable pixel arrangement structure based on the timing synchronization signals and supply the aligned digital video data to the data driver 200. The timing controller 300 can generate data control signals and scan control signals based on the timing synchronization signals. The timing controller 300 can control the supply timing of the data voltage to the data driver 200 based on the data control signals and control the supply timing of the scan signals to the scan driver 800 based on the scan control signals.

[0064] The power supply unit 400 can be mounted on the control circuit board 600 and can supply power voltage to the display panel 100 and the data driver 200. For example, the power supply unit 400 can generate drive voltage, common voltage, initialization voltage, bias voltage, gate high voltage, gate low voltage, and / or reference voltage. The power supply unit 400 can drive multiple pixels and the data driver 200 by supplying power voltage.

[0065] The data circuit board 500 can be disposed on a pad portion located at one edge of the display panel 100. The data circuit board 500 can be attached to the pad portion using a conductive adhesive component such as an anisotropic conductive film. The data circuit board 500 can be electrically connected to the signal lines of the display panel 100 via the anisotropic conductive film. The display panel 100 can receive data voltage and electrical voltage through the data circuit board 500. For example, the data circuit board 500 can be a flexible film (such as a flexible printed circuit board), a printed circuit board, or a flip-chip film.

[0066] The control circuit board 600 can be attached to the data circuit board 500 using low-resistance and high-reliability materials such as anisotropic conductive film or self-assembling anisotropic conductive paste (SAP). The control circuit board 600 can be electrically connected to the data circuit board 500. The control circuit board 600 can be a flexible printed circuit board or a printed circuit board.

[0067] Figure 2 This illustrates a display device 10 according to an embodiment (see also...) Figure 1 (A flowchart of a block diagram.)

[0068] Reference Figure 2 Display panel 100 (see) Figure 1 This can include the display area DA and the non-display area NDA (for example, see...). Figure 1 The non-display area (NDA) may include pixels (SP), gate lines (GL), light emission control lines (EML), data lines (DL), voltage lines (VL), and scan driver (800).

[0069] Each of the multiple pixels SP can be connected to a gate line GL, a data line DL, a light-emitting control line EML, and a voltage line VL. Each of the multiple pixels SP may include at least one transistor, a light-emitting element, and a capacitor.

[0070] Gate line GL can be in the X-axis direction (see Figure 1 It extends along the x-axis and can also extend along the y-axis direction intersecting the x-axis direction (see...). Figure 1 The gate lines (GL) are spaced apart from each other. The gate lines (GL) can sequentially supply gate signals to multiple pixels (SP).

[0071] The emission control lines (EMLs) can extend in the X-axis direction and can be spaced apart from each other in the Y-axis direction. The EMLs can sequentially supply emission signals to multiple pixels (SPs).

[0072] The data lines DL can extend in the Y-axis direction and can be spaced apart from each other in the X-axis direction. The data lines DL can supply data voltage received from the data driver 200 to the pixels SP. The data voltage can determine the brightness of each pixel SP.

[0073] Voltage lines VL can extend in the Y-axis direction and can be spaced apart from each other in the X-axis direction. Voltage lines VL can supply electrical voltage to multiple pixels SP. The electrical voltage can include at least one of a drive voltage, a common voltage, an initialization voltage, a bias voltage, a gate high voltage, a gate low voltage, and a reference voltage. For example, the drive voltage can be a high potential voltage used to drive the light-emitting elements of the pixels SP, and the common voltage can be a low potential voltage used to drive the light-emitting elements of the pixels SP.

[0074] The gate driver 810 may be disposed on one side of the display area DA, and the light emission control driver 820 may be disposed on the other side of the display area DA, but this disclosure is not limited thereto. As another example, both the gate driver 810 and the light emission control driver 820 may be disposed on one side or the other side of the display area DA. The scan driver 800 may include the gate driver 810 and the light emission control driver 820.

[0075] Gate driver 810 may include multiple transistors that generate a gate signal based on a gate control signal GCS. Light emission control driver 820 may include multiple transistors that generate a light emission signal based on a light emission control signal ECS. For example, gate driver 810 and light emission control driver 820 may include transistors disposed in a first active layer comprising a first material, and pixel SP may include transistors disposed in a second active layer comprising a second material different from the first material. Gate driver 810 may supply a gate signal to gate line GL, and light emission control driver 820 may supply a light emission signal to light emission control line EML.

[0076] The data driver 200 converts digital video data DATA into analog data voltage and supplies the analog data voltage to the data line DL. The gate signal of the gate driver 810 selects the pixel SP to which the data voltage is supplied, and the selected pixel SP can receive the data voltage through the data line DL.

[0077] The timing controller 300 can receive digital video data DATA and timing signals from the graphics device 700. For example, the graphics device 700 may be the graphics card of the display device 10, but is not limited thereto. The timing controller 300 can generate a data control signal DCS based on the timing signals and supply the digital video data DATA and the data control signal DCS to the data driver 200, thereby controlling the operating timing of the data driver 200. The timing controller 300 can generate a gate control signal GCS based on the timing signals and supply the gate control signal GCS to the gate driver 810, thereby controlling the operating timing of the gate driver 810. The timing controller 300 can generate a light emission control signal ECS based on the timing signals and supply the light emission control signal ECS to the light emission control driver 820, thereby controlling the operating timing of the light emission control driver 820. The timing controller 300 can change the driving frequency of the display panel 100 based on the input frequency of the digital video data DATA from the graphics device 700.

[0078] The power supply unit 400 can be installed on the data circuit board 500 (see...). Figure 3 The power supply unit 400 can generate a driving voltage and supply it to the driving voltage line, and can generate a common voltage and supply it to the common electrode shared by the light-emitting elements of the pixels SP. The power supply unit 400 can generate an initialization voltage and supply it to the initialization voltage line, and can generate a bias voltage and supply it to the bias voltage line. The power supply unit 400 can generate a gate high voltage and supply it to the gate high voltage line, generate a gate low voltage and supply it to the gate low voltage line, and generate a reference voltage and supply it to the reference voltage line.

[0079] Figure 1 This illustrates a display device 10 according to an embodiment (see also...) Figure 2 ) pixels SP (see Figure 3 The circuit diagram.

[0080] Reference Figure 1 Display panel 100 (see) Figure 4 It may include multiple pixels SP arranged along multiple rows and multiple columns. Each of the multiple pixels SP may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line GBL, a light emission control line EML, a data line DL, a drive voltage line VDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, a bias voltage line VBL, and a low potential line VSL.

[0081] A pixel SP may include a light-emitting element ED and a pixel circuit that drives the light-emitting element ED. The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, as well as a capacitor C1.

[0082] The first transistor T1 can control the drive current supplied to the light-emitting element ED. The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a third node N3, the first electrode of the first transistor T1 may be connected to a first node N1, and the second electrode of the first transistor T1 may be connected to a second node N2. For example, the first electrode of the first transistor T1 may be the drain electrode, and the second electrode of the first transistor T1 may be the source electrode, but it is not limited to these.

[0083] The first transistor T1 can control the drain-source current (Ids) (hereinafter referred to as the "drive current (Ids)") based on the data voltage applied to its gate electrode. The drive current (Ids) flowing through the channel of the first transistor T1 is proportional to the square of the difference between the voltage (Vgs) between the gate and source electrodes of the first transistor T1 and the threshold voltage (Vth) (Ids = k × (Vgs - Vth)). 2 Here, Ids is the drain-source current of the first transistor T1, k is a scaling factor determined by the structure and physical characteristics of the first transistor T1, Vgs is the gate-source voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.

[0084] An LED (Emitting Light Element) can emit light by receiving a driving current (Ids). The amount of light emitted by the LED, or the brightness of the LED, can be proportional to the magnitude of the driving current (Ids). The LED may include a first electrode, a second electrode, and an emitting layer disposed between the first and second electrodes. The first electrode of the LED can be connected to a fourth node N4. The first electrode of the LED can be electrically connected to the second electrode of a sixth transistor T6 and the first electrode of a seventh transistor T7 via the fourth node N4. The second electrode of the LED can be electrically connected to a low-potential line VSL and can receive a low-potential voltage from the low-potential line VSL. For example, the first electrode of the LED can be an anode electrode or a pixel electrode, and the second electrode of the LED can be a cathode electrode or a common electrode, but is not limited to these.

[0085] The second transistor T2 can be turned on by a first gate signal from the first gate line GWL, and electrically connects the data line DL to the first node N1, which is the first electrode of the first transistor T1. The first gate line GWL can correspond to a scan write line. The second transistor T2 can be turned on based on the first gate signal, thereby supplying a data voltage to the first node N1. The gate electrode of the second transistor T2 can be connected to the first gate line GWL, the first electrode of the second transistor T2 can be connected to the data line DL, and the second electrode of the second transistor T2 can be connected to the first node N1. The second electrode of the second transistor T2 can be electrically connected to the first electrode of the first transistor T1, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 through the first node N1. For example, the first electrode of the second transistor T2 can be the drain electrode, and the second electrode of the second transistor T2 can be the source electrode, but it is not limited to these.

[0086] The third transistor T3 can be turned on by the second gate signal of the second gate line GCL, and can electrically connect the second node N2, which is the second electrode of the first transistor T1, and the third node N3, which is the gate electrode of the first transistor T1. The gate electrode of the third transistor T3 can be connected to the second gate line GCL, the first electrode of the third transistor T3 can be connected to the second node N2, and the second electrode of the third transistor T3 can be connected to the third node N3. The first electrode of the third transistor T3 can be electrically connected to the second electrode of the first transistor T1 and the first electrode of the sixth transistor T6 through the second node N2. The second electrode of the third transistor T3 can be electrically connected to the gate electrode of the first transistor T1, the first electrode of the fourth transistor T4, and the first capacitor electrode of the capacitor C1 through the third node N3. For example, the first electrode of the third transistor T3 can be the drain electrode, and the second electrode of the third transistor T3 can be the source electrode, but it is not limited to these.

[0087] The fourth transistor T4 can be turned on by the third gate signal of the third gate line GIL, and the third node N3, which serves as the gate electrode of the first transistor T1, and the first initialization voltage line VIL1 are electrically connected. The fourth transistor T4 can be turned on based on the third gate signal, thereby initializing the gate electrode of the first transistor T1 to the first initialization voltage. The gate electrode of the fourth transistor T4 can be connected to the third gate line GIL, the first electrode of the fourth transistor T4 can be connected to the third node N3, and the second electrode of the fourth transistor T4 can be connected to the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 can be electrically connected to the gate electrode of the first transistor T1, the second electrode of the third transistor T3, and the first capacitor electrode of the capacitor C1 through the third node N3. For example, the first electrode of the fourth transistor T4 can be the drain electrode, and the second electrode of the fourth transistor T4 can be the source electrode, but it is not limited to these.

[0088] The fifth transistor T5 can be turned on by the light emission control line EML, and electrically connected to the driving voltage line VDL and the first node N1, which is the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the light emission control line EML, the first electrode of the fifth transistor T5 can be connected to the driving voltage line VDL, and the second electrode of the fifth transistor T5 can be connected to the first node N1. The second electrode of the fifth transistor T5 can be electrically connected to the first electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the eighth transistor T8 through the first node N1. For example, the first electrode of the fifth transistor T5 can be the drain electrode, and the second electrode of the fifth transistor T5 can be the source electrode, but it is not limited to these.

[0089] The sixth transistor T6 can be turned on by the light emission signal of the light emission control line EML, and is electrically connected to the second node N2, which is the second electrode of the first transistor T1, and the fourth node N4, which is the first electrode of the light emission element ED. The gate electrode of the sixth transistor T6 can be connected to the light emission control line EML, the first electrode of the sixth transistor T6 can be connected to the second node N2, and the second electrode of the sixth transistor T6 can be connected to the fourth node N4. The first electrode of the sixth transistor T6 can be electrically connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3 via the second node N2. The second electrode of the sixth transistor T6 can be electrically connected to the first electrode of the light emission element ED and the first electrode of the seventh transistor T7 via the fourth node N4. For example, the first electrode of the sixth transistor T6 can be the drain electrode, and the second electrode of the sixth transistor T6 can be the source electrode, but it is not limited to these.

[0090] When the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all turned on, the drive current (Ids) can be supplied to the light-emitting element ED.

[0091] The seventh transistor T7 can be turned on by the fourth gate signal of the fourth gate line GBL, and can electrically connect the second initialization voltage line VIL2 and the fourth node N4, which serves as the first electrode of the light-emitting element ED. The seventh transistor T7 can be turned on based on the fourth gate signal, thereby initializing the first electrode of the light-emitting element ED to the second initialization voltage. Here, the second initialization voltage of the second initialization voltage line VIL2 can be different from the first initialization voltage of the first initialization voltage line VIL1. As another example, the second initialization voltage can be the same as the first initialization voltage. The gate electrode of the seventh transistor T7 can be connected to the fourth gate line GBL, the first electrode of the seventh transistor T7 can be connected to the fourth node N4, and the second electrode of the seventh transistor T7 can be connected to the second initialization voltage line VIL2. The first electrode of the seventh transistor T7 can be electrically connected to the first electrode of the light-emitting element ED and the second electrode of the sixth transistor T6 through the fourth node N4. For example, the first electrode of the seventh transistor T7 can be the drain electrode, and the second electrode of the seventh transistor T7 can be the source electrode, but is not limited to this.

[0092] The eighth transistor T8 can be turned on by the fourth gate signal of the fourth gate line GBL, and electrically connects the bias voltage line VBL and the first node N1, which is the first electrode of the first transistor T1. The gate electrode of the eighth transistor T8 can be connected to the fourth gate line GBL, the first electrode of the eighth transistor T8 can be connected to the bias voltage line VBL, and the second electrode of the eighth transistor T8 can be connected to the first node N1. The second electrode of the eighth transistor T8 can be electrically connected to the first electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the fifth transistor T5 through the first node N1. For example, the first electrode of the eighth transistor T8 can be the drain electrode, and the second electrode of the eighth transistor T8 can be the source electrode, but it is not limited to this. Optionally, the eighth transistor T8 can be omitted.

[0093] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include oxide-based semiconductor regions. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may have a coplanar structure in which the gate electrode is disposed above the oxide-based semiconductor region. Transistors with a coplanar structure can have excellent leakage current characteristics and can be driven at low frequencies, thereby reducing power consumption. Therefore, the display device 10 includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 with excellent leakage current characteristics, thereby preventing leakage current from flowing inside the pixel and stably maintaining the voltage inside the pixel.

[0094] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can correspond to n-type transistors. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can output the current flowing into the first electrode to the second electrode based on the high gate voltage applied to the gate electrode.

[0095] As another example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a silicon-based semiconductor region. For example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may include a semiconductor region made of low-temperature polycrystalline silicon (LTPS). The semiconductor region made of LTPS can have high electron mobility and excellent conduction characteristics. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may correspond to a p-type transistor. A p-type transistor can output current flowing into the first electrode to the second electrode based on a low gate voltage applied to the gate electrode.

[0096] Capacitor C1 can be connected between the third node N3, which serves as the gate electrode of the first transistor T1, and the drive voltage line VDL. For example, the first capacitor electrode of capacitor C1 can be connected to the third node N3, and the second capacitor electrode of capacitor C1 can be connected to the drive voltage line VDL, thereby maintaining the potential difference between the drive voltage line VDL and the gate electrode of the first transistor T1.

[0097] Figure 1 This illustrates a display device 10 according to an embodiment (see also...) Figure 4 A plan view of the light-emitting region EA, the gate driver 810, and the clock line CKL.

[0098] Reference Figure 3 The display area DA may include multiple light-emitting areas EA. Each light-emitting area EA may emit light from a light-emitting element ED. Each light-emitting area EA may include a first light-emitting area EA1, a second light-emitting area EA2, and a third light-emitting area EA3. For example, the first light-emitting area EA1 may emit light of a first color, such as red light, the second light-emitting area EA2 may emit light of a second color, such as green light, and the third light-emitting area EA3 may emit light of a third color, such as blue light; however, this disclosure is not limited thereto.

[0099] A single pixel can represent a white grayscale level by including a first emitting region EA1, two second emitting regions EA2, and a third emitting region EA3, but the configuration of a single pixel is not limited to this. A white grayscale level can be represented by a combination of light emitted from a first emitting region EA1, light emitted from the two second emitting regions EA2, and light emitted from a third emitting region EA3.

[0100] The areas of the first luminous region EA1, the second luminous region EA2, and the third luminous region EA3 can be different from each other. For example, the area of ​​the third luminous region EA3 can be larger than the area of ​​the first luminous region EA1, and the area of ​​the first luminous region EA1 can be larger than the area of ​​the second luminous region EA2, but this is not a limitation. As another example, the areas of the first luminous region EA1, the second luminous region EA2, and the third luminous region EA3 can be the same.

[0101] Gate driver 810 may include a first gate driver 811 and a second gate driver 812. The first gate driver 811 can direct... Figure 3 The first gate line GWL supplies the first gate signal. The second gate driver 812 can supply the first gate signal. Figure 3 The second gate line GCL supplies the second gate signal and to Figure 2 The third gate line GIL supplies the third gate signal.

[0102] The first gate driver 811 may overlap with the light-emitting region EA. The first gate driver 811 may include multiple stages arranged in the Y-axis direction. In the scan driver 800, the first gate driver 811 may be located on the outermost side of the display region DA. For example, the first gate driver 811 may be located at the left or right edge of the display region DA. In the scan driver 800, the first gate driver 811 may be closest to the clock line CKL. Therefore, the display device 10 can improve the signal sensitivity of the first gate driver 811. The length of the first gate driver 811 in the X-axis direction may be greater than the width of the first gate driver 811 in the Y-axis direction.

[0103] The second gate driver 812 may overlap with the light-emitting region EA. The second gate driver 812 may include multiple stages arranged in the Y-axis direction. The second gate driver 812 may be positioned closer to the interior of the display region DA than the first gate driver 811. The second gate driver 812 may be positioned between the first gate driver 811 and the light-emitting control driver 820. The first gate driver 811 may be positioned between the clock line CKL and the second gate driver 812. The length of the second gate driver 812 in the X-axis direction may be greater than its width in the Y-axis direction. The number of second gate drivers 812 may be less than the number of first gate drivers 811, and the width of the second gate driver 812 in the Y-axis direction may be greater than the width of the first gate driver 811 in the Y-axis direction, but this disclosure is not limited thereto.

[0104] The light-emitting control driver 820 may overlap with the light-emitting region EA. The light-emitting control driver 820 may include multiple stages arranged in the Y-axis direction. The light-emitting control driver 820 may be positioned closer to the interior of the display region DA than the first gate driver 811 and the second gate driver 812. The light-emitting control driver 820 may not be positioned in the X-axis direction of the second gate driver 812, but may be positioned in a diagonal direction between the X-axis and Y-axis directions. The light-emitting control driver 820 and the second gate driver 812 may not be positioned in the same row. The length of the light-emitting control driver 820 in the X-axis direction may be greater than the width of the light-emitting control driver 820 in the Y-axis direction. The number of light-emitting control drivers 820 may be less than the number of first gate drivers 811, and the width of the light-emitting control driver 820 in the Y-axis direction may be greater than the width of the first gate driver 811 in the Y-axis direction, but this disclosure is not limited thereto.

[0105] The clock line CKL can be located in the non-display area NDA and extend in the Y-axis direction. The clock line CKL can be positioned adjacent to the display area DA to supply a clock signal to the scan driver 800. The clock line CKL can be located closest to the first gate driver 811 in the scan driver 800. The clock line CKL may not overlap with the light-emitting area EA. By positioning the clock line CKL in the non-display area NDA, it prevents the clock line CKL from intersecting with pixels SP in the display area DA (see...). Figure 5 The pixel circuits or signal lines are coupled together.

[0106] Therefore, the display device 10 includes a scan driver 800 disposed in the display area DA, thereby reducing the area of ​​the non-display area NDA and reducing power consumption.

[0107] Figure 1 This illustrates a display device 10 according to an embodiment (see also...) Figure 5 A plan view showing the connection relationship between the gate driver 810 and the clock line CKL.

[0108] Reference Figure 6 The clock line CKL may include a first write clock line WCK1, a second write clock line WCK2, a third write clock line WCK3 and a fourth write clock line WCK4, a first control clock line CCK1 and a second control clock line CCK2, as well as a first light emission clock line ECK1 and a second light emission clock line ECK2.

[0109] The first write clock line WCK1, the second write clock line WCK2, the third write clock line WCK3, and the fourth write clock line WCK4 can extend in the Y-axis direction and be spaced apart from each other in the X-axis direction. Among the clock lines CCKL, the first write clock line WCK1, the second write clock line WCK2, the third write clock line WCK3, and the fourth write clock line WCK4 can be closest to the display area DA. The first write clock line WCK1, the second write clock line WCK2, the third write clock line WCK3, and the fourth write clock line WCK4 can supply clock signals to the first gate driver 811 through the first connection line CNL1. The first connection line CNL1 can extend from the non-display area NDA to the display area DA in the X-axis direction. The first connection line CNL1 can intersect with the gate low voltage line VGLL in the display area DA.

[0110] The gate low voltage line VGLL and the gate high voltage line VGHL can be disposed on both sides of the first gate driver 811 and extend in the Y-axis direction. The gate low voltage line VGLL and the gate high voltage line VGHL can be disposed in the display area DA and electrically connected to the first gate driver 811.

[0111] The first control clock line CCK1 and the second control clock line CCK2 can extend in the Y-axis direction and be spaced apart from each other in the X-axis direction. The first control clock line CCK1 and the second control clock line CCK2 can be closer to the display area DA than the first light-emitting clock line ECK1 and the second light-emitting clock line ECK2. The first control clock line CCK1 and the second control clock line CCK2 can supply clock signals to the second gate driver 812 through the second connection line CNL2. The second connection line CNL2 can extend from the non-display area NDA to the display area DA in the X-axis direction. The second connection line CNL2 can pass between adjacent stages in the Y-axis direction among the multiple stages of the first gate driver 811. The second connection line CNL2 can intersect with the first write clock line WCK1, the second write clock line WCK2, the third write clock line WCK3, and the fourth write clock line WCK4 in the non-display area NDA, and can intersect with the gate low voltage line VGLL and the gate high voltage line VGHL in the display area DA.

[0112] The gate high voltage line VGHL, the first gate low voltage line VGLL1, and the second gate low voltage line VGLL2 can be disposed on both sides of the second gate driver 812 and extend in the Y-axis direction. The gate high voltage line VGHL, the first gate low voltage line VGLL1, and the second gate low voltage line VGLL2 can be disposed in the display area DA and electrically connected to the second gate driver 812.

[0113] The first light-emitting clock line ECK1 and the second light-emitting clock line ECK2 can extend in the Y-axis direction and are spaced apart from each other in the X-axis direction. Among the clock lines CKL, the first light-emitting clock line ECK1 and the second light-emitting clock line ECK2 can be furthest from the display area DA. The first light-emitting clock line ECK1 and the second light-emitting clock line ECK2 can supply clock signals to the light-emitting control driver 820 through the third connection line CNL3. The third connection line CNL3 can extend from the non-display area NDA to the display area DA in the X-axis direction. The third connection line CNL3 can pass between adjacent stages in the Y-axis direction among the multiple stages of the first gate driver 811, and can also pass between adjacent stages in the Y-axis direction among the multiple stages of the second gate driver 812. The third connection line CNL3 can intersect with the first write clock line WCK1, the second write clock line WCK2, the third write clock line WCK3, the fourth write clock line WCK4, the first control clock line CCK1, and the second control clock line CCK2 in the non-display area NDA, and can intersect with the gate low voltage line VGLL and the gate high voltage line VGHL in the display area DA.

[0114] The gate low voltage line VGLL3 and the gate high voltage line VGHL can be disposed on both sides of the light-emitting control driver 820 and extend in the Y-axis direction. The gate low voltage line VGLL3 and the gate high voltage line VGHL can be disposed in the display area DA and electrically connected to the light-emitting control driver 820.

[0115] The first starting connection line CFL1, the second starting connection line CFL2, and the third starting connection line CFL3 can pass through the left and top sides of the non-display area NDA and are electrically connected to the first starting line FLM1, the second starting line FLM2, and the third starting line FLM3 of the display area DA, respectively. Each of the first starting connection line CFL1, the second starting connection line CFL2, and the third starting connection line CFL3 may include a first portion extending in the Y-axis direction from the left side of the non-display area NDA, a second portion bending from the first portion and extending in the X-axis direction from the top side of the non-display area NDA, and a third portion bending from the second portion and extending to the display area DA. The first portion of the first starting connection line CFL1, the first portion of the second starting connection line CFL2, and the first portion of the third starting connection line CFL3 may be farther from the display area DA than the clock line CBL on the left side of the non-display area NDA. The first start connection line CFL1 can supply a first start signal to the first start line FLM1 electrically connected to the first gate driver 811, the second start connection line CFL2 can supply a second start signal to the second start line FLM2 electrically connected to the second gate driver 812, and the third start connection line CFL3 can supply a third start signal to the third start line FLM3 electrically connected to the light emission control driver 820.

[0116] Figure 1 This illustrates a display device 10 according to an embodiment (see also...) Figure 6 A block diagram of the first gate driver 811.

[0117] Reference Figure 3 The first gate driver 811 may include multiple stage STGs. A first write clock line WCK1, a second write clock line WCK2, a third write clock line WCK3, and a fourth write clock line WCK4 can supply the stage STGs with first clock signals CK1, second clock signals CK2, third clock signals CK3, and fourth clock signals CK4, respectively. A gate high voltage line VGHL can supply the stage STG with a gate high voltage VGH, and a gate low voltage line VGLL can supply the stage STG with a gate low voltage VGL. The stage STG can generate a first gate signal or a scan write signal and supply the generated signal to... Figure 7 The first gate line GWL or scan write line. The STG stages can include STG1, STG2, STG3, and STG4.

[0118] The first stage STG1 can be connected to the first start line FLM1 and can receive the start signal FLM. The first stage STG1 can receive the third clock signal CK3 and the fourth clock signal CK4, the gate high voltage VGH and the gate low voltage VGL, and supply the first scan write signal GW1 to the first scan write line GWL1.

[0119] The second-stage STG2 can receive the carry signal CR from the first-stage STG1. The second-stage STG2 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH and the gate low voltage VGL, and supply the second scan write signal GW2 to the second scan write line GWL2.

[0120] The third-stage STG3 can receive the carry signal CR from the second-stage STG2. The third-stage STG3 can receive the third clock signal CK3 and the fourth clock signal CK4, the gate high voltage VGH and the gate low voltage VGL, and supply the third scan write signal GW3 to the third scan write line GWL3.

[0121] The fourth stage STG4 can receive the carry signal CR from the third stage STG3. The fourth stage STG4 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH and the gate low voltage VGL, and supply the fourth scan write signal GW4 to the fourth scan write line GWL4.

[0122] Figure 1 This illustrates a display device 10 according to an embodiment (see also...) Figure 7 A block diagram of the second gate driver 812.

[0123] Reference Figure 3 The second gate driver 812 may include multiple stage STGs. A first control clock line CCK1 and a second control clock line CCK2 can supply a first clock signal CK1 and a second clock signal CK2 to the stage STGs. A gate high voltage line VGHL can supply a gate high voltage VGH to the stage STGs, a first gate low voltage line VGLL1 can supply a first gate low voltage VGL1 to the stage STGs, and a second gate low voltage line VGLL2 can supply a second gate low voltage VGL2 to the stage STGs. The stage STGs can generate a second gate signal or a scan control signal and supply the generated signal to... Figure 3 The second gate line (GCL) or scan control line. The STG stage can generate a third gate signal or scan initialization signal and supply the generated signal to... Figure 8 The third gate line GIL or scan initialization line.

[0124] The STG levels can include STG1 (first level), STG2 (second level), STG3 (third level), and STG4 (fourth level).

[0125] The first-stage STG1 can be connected to the second start line FLM2 and can receive the start signal FLM. The first-stage STG1 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH, the first gate low voltage VGL1 and the second gate low voltage VGL2, so as to supply the first scan control signal GC1 to the first scan control line GCL1 and the first scan initialization signal GI1 to the first scan initialization line GIL1.

[0126] The second-stage STG2 can receive the carry signal CR from the first-stage STG1. The second-stage STG2 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH, and the first gate low voltage VGL1 and the second gate low voltage VGL2 to supply the second scan control signal GC2 to the second scan control line GCL2 and the second scan initialization signal GI2 to the second scan initialization line GIL2.

[0127] The third-stage STG3 can receive the carry signal CR from the second-stage STG2. The third-stage STG3 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH, and the first gate low voltage VGL1 and the second gate low voltage VGL2 to supply the third scan control signal GC3 to the third scan control line GCL3, and to supply the third scan initialization signal GI3 to the third scan initialization line GIL3.

[0128] The fourth stage STG4 can receive the carry signal CR from the third stage STG3. The fourth stage STG4 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH, and the first gate low voltage VGL1 and the second gate low voltage VGL2 to supply the fourth scan control signal GC4 to the fourth scan control line GCL4, and to supply the fourth scan initialization signal GI4 to the fourth scan initialization line GIL4.

[0129] Figure 1 This illustrates a display device 10 according to an embodiment (see also...) Figure 8 Block diagram of the light-emitting control driver 820.

[0130] Reference Figure 3 The light-emitting control driver 820 may include multiple stage STGs. A first light-emitting clock line ECK1 and a second light-emitting clock line ECK2 can supply a first clock signal CK1 and a second clock signal CK2 to the stage STGs. A gate high voltage line VGHL can supply a gate high voltage VGH to the stage STGs, and a gate low voltage line VGLL can supply a gate low voltage VGL to the stage STGs. The stage STGs can generate light-emitting signals and supply the generated signals to... Figure 9The light emission control line EML. The STG level can include the first STG1, the second STG2, the third STG3, and the fourth STG4.

[0131] The first stage STG1 can be connected to the third start line FLM3 and can receive the start signal FLM. The first stage STG1 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH and the gate low voltage VGL, and supply the first light emission signal EM1 to the first light emission control line EML1.

[0132] The second-stage STG2 can receive the carry signal CR from the first-stage STG1. The second-stage STG2 can receive the first clock signal CK1 and the second clock signal CK2, the gate high voltage VGH and the gate low voltage VGL, and supply the second light-emitting signal EM2 to the second light-emitting control line EML2.

[0133] The third-stage STG3 can receive the carry signal CR from the second-stage STG2. The third-stage STG3 can receive the first clock signal CK1, the second clock signal CK2, the gate high voltage VGH, and the gate low voltage VGL, and supply the third light-emitting signal EM3 to the third light-emitting control line EML3.

[0134] The fourth stage STG4 can receive the carry signal CR from the third stage STG3. The fourth stage STG4 can receive the first clock signal CK1, the second clock signal CK2, the gate high voltage VGH, and the gate low voltage VGL, and supply the fourth light emission signal EM4 to the fourth light emission control line EML4.

[0135] Figure 1 This illustrates a display device 10 according to an embodiment (see also...) Figure 9 Cross-sectional view of ).

[0136] Reference Figure 1 Display panel 100 (see) Figure 4 It may include a substrate SUB, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GTI1, a first gate layer GTL1, a second gate insulating layer GTI2, a second gate layer GTL2, a first interlayer insulating layer ILD1, a first connection metal layer CTL1, a second interlayer insulating layer ILD2, a second connection metal layer CTL2, a third interlayer insulating layer ILD3, a second active layer ACTL2, a third gate insulating layer GTI3, a third gate layer GTL3, a fourth interlayer insulating layer ILD4, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, and a pixel electrode layer PXL.

[0137] The substrate SUB can be a matrix substrate or a matrix component. The substrate SUB can be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB can include, but is not limited to, polymer resins such as polyimide (PI). As another example, the substrate SUB can include glass or metal materials.

[0138] The buffer layer BF can be disposed on the substrate SUB. For example, the buffer layer BF may include an inorganic membrane capable of preventing the penetration of air or moisture. For example, the buffer layer BF may include multiple inorganic membranes stacked alternately.

[0139] The first active layer ACTL1 can be disposed on the buffer layer BF. The first active layer ACTL1 can include a silicon-based material. For example, the first active layer ACTL1 can be made of low-temperature polycrystalline silicon (LTPS). The first active layer ACTL1 can include the semiconductor region SACT of the scan transistor STR, the first electrode SSE, and the second electrode SDE.

[0140] The scan transistor STR can be set in the display area DA to form a scan driver 800 (see...). Figure 4 Therefore, the first gate driver 811 (see...) Figure 4 ) and second gate driver 812 (see Figure 4 ) and the light control driver 820 (see Figure 2 The scan driver 800 may include multiple scan transistors STRs disposed in the first active layer ACTL1 and the first gate layer GTL1. The scan transistors STRs of the scan driver 800 may be aligned with the pixel SP (see [link to scan driver]) in the thickness direction (Z-axis direction). Figure 5 The transistor TR overlaps.

[0141] The first gate insulating layer GTI1 can be disposed on the first active layer ACTL1. The first gate insulating layer GTI1 can insulate the first active layer ACTL1 and the first gate layer GTL1 from each other.

[0142] The first gate layer GTL1 can be disposed on the first gate insulating layer GTI1. The first gate layer GTL1 may include the gate electrode SGE of the scan transistor STR and the interconnect CNL. The interconnect CNL may be... Figure 6 One of the first connection line CNL1, the second connection line CNL2, and the third connection line CNL3 can be used to electrically connect the clock line CKL and the scan driver 800.

[0143] The second gate insulating layer GTI2 can be disposed on the first gate layer GTL1. The second gate insulating layer GTI2 can insulate the first gate layer GTL1 and the second gate layer GTL2 from each other.

[0144] A second gate layer GTL2 may be disposed on a second gate insulating layer GTI2. The second gate layer GTL2 may include a scan capacitor electrode SCP. The scan capacitor electrode SCP may overlap with the gate electrode SGE of the scan transistor STR to form the scan capacitor of the scan driver 800.

[0145] The first interlayer insulating layer ILD1 can be disposed on the second gate layer GTL2. The first interlayer insulating layer ILD1 can insulate the second gate layer GTL2 and the first interconnecting metal layer CTL1 from each other.

[0146] The first connection metal layer CTL1 can be disposed on the first interlayer insulating layer ILD1. The first connection metal layer CTL1 may include a first scan connection electrode SCE1, a gate low voltage line VGLL, a second scan connection electrode SCE2, and a first capacitor electrode CPE1. The first scan connection electrode SCE1 can electrically connect the clock line CKL and the connection line CNL. The gate low voltage line VGLL can connect the gate low voltage VGL (see...) Figure 8 or Figure 3 The signal is supplied to the scan driver 800. The second scan connection electrode SCE2 can electrically connect the connection line CNL, the connection electrode CE, and the first electrode SSE of the scan transistor STR. The first capacitor electrode CPE1 can overlap with the metal layer BML to form the first capacitor of the pixel SP.

[0147] The second interlayer insulation layer ILD2 can be disposed on the first connecting metal layer CTL1. The second interlayer insulation layer ILD2 can insulate the first connecting metal layer CTL1 and the second connecting metal layer CTL2 from each other.

[0148] A second connection metal layer CTL2 may be disposed on the second interlayer insulating layer ILD2. The second connection metal layer CTL2 may include a metal layer BML. The metal layer BML may overlap with the semiconductor region ACT of the transistor TR and block light incident on the semiconductor region ACT of the transistor TR. The metal layer BML may receive a predetermined voltage and maintain a stable voltage, and may prevent coupling between the scanning transistor STR and the transistor TR.

[0149] The third interlayer insulating layer ILD3 can be disposed on the second connecting metal layer CTL2. The third interlayer insulating layer ILD3 can insulate the second connecting metal layer CTL2 and the second active layer ACTL2 from each other.

[0150] The second active layer ACTL2 can be disposed on the third interlayer insulating layer ILD3. The second active layer ACTL2 may include an oxide-based material. The second active layer ACTL2 may include the semiconductor region ACT of the transistor TR, the first electrode DE, and the second electrode SE.

[0151] A transistor TR can be placed in the display area DA to form a pixel SP. Figure 3 One of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The transistor TR of the pixel SP and the scanning transistor STR of the scan driver 800 can be overlapped in the thickness direction (Z-axis direction).

[0152] The third gate insulating layer GTI3 can be disposed on the second active layer ACTL2. The third gate insulating layer GTI3 can insulate the second active layer ACTL2 and the third gate layer GTL3 from each other.

[0153] The third gate layer GTL3 can be disposed on the third gate insulating layer GTI3. The third gate layer GTL3 may include the gate electrode GE of the transistor TR.

[0154] The fourth interlayer insulating layer ILD4 can be disposed on the third gate layer GTL3. The fourth interlayer insulating layer ILD4 can insulate the third gate layer GTL3 and the first source metal layer SDL1 from each other.

[0155] The first source metal layer SDL1 can be disposed on the fourth interlayer insulating layer ILD4. The first source metal layer SDL1 may include a clock line CKL, a connection electrode CE, and a second capacitor electrode CPE2. The clock line CKL can be disposed in the non-display area NDA and extend in the Y-axis direction. The clock line CKL can be configured to be adjacent to the display area DA to supply a clock signal to the scan driver 800. The clock line CKL can be configured to be closest to the first gate driver 811 in the scan driver 800. The clock line CKL may not overlap with the light-emitting area EA. The connection electrode CE can electrically connect the second scan connection electrode SCE2 and the first electrode DE of the transistor TR. The second capacitor electrode CPE2 can overlap with the gate electrode GE of the transistor TR to form the second capacitor of the pixel SP.

[0156] The first via layer VIA1 can be disposed on the first source metal layer SDL1. The first via layer VIA1 can insulate the first source metal layer SDL1 and the second source metal layer SDL2 from each other.

[0157] A second source metal layer SDL2 can be disposed on the first via layer VIA1. The second source metal layer SDL2 may include an anode connection electrode ANE and a first low-potential line VSL1. The anode connection electrode ANE can electrically connect the pixel electrode AE ​​and the transistor TR. The first low-potential line VSL1 can supply a low-potential voltage to the second low-potential line VSL2.

[0158] The second via layer VIA2 can be disposed on the second source metal layer SDL2. The second via layer VIA2 can insulate the second source metal layer SDL2 and the pixel electrode layer PXL from each other.

[0159] The pixel electrode layer PXL can be disposed on the second via layer VIA2. The pixel electrode layer PXL may include a pixel electrode AE ​​and a second low-potential line VSL2. The pixel electrode AE ​​can be exposed through the light-emitting region EA. The pixel electrode AE ​​can be... ​ The first electrode of the light-emitting element (ED). The second low-potential line VSL2 can supply a low-potential voltage to the second electrode of the light-emitting element (ED).

[0160] A pixel-defining film (PDL) can be disposed on a second via layer (VIA2). The PDL can define multiple light-emitting regions (EA). The PDL can include an organic insulating material, such as polyimide (PI).

[0161] The dammed optical interlayer (DAM) can be disposed on the fourth interlayer insulating layer (ILD4) in the non-display area (NDA). The dammed DAM can surround the first via layer (VIA1), the second via layer (VIA2), and the pixel defining film (PDL). The clock line (CKL) can be surrounded by the dammed DAM.

[0162] This disclosure should not be construed as limiting itself to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of this disclosure to those skilled in the art.

[0163] While this disclosure has been specifically shown and described with reference to some embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: The display area includes pixels that emit light and scan drivers configured to supply scan signals to the pixels; and A non-display area surrounds the display area, and the non-display area includes a clock line configured to supply a clock signal to the scan driver, the clock line extending in a first direction. The scan driver includes: A first gate driver is configured to supply a first gate signal to the pixel; A second gate driver is configured to supply a second gate signal and a third gate signal to the pixel; and A light emission control driver, configured to supply a light emission signal to the pixel, and The clock line is closest to the first gate driver among the first gate driver, the second gate driver, and the light-emitting control driver.

2. The display device according to claim 1, wherein, The length of each of the first gate driver, the second gate driver, and the light-emitting control driver in a second direction intersecting the first direction is greater than the width of the corresponding one of the first gate driver, the second gate driver, and the light-emitting control driver in the first direction.

3. The display device according to claim 1, wherein, The width of the second gate driver in the first direction and the width of the light-emitting control driver in the first direction are both greater than the width of the first gate driver in the first direction.

4. The display device according to claim 1, wherein, The display device further includes a connecting line extending in a second direction intersecting the first direction, and the connecting line electrically connecting the clock line and the scan driver.

5. The display device according to claim 4, wherein, The clock line includes: Write the clock line and configure it to supply a first clock signal to the first gate driver; The control clock line is configured to supply a second clock signal to the second gate driver; and The light-emitting clock line is configured to supply a third clock signal to the light-emitting control driver.

6. The display device according to claim 5, wherein, Of the write clock line, the control clock line, and the light emission clock line, the write clock line is closest to the display area.

7. The display device according to claim 5, wherein, The connecting line includes: The first connection line electrically connects the write clock line and the first gate driver; The second connection line electrically connects the control clock line and the second gate driver; and The third connection line electrically connects the light-emitting clock line and the light-emitting control driver.

8. The display device according to claim 7, wherein, The first gate driver includes a plurality of stages arranged in the first direction, and The second connection line passes between the stages that are adjacent to each other in the first direction among the plurality of stages of the first gate driver.

9. The display device according to claim 8, wherein, The second gate driver includes multiple stages arranged in the first direction, and The third connection line passes between adjacent stages in the first direction among the plurality of stages of the first gate driver and between adjacent stages in the first direction among the plurality of stages of the second gate driver.

10. The display device according to claim 1, wherein, The display device further includes: A start connection line, disposed in the non-display area, is provided to supply a start signal; and A start line is provided in the display area and is connected to the start connection line to supply the start signal to the scan driver.

11. The display device according to claim 10, wherein, The starting line includes: A first start line is configured to supply a first start signal to the first gate driver; A second start line is configured to supply a second start signal to the second gate driver; and The third start line is configured to supply a third start signal to the light emission control driver, and The starting connection line includes: A first start connection line is configured to supply the first start signal to the first start line; A second start connection line is configured to supply the second start signal to the second start line; and The third start connection line is configured to supply the third start signal to the third start line.

12. The display device according to claim 11, wherein, Each of the first starting connection line, the second starting connection line, and the third starting connection line includes: The first part is disposed on a first side of the non-display area including the clock line, and the first part extends in the first direction; The second portion is connected to the first portion, and the second portion extends from the second side of the non-display area adjacent to the first side in a second direction intersecting the first direction; and The third part is connected to the second part and extends into the display area.

13. The display device according to claim 1, wherein, The scan driver further includes a scan transistor disposed in a first active layer comprising a first material, and The pixel includes a transistor disposed in a second active layer comprising a second material different from the first material.

14. The display device according to claim 13, wherein, The pixels include: Light-emitting elements; The first transistor supplies driving current to the light-emitting element; The second transistor supplies data voltage to the first electrode of the first transistor; The third transistor electrically connects the second electrode of the first transistor to the gate electrode of the first transistor. A fourth transistor is configured to supply an initialization voltage to the gate electrode of the first transistor; A fifth transistor is configured to supply a drive voltage to the first electrode of the first transistor; and The sixth transistor electrically connects the second electrode of the first transistor to the first electrode of the light-emitting element.

15. The display device according to claim 14, wherein, The first gate driver is configured to supply the first gate signal to the gate electrode of the second transistor. The second gate driver is configured to supply the second gate signal to the gate electrode of the third transistor and the third gate signal to the gate electrode of the fourth transistor. The light emission control driver is configured to supply the light emission signal to the gate electrode of each of the fifth and sixth transistors.

16. An electronic device, wherein, The electronic device includes: Display device for providing images, and The display device includes: The display area includes pixels and a scan driver, wherein the pixels include transistors to emit light, and the scan driver includes scan transistors to supply scan signals to the pixels; A non-display area surrounding the display area, and the non-display area including a clock line supplying a clock signal to the scan driver, the clock line extending in a first direction; The first active layer includes the semiconductor region of the scanning transistor; A first gate layer is disposed on the first active layer, and the first gate layer includes the gate electrode of the scan transistor; A second gate layer is disposed on the first gate layer; A first connection metal layer is disposed on the second gate layer, and the first connection metal layer includes a gate low voltage line; A second connecting metal layer is disposed on the first connecting metal layer, and the second connecting metal layer includes a metal layer; A second active layer is disposed on the second interconnecting metal layer, and the second active layer includes a semiconductor region of the transistor that overlaps with the metal layer; A third gate layer is disposed on the second active layer, and the third gate layer includes the gate electrode of the transistor; and A first source metal layer is disposed on the third gate layer, and the first source metal layer includes the clock line.

17. The electronic device according to claim 16, wherein, The scanning transistor and the transistor overlap in the thickness direction.

18. The electronic device according to claim 16, wherein, The electronic device further includes a connecting line disposed in the first connecting metal layer and electrically connecting the clock line and the scanning transistor.

19. The electronic device according to claim 16, wherein, The second gate layer includes a scan capacitor electrode that overlaps with the gate electrode of the scan transistor to form the scan capacitor of the scan driver. The first connecting metal layer further includes: a first capacitor electrode, overlapping the metal layer to form a first capacitor for the pixel, and The first source metal layer further includes a second capacitor electrode, which overlaps with the gate electrode of the transistor to form a second capacitor for the pixel.

20. The electronic device according to claim 16, wherein, The display device is a part of one of a television, laptop computer, monitor, billboard, Internet of Things device, mobile phone, smartphone, tablet PC, smartwatch, watch phone, mobile communication terminal, electronic notebook, e-book, portable multimedia player, navigation device, and ultra-mobile PC.

Images