Array substrate and display device

Abstract

The array substrate is provided with a peripheral area and a display area which are adjacently arranged, the array substrate comprises a substrate body, a plurality of scanning lines and a first gate drive circuit, and the scanning lines are arranged on the substrate body in the first direction; the first gate drive circuit is arranged in the peripheral area on the substrate and corresponds to the multiple scanning lines, the first gate drive circuit comprises multiple stages of cascaded shift register units, and each shift register unit corresponds to at least two scanning lines and provides a drive signal; the first gate drive circuit further comprises an auxiliary drive circuit, the auxiliary drive circuit comprises a control signal group and a plurality of switch groups, the auxiliary drive circuit is connected between each shift register unit and the at least two scanning lines corresponding to the shift register unit, and the drive signals are transmitted to the at least two scanning lines through the auxiliary drive circuit. The invention further provides a display device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display panel, in particular to an array substrate and a display device. BACKGROUND

[0002] The multi-stage shift register unit array of the gate drive circuit (GOA) of the traditional liquid crystal display array substrate (LCD) is arranged in the peripheral area of the array substrate, and is transmitted to the gate of the thin film transistor of each pixel unit through the horizontal scanning line and controls the switching thereof. Each stage of the shift register unit corresponds to a row of scanning lines (GL), and a row of scanning lines corresponds to the switching of a row of pixel units, that is, the number of stages of the shift register unit required is the same as the number of rows of scanning lines. The gate drive circuit of the traditional design occupies a large space. With the development of science and technology, the display panel has higher and higher requirements for narrow frame, and the traditional design is difficult to meet. SUMMARY

[0003] In order to solve the above problems, the present application provides an array substrate, which has a peripheral area and a display area arranged adjacent to each other, and the array substrate comprises:

[0004] a substrate;

[0005] a plurality of scanning lines arranged on the substrate in a first direction;

[0006] a first gate drive circuit arranged in the peripheral area on the substrate and corresponding to the plurality of scanning lines, the first gate drive circuit comprising a plurality of cascaded shift register units, each shift register unit corresponding to at least two scanning lines and providing a driving signal; the first gate drive circuit further comprising an auxiliary drive circuit, the auxiliary drive circuit comprising a control signal group and a plurality of switch groups, the auxiliary drive circuit being connected between each shift register unit and the at least two scanning lines corresponding thereto, and the driving signal being transmitted to the at least two scanning lines through the auxiliary drive circuit;

[0007] wherein the first gate drive circuit comprises a first shift register unit, the plurality of switch groups comprises a first switch group, the first shift register unit is connected to a first scanning line via the first switch group, the first switch group comprises a first switch and a second switch, the control end of the first switch and the control end of the second switch are connected to the control signal group, the first end of the first switch is used to receive a fixed low voltage, the first end of the second switch is connected to the output end of the first shift register unit, and the second end of the first switch and the second end of the second switch are connected to the first scanning line.

[0008] In an embodiment of the array substrate, the first shift register unit outputs a high level signal in a first time period, the first time period includes a first sub-period and a second sub-period in sequence, in the first sub-period, the second switch is open, the first switch is closed, and the first scan line receives the high level signal through the second switch; in the second sub-period, the first switch is open, the second switch is closed, and the first scan line receives the fixed low potential through the first switch.

[0009] In an embodiment of the array substrate, two scan lines adjacent in the second direction are denoted as the first scan line and the second scan line respectively, the first switch group further includes a third switch and a fourth switch, control ends of the third switch and the fourth switch are connected to the control signal group, a first end of the third switch is used for receiving the fixed low potential, a first end of the fourth switch is connected to an output end of the first shift register unit, and second ends of the third switch and the fourth switch are connected to the second scan line.

[0010] In an embodiment of the array substrate, the first shift register unit outputs a high level signal in a first time period, in a first sub-period of the first time period, the second switch and the third switch are open, the first switch and the fourth switch are closed, the first scan line receives the high level signal through the second switch, and the second scan line receives the fixed low potential through the third switch; in a second sub-period of the first time period, the first switch and the fourth switch are open, the second switch and the third switch are closed, the first scan line receives the fixed low potential through the first switch, and the second scan line receives the high level signal through the fourth switch.

[0011] In an embodiment of the array substrate, the control signal group includes a first signal line and a second signal line, the first signal line and the second signal line extend along the second direction;

[0012] In an embodiment of the array substrate, the first switch to the fourth switch are P-type transistors, a control end of the second switch and a control end of the third switch are connected to the first signal line to receive a first control signal, a control end of the first switch and a control end of the fourth switch are connected to the second signal line to receive a second control signal; in the first sub-period, the first control signal is high level, and the second control signal is low level; in the second sub-period, the first control signal is low level, and the second control signal is high level; or,

[0013] The first switch and the third switch are N-type transistors, the second switch and the fourth switch are P-type transistors, the control end of the first switch and the control end of the second switch are connected to the first signal line to receive a first control signal, and the control end of the third switch and the control end of the fourth switch are connected to the second signal line to receive a second control signal; in the first time period, the first control signal is high, and the second control signal is low; in the second time period, the first control signal is low, and the second control signal is high.

[0014] In an embodiment of the array substrate, the control signal group includes a first control signal, a second control signal, a third control signal, and a fourth control signal, the control end of the second switch is configured to receive the first control signal, the control end of the first switch is configured to receive the third control signal, the control end of the third switch is configured to receive the fourth control signal, and the control end of the fourth switch is configured to receive the second control signal; the first shift register unit outputs a high-level signal in a first time period, in a first time period of the first time period, the second switch and the third switch are turned on, and the first switch and the fourth switch are turned off, the first scan line receives the high-level signal through the second switch, and the second scan line receives the fixed low potential through the third switch.

[0015] In an embodiment of the array substrate, three scan lines adjacent in the second direction are denoted as the first scan line, the second scan line, and the third scan line, the control signal group includes a first control signal, a second control signal, a third control signal, a fourth control signal, a fifth control signal, and a sixth control signal, the first switch group further includes a fifth switch and a sixth switch, the control end of the first switch is configured to receive the third control signal, the control end of the second switch is configured to receive the first control signal, the control end of the third switch is configured to receive the fourth control signal, the control end of the fourth switch is configured to receive the second control signal, the control end of the fifth switch is configured to receive the sixth control signal, the control end of the sixth switch is configured to receive the fifth control signal, the first end of the fifth switch is configured to receive the fixed low potential, the first end of the sixth switch is connected to the output end of the first shift register unit, and the second end of the fifth switch and the second end of the sixth switch are connected to the third scan line.

[0016] In an embodiment of the array substrate, the first shift register unit outputs a high level signal in a first time period, in a first sub time period of the first time period, the second switch, the third switch and the fifth switch are opened, the first switch, the fourth switch and the sixth switch are closed, the first scan line receives the high level signal through the second switch, the second scan line and the third scan line receive the fixed low potential through the third switch and the fifth switch respectively; in a second sub time period of the first time period, the first switch, the fourth switch and the fifth switch are opened, the second switch, the third switch and the sixth switch are closed, the second scan line receives the high level signal through the fourth switch, the first scan line and the third scan line receive the fixed low potential through the first switch and the fifth switch respectively; in a third sub time period of the first time period, the first switch, the third switch and the sixth switch are opened, the second switch, the fourth switch and the fifth switch are closed, the third scan line receives the high level signal through the sixth switch, the first scan line and the second scan line receive the fixed low potential through the first switch and the third switch respectively.

[0017] In an embodiment of the array substrate, the first switch to the sixth switch are P-type transistors; in the first sub time period, the first control signal, the fourth control signal and the sixth control signal are high level, the second control signal, the third control signal and the fifth control signal are low level; in the second sub time period, the first control signal, the fourth control signal and the fifth control signal are low level, the second control signal, the third control signal and the sixth control signal are high level; in the third sub time period, the first control signal, the second control signal and the sixth control signal are low level, the third control signal, the fourth control signal and the fifth control signal are high level.

[0018] In an embodiment of the array substrate, in each sub time period, one of the first control signal, the second control signal and the fifth control signal is high level, two of the third control signal, the fourth control signal and the sixth control signal are high level.

[0019] In an embodiment of the array substrate, the array substrate further comprises a second gate driving circuit, the second gate driving circuit is located in the peripheral area, and the first gate driving circuit and the second gate driving circuit are located on opposite sides of the display area, the second gate driving circuit has a second shift register unit corresponding to the first shift register unit,

[0020] The first shift register unit and the second shift register unit are connected to two ends of the same scan line, or the first shift register unit and the second shift register unit are connected to one end of different scan lines respectively.

[0021] The application further provides a display device comprising the array substrate.

[0022] Compared with the prior art, the array substrate and the display device provided by the application set an auxiliary driving circuit in the gate driving circuit, and through a control signal group and a plurality of switch groups in the auxiliary driving circuit, the driving signal output by each shift register unit drives at least two scan lines, so that the number of shift register units is reduced, the occupied space of the gate driving circuit is reduced, and the narrow frame design of the display panel is facilitated.

[0023] For a better understanding of the features and technical contents of the application, please refer to the following detailed description and drawings of the application. However, the drawings provided are only used for reference and illustration, and are not used to limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A schematic diagram of an array substrate in an embodiment of the application is shown.

[0025] Figure 2 A waveform schematic diagram of a display substrate in an embodiment of the application is shown. Figure 1

[0026] Figure 3 A schematic diagram of an array substrate in another embodiment of the application is shown.

[0027] Figure 4 A waveform schematic diagram of a display substrate in an embodiment of the application is shown. Figure 3

[0028] A schematic diagram of an array substrate in another embodiment of the application is shown. Figure 5

[0029] A schematic diagram of an array substrate in another embodiment of the application is shown. Figure 6

[0030] A waveform schematic diagram of a display substrate in an embodiment of the application is shown. Figure 7 Figure 6 A schematic diagram of an array substrate in another embodiment of the application is shown.

[0031] Figure 8 A waveform schematic diagram of a display substrate in an embodiment of the application is shown.

[0032] Figure 9 Figure 8 A waveform schematic diagram of a display substrate in an embodiment of the application is shown. ​​​

[0033] Figure 10 A waveform diagram of a display substrate in another embodiment of the present application is shown.

[0034] Figure 11 A waveform diagram of a display substrate in another embodiment of the present application is shown. Figure 10

[0035] Figure 12 A waveform diagram of a display substrate in another embodiment of the present application is shown.

[0036] Figure 13 A waveform diagram of a display substrate in another embodiment of the present application is shown. Figure 12

[0037] Figure 14 A waveform diagram of a display substrate in another embodiment of the present application is shown.

[0038] Figure 15 A waveform diagram of a display substrate in another embodiment of the present application is shown. Figure 14

[0039] Figure 16 A schematic diagram of a display device in an embodiment of the present application is shown.

[0040] In the drawings:

[0041] 1…substrate

[0042] 2…auxiliary drive circuit

[0043] 21…switch group

[0044] 211…first switch

[0045] 212…second switch

[0046] 213…third switch

[0047] 214…fourth switch

[0048] 215…fifth switch

[0049] 216…sixth switch

[0050] 217…seventh switch

[0051] 218…eighth switch

[0052] 22…control signal group

[0053] s1…first signal line

[0054] s2…second signal line

[0055] ctrl1…first control signal ​​​

[0056] ctrl2 second control signal

[0057] ctrl3 third control signal

[0058] ctrl4 fourth control signal

[0059] ctrl5 fifth control signal

[0060] ctrl6 sixth control signal

[0061] 100 array substrate

[0062] 1000 display device

[0063] AA display area

[0064] BA peripheral area

[0065] SR1 first shift register unit

[0066] SR2 second shift register unit

[0067] GL scan line

[0068] GL1 first scan line

[0069] GL2 second scan line

[0070] GL3 third scan line

[0071] VGL fixed low potential

[0072] 1H first period

[0073] 1H1 first sub-period

[0074] 1H2 second sub-period

[0075] 1H3 third sub-period

[0076] d1 first direction

[0077] d2 second direction DETAILED DESCRIPTION

[0078] The advantages and effects of the present application can be understood by those skilled in the art from the disclosure of the present specification. However, the disclosure below is not intended to limit the scope of protection of the present application, and those skilled in the art can implement the present application in other different embodiments based on different viewpoints and applications without departing from the spirit and principles of the present application.

[0079] For clarity of presentation, the brief description of the drawing for the present application is a simplified schematic diagram, to illustrate the basic structure of the present application. Therefore, the structure shown in the drawing of the present application is not drawn according to the actual shape and size ratio. For example, the size of a particular component is enlarged for convenience of illustration.

[0080] In order to solve the problem that the space occupied by the traditional design of the gate drive circuit is large, it is difficult to meet the narrow frame requirement of the display panel, please refer to Figure 1 The present application provides an array substrate 100, which has a periphery area BA and a display area AA arranged adjacently, and the array substrate 100 comprises a substrate, a plurality of scan lines GL and a first gate drive circuit GOA1. The plurality of scan lines GL are arranged on the substrate along a first direction d1 and a second direction d2, the first direction d1 intersects the second direction d2, and in the embodiment, the first direction d1 can be perpendicular to the second direction d2. The first gate drive circuit GOA1 is arranged on the periphery area BA of the substrate and corresponds to the plurality of scan lines GL. The first gate drive circuit GOA1 comprises a plurality of cascaded shift register units, each shift register unit corresponds to at least two scan lines GL and provides a driving signal. The first gate drive circuit GOA1 further comprises an auxiliary driving circuit 2, which comprises a control signal group 22 and a plurality of switch groups. The auxiliary driving circuit 2 is connected between each shift register unit and at least two scan lines GL corresponding thereto, and the driving signal is transmitted to at least two scan lines GL through the auxiliary driving circuit 2. In the embodiment, the first gate drive circuit GOA1 comprises a first shift register unit SR1, the plurality of switch groups comprise a first switch group 21, the first shift register unit SR1 is connected to the first scan line GL1 through the first switch group 21, the first switch group 21 comprises a first switch 211 and a second switch 212, the control end of the first switch 211 and the control end of the second switch 212 are connected to the control signal group 22, the first end of the first switch 211 is used for receiving a fixed low potential VGL, the first end of the second switch 212 is connected to the output end of the first shift register unit SR1, and the second end of the first switch 211 and the second end of the second switch 212 are connected to the first scan line GL1. In the embodiment, through the control signal group 22 and the plurality of switch groups in the auxiliary driving circuit 2, the driving signal output by each shift register unit drives at least two scan lines GL, the number of shift register units is reduced, the space occupied by the gate drive circuit is reduced, and the narrow frame of the display panel is facilitated. Further, the first scan line GL1 is connected to the first switch 211 and the second switch 212 at the same time, so as to quickly realize the switching of the potential under the control of the first switch 211 and the second switch 212, and the display stability can be ensured.

[0081] Please refer to Figure 2In an embodiment, the first shift register unit SR1 outputs a high level signal in a first time period 1H, the first time period 1H includes a first sub time period 1H1 and a second sub time period 1H2 in sequence, in the first sub time period 1H1, the second switch 212 is opened, the first switch 211 is closed, and the first scan line GL1 receives the high level signal through the second switch 212; in the second sub time period 1H2, the first switch 211 is opened, the second switch 212 is closed, and the first scan line GL1 receives the fixed low potential VGL through the first switch 211. In actual operation, if the potential of the scan line is not pulled down in time after the scanning is completed, the residual high level may cause signal crosstalk to the adjacent scan line or the subsequent scanning process. For example, it may cause the adjacent pixel unit to be triggered by mistake, resulting in display blur, color cast and other problems. In the embodiment, the first switch 211 directly receives the fixed low potential VGL, which can quickly pull down the potential of the first scan line GL1 and quickly cut off the signal influence of the first scan line GL1, which is conducive to the control of the driving signal on the pixel unit, ensures that the signal is clean when the next row of scan lines is scanned, avoids signal interference, and ensures stable display.

[0082] Please refer to Figure 3 In an embodiment, two adjacent scan lines in the second direction d2 are denoted as a first scan line GL1 and a second scan line GL2, the first switch group 21 further includes a third switch 213 and a fourth switch 214, the control end of the third switch 213 and the control end of the fourth switch 214 are connected to the control signal group 22, the first end of the third switch 213 is used to receive the fixed low potential VGL, the first end of the fourth switch 214 is connected to the output end of the first shift register unit SR1, and the second end of the third switch 213 and the second end of the fourth switch 214 are connected to the second scan line GL2. In the embodiment, the four switches in the first switch group 21 are connected with the first scan line GL1 and the second scan line GL2, and the number of shift register units is reduced by half compared with the architecture of one-to-one correspondence between the number of shift register units and the scan lines (as shown in Figure 3 , the number of shift register units is m, m = 1 / 2*n), thereby reducing the occupied space of the gate driving circuit and being conducive to the narrow frame of the display panel. Further, the first scan line GL1 and the second scan line GL2 are respectively connected with two switches, so as to quickly realize the switching of the potential under the control of the two switches, and the display stability can be ensured.

[0083] Please refer to Figure 4, in an embodiment, the first shift register unit SR1 outputs a high level signal in the first time period 1H, in the first time period 1H, in the first time period 1H, the first time period 1H, the second switch 212 and the third switch 213 are opened, the first switch 211 and the fourth switch 214 are closed, the first scan line GL1 receives a high level signal through the second switch 212, and the second scan line GL2 receives a fixed low potential VGL through the third switch 213; in the second time period 1H2 of the first time period 1H, the first switch 211 and the fourth switch 214 are opened, the second switch 212 and the third switch 213 are closed, the first scan line GL1 receives a fixed low potential VGL through the first switch 211, and the second scan line GL2 receives a high level signal through the fourth switch 214. In this embodiment, in the second time period 1H2, the first switch 211 and the fourth switch 214 are opened, so that the first scan line GL1 directly receives the fixed low potential VGL through the first switch 211 while the second scan line GL2 receives the high level signal, thereby quickly pulling down the potential to quickly cut off the signal influence of the first scan line GL1, ensuring that the signal is clean when the second scan line GL2 scans, and ensuring stable display.

[0084] Please refer to Figures 5 to 7 , Figure 5 The waveform diagram in the embodiment is the same as Figure 4 , in an embodiment, the control signal group 22 includes a first signal line s1 and a second signal line s2, and the first signal line s1 and the second signal line s2 extend along the second direction d2. Among them, in an embodiment, the first switch 211 to the fourth switch 214 are all P-type transistors, the control end of the second switch 212 and the control end of the third switch 213 are connected to the first signal line s1 to receive the first control signal ctrl1, and the control end of the first switch 211 and the control end of the fourth switch 214 are connected to the second signal line s2 to receive the second control signal ctrl2; as shown in Figure 4 , in the first time period 1H1, the first control signal ctrl1 is high, and the second control signal ctrl2 is low; in the second time period 1H2, the first control signal ctrl1 is low, and the second control signal ctrl2 is high.

[0085] In another embodiment, the first switch 211 and the third switch 213 are N-type transistors, the second switch 212 and the fourth switch 214 are P-type transistors, the control end of the first switch 211 and the control end of the second switch 212 are connected to the first signal line s1 to receive the first control signal ctrl1, and the control end of the third switch 213 and the control end of the fourth switch 214 are connected to the second signal line s2 to receive the second control signal ctrl2; as shown in Figure 7As shown, during the first sub-period 1H1, the first control signal ctrl1 is high, and the second control signal ctrl2 is low; during the second sub-period 1H2, the first control signal ctrl1 is low, and the second control signal ctrl2 is high. The first signal line s1 and the second signal line s2 extend along the second direction d2, and each switch group is electrically connected to the first signal line s1 and the second signal line s2, thereby saving the space occupied by the control signal group 22 by multiplexing one first signal line s1 and one second signal line s2. In this embodiment, P-type transistors / N-type transistors are used as the first switch 211 to the fourth switch 214. Since each transistor is used as a switch, it can have a smaller size, thereby effectively controlling the occupied space of the first gate driving circuit GOA1 to cater to the demand for narrow frames.

[0086] Please refer to Figure 8 and Figure 9 In this embodiment, the connection mode of the first shift register unit SR1 to the first scan line GL1 and the second scan line GL2 is the same as that of the Figure 5 embodiment, except that the array substrate 100 further includes a second gate driving circuit GOA2, the second gate driving circuit GOA2 is located in the peripheral area BA, and the first gate driving circuit GOA1 and the second gate driving circuit GOA2 are located on opposite sides of the display area AA. The second gate driving circuit GOA2 has a second shift register unit SR2 corresponding to the first shift register unit SR1, and the connection mode of the second shift register unit SR2 to the switch group and the control signal group 22 is similar to that of the first gate driving circuit GOA1, that is, the control end of the sixth switch 216 and the control end of the seventh switch 217 are connected to the first signal line s1 to receive the first control signal ctrl1, and the control end of the fifth switch 215 and the control end of the eighth switch 218 are connected to the second signal line s2 to receive the second control signal ctrl2; the input end of the fifth switch 215 and the input end of the seventh switch 217 are connected to a fixed low potential VGL, the input end of the sixth switch 216 and the input end of the eighth switch 218 are connected to the second shift register unit SR2, the output end of the fifth switch 215 and the output end of the sixth switch 216 are connected to the third scan line GL3, and the output end of the seventh switch 217 and the output end of the eighth switch 218 are connected to the fourth scan line GL. In this embodiment, the first shift register unit SR1 and the second shift register unit SR2 on the array substrate 100 are respectively connected to one end of different scan lines GL, and the connection mode of the first gate driving circuit GOA1 and the second gate driving circuit GOA2 to each scan line GL is a double-side single-drive mode, and the waveform diagrams of each signal are depicted in Figure 9 .

[0087] Please refer to Figure 10 and Figure 11In this embodiment, the connection mode of the control terminals of the switches in the first switch group 21 is different from that in the foregoing embodiment. In the foregoing embodiment, the control terminals of the two switches receive the same control signal, and in this embodiment, the control terminals of the switches receive control signals respectively. Specifically, the control signal group 22 includes a first control signal ctrl1, a second control signal ctrl2, a third control signal ctrl3 and a fourth control signal ctrl4, the control terminal of the second switch 212 is configured to receive the first control signal ctrl1, the control terminal of the first switch 211 is configured to receive the third control signal ctrl3, the control terminal of the third switch 213 is configured to receive the fourth control signal ctrl4, and the control terminal of the fourth switch 214 is configured to receive the second control signal ctrl2; the first shift register unit SR1 outputs a high-level signal in the first time period 1H, in the first time period 1H, the second switch 212 and the third switch 213 are turned on, the first switch 211 and the fourth switch 214 are turned off, the first scan line GL1 receives the high-level signal through the second switch 212, and the second scan line GL2 receives a fixed low potential VGL through the third switch 213. In this embodiment, by using control signals to control each switch in the first switch group 21 separately, the flexibility in wiring is improved.

[0088] Please refer to Figure 12 and 13 In this embodiment, the connection mode of the first shift register unit SR1 and the first scan line GL1 and the second scan line GL2 is different from that in the foregoing embodiment. Figure 10The difference between the embodiment and the above embodiment is that the array substrate further comprises a second gate driving circuit GOA2, the second gate driving circuit GOA2 is located in the peripheral area BA, and the first gate driving circuit GOA1 and the second gate driving circuit GOA2 are located on opposite sides of the display area AA. The second gate driving circuit GOA2 has a second shift register unit SR2 corresponding to the first shift register unit SR1. The connection mode of the second shift register unit SR2 and the switch group and the control signal group 22 is similar to that of the first gate driving circuit GOA1. That is, the control end of the sixth switch 216 is connected to the first signal line s1 to receive the first control signal ctrl1, the control end of the fifth switch 215 receives the third control signal ctrl3, the control end of the seventh switch 217 receives the fourth control signal ctrl4, the control end of the eighth switch 218 is connected to the second signal line s2 to receive the second control signal ctrl2, the input ends of the fifth switch 215 and the seventh switch 217 are fixed to a low potential VGL, the input ends of the sixth switch 216 and the eighth switch 218 are connected to the second shift register unit SR2, the output ends of the fifth switch 215 and the sixth switch 216 are connected to the first scan line GL1, and the output ends of the seventh switch 217 and the eighth switch 218 are connected to the second scan line GL2. In this embodiment, the first shift register unit SR1 and the second shift register unit SR2 on the array substrate 100 are connected to both ends of the same scan line GL, the connection mode of the first gate driving circuit GOA1 and the second gate driving circuit GOA2 and each scan line GL is a double-sided double-drive mode, and the waveform diagrams of each signal are depicted in Figure 13 .

[0089] Please refer to Figure 14 and Figure 15, in an embodiment, three adjacent scan lines GL in the second direction d2 are denoted as a first scan line GL1, a second scan line GL2 and a third scan line GL3, respectively, the control signal group 22 includes a first control signal ctrl1, a second control signal ctrl2, a third control signal ctrl3, a fourth control signal ctrl4, a fifth control signal ctrl5 and a sixth control signal ctrl6, and the first switch group 21 further includes a fifth switch 215 and a sixth switch 216, the control terminals of the switches receive different control signals, respectively. Specifically, the control terminal of the first switch 211 receives the third control signal ctrl3, the control terminal of the second switch 212 receives the first control signal ctrl1, the control terminal of the third switch 213 receives the fourth control signal ctrl4, the control terminal of the fourth switch 214 receives the second control signal ctrl2, the control terminal of the fifth switch 215 receives the sixth control signal ctrl6, the control terminal of the sixth switch 216 receives the fifth control signal ctrl5, the first terminal of the fifth switch 215 receives a fixed low voltage VGL, the first terminal of the sixth switch 216 is connected to the output terminal of the first shift register unit SR1, and the second terminal of the fifth switch 215 and the second terminal of the sixth switch 216 are connected to the third scan line GL3. Compared with the architecture in which the number of shift register units and the number of scan lines are in one-to-one correspondence, the number of shift register units in the embodiment is reduced by two-thirds (e.g. Figure 3 As shown in the figure, the number of stages of the shift register unit is m, and m = 1 / 3*n, which further reduces the occupied space of the gate drive circuit and is beneficial to the narrow frame of the display panel. Further, each scan line is connected to two switches, so as to quickly realize the switching of the potential under the control of the two switches, and the display stability can be ensured. In other embodiments, the number of scan lines GL corresponding to the first shift register unit SR1 is not limited to two or three, and the number of scan lines GL corresponding thereto can also be greater than three.

[0090] In an embodiment, the first shift register unit SR1 outputs a high level signal in the first time period 1H, in the first sub time period 1H1 of the first time period 1H, the second switch 212, the third switch 213 and the fifth switch 215 are opened, the first switch 211, the fourth switch 214 and the sixth switch 216 are closed, the first scan line GL1 receives the high level signal through the second switch 212, the second scan line GL2 and the third scan line GL3 receive the fixed low potential VGL through the third switch 213 and the fifth switch 215 respectively; in the second sub time period 1H2 of the first time period 1H, the first switch 211, the fourth switch 214 and the fifth switch 215 are opened, the second switch 212, the third switch 213 and the sixth switch 216 are closed, the second scan line GL2 receives the high level signal through the fourth switch 214, the first scan line GL1 and the third scan line GL3 receive the fixed low potential VGL through the first switch 211 and the fifth switch 215 respectively; in the third sub time period 1H3 of the first time period 1H, the first switch 211, the third switch 213 and the sixth switch 216 are opened, the second switch 212, the fourth switch 214 and the fifth switch 215 are closed, the third scan line GL3 receives the high level signal through the sixth switch 216, the first scan line GL1 and the second scan line GL2 receive the fixed low potential VGL through the first switch 211 and the third switch 213 respectively. In the embodiment, when the gate driving circuit sends the driving signal to control the pixel unit, in the first time period 1H, the first shift register unit SR1 transmits the driving signal to the first scan line GL1, in the second sub time period 1H2, the first shift register unit SR1 transmits the driving signal to the second scan line GL2, in the third sub time period 1H3, the first shift register unit SR1 transmits the driving signal to the third scan line GL3, similarly, the other shift register units also drive the corresponding three scan lines in the same way as the first shift register unit SR1.

[0091] In this embodiment, during the first sub-period 1H1, the first scan line GL1 receives a high-level signal, while the second scan line GL2 and the third scan line GL3 receive a fixed low potential VGL via the third switch 213 and the fifth switch 215, respectively, ensuring a clean signal during the scanning of the first scan line GL1. During the second sub-period 1H2, while the second scan line GL2 receives a high-level signal, the first scan line GL1 directly receives a fixed low potential VGL via the first switch 211 to quickly lower its potential, while the third scan line GL3 continues to receive a fixed low potential VGL, thereby quickly cutting off the signal influence of the first scan line GL1 and ensuring a clean signal during the scanning of the second scan line GL2. During the third sub-period 1H3, while the third scan line GL3 receives a high-level signal, the second scan line GL2 directly receives a fixed low potential VGL via the third switch 213 to quickly lower its potential, while the first scan line GL1 continues to receive a fixed low potential VGL, thereby quickly cutting off the signal influence of the second scan line GL2 and ensuring a clean signal during the scanning of the third scan line GL3, thus guaranteeing stable display.

[0092] like Figure 15 As shown, in one embodiment, the first switch 211 to the sixth switch 216 are all P-type transistors; during the first sub-period 1H1, the first control signal ctrl1, the fourth control signal ctrl4, and the sixth control signal ctrl6 are at a high level, and the second control signal ctrl2, the third control signal ctrl3, and the fifth control signal ctrl5 are at a low level; during the second sub-period 1H2, the first control signal ctrl1, the fourth control signal ctrl4, and the fifth control signal ctrl5 are at a low level, and the second control signal ctrl2, the third control signal ctrl3, and the sixth control signal ctrl6 are at a high level; during the third sub-period 1H3, the first control signal ctrl1, the second control signal ctrl2, and the sixth control signal ctrl6 are at a low level, and the third control signal ctrl3, the fourth control signal ctrl4, and the fifth control signal ctrl5 are at a high level. In other embodiments, the first switch 211 to the sixth switch 216 are not limited to being all P-type transistors, and each control signal can be adjusted according to the transistor type.

[0093] In one embodiment, during each sub-time period, one of the first control signal ctrl1, the second control signal ctrl2, and the fifth control signal ctrl5 is at a high level, and two of the third control signal ctrl3, the fourth control signal ctrl4, and the sixth control signal ctrl6 are at a high level. Thus, during each sub-time period 1H in which the first shift register unit SR1 outputs a high-level signal, while the corresponding scan line receives a high level, the other two scan lines receive a fixed low potential VGL, avoiding interference with the signal of the current scan line, ensuring a clean signal during scanning, and guaranteeing stable display.

[0094] The application also provides a display device 1000 comprising the array substrate 100. Further, the display device 1000 can be a liquid crystal display device, an OLED or a Micro-LED.

[0095] Compared with the prior art, the array substrate and the display device disclosed by the application set an auxiliary driving circuit in the gate driving circuit, and through a control signal group and a plurality of switch groups in the auxiliary driving circuit, the driving signal output by each shift register unit drives at least two scan lines, the number of shift register units is reduced, the occupied space of the gate driving circuit is reduced, and the narrow frame design of the display panel is facilitated.

[0096] The above disclosure is only a preferred and feasible embodiment of the application, and does not limit the patent application range of the application, so any equivalent technical change made by applying the content of the application specification and drawings falls within the patent application range of the application.

Claims

1. An array substrate having an adjacent peripheral area and a display area, characterized in that, The array substrate comprises: substrate; Multiple scan lines are disposed on the substrate, extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect; and A first gate driving circuit is disposed on the peripheral region of the substrate and corresponds to the plurality of scan lines. The first gate driving circuit includes cascaded multi-stage shift register units, each shift register unit corresponding to at least two scan lines and providing a driving signal. The first gate driving circuit also includes an auxiliary driving circuit, which includes a control signal group and a plurality of switch groups. The auxiliary driving circuit is connected between each shift register unit and the corresponding at least two scan lines, and the driving signal is transmitted to the at least two scan lines through the auxiliary driving circuit. The first gate driving circuit includes a first shift register unit, the plurality of switch groups include a first switch group, the first shift register unit is connected to a first scan line via the first switch group, the first switch group includes a first switch and a second switch, the control terminals of the first switch and the second switch are connected to the control signal group, the first terminal of the first switch is used to receive a fixed low potential, the first terminal of the second switch is connected to the output terminal of the first shift register unit, and the second terminals of the first switch and the second switch are connected to the first scan line.

2. The array substrate according to claim 1, characterized in that, The first shift register unit outputs a high-level signal during a first time period, which includes a first sub-time period and a second sub-time period in sequence. During the first sub-time period, the second switch is turned on and the first switch is turned off, and the first scan line receives the high-level signal via the second switch. During the second sub-period, the first switch is turned on, the second switch is turned off, and the first scan line receives the fixed low potential via the first switch.

3. The array substrate according to claim 1, characterized in that, The two adjacent scan lines in the second direction are respectively referred to as the first scan line and the second scan line. The first switch group also includes a third switch and a fourth switch. The control terminals of the third switch and the fourth switch are connected to the control signal group. The first terminal of the third switch is used to receive the fixed low potential. The first terminal of the fourth switch is connected to the output terminal of the first shift register unit. The second terminals of the third switch and the fourth switch are connected to the second scan line.

4. The array substrate according to claim 3, characterized in that, The first shift register unit outputs a high-level signal during a first time period. During the first sub-time period of the first time period, the second switch and the third switch are turned on, and the first switch and the fourth switch are turned off. The first scan line receives the high-level signal via the second switch, and the second scan line receives the fixed low potential via the third switch. During the second sub-time period of the first time period, the first switch and the fourth switch are turned on, and the second switch and the third switch are turned off. The first scan line receives the fixed low potential via the first switch, and the second scan line receives the high-level signal via the fourth switch.

5. The array substrate according to claim 4, characterized in that, The control signal group includes a first signal line and a second signal line, which extend along the second direction. Wherein, the first to fourth switches are all P-type transistors; the control terminals of the second and third switches are connected to the first signal line to receive a first control signal; the control terminals of the first and fourth switches are connected to the second signal line to receive a second control signal; during the first sub-period, the first control signal is high and the second control signal is low; during the second sub-period, the first control signal turns low and the second control signal turns high; or... Wherein, the first switch and the third switch are N-type transistors, the second switch and the fourth switch are P-type transistors, the control terminals of the first switch and the second switch are connected to the first signal line to receive the first control signal, and the control terminals of the third switch and the fourth switch are connected to the second signal line to receive the second control signal; during the first sub-period, the first control signal is at a high level and the second control signal is at a low level; during the second sub-period, the first control signal turns low and the second control signal turns high.

6. The array substrate according to claim 3, characterized in that, The control signal group includes a first control signal, a second control signal, a third control signal, and a fourth control signal. The control terminal of the second switch is used to receive the first control signal, the control terminal of the first switch is used to receive the third control signal, the control terminal of the third switch is used to receive the fourth control signal, and the control terminal of the fourth switch is used to receive the second control signal. The first shift register unit outputs a high-level signal during a first time period. During the first sub-time period of the first time period, the second switch and the third switch are turned on, and the first switch and the fourth switch are turned off. The first scan line receives the high-level signal via the second switch, and the second scan line receives the fixed low potential via the third switch.

7. The array substrate according to claim 3, characterized in that, The three adjacent scan lines in the second direction are respectively designated as the first scan line, the second scan line, and the third scan line. The control signal group includes a first control signal, a second control signal, a third control signal, a fourth control signal, a fifth control signal, and a sixth control signal. The first switch group also includes a fifth switch and a sixth switch. The control terminal of the first switch is used to receive the third control signal, the control terminal of the second switch is used to receive the first control signal, the control terminal of the third switch is used to receive the fourth control signal, the control terminal of the fourth switch is used to receive the second control signal, the control terminal of the fifth switch is used to receive the sixth control signal, the control terminal of the sixth switch is used to receive the fifth control signal, the first terminal of the fifth switch is used to receive the fixed low potential, the first terminal of the sixth switch is connected to the output terminal of the first shift register unit, and the second terminals of the fifth switch and the sixth switch are connected to the third scan line.

8. The array substrate according to claim 7, characterized in that, The first shift register unit outputs a high-level signal during a first time period. During the first sub-time period of the first time period, the second, third, and fifth switches are turned on, and the first, fourth, and sixth switches are turned off. The first scan line receives the high-level signal via the second switch, and the second and third scan lines receive the fixed low potential via the third and fifth switches, respectively. During the second sub-time period of the first time period, the first, fourth, and fifth switches are turned on, and the second, third, and sixth switches are turned off. The second scan line receives the high-level signal via the fourth switch, and the first and third scan lines receive the fixed low potential via the first and fifth switches, respectively. During the third sub-time period of the first time period, the first, third, and sixth switches are turned on, and the second, fourth, and fifth switches are turned off. The third scan line receives the high-level signal via the sixth switch, and the first and second scan lines receive the fixed low potential via the first and third switches, respectively.

9. The array substrate according to claim 8, characterized in that, All of the first to sixth switches are P-type transistors; during the first sub-period, the first, fourth, and sixth control signals are at a high level, and the second, third, and fifth control signals are at a low level; during the second sub-period, the first, fourth, and fifth control signals are at a low level, and the second, third, and sixth control signals are at a high level; during the third sub-period, the first, second, and sixth control signals are at a low level, and the third, fourth, and fifth control signals are at a high level.

10. The array substrate according to claim 8, characterized in that, In each sub-time period, one of the first control signal, the second control signal, and the fifth control signal is at a high level, and two of the third control signal, the fourth control signal, and the sixth control signal are at a high level.

11. The array substrate according to claim 1, characterized in that, The array substrate further includes a second gate driving circuit located in the peripheral region, and the first gate driving circuit and the second gate driving circuit are located on opposite sides of the display area. The second gate driving circuit has a second shift register unit corresponding to the first shift register unit. In this configuration, the first shift register unit and the second shift register unit are connected to both ends of the same scan line; or, the first shift register unit and the second shift register unit are each connected to one end of a different scan line.

12. A display device comprising an array substrate as described in any one of claims 1 to 11.

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