Memory performance management

Abstract

The invention relates to memory performance management. A memory system may limit performance, for example, according to a target data rate of the memory system. For example, the memory system may implement one or more timers. In response to receiving an access command, the memory system may start a timer and may delay (e.g., restrain) execution of other access commands until the timer expires. Additionally or alternatively, the memory system may implement a credit-based approach to manage performance. For example, the memory system may periodically issue credits, e.g., by incrementing a counter. The memory system may consume credits to execute access commands. If the memory system receives a command to perform an access operation and does not have sufficient credits to perform the operation, the memory system may delay the operation, such as until sufficient credits are accumulated.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 19 / 195,336, entitled "Memory Performance Management," filed April 30, 2025, and U.S. Provisional Patent Application No. 63 / 649,834, entitled "Memory Performance Management," filed May 20, 2024, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves memory performance management. Background Technology

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, the memory device can read (e.g., sense, detect, retrieve, determine) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) the state to the memory cell.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic DRAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), autoselect memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described as volatile or non-volatile. Memory cells configured as non-volatile can maintain their stored logic state for extended periods, even without an external power supply. Memory cells configured as volatile may lose their stored state when disconnected from an external power supply. Summary of the Invention

[0006] A memory system is described. The memory system may include: one or more memory devices; and a processing circuitry system coupled to the one or more memory devices and configured such that the memory system: receives a first command associated with a first access operation; starts a timer at least in part based on receiving the first command; receives a second command associated with a second access operation; and suppresses the execution of the second access operation at least in part based on a timer value satisfying a threshold.

[0007] Describe another memory system. The memory system may include: one or more memory devices; and a processing circuitry system coupled to the one or more memory devices and configured to cause the memory system to: increment the value of a counter of the memory system, wherein the value of the counter is associated with performing an access operation at the memory system; receive a first command associated with a first access operation based at least in part on the incrementing of the counter value; perform the first access operation based at least in part on the counter value satisfying a first threshold; and adjust the value of the counter based at least in part on the performance of the first access operation.

[0008] A non-transitory computer-readable medium is described, storing code including instructions. The code includes instructions that, when executed by one or more processors of a memory system, cause the memory system to: receive a first command associated with a first access operation; start a timer at least in part based on receiving the first command; receive a second command associated with a second access operation; and suppress execution of the second access operation at least in part based on a timer value satisfying a threshold. Attached Figure Description

[0009] Figure 1 Examples of systems supporting memory performance management, such as those disclosed herein, are presented.

[0010] Figure 2 Examples of processes supporting memory performance management, as disclosed herein, are presented.

[0011] Figure 3 Examples of processes supporting memory performance management, as disclosed herein, are presented.

[0012] Figure 4 A block diagram illustrating a memory system supporting memory performance management, based on examples disclosed herein.

[0013] Figure 5 and 6 The flowchart illustrates a method or several methods for supporting memory performance management, as shown in the examples disclosed herein. Detailed Implementation

[0014] As memory system technology improves across generations, the costs associated with memory systems (e.g., manufacturing costs, research and development costs, and the like) can increase. For example, as memory system capacity increases, the performance and cost of the memory system relative to that capacity (e.g., performance per gigabyte (GB) and cost per GB) can also increase. However, the memory system market may expect performance improvements at similar or lower costs across generations. Furthermore, performance and capacity improvements may not be linear across generations, increasing the complexity of product roadmaps. Additionally, increased memory system performance may lead to consistent operation at high data rates, potentially resulting in premature device end-of-life and other challenges. Therefore, memory systems with one or more configurable performance characteristics are desirable.

[0015] As described herein, a memory system can limit (e.g., throttle) performance, for example, based on a target data rate. For instance, the memory system can implement one or more timers. In response to or based on a received command (e.g., an access command), the memory system can start a timer and delay the execution of one or more other access commands until the timer expires. Alternatively, the memory system can implement a credit-based approach to manage performance. For example, the memory system can periodically issue credits, for instance, by incrementing a counter. If an access command is executed, the memory system can consume credits (e.g., decrement the counter). If the memory system receives a command to perform an access operation but does not have sufficient credits to perform the operation, the memory system can delay the operation, for example, until enough credits have accumulated. Such techniques can support increased control over the performance of the memory system, which can support improved market planning and / or increased memory system lifespan, among other benefits.

[0016] Beyond its applicability to memory systems as described herein, techniques for memory performance management can generally be implemented to improve the performance of a wide range of electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games. Some electronic device applications, including high-performance applications such as AI, AR, VR, and games, are associated with relatively high processing demands to meet user expectations. Therefore, increasing the processing power of electronic devices by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, as well as other performance metrics, can improve user experience or appeal. Implementing the techniques described herein can improve the performance of electronic devices by managing performance according to a target data rate, which can improve processing or latency, improve response time, or otherwise improve user experience and other benefits.

[0017] Beyond their applicability to memory systems as described herein, techniques for memory performance management can generally be implemented to improve the sustainability of various electronic devices and systems. As the use of electronic devices becomes more widespread, energy consumption and hazardous emissions associated with their production and operation have increased. Furthermore, the amount of waste (e.g., e-waste) associated with electronic device disposal can also cause environmental problems. Implementing the techniques described herein can improve the impacts associated with electronic devices by reducing the impact of consistently operating electronic devices at high data rates, which can extend the lifespan of electronic devices and thereby reduce e-waste, among other benefits.

[0018] Features of this disclosure are described and illustrated in the context of systems, apparatus, and circuits. Features of this disclosure are further described and illustrated in the context of processes and flowcharts.

[0019] Figure 1 An example of a system 100 supporting memory performance management, as disclosed herein, is shown. System 100 includes a host system 105 coupled to a memory system 110. System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle, device with Internet of Things (IoT) capability, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked commercial device), or any other computing device containing memory and processing power.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other devices.

[0021] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to one or more host system controllers 106, which may be instances of controllers or control components configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the host system 105 or included in the host system 105), one or more memory controllers (e.g., NVDIMM controllers), and one or more memory protocol controllers (e.g., Peripheral Component Rapid Interconnect (PCIe) controllers, Serial Advanced Technology Attachment (SATA) controllers). The host system 105 can use the memory system 110 (for example) to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM slot interfaces), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in one or more host system controllers 106 of host system 105 and one or more memory system controllers 115 of memory system 110, or otherwise supported between one or more host system controllers 106 and one or more memory system controllers 115. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., one or more host system controllers 106 may be coupled to one or more memory system controllers 115).

[0023] Memory system 110 may include one or more memory system controllers 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to enable the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading, writing, erasing, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, discard item collection operations, error control operations such as error detection or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include a circuit system having dedicated (e.g., hard-coded) logic for performing the operations described herein attributed to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit system.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions described herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions described herein. Additionally, or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, the data may be stored in local memory 120, and the data in local memory 120 may be available to the host system 105 for subsequent retrieval or manipulation (e.g., updates) according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0028] although Figure 1 An example of memory system 110 has been described as including one or more memory system controllers 115, but in some cases, memory system 110 may not include memory system controllers 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, which may be located within memory device 130, to perform the functions attributed herein to memory system controller 115. Typically, in some cases, one or more functions attributed herein to memory system controller 115 may alternatively be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 managed at least partially by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may (e.g., on the same die, within the same package) include one or more local controllers 135 that can perform operations on one or more memory cells of the respective memory device 130. Local controllers 135 may operate in conjunction with memory system controller 115, or may perform one or more functions categorized herein as those of memory system controller 115. For example, as Figure 1 As described herein, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a single piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If the memory cells are configured to each store two bits of information, they may be referred to as multi-level cells (MLC); if the memory cells are configured to each store three bits of information, they may be referred to as three-level cells (TLC); if the memory cells are configured to each store four bits of information, they may be referred to as four-level cells (QLC), or more generally, multi-level memory cells. Compared to SLC memory cells, multi-level memory cells can provide greater storage density, but in some cases, this may involve narrower read or write margins or greater complexity in the supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations can be performed on different planes 165. For example, concurrent operations can be performed on memory cells within different blocks 170 as long as different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which concurrent operations can occur. For example, concurrent operations can be performed on blocks 170-a, 170-b, 170-c, and 170-d located in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, and so on). In some cases, concurrent operations performed in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address in their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level or a portion thereof), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest memory unit (e.g., a group of memory cells) that can be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and block 170 may be the smallest memory unit (e.g., a group of memory cells) that can be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 cannot be updated until the entire block 170 containing page 175 has been erased.

[0036] In some cases, memory system 110 may utilize one or more memory system controllers 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0037] System 100 may include any number of non-transitory computer-readable media supporting memory performance management. For example, host system 105 (e.g., host system controller 106), memory system 110 (e.g., memory system controller 115), or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to host system 105, memory system 110, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system 110 (e.g., by memory system controller 115), or memory device 130 (e.g., by local controller 135), may cause host system 105, memory system 110, or memory device 130 to perform the associated functions as described herein.

[0038] In some cases, memory system 110 may limit (e.g., throttling) performance, for example, based on a target data rate. For instance, memory system 110 may implement one or more timers. In response to receiving a command (e.g., an access command), memory system 110 may start a timer and may delay the execution of other access commands until the timer expires. Alternatively, memory system 110 may implement a credit-based approach to manage performance. For example, memory system 110 may periodically issue credits, for example, by incrementing a counter. If an access command is executed, memory system 110 may consume credits (e.g., decrement the counter). If memory system 110 receives a command to perform an access operation but does not have sufficient credits to perform the operation, memory system 110 may delay the operation, for example, until sufficient credits have accumulated. Such techniques can support increased control over the performance of memory system 110, which can support improved market planning, increased lifespan of memory system 110, or both, and other benefits.

[0039] Figure 2 Examples of a process 200 supporting memory performance management, as disclosed herein, are presented. In some examples, the memory system (which may be as described in the references) Figure 1 An example of the described memory system 110 may use one or more memory system controllers (e.g., memory system controller 115) to implement aspects of process 200. In the following description of process 200, operations may be performed in a different order than those shown. For example, a particular operation may be excluded from process 200, or other operations may be added to process 200.

[0040] Aspects of process 200 may be implemented by a processing circuitry system (e.g., one or more controllers and other components). Alternatively, aspects of process 200 may be implemented as instructions stored in one or more memories (e.g., firmware stored in one or more memories coupled to a memory system (e.g., memory device 130 or local memory 120 (or both))). For example, when executed by one or more controllers (e.g., memory system controller 115), the instructions may cause one or more controllers (or devices or systems) to perform the operation of process 200.

[0041] Procedure 200 may illustrate a method of implementing one or more timers to manage the performance of a memory system. For example, a memory system may use timers to control the pace of performing various types of access operations. In response to receiving an access command, such as from a host system (e.g., reference...), Figure 1Upon receiving an access command, the host system 105 described herein may start (e.g., initiate) one or more timers and initiate the execution of an access operation (e.g., a read operation, a write operation) corresponding to the access command. If the memory system receives a second access command after starting a timer, the memory system may determine whether the timer has reached a threshold (e.g., whether the timer has reached "0", or whether the timer has expired). If the memory system determines that the timer has reached the threshold, the memory system may execute the second access operation corresponding to the second access command. Alternatively, if the timer has not yet reached the threshold, the memory system may delay the execution of the second access operation until the timer reaches the threshold.

[0042] In some cases, the memory system, the host system, or both can manage aspects of one or more timers, such as the timer's initial value, the type of access operation associated with the timer, the threshold associated with the timer, or combinations thereof. For example, at 205, one or more initial parameters can be used to set the timer. In some cases, the host system can transmit a command indicating the initial parameters to the memory system. The command can be an instance of a setting characteristic command, and the memory system can set the parameters of the timer indicated by the command in response to receiving the command.

[0043] One or more parameters of a timer may include the timer's initial value, a threshold associated with the timer, the type of access operation corresponding to the timer, the target data rate of the memory system, or a combination thereof. For example, if one or more parameters indicate the timer's initial value, the memory system may set the timer to the initial value. After the timer is started, it may "decrement" until it expires (e.g., reaches the value "0"). Alternatively, if one or more parameters indicate a threshold associated with the timer, the memory system may initially set the timer to the value "0". After the timer is started, it may "increment", and if the timer exceeds the indicated threshold, the memory system may determine that the timer meets the indicated threshold.

[0044] In some instances, the memory system can manage timers at various granularities. For example, the memory system can maintain separate timers for each type of access operation (e.g., a first timer corresponding to a read operation, a second timer corresponding to a write operation), or separate timers for different groups of memory cells (e.g., a corresponding timer for each block of memory cells, a corresponding timer for each plane of memory cells), or combinations thereof. In such instances, the memory system, the host system, or both can independently configure the parameters of each timer (e.g., using set feature commands).

[0045] At 210, a first command associated with the first access operation may be received. In some instances, the first command may be a write command for writing data to the memory system or a read command for reading data from the memory system. For example, the memory system may receive the first access command from the host system and may execute the first access operation.

[0046] At 215, one or more parameters of the first access command can be identified. The memory system can, for example, identify the size of the data associated with the first access command (e.g., the size of the data to be written, the size of the data to be read), the type of the first access operation, the number of memory system planes associated with the first access operation, or a combination thereof. Based on the identified parameters, the memory system can determine (e.g., select, calculate) the initial value of the timer associated with the first access operation. For example, a relatively large data size may correspond to a corresponding long value of the timer, while a relatively small data size may correspond to a short value of the timer. Alternatively or concurrently, the memory system can select the value of the timer to adjust the data rate of the memory system toward a target data rate.

[0047] At 220, a timer can be started. In some instances, the timer can be started in response to receiving a first access command (e.g., at 210), in response to recognizing one or more parameters (e.g., at 215), or both.

[0048] At position 225, a second access command associated with the second access operation can be received. For example, the memory system can receive the second access command from the host system.

[0049] At position 230, it can be determined whether the timer value meets the threshold. For example, the memory system can determine whether the timer value has expired (e.g., whether the timer value has reached the "0" value).

[0050] At position 235, a second access command can be suppressed. For example, if the timer value does not meet a threshold, the memory system can suppress the execution of the second access command. That is, the memory system can avoid executing the second access command for a certain duration. For example, the memory system can store the second access command in a buffer or queue (e.g., a command queue managed by memory system controller 115, as shown in reference 115). Figure 1 (as described). In some cases, the process can periodically return to 230, and the memory system can therefore periodically determine whether the timer value meets the threshold.

[0051] At point 240, a second access command can be executed. For example, after a timer expires, the process can proceed to point 240, and the memory system can execute the second access command. Alternatively, the expiration of the timer can act as a trigger for the memory system to proceed to point 240 and execute the second access command.

[0052] At position 245, one or more parameters can be updated. In some instances, one or more parameters of a timer can be updated. For example, the memory system can autonomously update (e.g., reset) the value of a timer, such as updating it to an initial value. Alternatively, the memory system can adjust or modify the initial value, for example, by adjusting the initial value to modify the data rate of the memory system toward a target data rate. Alternatively or alternatively, the memory system can receive commands (e.g., set characteristic commands) from the host system to modify one or more parameters. In such instances, the command may include one or more values ​​and fields indicating the values ​​of one or more parameters, and the memory system can set one or more parameters based on one or more values.

[0053] At position 250, one or more parameters for the timer can be provided. For example, the host system can transmit a command requesting indications of one or more parameters (e.g., a characteristic acquisition command), such as an indication of the timer's initial value, a target data rate, the type of access operation associated with the timer, and other instances. In response to the command, the memory system can transmit to the host system one or more values ​​indicating one or more parameters. By using one or more timers to manage the performance of the memory system, the memory system can support increased control over its performance, which can support improved market planning, increased memory system lifespan, or both, and other benefits.

[0054] Figure 3 This document demonstrates an example of a process 300 supporting memory performance management, as disclosed herein. In some examples, the memory system (which may be as described in the references) Figure 1 An example of the described memory system 110 may use one or more memory system controllers (e.g., memory system controller 115) to implement aspects of process 300. In the following description of process 300, operations may be performed in a different order than those shown. For example, a particular operation may be excluded from process 300, or other operations may be added to process 300.

[0055] Aspects of process 300 may be implemented by a processing circuitry system (e.g., one or more controllers and other components). Alternatively, aspects of process 300 may be implemented as instructions stored in one or more memories (e.g., firmware stored in one or more memories coupled to a memory system (e.g., memory device 130 or local memory 120 (or both))). For example, when executed by one or more controllers (e.g., memory system controller 115), the instructions may cause one or more controllers (or devices or systems) to perform the operation of process 300.

[0056] Process 300 illustrates a method for implementing a credit-based system to manage the performance of a memory system using one or more counters. For example, a memory system can use counters to control the pace of performing various types of access operations. In response to receiving an access command (e.g., from a host system (e.g., reference...)... Figure 1 In the case of an access command from the host system 105 described above, the memory system can determine whether the value of a counter meets a threshold associated with the access operation corresponding to the access command (e.g., whether the counter indicates sufficient credit for the access operation). If the value of the counter meets the threshold, then the memory system can perform the access operation. Alternatively, if the value of the counter does not meet the threshold, then the memory system can delay performing the access operation until the counter has reached a sufficient value.

[0057] In some cases, the memory system, host system, or both may manage aspects of one or more counters, such as the period or frequency of the incrementing counter, the amount of the incrementing counter, the size or number of credits for a particular type of access operation, the size or number of credits for the amount of data associated with the access operation, the upper limit of the counter value, or a combination thereof.

[0058] At position 305, one or more initial parameters can be used to set the counter. In some cases, the host system can transmit a command indicating the initial parameters to the memory system. The command can be an instance of a setting feature command, and the memory system can set the parameters of the counter indicated by the command in response to receiving the command.

[0059] One or more parameters of the timer may include the period or frequency of the incrementing counter, the incrementing counter value, the size or number of credits for a particular type of access operation, the size or number of credits for the amount of data associated with the access operation, the upper limit of the counter value, the target data rate of the memory system, or a combination thereof.

[0060] In some cases, memory systems can manage counters at various granularities. For example, a memory system may maintain separate counters for each type of access operation (e.g., a first counter corresponding to a read operation, a second counter corresponding to a write operation), separate counters for different groups of memory cells (e.g., a corresponding counter for each block of memory cells, a corresponding counter for each plane of memory cells), or combinations thereof. In such instances, the memory system, the host system, or both may configure the parameters of each counter independently (e.g., using set feature commands).

[0061] At 310, the counter can be incremented (e.g., adjusted by a value of 1 or by values ​​greater than 1). For example, the memory system can periodically add values ​​to the counter (e.g., issue one or more credits), such as by maintaining a free-running timer. After the timer expires, the memory system can increment the counter and reset the timer. In some instances, the host system can modify the counter, for example, by transmitting a command to reset the free-running timer and add values ​​to the counter accordingly. In some instances, the counter value can correspond to a positive integer, such that incrementing or adding a value to the counter corresponds to adding one or more positive integers to the counter.

[0062] In some instances, the memory system may support an upper limit or threshold for the counter. For example, the memory system may determine whether the value of the counter is equal to or greater than the upper limit (or whether incrementing the counter would cause the value to exceed the upper limit). If the value of the counter is equal to or greater than the upper limit, then the memory system may avoid incrementing the counter.

[0063] At 315, commands associated with access operations can be received (e.g., write commands to write data to the memory system, read commands to read data from the memory system). For example, the memory system can receive commands such as access commands from the host system, and can perform a first access operation based on the access commands.

[0064] At 320, one or more parameters of the access command can be identified. The memory system can, for example, identify the size of the data associated with the first access command (e.g., the size of the data to be written, the size of the data to be read), the type of the first access operation, the number of memory system planes associated with the first access operation, or a combination thereof. Based on the identified parameters, the memory system can determine (e.g., select, calculate) a value associated with the access operation (e.g., the "cost" of the access operation). For example, a relatively large data size may correspond to a correspondingly large value, and a relatively small data size may correspond to a small value. Alternatively or additionally, the memory system can select values ​​to adjust the data rate of the memory system toward a target data rate.

[0065] At position 325, it can be determined whether the counter value meets the threshold. For example, the memory system can compare the value determined at position 320 with the counter value.

[0066] At 330, a second access command can be suppressed. For example, if the value of the counter is less than a determined value, the memory system can suppress the execution of the access command. For example, the memory system can store the access command in a buffer or queue (e.g., a command queue managed by the memory system controller 115, as referenced). Figure 1 (as described). In some cases, process 300 may periodically return to 325, and the memory system may therefore periodically determine whether the value of the counter meets the threshold.

[0067] At point 335, an access operation can be performed. For example, after the counter has accumulated a sufficient value (e.g., greater than or equal to a determined value), process 300 can proceed to point 335, and the memory system can perform an access operation.

[0068] At position 340, a counter can be decremented. For example, as part of performing an access operation or in response to performing an access operation, the counter can be decremented at position 340. In some instances, the memory system can decrease the value of the counter by a predetermined value.

[0069] At point 345, one or more parameters of the counter can be provided. For example, the host system can transmit a command requesting instructions for one or more parameters (e.g., a characteristic command), such as the period or frequency of incrementing the counter, the amount of incrementing the counter, the size or number of credits for a specific type of access operation, the size or number of credits for the amount of data associated with the access operation, an upper limit on the counter's value, a target data rate for the memory system, or combinations thereof, and other instances. In response to the command, the memory system can transmit one or more values ​​indicating one or more parameters to the host system. By using counters to manage the performance of the memory system, the memory system can support increased control over its performance, which can support improved marketing, increased memory system lifespan, or both, and other benefits.

[0070] Figure 4 A block diagram 400 illustrates a memory system 420 supporting memory performance management, as disclosed herein. The memory system 420 may be used as a reference. Figures 1 to 3 Examples of aspects of the described memory system. Memory system 420 or its various components may be examples of constructs for performing the various aspects of memory performance management described herein. For example, memory system 420 may include a receiving component 425, a timer management component 430, an operation management component 435, a counter management component 440, a transmission component 445, a command management component 450, or any combination thereof. Components of each of these components or their sub-components (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0071] The receiving component 425 may be configured or otherwise supported to include means for receiving a first command associated with a first access operation. The timer management component 430 may be configured or otherwise supported to include means for starting a timer at least in part based on the receipt of the first command. In some instances, the receiving component 425 may be configured or otherwise supported to include means for receiving a second command associated with a second access operation. The operation management component 435 may be configured or otherwise supported to include means for suppressing the execution of a second access operation at least in part based on a timer value satisfying a threshold.

[0072] In some instances, receiving component 425 may be configured or otherwise supported to include means for receiving a third command containing an indication of the initial value of a timer. In some instances, timer management component 430 may be configured or otherwise supported to include means for setting the initial value of a timer based at least in part on the receipt of a third command.

[0073] In some instances, receiving component 425 may be configured or otherwise supported for receiving a fourth command containing an updated initial value for a timer. In some instances, timer management component 430 may be configured or otherwise supported for updating the initial value of a timer based at least in part on the receipt of the fourth command.

[0074] In some instances, receiving component 425 may be configured or otherwise supported to include means for receiving a fifth command requesting an initial value for a timer. In some instances, transmitting component 445 may be configured or otherwise supported to include means for transmitting an indication of the initial value of a timer based at least in part on the receipt of a fifth command.

[0075] In some instances, the operation management component 435 may be configured or otherwise supported for performing a second access operation based at least in part on the failure of a timer value to meet a threshold.

[0076] In some instances, the command management component 450 may be configured or otherwise supported to include means for identifying one or more parameters associated with the first command. In some instances, the timer management component 430 may be configured or otherwise supported to include means for selecting the initial value of a timer based at least in part on one or more parameters, wherein the timer contains an initial value when it is started.

[0077] In some instances, one or more parameters include the size of the data associated with the first access operation, the type of the first access operation, the number of planes of the memory system associated with the first access operation, or a combination thereof.

[0078] In some instances, the command management component 450 may be configured or otherwise supported to enable the memory system to determine a target rate for processing commands. In some instances, the timer management component 430 may be configured or otherwise supported to enable the selection of an initial value for a timer based at least in part on the target rate, wherein the timer contains an initial value when it is started.

[0079] In some instances, the operation management component 435 may be configured or otherwise supported to enable the execution of a first access operation based at least in part on receiving a first command, wherein the start of a timer is based at least in part on the execution of the first access operation.

[0080] In some instances, the value at which the timer fails to meet the threshold corresponds to the value at which the timer expires.

[0081] Counter management component 440 may be configured or otherwise supported to support means for incrementing the value of a counter in the memory system, wherein the value of the counter is associated with performing an access operation at the memory system. In some instances, receiving component 425 may be configured or otherwise supported to support means for receiving a first command associated with a first access operation based at least in part on the incrementing value of the counter. In some instances, operation management component 435 may be configured or otherwise supported to support means for performing a first access operation based at least in part on the counter value satisfying a first threshold. In some instances, counter management component 440 may be configured or otherwise supported to support means for adjusting the value of the counter based at least in part on the performance of the first access operation.

[0082] In some instances, receiving component 425 may be configured or otherwise supported to receive a second command associated with a second access operation based at least in part on the value of an adjustment counter. In some instances, operation management component 435 may be configured or otherwise supported to avoid performing a second access operation based at least in part on the fact that the value of the counter fails to meet a first threshold.

[0083] In some instances, the counter value contains a positive integer when the counter value meets a first threshold.

[0084] In some instances, the counter management component 440 may be configured or otherwise supported to support means for determining that the value of the counter meets a second threshold. In some instances, the counter management component 440 may be configured or otherwise supported to support means for avoiding incrementing the value of the counter, at least in part, based on determining that the value of the counter meets a second threshold.

[0085] In some instances, receiving component 425 may be configured or otherwise supported to include means for receiving a third command containing an indication of an initial value for the counter. In some instances, counter management component 440 may be configured or otherwise supported to include means for setting the initial value of the counter based at least in part on the receipt of a third command.

[0086] In some instances, the command management component 450 may be configured or otherwise supported to support means for identifying one or more parameters associated with the first command. In some instances, the counter management component 440 may be configured or otherwise supported to support means for determining, at least in part, the number of values ​​to be adjusted for a counter based on one or more parameters, wherein the counter is adjusted at least in part based on a determined number of values.

[0087] In some instances, one or more parameters include the size of the data associated with the first access operation, the type of the first access operation, the number of planes of the memory system associated with the first access operation, or a combination thereof.

[0088] In some instances, command management component 450 may be configured or otherwise supported for means to determine, by the memory system, a target rate for processing commands. In some instances, counter management component 440 may be configured or otherwise supported for means to determine, at least in part, the amount of value to be adjusted for a counter based on a determined amount of value.

[0089] In some instances, the counter value is incremented at fixed intervals.

[0090] In some instances, to support adjusting the value of the counter, the counter management component 440 may be configured or otherwise support components for decrementing the value of the counter.

[0091] In some instances, the described functionality of memory system 420 or its various components may be supported by, or involve at least a portion of, at least one processor, wherein such at least one processor may comprise one or more processing elements (e.g., a controller, microprocessor, microcontroller, digital signal processor, state machine, discrete gate logic, discrete transistor logic, discrete hardware component, or any combination of one or more such elements). In some instances, the described functionality of memory system 420 or its various components may be implemented at least in part by instructions executable by such at least one processor (e.g., stored in memory, non-transitory computer-readable medium).

[0092] Figure 5The flowchart illustrates a method 500 for supporting memory performance management based on examples disclosed herein. The operation of method 500 can be implemented by a memory system or its components as described herein. For example, the operation of method 500 can be implemented by a reference... Figures 1 to 4 The memory system described is used for execution. In some instances, the memory system can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0093] At 505, the method may include receiving a first command associated with the first access operation. In some instances, aspects of operation 505 may be as described in the reference. Figure 4 The described receiving component 425 is used to perform this action.

[0094] At point 510, the method may include starting a timer based at least in part on receiving a first command. In some instances, aspects of operation 510 may be as described in the reference. Figure 4 The timer management component 430 described is used to perform this.

[0095] At 515, the method may include receiving a second command associated with the second access operation. In some instances, aspects of operation 515 may be provided as referenced. Figure 4 The described receiving component 425 is used to perform this action.

[0096] At 520, the method may include suppressing the execution of a second access operation based at least in part on the timer value satisfying a threshold. In some instances, aspects of operation 520 may be as described in the reference. Figure 4 The described operation management component 435 is used to perform this.

[0097] In some instances, the device may execute a method or several methods, such as method 500, as described herein. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0098] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving a first command associated with a first access operation; starting a timer at least in part based on receiving the first command; receiving a second command associated with a second access operation; and suppressing the execution of the second access operation at least in part based on a value of the timer satisfying a threshold.

[0099] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for receiving a third command containing an indication of an initial value of the timer and setting the initial value of the timer at least in part based on receiving the third command.

[0100] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to aspect 2, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for receiving a fourth command containing an updated initial value of the timer and updating the initial value of the timer at least in part based on receiving the fourth command.

[0101] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 3, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for receiving a fifth command containing a request for an initial value of the timer and an indication to transmit the initial value of the timer at least in part based on the receipt of the fifth command.

[0102] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 4, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for performing the second access operation at least in part based on the fact that the value of the timer cannot satisfy the threshold.

[0103] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 5, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for identifying one or more parameters associated with the first command and selecting an initial value of the timer at least in part based on the one or more parameters, wherein the timer includes the initial value upon startup.

[0104] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to aspect 6, wherein the one or more parameters include the size of the data associated with the first access operation, the type of the first access operation, the number of planes of the memory system associated with the first access operation, or a combination thereof.

[0105] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 7, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for determining a target rate for processing commands by the memory system and selecting an initial value for the timer at least in part based on the target rate, wherein the timer includes the initial value upon startup.

[0106] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for performing the first access operation at least in part based on receiving the first command, wherein starting the timer is at least in part based on performing the first access operation.

[0107] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9, wherein the value of the timer cannot satisfy the threshold corresponding to the value at which the timer expires.

[0108] Figure 6 The flowchart illustrates a method 600 for supporting memory performance management, as disclosed herein. The operation of method 600 can be implemented by a memory system or its components as described herein. For example, the operation of method 600 can be implemented by a reference... Figures 1 to 4 The memory system described is used for execution. In some instances, the memory system can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0109] At 605, the method may include incrementing the value of a counter in the memory system, wherein the value of the counter is associated with performing an access operation in the memory system. In some instances, aspects of operation 605 may be provided as referenced. Figure 4 The counter management component 440 described herein is used to perform this.

[0110] At 610, the method may include receiving a first command associated with the first access operation based at least in part on the value of an incrementing counter. In some instances, aspects of operation 610 may be provided as referenced. Figure 4 The described receiving component 425 is used to perform this action.

[0111] At 615, the method may include performing a first access operation based at least in part on the value of a counter satisfying a first threshold. In some instances, aspects of operation 615 may be as described in the reference. Figure 4 The described operation management component 435 is used to perform this.

[0112] At 620, the method may include adjusting the value of a counter based at least in part on performing the first access operation. In some instances, aspects of operation 620 may be as described in the reference. Figure 4 The counter management component 440 described herein is used to perform this.

[0113] In some instances, the device may execute a method or methods as described herein, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0114] Aspect 11: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for incrementing the value of a counter in a memory system, wherein the value of the counter is associated with performing an access operation in the memory system; receiving a first command associated with a first access operation based at least in part on incrementing the value of the counter; performing the first access operation based at least in part on the value of the counter satisfying a first threshold; and adjusting the value of the counter based at least in part on performing the first access operation.

[0115] Aspect 12: The method, apparatus, or non-transitory computer-readable medium according to aspect 11, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for receiving a second command associated with a second access operation based at least in part on adjusting the value of the counter and for avoiding the execution of the second access operation based at least in part on the fact that the value of the counter fails to meet the first threshold.

[0116] Aspect 13: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 11 to 12, wherein the value of the counter contains a positive integer when the value of the counter satisfies the first threshold.

[0117] Aspect 14: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 11 to 13, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for determining that the value of the counter satisfies a second threshold and avoiding incrementing the value of the counter based on the determination that the value of the counter satisfies the second threshold.

[0118] Aspect 15: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 11 to 14, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for receiving a third command containing an indication of an initial value of the counter and setting the initial value of the counter at least in part based on receiving the third command.

[0119] Aspect 16: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 11 to 15, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for identifying one or more parameters associated with the first command and determining, at least in part based on the one or more parameters, an amount by which the value of the counter is adjusted, wherein the counter is adjusted at least in part based on the determined amount of the value.

[0120] Aspect 17: The method, apparatus, or non-transitory computer-readable medium according to aspect 16, wherein the one or more parameters include the size of the data associated with the first access operation, the type of the first access operation, the number of planes of the memory system associated with the first access operation, or a combination thereof.

[0121] Aspect 18: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 11 to 17, further comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for determining a target rate for processing commands by the memory system and determining an amount to adjust the value of the counter based at least in part on the target rate, wherein the counter is adjusted at least in part based on the determined amount of the value.

[0122] Aspect 19: A method, apparatus or non-transitory computer-readable medium according to any one of aspects 11 to 18, wherein the value of the counter is incremented at fixed intervals.

[0123] Aspect 20: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 11 to 19, wherein adjusting the value of the counter comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for decrementing the value of the counter.

[0124] It should be noted that the described techniques include possible implementations, and the operation and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more of the described methods may be combined.

[0125] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a signal bus, which may have various bit widths.

[0126] The terms “electronically connected,” “conductively contacted,” “connected,” and “coupled” refer to the relationship between components that support signal flow between them. Components are considered electronically connected (or electrically contacted, connected, or coupled) if any conductive path exists between them that can support signal flow between them at any time. At any given time, the conductive path between electronically connected (or electrically contacted, connected, or coupled) components may be open or closed based on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0127] The term "coupling" (e.g., "electrical coupling") can refer to a condition that changes from an open-circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components via conductive paths). If a component (e.g., a controller) couples other components together, then that component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

[0128] The term "isolation" refers to a relationship between components in which signals are currently unable to flow between them. If there is an open circuit between components, then they are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents signals from flowing between the components using the conductive paths that previously allowed signal flow.

[0129] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe the connection between conditional actions, conditional procedures, or parts of a procedure.

[0130] The term "in response to" may refer to a condition or action that occurs at least partially (if not entirely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether following one or more other intermediate conditions or actions that occur immediately after the first condition or action or following one or more other intermediate conditions or actions that occur after the first condition or action).

[0131] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions thereof can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or any other doping method.

[0132] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0133] The descriptions set forth herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concept of the described instances.

[0134] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a hyphen after the reference label and a second label to differentiate similar components. When the first reference label is used only in the specification, the description is applicable to any of the similar components having the same first reference label, regardless of the second reference label.

[0135] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored as one or more instructions (e.g., code) on or transmitted over a computer-readable medium. Due to the nature of the software, the functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0136] For example, the illustrative blocks and modules described herein may be implemented or executed using one or more processors (e.g., DSPs, ASICs, FPGAs, discrete gate logic or discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. The processor may be an instance of a microprocessor, controller, microcontroller, state machine, or other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0137] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0138] As used herein (included in the claims), the article “a” preceding a noun is open-ended and should be understood to refer to “at least one” or “one or more” of those nouns. Therefore, the terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. For example, if a claim refers to a “component” performing one or more functions, then each of the individual functions can be performed by a single component or by any combination of multiple components. Therefore, the term “component” having a characteristic or performing a function can refer to “at least one of one or more components” having a particular characteristic or performing a particular function. Subsequent references to a component introduced by the article “a” using the terms “the” or “said” can refer to any or all of the one or more components. For example, a component introduced by the article “a” can be understood to mean “one or more components,” and subsequent references to “the component” in the claims can be understood to be equivalent to referring to “at least one of one or more components.” Similarly, subsequent references to a component introduced as "one or more components" using the terms "the" or "said" may refer to any or all of the components. For example, subsequent references to "one or more components" in the claims may be understood as equivalent to references to "at least one of the components."

[0139] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave), then the definition of media includes coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technology (e.g., infrared, radio, and microwave). As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these contents are also included within the scope of computer-readable media.

[0140] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: One or more memory devices; and A processing circuitry system coupled to and configured with the one or more memory devices to enable the memory system to: Receive the first command associated with the first access operation; The timer is started at least in part based on receiving the first command; Receive the second command associated with the second access operation; as well as The execution of the second access operation is suppressed at least in part based on the timer value meeting a threshold.

2. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Receive a third command including an indication of the initial value of the timer; and The initial value of the timer is set at least in part based on receiving the third command.

3. The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: Receive a fourth command including the updated initial value of the timer; and The initial value of the timer is updated at least in part based on receiving the fourth command.

4. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Receive a fifth command including a request for an initial value for the timer; and At least in part, it is based on the instruction to transmit the initial value of the timer upon receiving the fifth command.

5. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: The second access operation is performed at least in part based on the fact that the value of the timer cannot meet the threshold.

6. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: Identify one or more parameters associated with the first command; and The initial value of the timer is selected based at least in part on one or more of the parameters, wherein the initial value is included when the timer is started.

7. The memory system of claim 6, wherein the one or more parameters include the size of the data associated with the first access operation, the type of the first access operation, the number of planes of the memory system associated with the first access operation, or a combination thereof.

8. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: The target rate for processing commands is determined by the memory system; and The initial value of the timer is selected at least in part based on the target rate, wherein the initial value is included when the timer is started.

9. The memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: The first access operation is performed at least in part based on receiving the first command, wherein starting the timer is at least in part based on performing the first access operation.

10. The memory system of claim 1, wherein the value at which the timer fails to meet the threshold corresponds to the value at which the timer expires.

11. A memory system comprising: One or more memory devices; and A processing circuitry system coupled to and configured with the one or more memory devices to enable the memory system to: Increment the value of a counter in the memory system, wherein the value of the counter is associated with performing an access operation in the memory system; The first command associated with the first access operation is received at least in part based on the incrementing value of the counter; The first access operation is performed at least in part based on the value of the counter satisfying a first threshold. as well as The value of the counter is adjusted at least in part based on the execution of the first access operation.

12. The memory system of claim 11, wherein the processing circuitry is further configured to cause the memory system to: The second command associated with the second access operation is received, at least in part, based on adjusting the value of the counter; and The second access operation is avoided at least in part because the value of the counter cannot meet the first threshold.

13. The memory system of claim 11, wherein when the value of the counter satisfies the first threshold, the value of the counter includes a positive integer.

14. The memory system of claim 11, wherein the processing circuitry is further configured to cause the memory system to: Determine that the value of the counter satisfies the second threshold; and The incrementing of the counter value is avoided, at least in part, based on determining that the value of the counter satisfies the second threshold.

15. The memory system of claim 11, wherein the processing circuitry is further configured to cause the memory system to: Receive a third command including an indication of the initial value of the counter; and The initial value of the counter is set at least in part based on receiving the third command.

16. The memory system of claim 11, wherein the processing circuitry is further configured to cause the memory system to: Identify one or more parameters associated with the first command; and The number of values ​​used to adjust the counter is determined based at least in part on one or more of the parameters, wherein the counter is adjusted based at least in part on the determined number of values.

17. The memory system of claim 16, wherein the one or more parameters include the size of the data associated with the first access operation, the type of the first access operation, the number of planes of the memory system associated with the first access operation, or a combination thereof.

18. The memory system of claim 11, wherein the processing circuitry is further configured to cause the memory system to: The target rate for processing commands is determined by the memory system; and The number of times the value of the counter is adjusted is determined at least in part based on the target rate, wherein the counter is adjusted at least in part based on the determined number of values.

19. The memory system of claim 11, wherein the value of the counter is incremented at fixed intervals.

20. The memory system of claim 11, wherein adjusting the value of the counter includes the processing circuitry being configured such that the memory system: Decrease the value of the counter.

21. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of a memory system, cause the memory system to: Receive the first command associated with the first access operation; The timer is started at least in part based on receiving the first command; Receive the second command associated with the second access operation; as well as The execution of the second access operation is suppressed at least in part based on the timer value meeting a threshold.

22. The non-transitory computer-readable medium of claim 21, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: Receive a third command including an indication of the initial value of the timer; and The initial value of the timer is set at least in part based on receiving the third command.

23. The non-transitory computer-readable medium of claim 22, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: Receive a fourth command including the updated initial value of the timer; and The initial value of the timer is updated at least in part based on receiving the fourth command.

24. The non-transitory computer-readable medium of claim 21, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: Receive a fifth command including a request for an initial value for the timer; and At least in part, it is based on the instruction to transmit the initial value of the timer upon receiving the fifth command.

25. The non-transitory computer-readable medium of claim 21, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: The second access operation is performed at least in part based on the fact that the value of the timer cannot meet the threshold.

Images