Multi-level analog programming convergence control of memory cells in memory device

Abstract

The invention relates to multi-level analog programming convergence control of memory cells in a memory device. A memory device includes a memory array having a plurality of memory cells formed at respective intersections of a plurality of word lines and a plurality of bit lines. The memory device further includes a page buffer circuit coupled to the memory array, the page buffer circuit having a plurality of dynamic latch circuits to store values representative of respective data line bias voltages applied to the plurality of bit lines. Each of the plurality of dynamic latch circuits includes: a storage element for storing a value representing a respective data line bias voltage; a first switch and a second switch in a load path coupled to the storage element; and a third switch in a decode path coupled to the first switch in the load path.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to multilevel analog programming convergence control of memory cells in memory devices of memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] On one hand, this disclosure relates to a memory device comprising: a memory array including a plurality of memory cells formed at corresponding intersections of a plurality of word lines and a plurality of bit lines; and a page buffer circuit coupled to the memory array, the page buffer circuit including a plurality of dynamic latch circuits for storing values ​​representing corresponding data line bias voltages applied to the plurality of bit lines, wherein each of the plurality of dynamic latch circuits includes: a memory element for storing the value representing the corresponding data line bias voltage; a first switch and a second switch in a loading path coupled to the memory element, wherein when the first and second switches are activated, the value is loaded into the memory element via the loading path; and a third switch in a decoding path coupled to the first switch in the loading path, wherein the third switch is controlled by a shared decode loading control signal, and wherein corresponding signals corresponding to different subsets of the plurality of memory cells are driven on the decoding path to selectively enable the first switch in the loading path.

[0004] On the other hand, this disclosure relates to a method comprising: initiating a programming operation on a memory array of a memory device, the memory array including a plurality of memory cells formed at corresponding intersections of a plurality of word lines and a plurality of bit lines, the memory device including a page buffer circuit coupled to the memory array, the page buffer circuit including a plurality of dynamic latching circuits for storing values ​​representing corresponding data line bias voltages applied to the plurality of bit lines, wherein each of the plurality of dynamic latching circuits includes a memory element, a first switch and a second switch in a loading path coupled to the memory element, and a third switch in a decoding path coupled to the first switch in the loading path; and causing a shared decoding loading control signal to be applied to the third switch in the decoding path, wherein corresponding signals corresponding to different subsets of the plurality of memory cells drive the loading path to selectively activate the loading path.

[0005] On the other hand, this disclosure relates to a memory device comprising: a memory array including a plurality of memory cells formed at corresponding intersections of a plurality of word lines and a plurality of bit lines; a page buffer circuit coupled to the memory array, the page buffer circuit including a plurality of dynamic latch circuits for storing values ​​representing corresponding data line bias voltages applied to the plurality of bit lines, wherein each of the plurality of dynamic latch circuits includes a memory element, a first switch and a second switch in a loading path coupled to the memory element, and a third switch in a decoding path coupled to the first switch in the loading path; and control logic operatively coupled to the memory array and the page buffer circuit to perform an operation including: causing a shared decode loading control signal to be applied to the third switch in the decoding path, wherein corresponding signals corresponding to different subsets of the plurality of memory cells drive on the decoding path to selectively activate the loading path. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1A This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 2 Some embodiments of this disclosure may be used for reference. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] Figure 3 This is a schematic diagram illustrating a portion of the dynamic latch circuitry in the page buffer of a memory device according to some embodiments of the present disclosure.

[0011] Figure 4 This describes the application of some embodiments of the present disclosure to... Figure 3 A diagram of the waveforms used for convergence control in a dynamic latch circuit for multi-level analog programming.

[0012] Figure 5 This is a flowchart of an example method for multi-level analog programming convergence control of memory cells in a memory device of a memory subsystem according to some embodiments of the present disclosure.

[0013] Figure 6 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0014] This disclosure relates to multi-level analog programming convergence control of memory cells in a memory device within a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of both. Examples of storage devices and memory modules are described below with reference to Figure 1. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data retrieved from the memory subsystem.

[0015] A memory subsystem may include high-density non-volatile memory devices in which data is expected to be retained when no power is supplied to the memory device. For example, NAND memory (e.g., 3D flash NAND memory) provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die containing one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and have various logic states related to the number of bits stored. Logic states may be represented by binary values ​​such as “0” and “1” or combinations of such values.

[0016] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in arrays of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which, together with one or more bit lines, is used to generate the address of each memory cell. The intersection of a bit line and a word line constitutes the address of the memory cell. A block, hereinafter, refers to a unit of a memory device used to store data and can include groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of the memory device to allow concurrent operations to occur on each plane. A memory device can include circuitry that performs concurrent memory page accesses on two or more memory planes. For example, a memory device can include multiple access line driver circuits and power circuitry that can be shared by planes of the memory device to facilitate concurrent access to pages (containing different page types) on two or more memory planes. For ease of description, these circuits are often referred to as independent plane driver circuitry. Depending on the storage architecture used, data can be stored across memory planes (i.e., in stripes). Therefore, a request to read a data segment (e.g., corresponding to one or more data addresses) can result in a read operation on two or more of the memory planes of the memory device.

[0017] Programming a memory device can be achieved by applying one or more programming pulses separated by verification pulses to program each memory cell in a selected group of memory cells to a corresponding target data state (which may be an intermediate or final data state). In this method, the programming pulse is applied to the access line of the selected memory cell, such as an access line commonly referred to as a word line. After each programming pulse, one or more verification voltage levels are typically used to verify the programming of the selected memory cell. In the Incremental Step Pulse Programming (ISPP) scheme, programming typically uses a number of programming pulses, where each programming pulse is a single-level pulse that shifts the threshold voltage of the memory cell by a certain amount.

[0018] A programming pulse can be applied to a selected access line (e.g., a word line) and thus to the control gate of the memory cell row connected to the selected access line (e.g., to connect its control gate to the selected access line). A typical programming pulse may start at or near 13V and tends to increase in amplitude with each subsequent programming pulse. When a programming potential (e.g., the voltage level of the programming pulse) is applied to the selected access line, an enable voltage, such as a reference potential (e.g., 0V), can be applied to the channel of the memory cell selected for programming (i.e., those memory cells whose data state is to be shifted to a higher level by the programming operation). This can cause charge to transfer from the channel to the charge storage structure of these selected memory cells. For example, floating gates are typically charged by direct injection of electrons from the channel to the floating gate or by Fowler-Nordheim tunneling, resulting in an increase in the threshold voltage in the programming state.

[0019] During programming, a suppression voltage (e.g., Vcc) may be applied to data lines (e.g., bit lines) selectively connected to a string of memory cells (including memory cells connected to selected access lines and not selected for programming or no longer selected for programming). For example, in a memory device using multiple programming levels (e.g., where each programming level corresponds to a different target data state of a multi-level cell memory, such as MLC, TLC, QLC, etc.), unselected memory cells may include memory cells associated with a programming level different from the current programming level to which the selected memory cells are programmed. In addition to data lines selectively connected to memory cells already in their target data state, these unselected data lines may further include data lines not addressed by programming operations. For example, a logical data page may correspond to memory cells connected to a specific access line and selectively connected to a specific subset of data lines (e.g., every other data line), such that the remaining subset of data lines is not selected for programming operations and is therefore suppressed.

[0020] Between the application of one or more programming pulses, a verification phase of the programming operation can be performed to check each selected memory cell to determine whether it has reached the target data state. If a selected memory cell has reached the target data state, further programming of it can be inhibited if other selected memory cells still require additional programming pulses to reach their target data state. After the verification phase, if there are memory cells that have not yet been programmed, additional programming pulses can be applied. This process of applying programming pulses followed by verification (e.g., the programming phase and verification or sensing phase of the programming operation) typically continues until all selected memory cells have reached their target data state. For example, if a certain number of programming pulses (e.g., the maximum number) have been applied or a certain voltage level of programming pulses (e.g., the maximum voltage level) has been reached and one or more selected memory cells have still not been programmed, these memory cells can be marked as defective.

[0021] In a programming scheme known as Selective Slow Programming Convergence (SSPC), different voltage levels can be used on the data lines enabled for programming. Memory cells closer to their respective target data states (e.g., partially enabled for programming) are programmed more slowly when they receive the same voltage level at their respective control gates, compared to memory cells farther from their target data states (e.g., fully enabled for programming). Compared to more traditional programming schemes that rely on fully enabling or suppressing programming of memory cells, SSPC facilitates a narrower distribution of threshold voltages defining each data state. By narrowing the threshold voltage distribution and thus providing a larger dead zone or margin between adjacent threshold voltage distributions, the accuracy of determining the data state of memory cells can be improved, and / or memory density (e.g., the number of data bits per memory cell) can be increased.

[0022] While SSPC programming schemes offer a tighter threshold voltage distribution than more traditional programming schemes, these benefits typically come at the cost of increased cost. Specifically, for each programming pulse, the memory cells undergoing programming are typically assigned to different subsets of memory cells (e.g., a subset of memory cells with suppressed programming, a subset of memory cells fully enabled for programming, and a subset of memory cells with partially enabled programming). Each subset of memory cells corresponds to a specific mutually exclusive range of threshold voltages. The threshold voltage of each memory cell undergoing programming is typically determined or estimated in order to assign it to the appropriate subset of memory cells. This increases the time and / or complexity of the verification phase of the programming operation.

[0023] Various methods attempt to further narrow the threshold voltage distribution compared to typical SSPC programming schemes, while reducing the need to allocate memory cells for each level enabled for partial programming. Such methods can provide a data line voltage level during subsequent programming pulses, which corresponds to the memory string current level (e.g., It) during the verification phase of the programming operation (e.g., the verification phase immediately preceding the programming operation). string The control logic in the memory device can capture the reserved voltage level of the node in the page buffer circuit after or during the verification phase of the programming operation. During the verification phase of the programming operation, the node can be pre-charged and then selectively discharged through the data line in response to the activation level of the selected memory cell in the programming operation. Therefore, a higher threshold voltage (e.g., a lower Ig in response to a given control gate voltage level) is expected. string ) memory cells can cause the retention voltage level at the node to be higher than that with a lower threshold voltage (e.g., a higher I in response to a given control gate voltage level). string The remaining voltage level of the node can then be used as the control voltage for the source follower to generate the data line voltage levels for subsequent programming operations. In this way, memory cells closer to their target threshold voltage are expected to receive higher data line voltages (e.g., lower levels for partial enable) and memory cells farther from their target threshold voltage are expected to receive lower data line voltages (e.g., higher levels for partial enable). The result is an analog programming convergence method where the data line voltage varies depending on the threshold voltage of the selected memory cell, rather than using a digital programming convergence method (e.g., where the cell is fully enabled for programming, partially enabled for programming, or suppressed).

[0024] However, these analog methods have several drawbacks. For example, a page buffer associated with a memory array of a memory device may contain a corresponding dynamic latch circuit corresponding to each bit line in the array and therefore to each vertical string of memory cells in the array. Each dynamic latch circuit may contain a memory element to which a value representing a data line bias voltage can be loaded, and when subsequently enabled, the value can be used to drive the corresponding bit line to the data line bias voltage to affect the appropriate level of partial enable. However, given that loading and enabling are controlled by a global control signal shared by each of the dynamic latch circuits, only a single programming level of data line bias voltage can be applied at a time. Since different programming levels will utilize different data line bias voltages, any attempt to load values ​​of different programming levels into a memory element will overwrite or at least partially corrupt any previously loaded value unless the entire programming cycle of the previous programming level (e.g., initial programming pulse, verification operation, and subsequent programming pulses) has been completed. Therefore, for a single programming level per programming cycle, such a memory device can only implement the digital programming convergence method described herein. This increases the total programming time as well as the power and resource utilization during programming operations.

[0025] This disclosure addresses the aforementioned and other drawbacks by implementing multi-level analog programming convergence control for memory cells in a memory device within a memory subsystem. In one embodiment, each dynamic latch circuit in the page buffer includes an additional switch controlled by a global control signal, which can be used to selectively enable a load path for memory elements corresponding to individual bits being programmed. Selective load path enabling allows a corresponding value representing a data line bias voltage to be loaded into memory elements of a specific group of memory cells (e.g., memory cells associated with a given programming level) without corrupting values ​​previously loaded into memory elements of another group of memory cells. A global enable signal can then be applied to cause data line bias voltages based on different groups of memory values ​​to be applied simultaneously to the corresponding bit lines when a single programming pulse is applied to the word line. In this way, during the same programming cycle (e.g., without an intermediate programming pulse being applied), data line biasing for analog programming convergence can be performed for memory cells of multiple programming levels or any other group utilizing different data line bias voltages.

[0026] The advantages of this method include, but are not limited to, improved performance of the memory subsystem. The method described in this paper reduces total programming time and power consumption by allowing the application of appropriate data line bias voltages for analog programming convergence, without requiring a separate programming pulse for each group of memory cells.

[0027] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0028] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0029] The computing system 100 may be, for example, a desktop computer, a laptop computer, a web server, a mobile device, a vehicle (e.g., an airplane, drone, train, car or other means of transport), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked commercial device), or a computing device containing memory and processing devices.

[0030] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0031] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller, a CXL controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0032] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Compute Fast Link (CXL) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), and Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe or CXL interface), host system 120 can further access memory components (e.g., memory device 130) using an NVM High Speed ​​(NVMe) interface. The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1AFor example, memory subsystem 110 is described. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or a combination of communication connections.

[0033] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0034] Examples of non-volatile memory devices (such as memory device 130) include NAND flash memory and in-situ write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can perform bit storage based on volume resistance variations combined with a stackable cross-gate format data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0035] Each of the memory devices 130 may include one or more arrays of memory cells. For example, one type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, or QLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0036] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0037] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0038] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrative example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0039] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1A The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0040] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, discard item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0041] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0042] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Memory device 130 may, for example, represent a single die on which some control logic (e.g., local media controller 135) is embodied. In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0043] In one embodiment, the memory subsystem 110 includes a memory interface 113 responsible for handling interactions between the memory subsystem controller 115 and memory devices (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface 113 may send memory access commands, such as programming commands, read commands, or other commands, to the memory device 130 in response to a request received from the host system 120. Additionally, the memory interface 113 may receive data from the memory device 130, such as data retrieved in response to confirmation that a read command or programming command has been successfully executed. In some embodiments, the memory subsystem controller 115 includes at least a portion of the memory interface 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0044] In one embodiment, the local media controller 135 of the memory device 130 includes a programming convergence management component 150. The programming convergence management component 150 manages programming convergence associated with memory cells in the memory array 104 of the memory device 130. For example, the programming convergence management component 150 may use a dynamic latch circuitry system 162 in a page buffer 160 to implement multi-level analog programming convergence control of the memory cells in the memory array 104. In one embodiment, the programming convergence management component 150 may determine the corresponding data line bias voltages of memory cells in different groups (e.g., associated with multiple programming levels) during successive programming verification operations. The programming convergence management component 150 may sequentially use control signals applied to elements of the dynamic latch circuitry system 162 for different groups to cause corresponding values ​​representing data line bias voltages to be stored in the dynamic latch circuitry system 162, such that corresponding data line bias voltages can be applied together to the corresponding bit lines in the memory array 104 without applying intermediate programming pulses between groups. The following describes further details regarding the operation of the programmable convergence management component 150 and the dynamic latch circuitry system 162.

[0045] Figure 1B It is a memory subsystem according to an embodiment (e.g.) Figure 1A This is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 (of the memory subsystem 110). Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device. In one embodiment, the memory subsystem controller 115 includes a memory interface 113.

[0046] Memory device 130 includes a memory cell array 104 logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in memory cell array 104 ( Figure 1B (Not shown in the text) It can be programmed to one of at least two target data states.

[0047] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 160 for managing commands, addresses, and data input to and from memory device 130 and data and status information output from memory device 130. Address register 114 communicates with I / O control circuitry 160, row decoding circuitry 108, and column decoding circuitry 109 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 160 and local media controller 135 to latch incoming commands.

[0048] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115. Specifically, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 109 to control them in response to addresses. In one embodiment, the local media controller 135 includes a programming management component 150 that can implement multi-step simulated programming convergence of memory cells in memory array 104, as described herein.

[0049] The local media controller 135 also communicates with cache register 172. Cache register 172 latches incoming or outgoing data for temporary storage, as directed by the local media controller 135, when memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 172 to data register 170 for transfer to memory cell array 104; subsequently, new data can be latched from I / O control circuitry system 160 into cache register 172. During read operations, data can be transferred from cache register 172 to I / O control circuitry system 160 for output to memory subsystem controller 115; subsequently, new data can be transferred from data register 170 to cache register 172. Cache register 172 and / or data register 170 may form a page buffer 160 of memory device 130 (e.g., may form part of the page buffer). Page buffer 160 may further include sensing means for sensing the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cell array 104. Figure 1B (Not shown in the image). Status register 122 can communicate with I / O control circuitry 160 and local media controller 135 to latch status information for output to memory subsystem controller 115. Additionally, page buffer 160 may contain several dynamic latch circuits 162. For example, corresponding dynamic latch circuits 162 may exist for each vertical string of memory cells in memory cell array 104 and therefore for each bit line of memory cell array 104.

[0050] The memory device 130 enables the local media controller 135 to receive control signals from the memory subsystem controller 115 via control link 182. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) may be further received via control link 182 depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the memory subsystem controller 115 via a multiplexed input / output (I / O) bus 184 and outputs data to the memory subsystem controller 115 via the I / O bus 184.

[0051] For example, commands can be received at I / O control circuitry 160 via I / O pins [7:0] of I / O bus 184 and then written to command register 124. Addresses can be received at I / O control circuitry 160 via I / O pins [7:0] of I / O bus 184 and then written to address register 114. Data can be received at I / O control circuitry 160 via I / O pins [7:0] of 8-bit devices or I / O pins [15:0] of 16-bit devices and then written to cache register 172. Data can then be written to data register 170 for programming memory cell array 104.

[0052] In this embodiment, cache register 172 may be omitted and data may be written directly to data register 170. Data may also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connections to memory device 130 via external devices, such as memory subsystem controller 115.

[0053] Those skilled in the art should understand that additional circuitry and signals can be provided, and have been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described is not necessarily separated into different components or component parts of an integrated circuit device. For example, a single component or component part of an integrated circuit device can be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins have been described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0054] Figure 2 This is a reference based on the embodiments. Figure 1B A schematic diagram of a portion of a memory cell array 104, such as a NAND memory array, in a memory of the described type. Memory array 104 includes access lines (e.g., word lines 2020 to 202). N ) and data lines (e.g., bit lines 2040 to 204) M Word line 202 can be connected to global access lines (e.g., global word lines) in a many-to-one relationship. Figure 2(Not shown in the text). In some embodiments, the memory array 104 may be formed over a semiconductor, which may be conductively doped to have a conductivity type, for example, p-type conductivity for forming a p-well or n-type conductivity for forming an n-well.

[0055] The memory array 104 can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a series of serially connected memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 can be connected (e.g., selectively connected) to the common source (SRC) 216 and can contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for data storage. The memory cell 208 of each NAND string 206 may be connected in series with select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it could be a source-select transistor, often referred to as a select-gate-source) and select gate 212 (e.g., a field-effect transistor) (e.g., select gates 2120 to 212) M Between one of them (for example, it could be a drain-select transistor, often referred to as a select gate-drain). Select gates 2100 to 210 M They can be connected together to select line 214 (e.g., source select line (SGS)), and select gates 2120 to 212. M They can be connected together to select line 215 (e.g., drain select line (SGD)). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0056] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0057] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0058] Figure 2 The memory array 104 can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a substantially parallel plane. Alternatively, Figure 2 The memory array 104 in the array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and substantially parallel to the plane containing the bit line 204.

[0059] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or the like) that determines the data state of the memory cell (e.g., through changes in a threshold voltage), and a control gate 236, such as... Figure 2 The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a source / drain defining electrode (e.g., source) 230 and a source / drain defining electrode (e.g., drain) 232. The memory cell 208 connects its control gate 236 to (and in some cases forms) a word line 202.

[0060] A row of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may, but may not, include all memory cells 208 commonly connected to a given word line 202. Multiple rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically include every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202... NFurthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202... N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd memory cell).

[0061] although Figure 2 Bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is evident from the figure that the bit lines 204 of the memory cell array 104 can be consecutively numbered from bit line 2040 to bit line 204. M Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For a given memory device, all memory cells commonly connected to a given word line may be considered physical pages of the memory cell. A portion (e.g., the previous or next page of the memory cell) of a physical page of a memory cell read during a single read operation or programmed during a single programmable operation (in some embodiments, it may still be an entire line) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a page of memory cell referred to herein refers to the memory cell of a logical page of the memory cell. Although Figure 2 Examples are discussed in conjunction with NAND flash memory, but the embodiments and concepts described herein are not limited to a specific array architecture or structure, but may include other structures (such as SONOS, phase change, ferroelectric, etc.) and other architectures (such as AND arrays, NOR arrays, etc.).

[0062] Figure 3This is a schematic diagram illustrating a portion of the dynamic latch circuitry 162 in the page buffer of a memory device according to some embodiments of the present disclosure. For example, the page buffer 160 associated with the memory array 104 of the memory device 130 may include a corresponding dynamic latch circuitry corresponding to each bit line in the array 104 and therefore to each vertical string of memory cells in the array 104. Dynamic latch circuitry 162 is an example of one of these circuits, and for each bit line in the array 104, the page buffer 160 may include a copy of dynamic latch circuitry 162. In one embodiment, dynamic latch circuitry 162 includes a storage element 332 to which a value representing a data line bias voltage can be loaded (e.g., via load path 320), and when enable path 330 is subsequently activated, the value from storage element 332 can be used to drive the corresponding bit line 304 to the data line bias voltage to influence the appropriate level of partial enable for programming operations on one or more memory cells associated with bit line 304. For example, load path 320 may include a first switch 322 and a second switch 324 (e.g., implemented as transistors), which, when activated, allow a value representing a data line bias voltage to be loaded into storage element 332 via load path 320. In one embodiment, the first switch 322 is controlled by decoding path 310 and the second switch is controlled by a shared load control signal (i.e., asspc_load).

[0063] In one embodiment, the dynamic latch circuit 162 includes a third switch 312 in the decoding path 310, coupled to a first switch 322 in the loading path 320. The third switch 312 may be controlled by a control signal (i.e., asspc_dec_load) associated with a subset of memory cells. Since the signals driven on the decoding path 310 may differ for memory cells programmed to different programming levels, it can be used to selectively enable the loading path 320 for memory elements corresponding to individual bits being programmed. Selectively enabling the loading path allows a corresponding value representing a data line bias voltage to be loaded into the memory elements of a specific group of memory cells (e.g., memory cells associated with a given programming level) without corrupting values ​​previously loaded into memory elements of another group of memory cells. For example, the signals driven on the decoding path 310 (i.e., asspc_dec_Lx, where Lx represents corresponding programming levels L1, L2, L3, etc.) may correspond to a desired grouping of cells programmed to a specific level and may be generated in any manner, including but not limited to logical operations on internal signals / data, external inputs, etc. In one embodiment, enable path 330 includes a fourth switch 334 coupled to storage element 332 and controlled by a shared enable control signal (i.e., asspc_en). When the fourth switch 334 is enabled, a corresponding data line bias voltage (i.e., based on the value stored in storage element 332) can be applied to the corresponding bit line 304 via enable path 330.

[0064] Figure 4 This describes the application of some embodiments of the present disclosure to... Figure 3 This is a diagram of waveforms used for multi-level analog programming convergence control in a dynamic latch circuit. Waveform 400 represents a voltage that can be applied to a word line (e.g., one of word lines 202) in the memory cell array 104 during a programming operation. For example, to program a memory cell associated with a word line, control logic in memory device 130 (e.g., programming management component 150) can cause a first programming pulse 402 to be applied to the word line. A programming verification operation can be used after the first programming pulse 402 to verify whether certain memory cells have been programmed to their corresponding programming level (e.g., L1, L2, etc.). For example, to perform a first programming verification 404 on a memory cell associated with a word line that will be programmed to the first programming level (L1), the control logic can read these memory cells and compare the current voltage level with the corresponding target voltage level of L1. For each memory cell, the control logic can determine the corresponding data line bias voltage to be applied to influence the appropriate level of partial enable. During the first programming verification 404, the control logic can activate switches 312 corresponding to all memory cells in the decoding path 310 of the dynamic latch 162. This is indicated by the assertion of the control signal asspc_dec_load at the gate terminal of switch 312 during the first programming verification 404. When switch 312 is activated, a signal corresponding to the memory cell to be programmed into L1 is provided on the decoding path 310. For example, the signal asspc_dec_L1 is driven high during the first programming verification 404, which in turn activates switch 322 in the loading path 320 for the corresponding memory cell. Once the corresponding data line bias voltage for each L1 cell is determined, the control logic can cause the shared load control signal asspc_load to be asserted at the gate terminal of switch 324 in the loading path. Therefore, since both switches 322 and 324 corresponding to L1 memory cells in the dynamic latch 162 are activated, it indicates that the value of the data line bias voltage for each L1 memory cell can be loaded into the corresponding memory element 332. Although switch 312 corresponding to the memory cell to be programmed to L2 is also activated by asspc_dec_load, the signal asspc_dec_L2 driven on decoding path 310 remains low, so that switch 322 is not activated for these memory cells. The same applies to any remaining programming levels, such that signals in decoding path 310 are driven high only for memory cells to be programmed to a specific programming level during the corresponding programming verification operation, while signals in decoding path 310 remain low for memory cells to be programmed to other programming levels.

[0065] To perform a second programming verification 406 on memory cells associated with word lines that will be programmed to the second programming level (L2), the control logic may read these memory cells and compare the current voltage level with the corresponding target voltage level of L2. For each memory cell, the control logic may determine the corresponding data line bias voltage to be applied to influence the appropriate level of partial enable. During the second programming verification 406, the control logic may activate switches 312 in the decoding path 310 of the dynamic latch 162 corresponding to all memory cells. This is illustrated by the assertion control signal asspc_dec_load at the gate terminal of switch 312 during the second programming verification 406. When switch 312 is activated, a signal corresponding to the memory cell to be programmed to L2 is provided on the decoding path 310. For example, the signal asspc_dec_L2 is driven high during the second programming verification 406, which in turn activates switch 322 in the loading path 320 of the corresponding memory cell. Once the corresponding data line bias voltage for each L2 cell is determined, the control logic causes the shared load control signal asspc_load to be asserted at the gate terminal of switch 324 in the load path. Therefore, since both switches 322 and 324 in dynamic latch 162 corresponding to L2 memory cells are activated, the value indicating the data line bias voltage for each L2 memory cell can be loaded into the corresponding memory element 332. Although the switch 312 corresponding to the memory cell to be programmed into L1 is also activated by asspc_dec_load, the signal asspc_dec_L1 driven on the decoding path 310 remains low, preventing the switches 322 for these memory cells from being activated. Because the switches 322 in dynamic latch 162 corresponding to L1 memory cells are not activated, the values ​​stored in the memory elements 332 of these dynamic latches 162 are not corrupted. A similar process can be repeated for any number of additional groups of memory cells (e.g., memory cells associated with additional programming levels).

[0066] Once the value indicating the data line bias voltage has been loaded into the corresponding memory element 332 of each group of memory cells, the control logic can cause the shared enable control signal asspc_en to be applied to the switch 334 in the enable path of each dynamic latch circuit 162, resulting in the data line bias voltage based on the memory value of the different groups being simultaneously applied to the corresponding bit line 304 when the second programming pulse is applied to the word line 408. The corresponding data line bias voltage affects the corresponding level of partial enable on each bit line to control programming convergence during the programming operation. In this way, during the same programming cycle (e.g., without the application of an intermediate programming pulse), data line biasing for simulating programming convergence can be performed on memory cells of multiple programming levels or any other group using different data line bias voltages.

[0067] Figure 5 This is a flowchart illustrating an example method for multi-level analog programming convergence control of memory cells in a memory device according to some embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1A and Figure 1B The programming convergence management component 150 is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0068] At operation 505, a programming operation is initiated. For example, processing logic (e.g., programming convergence management component 150) may initiate a programming operation on memory array 104, which includes multiple programming pulses, such as programming pulses 402 and 408. In one embodiment, each of the programming pulses is separated by one or more verification operations and applied to an access line (e.g., a word line) associated with a selected memory cell to program the selected memory cell to a corresponding target data state. After each programming pulse, one or more verification voltage levels are typically used to verify the programming of the selected memory cell. In an incremental step-pulse programming (ISPP) scheme, programming typically uses a number of programming pulses, where each programming pulse is a single-level pulse that shifts the threshold voltage of the memory cell by a certain amount. In one embodiment, memory array 104 includes a plurality of memory cells formed at corresponding intersections of a plurality of word lines and a plurality of bit lines, and memory device 130 includes page buffer circuitry 160 coupled to memory array 104. Page buffer circuit 160 may include multiple dynamic latch circuits (e.g., dynamic latch circuit 162) to store values ​​representing corresponding data line bias voltages applied to multiple bit lines. Each of the multiple dynamic latch circuits 162 includes a storage element 332, a first switch 322 and a second switch 324 coupled to a loading path 320 of the storage element 332, and a third switch 312 coupled to a decoding path 310 of the first switch 322 of the loading path 320.

[0069] At operation 510, a shared decode load control signal is applied. For example, processing logic may cause a shared decode load control signal (e.g., asspc_dec_load) to be applied to a third switch 312 in the decode path 310 of the plurality of dynamic latch circuits 162 to activate the decode path 310. In one embodiment, a signal (e.g., asspc_dec_L1) corresponding to a first subset of the plurality of memory cells is provided on the decode path 310 and driven high during the first programming verification 404, which in turn activates the load path 320 in the first group of the plurality of dynamic latch circuits 162 associated with the first subset of the plurality of memory cells. This allows a value representing a data line bias voltage (e.g., via load path 320) to be loaded into the memory elements 332 of the first group of the plurality of dynamic latch circuits 162. In one embodiment, the first subset of the plurality of memory cells includes one or more memory cells in a page that will be programmed to a first programming level (e.g., L1). In other embodiments, the first subset of the plurality of memory cells may include any other group of memory cells. For a second subset of multiple memory cells (e.g., memory cells to be programmed to a second programming level (e.g., L2), a signal (e.g., asspc_dec_L2) remains low during the first programming verification 404, such that load paths 320 in the second group of multiple dynamic latch circuits 162 associated with the second subset of multiple memory cells are not activated.

[0070] At operation 515, a shared load control signal is applied. For example, the processing logic may cause a shared load control signal (e.g., asspc_load) to be applied to the corresponding second switch 324 in each of the multiple dynamic latch circuits 162 to concurrently activate the corresponding second switch 324.

[0071] At operation 520, a shared decode load control signal is applied. For example, processing logic may cause a shared decode load control signal (e.g., asspc_dec_load) to be applied to a corresponding third switch 312 in the decode path 310 of the plurality of dynamic latch circuits 162 to activate the decode path 310. In one embodiment, a signal (e.g., asspc_dec_L2) corresponding to a second subset of the plurality of memory cells is provided on the decode path 310 and driven high during the second programming verification 406, which in turn activates the load path 320 in the second group of the plurality of dynamic latch circuits 162 associated with the second subset of the plurality of memory cells. This allows a value representing a data line bias voltage (e.g., via load path 320) to be loaded into the memory elements 332 of the second group of the plurality of dynamic latch circuits 162. In one embodiment, the second subset of the plurality of memory cells includes one or more memory cells in a page that will be programmed to a second programming level (e.g., L2). In other embodiments, the second subset of the plurality of memory cells may include any other group of memory cells, such as a group of memory cells that will be programmed to the same programming level as the first subset. For a second subset of multiple memory cells (e.g., memory cells to be programmed to a first programming level (e.g., L1), a signal (e.g., asspc_dec_L1) remains low during the second programming verification 406, such that load paths 320 in the first group of multiple dynamic latch circuits 162 associated with the second subset of multiple memory cells are not activated.

[0072] At operation 525, a shared load control signal is applied. For example, the processing logic may cause a shared load control signal (e.g., asspc_load) to be applied to the corresponding second switch 324 in each of the multiple dynamic latch circuits 162 to concurrently activate the corresponding second switch 324.

[0073] At operation 530, a shared enable control signal is applied. For example, the processing logic may cause a shared enable control signal (e.g., asspc_en) to be applied to the corresponding fourth switch 334 in the enable path 330 of each of the plurality of dynamic latch circuits 162 to concurrently activate the corresponding fourth switch 334. In one embodiment, when the fourth switch 334 is activated, a corresponding data line bias voltage is applied via the enable path 330 to its corresponding bit line 304. For example, a value from the memory element 332 may be used to drive the corresponding bit line 304 to the data line bias voltage to affect the appropriate level of partial enable on each programming level of one or more memory cells associated with the bit line 304.

[0074] At operation 535, a programming pulse is applied. For example, the processing logic may cause a second programming pulse 408 to be applied to the word line to program the memory cell to its corresponding target data state using a partially enabled level based on the corresponding data line bias voltage.

[0075] Figure 6 The computer system 600 describes an example machine within which a set of instructions can be executed to cause the machine to perform any or more of the methodologies discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1A The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1A (Operation of the programming convergence management component 150 or the local media controller 135). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0076] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0077] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 618, which communicate with each other via a bus 630.

[0078] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0079] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 626 or software embodying any or more of the methodologies or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1A The memory subsystem 110.

[0080] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1A The programming convergence management component 150 provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0081] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are generally conceived here as self-consistent sequences of operations that lead to desired results. Operations are operations that require the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0082] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0083] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used in conjunction with the teachings herein, or it can be demonstrated that it is convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the appended claims. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0085] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0086] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than limiting.

Claims

1. A memory device comprising: A memory array comprising multiple memory cells formed at corresponding intersections of multiple word lines and multiple bit lines; and Page buffer circuitry coupled to the memory array, the page buffer circuitry including a plurality of dynamic latch circuits for storing values ​​representing corresponding data line bias voltages applied to the plurality of bit lines, each of the plurality of dynamic latch circuits including: Storage element, used to store values ​​representing the bias voltage of the corresponding data line; A first switch and a second switch are coupled to a loading path of the storage element, wherein when the first and second switches are activated, the value is loaded into the storage element via the loading path; and A third switch is coupled to the decoding path of the first switch in the loading path, wherein the third switch is controlled by a shared decoding loading control signal, and wherein corresponding signals corresponding to different subsets of the plurality of memory units are driven on the decoding path to selectively enable the first switch in the loading path.

2. The memory device of claim 1, wherein the second switch is controlled by a shared load control signal for concurrently activating a corresponding second switch in each of the plurality of dynamic latch circuits.

3. The memory device of claim 1, wherein the first subset of the plurality of memory cells includes one or more memory cells in a page to be programmed to a first programming level, and wherein the second subset of the plurality of memory cells includes one or more memory cells in a page to be programmed to a second programming level.

4. The memory device of claim 3, wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the first subset of the plurality of memory cells is driven to a high state during a first programming verification operation corresponding to the first programming level, and wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the second subset of the plurality of memory cells is driven to a low state during the first programming verification operation.

5. The memory device of claim 4, wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the first subset of the plurality of memory cells is driven to a low state during a second programming verification operation corresponding to the second programming level, and wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the second subset of the plurality of memory cells is driven to a high state during the second programming verification operation.

6. The memory device of claim 1, wherein each of the plurality of dynamic latching circuits further comprises: A fourth switch, which is in an enable path coupled to the memory element, wherein when the fourth switch is activated, the corresponding data line bias voltage is applied to the corresponding bit line via the enable path.

7. The memory device of claim 6, wherein the fourth switch is controlled by a shared enable control signal for concurrently activating a corresponding fourth switch in each of the plurality of dynamic latching circuits.

8. A method comprising: Initiating a programming operation on a memory array of a memory device, the memory array comprising a plurality of memory cells formed at corresponding intersections of a plurality of word lines and a plurality of bit lines, the memory device comprising a page buffer circuit coupled to the memory array, the page buffer circuit comprising a plurality of dynamic latch circuits for storing values ​​representing corresponding data line bias voltages applied to the plurality of bit lines, wherein each of the plurality of dynamic latch circuits comprises a memory element, a first switch and a second switch in a load path coupled to the memory element, and a third switch in a decoding path coupled to the first switch in the load path; and This causes a shared decoder loading control signal to be applied to the third switch in the decoding path, wherein corresponding signals for different subsets of the plurality of memory units drive the loading path to selectively activate the loading path.

9. The method of claim 8, further comprising: This causes a shared load control signal to be applied to the corresponding second switch in each of the plurality of dynamic latch circuits to concurrently activate the corresponding second switch.

10. The method of claim 8, wherein the first subset of the plurality of memory cells includes one or more memory cells in the page to be programmed to a first programming level, and wherein the second subset of the plurality of memory cells includes one or more memory cells in the page to be programmed to a second programming level.

11. The method of claim 10, wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the first subset of the plurality of memory cells is driven to a high state during a first programming verification operation corresponding to the first programming level, and wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the second subset of the plurality of memory cells is driven to a low state during the first programming verification operation.

12. The method of claim 11, wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the first subset of the plurality of memory cells is driven to a low state during a second programming verification operation corresponding to the second programming level, and wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the second subset of the plurality of memory cells is driven to a high state during the second programming verification operation.

13. The method of claim 8, wherein each of the plurality of dynamic latching circuits further includes a fourth switch coupled to an enable path of the memory element, wherein when the fourth switch is activated, the corresponding data line bias voltage is applied to the corresponding bit line via the enable path.

14. The method of claim 13, further comprising: This causes a shared enable control signal to be applied to the corresponding fourth switch in each of the plurality of dynamic latch circuits to concurrently activate the corresponding fourth switch.

15. A memory device comprising: A memory array comprising multiple memory cells formed at corresponding intersections of multiple word lines and multiple bit lines; Page buffer circuitry coupled to the memory array, the page buffer circuitry including a plurality of dynamic latch circuitry to store values ​​representing corresponding data line bias voltages applied to the plurality of bit lines, wherein each of the plurality of dynamic latch circuitry includes a storage element, a first switch and a second switch in a loading path coupled to the storage element, and a third switch in a decoding path coupled to the first switch in the loading path; and Control logic, operably coupled to the memory array and the page buffer circuitry, to perform operations including: This causes a shared decoder loading control signal to be applied to the third switch in the decoding path, wherein corresponding signals for different subsets of the plurality of memory units drive the loading path to selectively activate the loading path.

16. The memory device of claim 15, wherein the control logic is configured to perform operations further including: This causes a shared load control signal to be applied to the corresponding second switch in each of the plurality of dynamic latch circuits to concurrently activate the corresponding second switch.

17. The memory device of claim 15, wherein a first subset of the plurality of memory cells includes one or more memory cells in a page to be programmed to a first programming level, and wherein a second subset of the plurality of memory cells includes one or more memory cells in a page to be programmed to a second programming level.

18. The memory device of claim 17, wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the first subset of the plurality of memory cells is driven to a high state during a first programming verification operation corresponding to the first programming level, and wherein the corresponding signal driven on the decoding path in the corresponding page buffer circuit of the second subset of the plurality of memory cells is driven to a low state during the first programming verification operation.

19. The memory device of claim 15, wherein each of the plurality of dynamic latching circuits further includes a fourth switch coupled to an enable path of the memory element, wherein when the fourth switch is activated, the corresponding data line bias voltage is applied to a corresponding bit line via the enable path.

20. The memory device of claim 19, wherein the control logic is configured to perform operations further including: This causes a shared enable control signal to be applied to the corresponding fourth switch in each of the plurality of dynamic latch circuits to concurrently activate the corresponding fourth switch.

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