Multi-step analog programming convergence of memory cells in memory device

Abstract

The invention relates to multi-step analog program convergence of memory cells in a memory device. A control logic in a memory device initiates a program operation on a memory array of the memory device, the memory array including a plurality of memory cells, and the program operation including a plurality of program pulses. The control logic further identifies a first subset of the plurality of memory cells and a second subset of the plurality of memory cells based on respective threshold voltages after applying a first program pulse of the plurality of program pulses, and boost a voltage potential in one or more pillars of the memory array corresponding to a first subset of the plurality of memory cells prior to applying a second programming pulse of the plurality of programming pulses.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to multi-step analog programming convergence of memory cells in a memory device of a memory sub-system. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which:

[0004] Figure 1A An example computing system that includes a memory sub-system in accordance with some embodiments of the present disclosure is described.

[0005] Figure 1B is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system in accordance with some embodiments of the present disclosure.

[0006] Figure 2 is a schematic diagram of a portion of an array of memory cells in a memory of the type described for reference Figure 1B to some embodiments in accordance with the present disclosure.

[0007] Figure 3 is a flow diagram of an example method of multi-step analog programming convergence of memory cells in a memory device of a memory sub-system in accordance with some embodiments of the present disclosure.

[0008] Figure 4A is a graph illustrating a programming distribution of a plurality of memory cells that are desired to be programmed to a given program level (i.e., state) in accordance with some embodiments of the present disclosure.

[0009] Figure 4B is a graph illustrating a data line bias voltage applied to different memory cells during analog programming convergence in accordance with some embodiments of the present disclosure.

[0010] Figure 5 is a flow diagram of an example method of multi-step analog programming convergence of memory cells in a memory device of a memory sub-system in accordance with some embodiments of the present disclosure.

[0011] Figure 6 is a graph illustrating various signals applied during multi-step analog programming convergence in accordance with some embodiments of the present disclosure.

[0012] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to multi-step analog programming convergence of memory cells in a memory device of a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with FIG. 1. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0014] A memory sub-system can include high-density non-volatile memory devices in which it is desirable to retain data in the absence of a supply of electrical power to the memory device. For example, NAND memory, such as 3D flash NAND memory, supplies storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die including one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and has various logical states related to the number of bits stored. The logical states can be represented by binary values such as “0” and “1” or combinations of such values.

[0015] Memory devices can be made up of bits arranged in two-dimensional or three-dimensional grids. Memory cells are formed on a silicon die in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell. A block refers below to a unit of a memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of a memory device in order to allow concurrent operations on each plane. A memory device can include circuitry to perform concurrent memory page accesses of two or more memory planes. For example, a memory device can include multiple access line driver circuits and power circuits that can be shared by the planes of the memory device to facilitate concurrent access of pages (including different page types) of two or more memory planes. For ease of description, these circuits can be referred to collectively as independent plane driver circuits. Depending on the storage architecture employed, data can be stored across memory planes (i.e., in a striped fashion). Thus, one request to read a segment of data (e.g., corresponding to one or more data addresses) can result in read operations performed on two or more memory planes of a memory device.

[0016] Programming of a memory device can be accomplished by applying one or more programming pulses separated by verify pulses to program each memory cell in a selected group of memory cells to a respective target data state (which can be an intermediate or final data state). In this approach, programming pulses are applied to access lines, such as those commonly referred to as word lines, for the selected memory cells. After each programming pulse, the programming of the selected memory cells is verified, typically using one or more verify voltage levels. Programming is typically done using many programming pulses in an incremental step pulse programming (ISPP) scheme, where each programming pulse is a single-level pulse that moves the memory cell threshold voltage by an amount.

[0017] A program pulse can be applied to a selected access line (e.g., word line) and thus to the control gates of a row of memory cells connected to the selected access line (e.g., have their control gates connected to the selected access line). A typical program pulse can start at 13V or near 13V, and its magnitude tends to increase for each subsequent program pulse application. When a program potential (e.g., the voltage level of a program pulse) is applied to a selected access line, an enable voltage, such as a reference potential (e.g., 0V), can be applied to the channels of memory cells selected for programming (i.e., those whose programming operation is intended to shift their data state to some higher level). This can cause a transfer of charge from the channels of these selected memory cells to their charge storage structures. For example, a floating gate is typically charged by direct injection of electrons from the channel to the floating gate or Fowler-Nordheim tunneling, resulting in an increase in threshold voltage in the programmed state.

[0018] During programming, an inhibit voltage (e.g., Vcc) can be applied to data lines (e.g., bit lines) selectively connected to strings of memory cells that include memory cells connected to a selected access line and not selected for programming or no longer selected for programming. In addition to data lines selectively connected to memory cells already in their target data state, these unselected data lines can further include data lines not addressed by the programming operation. For example, a logical page of data can correspond to a certain particular subset of memory cells connected to a particular access line and selectively connected to a certain particular subset of data lines (e.g., every other data line), such that the remaining subset of data lines will be unselected for the programming operation and thus inhibited.

[0019] Between the application of one or more program pulses, a verify phase of the programming operation can be performed to check each selected memory cell to determine whether it has reached the target data state. If a selected memory cell has reached the target data state, it can be inhibited from further programming in the presence of other selected memory cells that still need additional program pulses to reach their target data state. After the verify phase, an additional program pulse can be applied if there are memory cells that have not completed programming. This process of applying a program pulse followed by a verify (e.g., a program phase and a verify or sense phase of the programming operation) continues until all selected memory cells have reached their target data state. For example, if a certain number of program pulses have been applied (e.g., a maximum number), or a certain voltage level of program pulses has been reached (e.g., a maximum voltage level), and one or more selected memory cells have not completed programming, those memory cells can be flagged as defective.

[0020] In a programming scheme known as selective slow program convergence (SSPC), the use of different voltage levels on data lines that are enabled for programming can occur, where memory cells closer to their respective target data states (e.g., partially enabled for programming) are programmed more slowly (e.g., enabled for programming more fully) than memory cells further from their respective target data states, while receiving the same voltage level at their respective control gates. Relative to more traditional programming schemes that rely on memory cells being either fully enabled or inhibited from programming, the SSPC programming scheme can facilitate a narrower distribution of threshold voltages defining each data state. By narrowing the threshold voltage distribution, and thus providing more dead space or margin between adjacent threshold voltage distributions, the accuracy of determining the data state of a memory cell can be improved and / or memory density (e.g., the number of data bits per memory cell) can be increased.

[0021] While the SSPC programming scheme can provide tighter threshold voltage distributions than more traditional programming schemes, the benefit often comes at a cost. In particular, for each program pulse, the memory cells subjected to the program operation are typically assigned to different subgroups of memory cells (e.g., one subgroup of memory cells to be inhibited from programming, one subgroup of memory cells to be fully enabled for programming, and one subgroup of memory cells to be partially enabled for programming). Each subgroup of memory cells corresponds to a respective, mutually exclusive threshold voltage range. The threshold voltage of each memory cell subjected to the program operation is typically determined or estimated in order to assign it to the appropriate subgroup of memory cells. This can increase the time and / or complexity of the verify phase of the program operation.

[0022] Various methods seek to facilitate further narrowing of the threshold voltage distribution relative to typical SSPC programming schemes, while mitigating the need to assign memory cells for each partial enable level of programming. Such methods can provide data line voltage levels during a subsequent program pulse that are inversely related to their corresponding memory string current levels (e.g., I 串 ) during a verify phase of the program operation (e.g., the immediately preceding verify phase of the program operation). Control logic in the memory device can capture the retained voltage levels of the nodes of the page buffer circuit after or during the verify phase of the program operation. During the verify phase of the program operation, the nodes can be precharged and then selectively discharged through the data lines in response to the activation level of the selected memory cells of the program operation. Thus, memory cells with higher threshold voltages (e.g., lower I 串 ) in response to a given control gate voltage level) can be expected to have higher retained voltage levels than memory cells with lower threshold voltages (e.g., higher I 串The memory cells of the selected group cause a higher retention voltage level at the node. The remaining voltage level of the node can then be used as a control voltage for a source follower to generate a data line voltage level for a subsequent programming operation. As such, memory cells closer to their target threshold voltage can be expected to receive a higher data line voltage (e.g., a lower partial activation level), and memory cells further from their target threshold voltage can be expected to receive a lower data line voltage (e.g., a higher partial activation level). The result is an analog programming convergence method, where the data line voltage varies depending on the threshold voltage of the selected memory cells, rather than using a digital programming convergence method (e.g., where cells are fully activated for programming, partially activated for programming, or inhibited).

[0023] However, these analog methods have multiple drawbacks. For optimal operation, a memory device needs to generate a large range of voltages to bias the data line in order to achieve different partial activation levels during programming. However, due to the limited window of control signals including the drain side select gate device (SGD) in a memory string, the limited window of cell current (Icell) versus threshold voltage, and the variation of string current (Istring) present in 串 ) can be challenging to achieve. For example, the maximum bias voltage that can be achieved is limited by the switching window of the SGD transistor. Thus, the bias voltage needs to be low enough to be driven into the pillar, while at the same time, the inhibit bias (VCC) needs to be high enough to ensure that the pillar is turned off for boosting. Additionally, if the window of Icell versus threshold voltage or gate bias is smaller than the range of threshold voltages of interest, then the translation of Icell to bit line bias voltage cannot be achieved across the desired range. Furthermore, the variation of string current further reduces the useful Icell versus threshold voltage window.

[0024] Aspects of the present disclosure address the above and other deficiencies by implementing a multi-step analog programming convergence of memory cells in a memory device of a memory sub-system. In one embodiment, the range of data line bias voltages for analog programming convergence can be divided into two or more steps, which correspond to different groups of memory cells for which different partial activation levels are suitable. For example, one step can correspond to a first group of memory cells closer to their target threshold voltage (i.e., thus requiring a more significant data line bias), and another step can correspond to a second group of memory cells further from their target threshold voltage (i.e., thus requiring a smaller data line bias). In one embodiment, the control logic of the memory device can cause the pillars of the memory device corresponding to the memory cells in the first group to be boosted during programming to increase the data line bias of those memory cells. Thus, a larger range of data line bias voltages is available, such that more partial activation levels can be achieved during programming.

[0025] Advantages of such an approach include, but are not limited to, performance improvement of the memory sub-system. The approach described herein allows for a greater data line bias voltage range to be achieved without the need for additional voltage generating circuitry. The greater data line bias voltage range ensures that the analog programming convergence technique can be more accurately applied to memory cells that are at different distances from their target voltage, which reduces programming latency.

[0026] Figure 1A An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the present disclosure is illustrated. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination thereof.

[0027] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash memory drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an Internet of Things (IoT) capable device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including memory and a processing device.

[0029] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1A An example of a host system 120 coupled to one memory sub-system 110 is illustrated. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0030] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers, CXL controllers). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0031] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Compute Express Link (CXL) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe or CXL interface), the host system 120 can further access the memory components (e.g., the memory devices 130) using an NVM Express (NVMe) interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1A The memory sub-system 110 is illustrated as an example. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM).

[0033] Some examples of non-volatile memory devices, such as memory devices 130, include negative-and (NAND)-type flash memory and in-situ write memory, such as three-dimensional cross-point (“3D cross-point”) memory. Cross-point arrays of non-volatile memory can perform bit storage based on bulk resistance changes along with a stackable cross-grid data access array. Further, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where a non-volatile memory cell can be programmed without previously erasing the non-volatile memory cell. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC), can store multiple bits per cell. In some embodiments, each of memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device can include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of memory devices 130 can be grouped into pages, which can refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages can be grouped to form blocks.

[0035] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memory (such as 2D NAND, 3D NAND) have been described, memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0036] The memory sub-system controller 115 (or, for simplicity, the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with specialized (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory sub-system controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0038] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 has been illustrated as including the memory sub-system controller 115, in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system). Figure 1A

[0039] Generally, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations associated with the memory devices 130 such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., a logical block address (LBA), a namespace) and a physical address (e.g., a physical block address). The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions for accessing the memory devices 130, and convert responses associated with the memory devices 130 into information for the host system 120.​

[0040] Memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0041] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory devices 130 are managed memory devices, which are original memory devices 130 with control logic (e.g., local controller 135) on the die and a controller (e.g., memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory devices 130 can represent a single die with some control logic (e.g., local media controller 135) embodied thereon. In some embodiments, one or more components of memory sub-system 110 can be omitted.

[0042] In one embodiment, memory sub-system 110 includes a memory interface 113 that is responsible for handling the interaction of memory sub-system controller 115 with memory devices of memory sub-system 110, such as memory devices 130. For example, memory interface 113 can send memory access commands, such as program commands, read commands, or other commands, to memory devices 130 corresponding to requests received from host system 120. Additionally, memory interface 113 can receive data from memory devices 130, such as data retrieved in response to a read command or confirmation that a program command was successfully executed. In some embodiments, memory sub-system controller 115 includes at least a portion of memory interface 113. For example, memory sub-system controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0043] In one embodiment, the local media controller 135 of the memory device 130 includes a program convergence management component 150. The program convergence management component 150 can manage program convergence associated with memory cells in the memory array 104 of the memory device 130. For example, the program convergence management component 150 can implement multi-step analog program convergence of memory cells in the memory array 104. In one embodiment, the program convergence management component 150 can divide a range of data line bias voltages to be used for analog program convergence into two or more steps corresponding to different groups of memory cells suitable for different partial enable levels. For example, one step can correspond to a first group of memory cells closer to their target threshold voltages (i.e., thus requiring greater data line bias), and another step can correspond to a second group of memory cells further from their target threshold voltages (i.e., thus requiring less data line bias). In one embodiment, the program convergence management component 150 can cause pillars of the memory array 104 corresponding to memory cells in the first group to be boosted during programming to increase data line bias for those memory cells, such that a greater range of data line bias voltages is available, allowing more partial enable levels to be implemented during programming. Further details regarding the operation of the program convergence management component 150 are described below.

[0044] Figure 1B is a simplified block diagram of a first device in the form of a memory device 130 in communication with a second device in the form of a memory sub-system controller 115 of a memory sub-system (e.g., Figure 1A of a memory sub-system 110) in accordance with an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home electronics, vehicles, wireless devices, mobile telephones, and the like. The memory sub-system controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device. In one embodiment, the memory sub-system controller 115 includes a memory interface 113.

[0045] The memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. The memory cells of a logical row are typically connected to the same access line (e.g., word line), while the memory cells of a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. The memory cells of at least a portion of the array 104 of memory cells (not shown in Figure 1B are capable of being programmed to one of at least two target data states.

[0046] Row decode circuitry 108 and column decode circuitry 109 are provided to decode address signals. The address signals are received and decoded to access the memory cell array 104. The memory device 130 also includes input / output (I / O) control circuitry 160 to manage inputs to, and outputs from, the memory device 130, including commands, addresses, and data. The address register 114 is in communication with the I / O control circuitry 160, and the row and column decode circuitry 108, 109 to latch the address signals prior to decoding. The command register 124 is in communication with the I / O control circuitry 160 and the local media controller 135 to latch incoming commands.

[0047] The controller, such as the local media controller 135 internal to the memory device 130, controls access to the memory cell array 104 in response to commands and generates status information for the external memory subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations, such as read, program, and / or erase operations, to the memory cell array 104. The local media controller 135 is in communication with the row and column decode circuitry 108, 109 to control the row and column decode circuitry 108, 109 in response to addresses. In one embodiment, the local media controller 135 includes a program management component 150 that can implement multi-step analog program convergence of memory cells in the memory array 104, as described herein.

[0048] The local media controller 135 is also in communication with a cache register 172. The cache register 172 latches incoming or outgoing data under the direction of the local media controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data, respectively. During a program operation, such as a write operation, data can be transferred from the cache register 172 to the data register 170 for transfer to the memory cell array 104; then, new data can be latched from the I / O control circuitry 160 into the cache register 172. During a read operation, data can be transferred from the cache register 172 to the I / O control circuitry 160 for output to the memory subsystem controller 115; then, new data can be transferred from the data register 170 to the cache register 172. The cache register 172 and / or the data register 170 can form a page buffer of the memory device 130, such as can form a portion of a page buffer. The page buffer can further include a sensing device to sense data states of memory cells connected to the memory cell array 104, such as by sensing a state of a data line of the memory cells. Figure 1BThe status register 122 can communicate with the I / O control circuitry 160 and the local memory controller 135 to latch status information for output to the memory sub-system controller 115.

[0049] The memory device 130 receives control signals at the local media controller 135 from the memory sub-system controller 115 over the control link 182. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be received over the control link 182 depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller 115 over a multiplexed input / output (I / O) bus 184 and outputs data to the memory sub-system controller 115 over the I / O bus 184.

[0050] For example, a command can be received at the I / O control circuitry 160 over input / output (I / O) pins [7:0] of the I / O bus 184 and then can be written into the command register 124. An address can be received at the I / O control circuitry 160 over input / output (I / O) pins [7:0] of the I / O bus 184 and then, can be written into the address register 114. Data can be received at the I / O control circuitry 160 over input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices and then, can be written into the cache register 172. The data can then be written into the data register 170 for programming the memory cell array 104.

[0051] In an embodiment, the cache register 172 can be omitted and data can be written directly into the data register 170. Data can also be output over input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although reference can be made to I / O pins, these can include any electrically conductive node, such as a conductive pad or a conductive bump, as commonly used, that provides an electrical connection from an external device, such as the memory sub-system controller 115, to the memory device 130.

[0052] It will be appreciated by those skilled in the art that additional circuitry and signals can be provided, and that the memory device 130 has been simplified Figure 1B It will be appreciated that reference has been made to Figure 1BThe functionality described for various block components can not necessarily be separated into different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device can be adapted to perform the functionality of more than one block component described Figure 1B . Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform the functionality of a single block component described Figure 1B . In addition, while specific I / O pins are described in terms of popular convention for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) can be used in various embodiments.

[0053] Figure 2 is a schematic diagram of a portion of a memory cell array 104 (e.g., a NAND memory array) in a memory such as can be used for reference Figure 1B described in accordance with embodiments. The memory array 104 includes access lines (e.g., word lines 2020 through 202 N ) and data lines (e.g., bit lines 2040 through 204 M ). The word lines 202 can be connected to global access lines (e.g., global word lines) not shown in Figure 2 . For some embodiments, the memory array 104 can be formed on a semiconductor, e.g., the semiconductor can be conductively doped to have one conductivity type, e.g., to have p-type conductivity to form, e.g., a p-well, or to have n-type conductivity to form, e.g., an n-well.

[0054] The memory array 104 can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can include a string of series-connected memory cells (e.g., non-volatile memory cells), such as one of the NAND strings 2060 through 206 M . Each NAND string 206 can be connected (e.g., selectively connected) to a common source (SRC) 216 and can include memory cells 2080 through 208 N . The memory cells 208 can represent non-volatile memory cells for data storage. The memory cells 208 of each NAND string 206 can be connected in series between a select gate 210 (e.g., a field effect transistor), such as one of the select gates 2100 through 210 M (e.g., which can be a source select transistor, commonly referred to as a select gate source), and a select gate 212 (e.g., a field effect transistor), such as one of the select gates 2120 through 212 M (e.g., which can be a drain select transistor, commonly referred to as a select gate drain). The select gates 2100 through 210 M may be commonly connected to a select line 21, e.g., a source select line (SGS), and the select gates 2120 through 212 MThe common source 216 can be connected to a select line 214, such as a word line (WLn). The common source 216 can be connected to a select line 215, such as a drain select line (SGD). Although depicted as conventional field effect transistors, the select gates 210 and 212 can utilize structures similar to (e.g., the same as) the memory cells 208. The select gates 210 and 212 can represent several select gates connected in series, where each select gate in series is configured to receive the same or independent control signals.

[0055] The drain of each select gate 210 can be connected to a memory cell 2080 of a corresponding NAND string 2060. For example, the drain of select gate 2100 can be connected to memory cell 2080 of corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0056] The drain of each select gate 212 can be connected to a bit line 204 of a corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 of corresponding NAND string 2060. The source of each select gate 212 can be connected to a memory cell 208 N of a corresponding NAND string 206. For example, the source of select gate 2120 can be connected to memory cell 208 N of corresponding NAND string 2060. Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0057] Figure 2 The memory array 104 in FIG. 1 can be a quasi-two-dimensional memory array and can have a substantially planar structure, e.g., where the common sources 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2 The memory array 104 in FIG. 1 can be a three-dimensional memory array, e.g., where the NAND strings 206 can extend substantially perpendicular to a plane containing the common sources 216 and a plane containing the bit lines 204 can extend substantially parallel to the plane containing the common sources 216.

[0058] A typical construction of a memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine a data state of the memory cell (e.g., by a change in threshold voltage), and a control gate 236, as Figure 2The data storage structure 234 can include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 can further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases formed by) a word line 202.

[0059] A column of memory cells 208 can be a NAND string 206 or several NAND strings 206 selectively connected to a given bit line 204. A row of memory cells 208 can be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 can, but need not, include all memory cells 208 commonly connected to a given word line 202. Multiple rows of memory cells 208 can generally be divided into one or more physical page groups of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 commonly connected to a given word line 202. For example, memory cells 208 commonly connected to a word line 202 N and selectively connected to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be one physical page of memory cells 208 (e.g., even memory cells), while memory cells 208 commonly connected to a word line 202 N and selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cells 208 (e.g., odd memory cells).

[0060] Although not explicitly depicted in Figure 2 FIG. 1, it is readily apparent from the figure that the bit lines 204 of the memory cell array 104 can be numbered consecutively from bit line 2040 to bit line 204 M . Other groupings of memory cells 208 commonly connected to a given word line 202 can also define physical pages of memory cells 208. For a particular memory device, all memory cells commonly connected to a given word line can be considered a physical page of memory cells. A portion of a physical page of memory cells read during a single read operation or programmed during a single program operation (which can still be an entire row in some embodiments) (e.g., an upper page or a lower page of memory cells) can be considered a logical page of memory cells. A block of memory cells can include those memory cells configured to be erased together, such as all memory cells connected to word lines 2020 to 202 N . Unless explicitly distinguished, references herein to memory cell pages refer to memory cells of logical pages of memory cells. Although Figure 2Examples are discussed in connection with NAND flash memory, but the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0061] Figure 3 is an example method of multi-step analog programming convergence of memory cells in a memory device of a memory sub-system according to some embodiments of the present disclosure. The method 300 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by the programming convergence management component 150. Figure 1A and Figure 1B are performed by the programming convergence management component 150. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0062] At operation 305, a program operation is initiated. For example, processing logic (e.g., the programming convergence management component 150) can initiate a program operation on a memory array, the program operation comprising a plurality of program pulses. In one embodiment, each of the program pulses is separated by a verify pulse and is applied to an access line (e.g., word line) associated with a selected memory cell to program the selected memory cell to a respective target data state. After each program pulse, the programming of the selected memory cells is typically verified using one or more verify voltage levels. Programming typically uses many program pulses in an incremental step- pulse programming (ISPP) scheme, where each program pulse is a single-level pulse that moves the memory cell threshold voltage by an amount.

[0063] At operation 310, a subset of memory cells is identified. For example, processing logic identifies a first subset of the plurality of memory cells and a second subset of the plurality of memory cells based on respective threshold voltages after applying a first program pulse of the plurality of program pulses. In one embodiment, after each program pulse is applied, a program verify pulse can be applied to determine a respective threshold voltage of each memory cell associated with a given word line. The programming convergence management component 150 can compare the respective threshold voltage to a plurality of thresholds, such as a program verify (PV) threshold that can represent a target voltage to which the memory cell is intended to be programmed and a pre-program verify (PPV) threshold that can be a voltage level lower than the program verify threshold by an amount. Examples of these subsets are discussed in Figure 4AThe middle illustration. Figure 4A is an illustration of a programming distribution of a plurality of memory cells that are desirous of being programmed to a given program level (i.e., state) according to some embodiments of the disclosure. After a previous program pulse is applied, a certain number of memory cells in the distribution can have reached a threshold voltage that is greater than or equal to a program verify (PV) threshold, and thus do not require further programming. The processing logic can identify a first subset of memory cells that have a threshold voltage that is less than the program verify (PV) threshold but greater than a pre-program verify (PPV) threshold. In Figure 4A , this first subset can include memory cells in the range labeled "ASSPC1." The processing logic can identify a second subset of memory cells that have a threshold voltage that is less than the pre-program verify (PPV) threshold. In Figure 4A , this second subset can include memory cells in the range labeled "ASSPC2." In other embodiments, there can be some other number of subsets and / or different or additional criteria can be used to identify subsets of memory cells. The Icell vs. threshold voltage (VT) curve represents the cell current drawn by the string in response to a gate bias (e.g., PPV or PV). For example, if a cell has a VT location at the PV threshold, then Icell will be low. As this cell VT moves down, the corresponding cell current will increase in some relationship to the VT.

[0064] Referring again to Figure 3 , at operation 315, the column voltage potential is boosted. For example, prior to applying a second program pulse of the plurality of program pulses, the processing logic boosts the voltage potential in one or more columns of the memory array corresponding to the first subset of the plurality of memory cells. Boosting the voltage in the column corresponding to the first subset of the plurality of memory cells (i.e., those memory cells closer to the target program voltage) will increase the effective data line bias voltage (Vaaspc) of the first subset of the plurality of memory cells, as Figure 4B illustrated in the middle illustration. Figure 4B is an illustration of a data line bias voltage applied to different memory cells during analog program convergence according to some embodiments of the disclosure. In one embodiment, the voltage supply in the memory sub-system 110 can be configured to provide a range of data line bias voltages (Vasspc) for memory cells having a threshold voltage (VT) that falls within the Vasspc2 range. To increase the effective data line bias voltage of those memory cells having a threshold voltage (VT) that falls within the Vasspc1 range, the program convergence management component 150 boosts the voltage potential in the corresponding column, as described in more detail below with respect to operation 500 of Figure 5 .

[0065] Referring again to Figure 3At operation 320, a program pulse is applied. For example, the processing logic causes a second program pulse to be applied to the memory array 104. When the second program pulse is applied to the selected word line, the partial program enable level can be controlled by a difference in the bit line bias voltage applied to different memory cells, including a higher bit line bias voltage applied to those memory cells within the range of Vasspcl. Thus, memory cells closer to their target threshold voltage can receive a higher data line bias voltage (e.g., a lower partial enable level) and thus will be programmed more "slowly," and memory cells further from their target threshold voltage can receive a lower data line bias voltage (e.g., a higher partial enable level) and thus will be programmed less "slowly."

[0066] Figure 5 FIG. 5 is a flow diagram of an example method of multi-step analog program convergence of memory cells in a memory device of a memory sub-system, according to some embodiments of the present disclosure. The method 500 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by the program convergence management component 150 of the memory sub-system 100. Figure 1A and Figure 1B of the memory sub-system 100. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0067] At operation 505, a program pulse is applied. For example, processing logic (e.g., the program convergence management component 150) can cause a first program pulse of a plurality of program pulses associated with a program operation to be applied to a memory array 104 of a memory device (e.g., the memory device 130). In one embodiment, the first program pulse is applied to a selected word line of the memory array 104 associated with one or more memory cells to be programmed to certain program levels (e.g., states).

[0068] At operation 510, a verify phase of the program operation is initiated. For example, the processing logic can initiate a verify phase of the program operation after applying the first program pulse to determine respective threshold voltages of the plurality of memory cells. In one embodiment, after each program pulse is applied, a program verify pulse can be applied to determine a respective threshold voltage of each memory cell associated with the selected word line.

[0069] At operation 515, a comparison is performed. For example, the processing logic can compare the respective threshold voltage to a program verify (PV) threshold level and a pre-program verify (PPV) threshold level. As Figure 4A explained in FIG. 1, the processing logic can identify a first subset of memory cells in the range labeled "ASSPC1" that have a threshold voltage less than the program verify (PV) threshold but greater than the pre-program verify (PPV) threshold. The processing logic can further identify a second subset of memory cells in the range labeled "ASSPC2" that have a threshold voltage less than the pre-program verify (PPV) threshold.

[0070] At operation 520, a data line bias voltage is applied. For example, the processing logic can cause a data line bias voltage to be applied to a plurality of respective bit lines corresponding to a plurality of memory cells. This data line bias voltage (Vasspc) can be any of a plurality of voltage magnitudes that can be produced by a voltage source in the memory sub-system 110. In one embodiment, the data line bias voltage applied to the data lines corresponding to the first subset of memory cells (i.e., BL1 and denoted by VASSPC1) and the data line bias voltage applied to the data lines corresponding to the second subset of memory cells (i.e., BL2 and denoted by VASSPC2) initially have the same magnitude, as shown in Figure 6 Figure 6 is a graph illustrating various signals applied during multi-step analog programming convergence according to some embodiments of the present disclosure. It should be noted that in Figure 6 , the signals BL1 and BL2 and the corresponding active data line bias voltage levels VASSPC1 and VASSPC2 are illustrated as gradient bars to indicate that the actual data line bias voltage corresponding to each individual memory cell can be any voltage magnitude within a certain range, and the data line bias voltage applied to different memory cells can vary according to the analog nature of the algorithm (e.g., based on different cell currents (Icell)). In one embodiment, the processing logic performs a current integration of Icell onto a capacitor. This capacitor can initially be pre-charged to a certain level, and then discharged with a current equal to Icell for a certain time interval. After that, the discharge voltage on the capacitor is proportional to Icell. Thus, for cells with low Icell, this capacitor voltage is higher, while cells with high Icell have a lower capacitor voltage. The voltage is then transferred to the gate of a source follower driver, which drives this bias onto the bit line during the program pulse phase, where the bias is inversely proportional to Icell.

[0071] Referring again to Figure 5 , at operation 525, a voltage signal is applied to a word line. For example, the processing logic can cause a voltage signal to be applied to a word line (i.e., a selected word line) associated with a plurality of memory cells, the voltage signal having an intermediate magnitude. As Figure 6 ​As shown, voltage signal 602 can ramp up from a low voltage (e.g., 0V) to an intermediate voltage, which can be represented by subtracting the boost step from the voltage (Vpass). The boost step is a configurable amount that can vary depending on the implementation.

[0072] In operation 530, the selector gate device is disabled. For example, the processing logic may disable the corresponding selector gate devices (e.g., selectors 2120 to 212) on the drain side of one or more pillars. M One or more of the data lines are deactivated. The selector can be deactivated via the control signal SGD (i.e., by driving the SGD signal low for a period of time). Deactivating the selector disconnects the pin from the corresponding data line (e.g., a bit line), causing the pin to float.

[0073] In operation 535, the voltage signal is increased. For example, the processing logic can cause the voltage signal 602 applied to the select word line to ramp up to a pass voltage value (Vpass). As described above, the pass voltage value is a boost step larger than the intermediate value. The increased value of voltage signal 602 will boost the voltage potential in each pillar of the memory array, including the voltage potential in those pillars corresponding to the memory cells in both the Vasspc1 and Vasspc2 ranges. Figure 6 This is illustrated by the effective data line bias voltage VASSPC1 being boosted to a higher value (i.e., "pillar boost step"). It should be noted that the effective data line bias voltage VASSPC2 is also boosted to a higher value, although only temporarily and will be reduced, as described in more detail below.

[0074] In operation 540, the bit lines are biased. For example, the processing logic can cause the first subgroup of multiple bit lines associated with the first subgroup of multiple memory cells (i.e., cells within the Vasspc1 range) to be driven with a high voltage. This is in Figure 6 This is illustrated by signal BL1 being driven high (i.e., to a value greater than its previous data line bias voltage). Additionally, the processing logic can cause the second subgroup of multiple bit lines associated with the second subgroup of multiple memory cells (i.e., cells within the Vasspc2 range) to be driven using the original data line bias voltage. This is in... Figure 6 This is illustrated by maintaining the same level for signal BL2.

[0075] At operation 545, the select gate device is enabled. For example, the processing logic can cause the respective select gate device to be re-enabled. The select gate device can be enabled via the control signal SGD (i.e., by driving the SGD signal high again). Once the select gate device is re-enabled, the active data line bias voltage (VASSPC2) of the second subset of memory cells is driven back to the original magnitude because the signal BL2 remains unchanged. However, the active data line bias voltage (VASSPC1) of the first subset of memory cells remains at the boosted potential level because the signal BL1 is driven high. When the select gate is re-enabled, BL2 is re-driven into the column to restore the column potential represented by "VASSPC2" to the originally intended target after boosting. The signal BL1 is driven high in order to cut off the column intended for the "VASSPC2" level. Thus, the column remains at the boosted potential when SGD is re-enabled. This requires careful control of the boost_step, SGD bias, BL1, and BL2 levels to ensure that the boosted potential of VASSPC1 can be preserved while being able to drive VASSPC2 at the same time. Thus, a higher range of active data line bias voltage can be used for those memory cells with threshold voltages (VT) that fall within the Vasspc1 range, as Figure 4B explained in the

[0076] At operation 550, a program pulse is applied. For example, the processing logic can cause the voltage signal 602 applied to the word line to ramp up to a program voltage magnitude corresponding to a second program pulse. When the second program pulse is applied to the selected word line, the partial program enable level can be controlled by the difference in bit line bias voltage applied to different memory cells, including the higher active bit line bias voltage applied to those memory cells within the Vasspc1 range. Thus, memory cells closer to their target threshold voltage can receive a higher data line bias voltage (e.g., a lower partial enable level) and therefore will be programmed more "slowly," and memory cells further from their target threshold voltage can receive a lower data line bias voltage (e.g., a higher partial enable level) and therefore will be programmed less "slowly."

[0077] Figure 7 An example machine of a computer system 700 is illustrated in FIG. 7, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein can be executed. In some embodiments, the computer system 700 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1), or can be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to the controller 120 of FIG. 1). Figure 1A Figure 1A Figure 1A ​​The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a

[0078] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a

[0079] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0080] Processing device 702 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 702 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate over the network 720.

[0081] The data storage system 718 can include a machine-readable storage medium 724 (also known as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 can also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and / or main memory 704 can correspond to memory subsystem 110 of FIG. 1. Figure 1A

[0082] In one embodiment, the instructions 726 include instructions to implement functionality corresponding to the program convergence management component 150 of FIG. 1. While the machine-readable storage medium 724 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media. Figure 1A

[0083] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These

[0084] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0085] ​​The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as follows without departing from the scope of the present disclosure. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0087] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as a read only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0088] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory device comprising: a memory array comprising a plurality of memory cells; and control logic operably coupled with the memory array, the control logic to perform operations comprising: initiating a program operation on the memory array, the program operation comprising a plurality of program pulses; identifying, after application of a first program pulse of the plurality of program pulses, a first subset of the plurality of memory cells based on respective threshold voltages and a second subset of the plurality of memory cells based on the respective threshold voltages; and boosting a voltage potential in one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells prior to application of a second program pulse of the plurality of program pulses.

2. The memory device of claim 1, wherein identifying the first subset of the plurality of memory cells and the second subset of the plurality of memory cells comprises initiating a verify phase of the program operation to determine the respective threshold voltages and comparing the respective threshold voltages to a program verify threshold level and a pre-program verify threshold level.

3. The memory device of claim 2, wherein the first subset of the plurality of memory cells have respective threshold voltages less than the program verify threshold level but greater than the pre-program verify threshold level, and wherein the second subset of the plurality of memory cells have respective threshold voltages less than the pre-program verify threshold level.

4. The memory device of claim 1, wherein the control logic to perform operations further comprising: causing a data line bias voltage to be applied to a plurality of respective bit lines corresponding to the plurality of memory cells, wherein boosting the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells increases an effective data line bias voltage for the first subset of the plurality of memory cells.

5. The memory device of claim 4, wherein boosting the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells comprises: causing a voltage signal to be applied to a word line associated with the plurality of memory cells, the voltage signal having an intermediate magnitude; and causing respective select gate devices at a drain side of the one or more pillars to be disabled.

6. The memory device of claim 5, wherein boosting the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells further comprises: ramping up the voltage signal applied to the word line to a pass voltage magnitude; causing a first subset of the plurality of bit lines associated with the first subset of the plurality of memory cells to be driven with a high voltage, wherein the high voltage is greater than the data line bias voltage, and causing a second subset of the plurality of bit lines associated with the second subset of the plurality of memory cells to be driven with the data line bias voltage; and causing the respective select gate devices to be re-enabled. ​ 7. The memory device of claim 6, wherein the control logic is to perform operations further comprising: ramping up the voltage signal applied to the word line to a program voltage magnitude corresponding to the second program pulse, wherein the active data line bias voltage of the plurality of respective bit lines is to control a respective level of partial enablement of programming the plurality of memory cells.

8. A method comprising: initiating a program operation on a memory array of a memory device, the memory array comprising a plurality of memory cells, and the program operation comprising a plurality of program pulses; identifying, based on respective threshold voltages, a first subset of the plurality of memory cells and a second subset of the plurality of memory cells after applying a first program pulse of the plurality of program pulses; and boosting a voltage potential in one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells prior to applying a second program pulse of the plurality of program pulses.

9. The method of claim 8, wherein identifying the first subset of the plurality of memory cells and the second subset of the plurality of memory cells comprises initiating a verify phase of the program operation to determine the respective threshold voltages, and comparing the respective threshold voltages to a program verify threshold level and a pre-program verify threshold level.

10. The method of claim 9, wherein the first subset of the plurality of memory cells has respective threshold voltages less than the program verify threshold level but greater than the pre-program verify threshold level, and wherein the second subset of the plurality of memory cells has respective threshold voltages less than the pre-program verify threshold level.

11. The method of claim 8, further comprising: causing a data line bias voltage to be applied to a plurality of respective bit lines corresponding to the plurality of memory cells, wherein boosting the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells increases an active data line bias voltage for the first subset of the plurality of memory cells.

12. The method of claim 11, wherein boosting the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells comprises: causing a voltage signal to be applied to a word line associated with the plurality of memory cells, the voltage signal having an intermediate magnitude; and causing respective select gate devices at a drain side of the one or more pillars to be disabled.

13. The method of claim 12, wherein boosting the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells further comprises: ramping up the voltage signal applied to the word line to a pass voltage magnitude; driving a first subset of the plurality of bit lines associated with the first subset of the plurality of memory cells with a high voltage, wherein the high voltage is greater than the data line bias voltage, and driving a second subset of the plurality of bit lines associated with the second subset of the plurality of memory cells with the data line bias voltage; and re-enabling the respective select gate devices.

14. The method of claim 13, further comprising: ramping up the voltage signal applied to the word line to a program voltage magnitude corresponding to the second program pulse, wherein the active data line bias voltage of the respective plurality of bit lines is used to control a respective level of partial enablement of programming the plurality of memory cells.

15. A non-transitory computer-readable storage medium storing instructions that, when executed by a processing device, cause the processing device to perform operations comprising: initiating a program operation on a memory array of a memory device, the memory array comprising a plurality of memory cells, and the program operation comprising a plurality of program pulses; identifying, based on respective threshold voltages, a first subset of the plurality of memory cells and a second subset of the plurality of memory cells after applying a first program pulse of the plurality of program pulses; and boosting, prior to applying a second program pulse of the plurality of program pulses, a voltage potential in one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells.

16. The non-transitory computer-readable storage medium of claim 15, wherein identifying the first subset of the plurality of memory cells and the second subset of the plurality of memory cells comprises initiating a verify phase of the program operation to determine the respective threshold voltages, and comparing the respective threshold voltages to a program verify threshold level and a pre-program verify threshold level.

17. The non-transitory computer-readable storage medium of claim 16, wherein the first subset of the plurality of memory cells has respective threshold voltages less than the program verify threshold level but greater than the pre-program verify threshold level, and wherein the second subset of the plurality of memory cells has respective threshold voltages less than the pre-program verify threshold level.

18. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing device to perform operations further comprising: applying a data line bias voltage to a respective plurality of bit lines corresponding to the plurality of memory cells, wherein boosting the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells increases an active data line bias voltage for the first subset of the plurality of memory cells.

19. The non-transitory computer-readable storage medium of claim 18, wherein boosting the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells comprises: causing a voltage signal to be applied to a word line associated with the plurality of memory cells, the voltage signal having an intermediate magnitude; and causing respective select gate devices at a drain side of the one or more pillars to be disabled.

20. The non-transitory computer-readable storage medium of claim 19, wherein causing the voltage potential in the one or more pillars of the memory array corresponding to the first subset of the plurality of memory cells to be boosted further comprises: causing the voltage signal applied to the word line to ramp up to a pass voltage magnitude; causing a first subset of the plurality of bit lines associated with the first subset of the plurality of memory cells to be driven with a high voltage, wherein the high voltage is greater than the data line bias voltage, and causing a second subset of the plurality of bit lines associated with the second subset of the plurality of memory cells to be driven with the data line bias voltage; causing the respective select gate devices to be re-enabled; and causing the voltage signal applied to the word line to ramp up to a program voltage magnitude corresponding to the second program pulse, wherein the active data line bias voltage of the plurality of respective bit lines is used to control a respective level of partial enable for programming the plurality of memory cells.

21. The non-transitory computer-readable storage medium of claim 20, wherein causing the voltage signal applied to the word line to ramp up to the program voltage magnitude further comprises: causing the voltage signal applied to the word line to ramp up to the program voltage magnitude at a rate that is slower than a rate at which the voltage signal is ramped up to the pass voltage magnitude.

22. The non-transitory computer-readable storage medium of claim 20, wherein causing the voltage signal applied to the word line to ramp up to the program voltage magnitude further comprises: causing the voltage signal applied to the word line to ramp up to the program voltage magnitude at a rate that is faster than a rate at which the voltage signal is ramped up to the pass voltage magnitude.

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