A method for fabricating an LDMOS device and the LDMOS device itself.

Abstract

This application discloses a method for fabricating an LDMOS device and an LDMOS device. The method for fabricating an LDMOS device includes: providing a semiconductor layer, the semiconductor layer including a first region for forming a body region and a second region for forming a drift region, the second region including a first sub-region, a second sub-region, and a third sub-region in sequence from the direction close to the first region to the direction far from the first region; forming a body region in the first region, forming a first drift region in the first sub-region of the second region, forming a second drift region in the second sub-region of the second region, and forming a third drift region in the third sub-region of the second region; forming a source region in the body region and a drain region in the drift region; forming a gate dielectric and a gate conductor on the surface of the semiconductor layer between the source region and the drain region; wherein the doping concentration of the first drift region and the third drift region is greater than the doping concentration of the second drift region.

Description

Technical Field

[0001] This invention relates to the field of LDMOS device technology, and in particular to a method for fabricating an LDMOS device and an LDMOS device. Background Technology

[0002] There are two main types of DMOS (Double-diffused MOSFET) devices: VDMOSFET (vertical double-diffused MOSFET) devices and LDMOSFET (lateral double-diffused MOSFET) devices. LDMOS devices are widely used due to their greater compatibility with CMOS processes, offering advantages such as thermal stability, frequency stability, higher gain, higher durability, lower noise, lower feedback capacitance, and simpler bias circuitry.

[0003] For LDMOS devices, the thickness of the epitaxial layer, the doping concentration, and the length of the drift region are the most important characteristic parameters. However, high breakdown voltage requires a thick, lightly doped epitaxial layer and a long drift region, while low on-resistance requires a thin, heavily doped epitaxial layer and a short drift region. Therefore, how to improve the high voltage withstand capability of the source and drain while maintaining a low source and drain on-resistance is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a method for fabricating an LDMOS device and an LDMOS device, which improves the breakdown voltage of the LDMOS device while enabling the LDMOS device to have a large on-current.

[0005] According to one aspect of the present invention, a method for fabricating an LDMOS device is provided, comprising: providing a semiconductor layer, the semiconductor layer including a first region for forming a body region and a second region for forming a drift region, the second region including a first sub-region, a second sub-region, and a third sub-region sequentially from the direction close to the first region to the direction far from the first region; forming a body region in the first region, forming a first drift region in the first sub-region of the second region, forming a second drift region in the second sub-region of the second region, and forming a third drift region in the third sub-region of the second region; forming a source region in the body region and a drain region in the drift region; forming a gate dielectric and a gate conductor on the surface of the semiconductor layer between the source region and the drain region; wherein the doping concentration of the first drift region and the third drift region is greater than the doping concentration of the second drift region.

[0006] Optionally, the method for forming the first drift region, the second drift region, and the third drift region includes: forming a patterned mask layer on the surface of the semiconductor layer, the patterned mask layer covering the surface of the second sub-region and exposing the surfaces of the first sub-region and the third sub-region; forming diffusion channels at the junction of the first sub-region and the second sub-region and at the junction of the third sub-region and the second sub-region via the patterned mask layer; forming the first drift region in the first sub-region and the third drift region in the third sub-region; and diffusing dopants from the first sub-region and the third sub-region to the second sub-region via the diffusion channels to form the second drift region in the second sub-region.

[0007] Optionally, ion implantation is performed at the junction of the first sub-region and the second sub-region, and at the junction of the third sub-region and the second sub-region, to form defects at the junction of the first sub-region and the second sub-region, which constitute diffusion channels from the first sub-region to the second sub-region and from the third sub-region to the second sub-region.

[0008] Optionally, H is injected into the boundary between the first and second sub-regions and the boundary between the third and second sub-regions. + .

[0009] Optionally, by adjusting the angle of ion implantation, ions are implanted at the boundary between the first sub-region and the second sub-region, and at the boundary between the third sub-region and the second sub-region, and diffusion channels are formed at the boundary between the first sub-region and the second sub-region, and at the boundary between the third sub-region and the second sub-region.

[0010] Optionally, high-temperature annealing is used to allow the dopants in the first and third sub-regions to diffuse into the second sub-region via diffusion channels, forming a second drift region in the second sub-region.

[0011] Alternatively, the annealing process can be carried out in a vacuum or inert gas environment.

[0012] Optionally, before forming the drift zone, the step of forming a shallow trench isolation structure in the second sub-region is also included.

[0013] Optionally, the shallow trench isolation structure has a depth of 0.2~0.8 μm and a lateral dimension of 0.04 μm~0.40 μm.

[0014] According to another aspect of the present invention, an LDMOS device is provided, which is formed using the method described above.

[0015] The unexpected technical effect of this application is:

[0016] In this embodiment, the doping concentration of the second drift region is lower, resulting in a higher resistance and improved breakdown voltage of the device. The doping concentrations of the first and third drift regions are higher than that of the second drift region, making their on-resistance lower than that of the second drift region. This reduces the overall on-resistance of the LDMOS device, leading to a larger on-current. Therefore, while increasing the breakdown voltage of the LDMOS device, it also provides a larger on-current, which is beneficial for improving the electrical performance of the semiconductor structure.

[0017] In this embodiment, by setting the doping concentration of the drift region to a high-low-high distribution, the electric field of the first drift region and the third drift region is reduced. At the same time, a new electric field peak is introduced in the second drift region, which increases the electric field of the second drift region and improves the surface electric field distribution.

[0018] This application forms diffusion channels at the junction of the first and second sub-regions and at the junction of the third and second sub-regions. These diffusion channels enhance the diffusion of dopants from the first and third drift regions into the second sub-region, preventing a non-conductive situation from occurring in the center of the second sub-region due to the absence of dopants when the width of the second sub-region is large.

[0019] Furthermore, in a preferred embodiment, hydrogen ions are injected into the boundary between the first and second sub-regions and the boundary between the third and second sub-regions to form diffusion channels. Annealing the silicon wafer at a high temperature promotes the escape of hydrogen ions from the silicon lattice.

[0020] In one embodiment, the annealing process is performed in a vacuum environment to further improve the hydrogen ion removal efficiency. Vacuum conditions reduce the interaction between hydrogen and ambient gas molecules, thereby accelerating the diffusion and escape of hydrogen.

[0021] In one embodiment, to prevent the silicon wafer from oxidizing at high temperatures, annealing can be performed under the protection of an inert gas (such as argon, Ar). This not only helps maintain the surface quality of the silicon wafer but also effectively promotes hydrogen removal.

[0022] In one embodiment, annealing is performed using Rapid Thermal Processing (RTP), a technique that rapidly heats and cools to achieve high temperatures in a short time, effectively activating hydrogen atoms and causing them to escape from the silicon wafer. The advantages of RTP include precise temperature and time control, reduced thermal budget, and suitability for heat-sensitive devices. Attached Figure Description

[0023] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 A schematic cross-sectional view of a conventional LDMOS device is shown;

[0025] Figure 2 A schematic cross-sectional view of an LDMOS device according to an embodiment of this application is shown;

[0026] Figure 3 A flowchart illustrating the fabrication method of the LDMOS device provided in the embodiments of this application is shown;

[0027] Figures 4a to 4i Schematic cross-sectional views of various stages in the manufacturing process of the LDMOS device provided in this application embodiment are shown, wherein:

[0028] Figure 4a A schematic cross-sectional view of the semiconductor layer of this application is shown;

[0029] Figure 4b A schematic cross-sectional view of the first region forming a body region in the semiconductor layer of this application is shown;

[0030] Figure 4c A schematic cross-sectional view of the shallow trench isolation structure formed in the second sub-region of the second region of this application is shown;

[0031] Figure 4d This invention illustrates a schematic cross-sectional view of a patterned mask layer formed on the surface of a semiconductor layer.

[0032] Figure 4e A schematic cross-sectional view showing the diffusion channel formed in this application is shown;

[0033] Figure 4f This illustration shows a schematic cross-sectional view of the first drift region formed in the first sub-region and the third drift region formed in the third sub-region of this application.

[0034] Figure 4g A schematic cross-sectional view showing the formation of a second drift zone in the second sub-region is shown;

[0035] Figure 4h A schematic cross-sectional view showing a source region formed in the volume region and a drain region formed in the drift region is shown.

[0036] Figure 4i A schematic cross-sectional view showing the formation of the gate dielectric and gate conductor in this application is shown. Detailed Implementation

[0037] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0038] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0039] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0040] Unless otherwise specified below, the various parts of an LDMOS device may be made of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), group IV-IV semiconductors such as silicon carbide (SiC), group II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and group IV semiconductors such as silicon (Si) and germanium (Ge). The gate conductor may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, and PtSi. x The gate dielectric can be composed of Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric can be made of SiO2 or materials with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0041] This application may be presented in various forms, some of which will be described below.

[0042] Figure 1 A schematic cross-sectional view of a conventional LDMOS device is shown. (e.g.) Figure 1As shown, the LDMOS device includes a semiconductor layer 101, a body region 102 and a drift region 103 located in the semiconductor layer 101, a source region 104 located in the body region 102, a drain region 105 located in the drift region 103, and a gate structure on the surface of the semiconductor layer 101 between the source region 104 and the drain region 105. The gate structure includes a gate dielectric 107 located on the surface of the semiconductor layer 101 and a gate conductor 108 located on the gate dielectric 107. The gate conductor 108 is isolated from the semiconductor layer 101 via the gate dielectric 107.

[0043] For LDMOS devices, the doping concentration of the drift region 103 is typically reduced to achieve a higher breakdown voltage. However, reducing the doping concentration of the drift region 103 increases the on-resistance Ron of the device.

[0044] Furthermore, under normal circumstances, the drift region 103 has the same doping concentration. The electric field on both sides of the drift region 103 (including the side of the drift region 103 near the body region 102 and the side of the drift region 103 near the drain region 105) is greater than the electric field in the middle of the drift region 103, and reaches a minimum in the central part of the drift region 103. Clearly, the electric field distribution throughout the drift region 103 is severely non-uniform.

[0045] In view of this, embodiments of this application provide an LDMOS device and its fabrication method, which introduces a new electric field peak in the middle of the drift region by setting the doping concentration of the drift region to a step change, thereby improving the electric field in the middle of the drift region, improving the surface electric field distribution, and increasing the breakdown voltage.

[0046] Figure 2 A schematic cross-sectional view of an LDMOS device according to an embodiment of this application is shown; as follows: Figure 2 As shown, the LDMOS device includes a semiconductor layer 101, a body region 102 and a drift region 103 located in the semiconductor layer 101, a source region 104 located in the body region 102, a drain region 105 located in the drift region 103, and a gate structure located between the source region 104 and the drain region 105.

[0047] Semiconductor layer 101 can be selected from any combination of a semiconductor substrate, a doped epitaxial semiconductor layer, or a combination thereof. Semiconductor layer 101 has a first doping type. It is worth noting that when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In), or combinations thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. In this embodiment, an example is given where the first doping type is P-type and the second doping type is N-type. Semiconductor layer 101 is, for example, P-type doped.

[0048] Body region 102 and drift region 103 extend from the surface of semiconductor layer 101 toward its interior, and body region 102 and drift region 103 are adjacent to each other. Body region 102 has a first doping type (e.g., P-type doping), and drift region 103 has a second doping type (e.g., N-type doping) opposite to the first doping type.

[0049] A source region 104 is disposed in a body region 102, and a drain region 105 is disposed in a drift region 103. The source region 104 is a doped region disposed in the body region 102, and its doping type is a second doping type (e.g., N-type doping) opposite to the doping type of the body region 102. The source region 104 extends from the surface of the body region 102 inwards and is exposed on the surface of the body region 102. The drain region 105 is a doped region disposed in the drift region 103, and its doping type is the same as the doping type of the drift region 103 (e.g., N-type doping). The drain region 105 extends from the surface of the drift region 103 inwards and is exposed on the surface of the drift region 103.

[0050] Furthermore, in this embodiment, from the direction near the body region 102 to the direction away from the body region 102, the drift region 103 includes a first drift region 103a, a second drift region 103b, and a third drift region 103c arranged sequentially. A shallow trench isolation structure 106 is formed in the second drift region 103b. Furthermore, the doping concentration of the first drift region 103a and the third drift region 103c is greater than the doping concentration of the second drift region 103b, and the doping concentration of the drift region 103 exhibits a high-low-high distribution from the direction near the body region 102 to the direction away from the body region 102.

[0051] In this embodiment, by setting the doping concentration of drift region 103 to a high-low-high distribution, the electric field of the first drift region 103a and the third drift region 103c is reduced. Simultaneously, a new electric field peak is introduced in the second drift region 103b, increasing its electric field and improving the surface electric field distribution. Furthermore, the lower doping concentration in the second drift region 103b results in a higher resistance, improving the device's breakdown voltage. The higher doping concentrations in the first and third drift regions 103a and 103c result in lower on-resistances than the second drift region 103b, reducing the overall on-resistance of the LDMOS device and allowing for a larger on-current. Therefore, while increasing the breakdown voltage of the LDMOS device, it also provides a larger on-current, which is beneficial for improving the electrical performance of the semiconductor structure.

[0052] Corresponding to Figure 2 The LDMOS device shown is illustrated in this embodiment. This embodiment also provides a method for fabricating an LDMOS device. Figure 3 A flowchart illustrating the fabrication method of the LDMOS device provided in this application embodiment is shown, as follows: Figure 3 As shown, the fabrication method of the LDMOS device provided in this application embodiment includes:

[0053] S10: Provide a semiconductor layer, the semiconductor layer including a first region for forming a body region and a second region for forming a drift region, the second region including a first sub-region, a second sub-region and a third sub-region in sequence from the direction close to the first region to the direction far from the first region;

[0054] S20: A body region is formed in the first region, a first drift region is formed in the first sub-region of the second region, a second drift region is formed in the second sub-region of the second region, and a third drift region is formed in the third sub-region of the second region;

[0055] S30: The source region is formed in the volume region, and the drain region is formed in the drift region;

[0056] S40: A gate dielectric and a gate conductor are formed on the surface of the semiconductor layer between the source and drain regions.

[0057] Figures 4a to 4i The following are schematic cross-sectional views illustrating various stages in the manufacturing process of the LDMOS device provided in the embodiments of this application. Figure 3 as well as Figures 4a to 4i The manufacturing process of the LDMOS device according to the embodiments of this application will be described.

[0058] In step S10, a semiconductor layer 101 is provided. The semiconductor layer 101 includes a first region 101a for forming a body region and a second region 101b for forming a drift region. From the direction closest to the first region 101a to the direction furthest from the first region 101a, the second region 101b sequentially includes a first sub-region 101b-1, a second sub-region 101b-2, and a third sub-region 101b-3, as shown below. Figure 4a As shown.

[0059] In step S20, a volume region 102 is formed in the first region 101a; a first drift region 103a is formed in the first sub-region 101b-1 of the second region 101b; a second drift region 103b is formed in the second sub-region 101b-2 of the second region 101b; and a third drift region 103c is formed in the third sub-region 101b-3 of the second region 101b. Figures 4b to 4g As shown.

[0060] like Figure 4bAs shown, a patterned resist mask layer is formed on the surface of semiconductor layer 101, and ion implantation is performed on the exposed first region 101a through the opening of the resist mask layer to form a body region 102 in the first region 101a of semiconductor layer 101. After the body region 102 is formed, the mask layer is removed.

[0061] Furthermore, this embodiment also includes the step of forming a shallow trench isolation structure 106 in the second sub-region 101b-2 of the second region 101b, such as... Figure 4c As shown.

[0062] In this step, a shallow trench is formed in the second sub-region 101b-2 of the second region 101b, and an isolation medium is filled in the shallow trench to form a shallow trench isolation structure 106. In one embodiment, the depth of the shallow trench isolation structure 106 is about 0.2um to 0.8um, and the depth-to-width ratio is about 2:1 to 5:1, that is, the lateral dimension is about 0.04um to 0.40um.

[0063] like Figure 4d As shown, a patterned mask layer PR is formed on the surface of semiconductor layer 101.

[0064] In this step, a mask layer PR is formed on the surface of semiconductor layer 101, and the mask layer PR is patterned using photolithography. The patterned mask layer PR covers the surface of body region 102 and the surface of the second sub-region 101b-2 of the second region 101b, thereby exposing the surfaces of the first sub-region 101b-1 and the third sub-region 101b-3 of the second region 101b.

[0065] like Figure 4e As shown, diffusion channels are formed at the junction of the first sub-region 101b-1 and the second sub-region 101b-2, and at the junction of the third sub-region 101b-3 and the second sub-region 101b-2, via the patterned mask layer PR.

[0066] In this step, ion implantation is performed at the junction of the first sub-region 101b-1 and the second sub-region 101b-2, and at the junction of the third sub-region 101b-3 and the second sub-region 101b-2, to disrupt the lattice of the semiconductor layer 101 and form defects at the junctions of the first sub-region 101b-1 and the second sub-region 101b-2, and at the junctions of the third sub-region 101b-3 and the second sub-region 101b-2. These defects constitute diffusion channels from the first sub-region 101b-1 to the second sub-region 101b-2 and from the third sub-region 101b-3 to the second sub-region 101b-2, which facilitate subsequent ion diffusion.

[0067] In one embodiment, H is injected into the boundary between the first sub-region 101b-1 and the second sub-region 101b-2, and into the boundary between the third sub-region 101b-3 and the second sub-region 101b-2. + Specifically, H2 ionizes and transforms into H. + The generated hydrogen ions are accelerated to the required energy level and focused into a fine beam by an electromagnetic field. The high-energy hydrogen ion beam is precisely guided to the boundary between the first sub-region 101b-1 and the second sub-region 101b-2, as well as the boundary between the third sub-region 101b-3 and the second sub-region 101b-2. When the hydrogen ions enter the semiconductor layer 101 (silicon lattice), they gradually decelerate and eventually stop within a certain depth range, forming silicon lattice defects.

[0068] Furthermore, by adjusting the ion implantation angle, diffusion channels are formed at the boundaries of the first sub-region 101b-1 and the second sub-region 101b-2, as well as at the boundaries of the third sub-region 101b-3 and the second sub-region 101b-2. Specifically, when exposing the mask layer PR opening of the first sub-region 101b-1, the ion implantation angle is tilted towards the second sub-region 101b-2; similarly, when exposing the mask layer PR opening of the third sub-region 101b-3, the ion implantation angle is tilted towards the second sub-region 101b-2.

[0069] like Figure 4f As shown, a first drift region 103a is formed in the first sub-region 101b-1, and a third drift region 103c is formed in the third sub-region 101b-3.

[0070] In this step, a dopant of the second doping type is injected into the first sub-region 101b-1 and the third sub-region 101b-3 via a patterned mask layer PR to form the first drift region 103a and the third drift region 103c, respectively.

[0071] like Figure 4g As shown, the dopants in the first sub-region 101b-1 and the third sub-region 101b-3 diffuse to the second sub-region 101b-2 via diffusion channels to form the second drift region 103b in the second sub-region 101b-2.

[0072] In this step, high-temperature annealing is used to allow the dopants in the first sub-region 101b-1 and the third sub-region 101b-3 to diffuse to the second sub-region 101b-2 via diffusion channels, forming the second drift region 103b in the second sub-region 101b-2.

[0073] Normally, ion implantation is used to dopant ions into a silicon substrate, which allows for precise control of the doping depth and type, with almost no lateral diffusion. However, the lateral dimension of the second sub-region 101b-2 in this application is greater than or equal to the lateral dimension (0.04um~0.40um) of the shallow trench isolation structure 106, making it impossible for the dopants in the first drift region 103a and the third drift region 103c to diffuse to the central region of the second sub-region 101b-2.

[0074] In this application, diffusion channels are formed at the junction of the first sub-region 101b-1 and the second sub-region 101b-2, and at the junction of the third sub-region 101b-3 and the second sub-region 101b-2. These diffusion channels enhance the diffusion of dopants from the first drift region 103a and the third drift region 103c into the second sub-region 101b-2, avoiding the non-conductive situation that would occur due to the large width of the second sub-region 101b-2 and the absence of dopants in the center of the second sub-region 101b-2.

[0075] Further, in a preferred embodiment, hydrogen ions are injected into the boundary between sub-region 101b-1 and the second sub-region 101b-2, and at the boundary between the third sub-region 101b-3 and the second sub-region 101b-2, to form diffusion channels. Annealing the silicon wafer at a high temperature promotes the escape of hydrogen ions from the silicon lattice. Typically, the annealing temperature ranges from 300°C to 800°C, depending on the desired hydrogen ion removal efficiency and the heat resistance of the material. High temperatures help activate hydrogen ions, making them more easily diffused from the silicon wafer surface.

[0076] In one embodiment, the annealing process is performed in a vacuum environment to further improve the hydrogen ion removal efficiency. Vacuum conditions reduce the interaction between hydrogen and ambient gas molecules, thereby accelerating the diffusion and escape of hydrogen.

[0077] In one embodiment, to prevent the silicon wafer from oxidizing at high temperatures, annealing can be performed under the protection of an inert gas (such as argon, Ar). This not only helps maintain the surface quality of the silicon wafer but also effectively promotes hydrogen removal.

[0078] In one embodiment, annealing is performed using Rapid Thermal Processing (RTP), a technique that rapidly heats and cools to achieve high temperatures in a short time, effectively activating hydrogen atoms and causing them to escape from the silicon wafer. The advantages of RTP include precise temperature and time control, reduced thermal budget, and suitability for heat-sensitive devices.

[0079] In step S30, a source region 104 is formed in the body region 102, and a drain region 105 is formed in the drift region 103, as follows. Figure 4h As shown.

[0080] In this step, a patterned resist mask layer is formed on the surface of the semiconductor layer 101, and ion implantation is performed through the openings in the resist mask layer to the exposed portions of the body region 102 and the drift region 103 to form a source region 104 in the body region 102 and a drain region 105 in the drift region 103. A second type of dopant is implanted into the body region 102 and the drift region 103 to form a second type of source region 104 and drain region 105.

[0081] In step S40, a gate dielectric and a gate conductor are formed on the surface of the semiconductor layer between the source and drain regions, such as... Figure 4i As shown.

[0082] In this step, for example, a dielectric layer and a conductor layer are formed on the surface of semiconductor layer 101 using a deposition process, with the dielectric layer located on the surface of semiconductor layer and the conductor layer located on the surface of dielectric layer. Then, the dielectric layer and conductor layer are patterned using photolithography and etching processes to form gate dielectric 107 and gate conductor 108, which are located on the surface of semiconductor layer 101 between source region 104 and drain region 105.

[0083] The unexpected technical effect of this application is:

[0084] In this embodiment, by setting the doping concentration of the drift region to a high-low-high distribution, the electric field of the first drift region and the third drift region is reduced. At the same time, a new electric field peak is introduced in the second drift region, which increases the electric field of the second drift region and improves the surface electric field distribution.

[0085] Furthermore, the lower doping concentration in the second drift region results in a higher resistance, improving the device's breakdown voltage. The higher doping concentrations in the first and third drift regions, the lower their on-resistance compared to the second drift region. This reduces the overall on-resistance of the LDMOS device, leading to a larger on-current. Therefore, by simultaneously increasing the breakdown voltage and providing a larger on-current, the electrical performance of the semiconductor structure can be improved.

[0086] This application forms diffusion channels at the junction of the first and second sub-regions and at the junction of the third and second sub-regions. These diffusion channels enhance the diffusion of dopants from the first and third drift regions into the second sub-region, preventing a non-conductive situation from occurring in the center of the second sub-region due to the absence of dopants when the width of the second sub-region is large.

[0087] Furthermore, in a preferred embodiment, hydrogen ions are injected into the boundary between the first and second sub-regions and the boundary between the third and second sub-regions to form diffusion channels. Annealing the silicon wafer at a high temperature promotes the escape of hydrogen ions from the silicon lattice.

[0088] In one embodiment, the annealing process is performed in a vacuum environment to further improve the hydrogen ion removal efficiency. Vacuum conditions reduce the interaction between hydrogen and ambient gas molecules, thereby accelerating the diffusion and escape of hydrogen.

[0089] In one embodiment, to prevent the silicon wafer from oxidizing at high temperatures, annealing can be performed under the protection of an inert gas (such as argon, Ar). This not only helps maintain the surface quality of the silicon wafer but also effectively promotes hydrogen removal.

[0090] In one embodiment, annealing is performed using Rapid Thermal Processing (RTP), a technique that rapidly heats and cools to achieve high temperatures in a short time, effectively activating hydrogen atoms and causing them to escape from the silicon wafer. The advantages of RTP include precise temperature and time control, reduced thermal budget, and suitability for heat-sensitive devices.

[0091] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing an LDMOS device, comprising: providing a semiconductor layer, the semiconductor layer comprising a first region for forming a body region and a second region for forming a drift region, the second region comprising a first sub-region, a second sub-region and a third sub-region in sequence from a direction close to the first region to a direction away from the first region; forming the body region in the first region; forming a shallow trench isolation structure in the second sub-region, the shallow trench isolation structure having a depth of 0.2-0.8um and a lateral dimension of 0.04um-0.40um; forming a patterned mask layer on a surface of the semiconductor layer, the patterned mask layer covering a surface of the second sub-region and exposing surfaces of the first sub-region and the third sub-region; forming diffusion channels at an interface between the first sub-region and the second sub-region and at an interface between the third sub-region and the second sub-region via the patterned mask layer; forming a first drift region in the first sub-region and a third drift region in the third sub-region; diffusing dopants of the first sub-region and the third sub-region to the second sub-region via the diffusion channels to form a second drift region in the second sub-region; forming a source region in the body region and a drain region in the drift region; forming a gate dielectric and a gate conductor on a surface of the semiconductor layer between the source region and the drain region; wherein the first drift region and the third drift region have a higher doping concentration than the second drift region.

2. The method of fabricating an LDMOS device according to claim 1, wherein, performing ion implantation at the interface between the first sub-region and the second sub-region and at the interface between the third sub-region and the second sub-region to form defects at the interface between the first sub-region and the second sub-region and at the interface between the third sub-region and the second sub-region, the defects constituting the diffusion channels from the first sub-region to the second sub-region and from the third sub-region to the second sub-region.

3. The method of fabricating an LDMOS device of claim 2, wherein, injecting H to the interface of the first sub-region and the second sub-region and the interface of the third sub-region and the second sub-region + .

4. The method of fabricating an LDMOS device of claim 2, wherein, adjusting an angle of ion implantation so that ions are implanted at the interface between the first sub-region and the second sub-region and at the interface between the third sub-region and the second sub-region, the diffusion channels being formed at the interface between the first sub-region and the second sub-region and at the interface between the third sub-region and the second sub-region.

5. The method of fabricating an LDMOS device of claim 1, wherein, performing high-temperature annealing so that the dopants of the first sub-region and the third sub-region diffuse to the second sub-region via the diffusion channels to form the second drift region in the second sub-region.

6. The method of fabricating an LDMOS device of claim 5, wherein, performing the annealing process in a vacuum or an inert gas environment. 7.An LDMOS device formed by the method of any one of claims 1-6.

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