A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The application provides a semiconductor device preparation method and a semiconductor device, relates to the technical field of semiconductor devices, and can reduce the risk of disconnection in a shared contact hole. The method comprises the following steps: providing a semiconductor initial structure, which comprises a semiconductor substrate, a first insulating layer and a gate structure arranged at intervals, the first insulating layer comprises a first insulating structure, a second insulating structure and a third insulating structure, the first insulating structure is located on the side of the gate structure, the second insulating structure is located on the side of the gate structure away from the semiconductor substrate, the third insulating structure is located between adjacent first insulating structures, and the first insulating structures are provided with a first opening between them; removing part of the first insulating structure and the second insulating structure to obtain a second insulating layer, the first insulating structure after processing is provided with a second opening between them, and the opening size of the first opening is smaller than the opening size of the second opening; forming a dielectric layer on the side of the second insulating layer away from the semiconductor substrate; and removing part of the dielectric layer to form a shared contact hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] With the advancement and development of semiconductor device technology, the requirements for the fabrication quality and efficiency of semiconductor devices are gradually increasing. For semiconductor devices with shared contact holes, the shared contact holes are used to accommodate shared contact plugs to electrically connect the gate and source / drain regions of the semiconductor device.

[0003] During the formation of a shared contact hole, after etching away the dielectric layer at the corresponding location of the shared contact hole, it is necessary to etch the etch stop layer down the gate sidewall. However, misalignment during the etching process can lead to insufficient spacing between the etch stop layers, or even prevent the etch stop layers from being etched through, affecting the fabrication quality of the shared contact hole. This increases the risk of open circuits in the shared contact hole, further increasing the fabrication difficulty of the semiconductor device, reducing its reliability and stability, and ultimately lowering its yield. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor device and a semiconductor device, which can improve the fabrication quality of shared contact holes, reduce the risk of open circuits in shared contact holes, reduce the fabrication difficulty of semiconductor devices, improve the reliability and stability of semiconductor devices, and increase the yield of semiconductor devices.

[0005] A first aspect of this application provides a method for fabricating a semiconductor device, comprising:

[0006] A semiconductor initial structure is provided, wherein the semiconductor initial structure includes a semiconductor substrate, a first insulating layer, and gate structures spaced apart. The first insulating layer includes a first insulating structure, a second insulating structure, and a third insulating structure. The first insulating structure is located on the periphery of the gate structure, the second insulating structure is located on the side of the gate structure away from the semiconductor substrate, and the third insulating structure is located between adjacent first insulating structures. Both the second insulating structure and the third insulating structure are connected to the first insulating structure, and a first opening is provided between adjacent first insulating structures.

[0007] A portion of the first insulating structure and the second insulating structure are removed to obtain a second insulating layer, wherein the processed first insulating structure has a second opening between them, and the opening size of the first opening is smaller than the opening size of the second opening.

[0008] A dielectric layer is formed on the side of the second insulating layer away from the semiconductor substrate;

[0009] A portion of the dielectric layer is removed to form a shared contact hole.

[0010] In some embodiments, removing portions of the first insulating structure and the second insulating structure to obtain a second insulating layer includes:

[0011] A sacrificial layer is formed on the side of the third insulating structure away from the semiconductor substrate;

[0012] According to the sacrificial layer, a portion of the first insulating structure is etched, wherein the opening size of the second opening on the side closer to the semiconductor substrate is smaller than the opening size of the second opening on the side farther from the semiconductor substrate;

[0013] Remove the sacrificial layer.

[0014] In some embodiments, forming a sacrificial layer on the side of the third insulating structure away from the semiconductor substrate includes:

[0015] An initial sacrificial layer is formed on the side of the first insulating layer away from the semiconductor substrate;

[0016] A portion of the initial sacrificial layer is removed to obtain the sacrificial layer, which is located between adjacent first insulating structures. In the thickness direction of the semiconductor substrate, the thickness dimension of the sacrificial layer is smaller than the depth dimension of the second opening.

[0017] In some embodiments, the sacrificial layer comprises amorphous carbon.

[0018] In some embodiments, providing the initial semiconductor structure includes:

[0019] A semiconductor substrate is provided, the semiconductor substrate including a trench region and source / drain doped regions, the trench region being spaced apart from the source / drain doped regions;

[0020] A grid insulating layer is formed on the surface of the trench region;

[0021] An initial gate structure is formed on the side of the gate insulating layer away from the semiconductor substrate;

[0022] A sidewall is formed on the periphery of the initial gate structure to obtain the gate structure, wherein the gate structure includes the initial gate structure, the sidewall and the gate insulating layer, and two spaced source and drain doped regions are provided between the orthogonal projections of two adjacent gate structures toward the semiconductor substrate, the source and drain doped regions corresponding to different gate structures are insulated from each other, and each source and drain doped region corresponds to one gate structure;

[0023] A conductive structure is formed on one side of the semiconductor substrate, the conductive structure being located on the same side of the semiconductor substrate as the initial gate structure, the conductive structure being used to electrically connect two spaced source / drain doped regions located between two adjacent gate structures;

[0024] The first insulating layer is formed between the periphery of the gate structure, the surface of the gate structure away from the semiconductor substrate, and the adjacent first insulating structure.

[0025] In some embodiments, forming a dielectric layer on the side of the second insulating layer away from the semiconductor substrate includes:

[0026] A first sub-dielectric layer is formed on the side of the second insulating layer away from the initial semiconductor structure, and the surface of the first sub-dielectric layer away from the initial semiconductor structure is flush with the surface of the gate structure away from the semiconductor substrate;

[0027] A second sub-dielectric layer is formed on the side of the first sub-dielectric layer away from the initial semiconductor structure, the dielectric layer comprising the first sub-dielectric layer and the second sub-dielectric layer.

[0028] In some embodiments, removing portions of the first insulating structure and the second insulating structure to obtain a second insulating layer includes:

[0029] Remove part of the first insulating structure;

[0030] The second insulating structure is removed by a planarization process.

[0031] In some embodiments, prior to the step of forming a first sub-dielectric layer on the side of the second insulating layer away from the initial semiconductor structure, the method further includes:

[0032] An initial dielectric layer is formed on the side of the first insulating layer away from the initial semiconductor structure, and the surface of the initial dielectric layer on the side away from the initial semiconductor structure extends beyond the surface of the second insulating structure on the side away from the semiconductor substrate;

[0033] The removal of the second insulating structure by planarization process includes:

[0034] A planarization process is used to remove part of the initial dielectric layer and the second insulating structure to obtain the second insulating layer and the first sub-dielectric layer.

[0035] In some embodiments, providing the initial semiconductor structure includes:

[0036] A pseudo-gate structure is formed on the side of the gate insulating layer of the initial semiconductor structure away from the semiconductor substrate using polycrystalline silicon material. The pseudo-gate structure has the same dimensions as the initial gate structure of the initial semiconductor structure.

[0037] After the step of removing part of the initial dielectric layer and the second insulating structure through a planarization process to obtain the second insulating layer and the first sub-dielectric layer, the method further includes:

[0038] Remove the pseudo-gate structure;

[0039] The gate structure is obtained by filling the space where the pseudo-gate structure is located with metal gate material.

[0040] A second aspect of this application provides a semiconductor device fabricated using the semiconductor device fabrication method described in any of the first aspects above.

[0041] An unexpected benefit of this application is that by removing a portion of the first insulating structure around the gate structure and the second insulating structure on the side of the gate structure away from the semiconductor substrate, the opening size of the second opening between the processed first insulating structures is larger than the opening size of the first opening between the gate structures. This reduces the size of the insulating structure around the gate structure, decreases the etching energy required for the insulating structure during shared contact hole etching, and shortens the etching time required for the insulating structure. This, in turn, increases the etching energy of the third insulating structure. Furthermore, even if the shared contact hole etching alignment is inaccurate, the etching opening of the third insulating structure can be enlarged, reducing the risk of open circuits within the shared contact hole, improving the fabrication quality of the shared contact hole, and consequently reducing the etching precision requirements during shared contact hole fabrication, thus reducing the fabrication difficulty of semiconductor devices. Simultaneously, by increasing the size of the second opening, voids can be avoided during the deposition of the dielectric layer on the side of the second insulating layer away from the semiconductor substrate, thereby preventing tungsten leakage within the shared contact hole, reducing the risk of short circuits within the shared contact hole, further improving the fabrication quality of the semiconductor device, increasing its reliability and stability, and improving its yield. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;

[0044] Figure 2 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0045] Figure 3 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0046] Figure 4 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0047] Figure 5 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0048] Figure 6 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0049] Figure 7 This is a schematic structural diagram of a semiconductor device provided in an embodiment of this application.

[0050] Explanation of reference numerals in the attached figures:

[0051] 100 - Initial semiconductor structure, 110 - Semiconductor substrate, 120 - Gate structure, 121 - Gate insulating layer, 122 - Initial gate structure, 123 - Sidewall, 130 - First insulating layer, 131 - First insulating structure, 132 - Second insulating structure, 133 - Third insulating structure, 140 - Conductive structure, 200 - Second insulating layer, 231 - Processed first insulating structure, 300 - Dielectric layer, 301 - Initial dielectric layer, 310 - First sub-dielectric layer, 400 - Sacrificial layer. Detailed Implementation

[0052] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0057] With the advancement and development of semiconductor device technology, the requirements for the fabrication quality and efficiency of semiconductor devices are gradually increasing. For semiconductor devices with shared contact holes, the shared contact holes are used to accommodate shared contact plugs to electrically connect the gate and source / drain regions of the semiconductor device.

[0058] During the formation of shared contact holes, after etching away the dielectric layer at the corresponding location of the shared contact hole, it is necessary to etch down the gate sidewalls to form an etch stop layer. However, misalignment during the etching process can lead to insufficient spacing between the etch stop layers, or even prevent the etch stop layers from being etched through. This increases the risk of open circuits in the shared contact hole, further complicating semiconductor device fabrication, reducing reliability and stability, and ultimately lowering yield. Furthermore, as the linewidth of semiconductor devices decreases, the spacing between adjacent gates also gradually decreases. Therefore, during dielectric layer deposition, deposition voids can easily form between adjacent gates, leading to tungsten leakage within the shared contact hole and causing short circuits in the contact plugs.

[0059] like Figure 1 As shown, a first aspect of this application provides a method for fabricating a semiconductor device, comprising:

[0060] Step S110: Provide a semiconductor initial structure, wherein the semiconductor initial structure includes a semiconductor substrate, a first insulating layer, and gate structures spaced apart. The first insulating layer includes a first insulating structure, a second insulating structure, and a third insulating structure. The first insulating structure is located on the periphery of the gate structure, the second insulating structure is located on the side of the gate structure away from the semiconductor substrate, and the third insulating structure is located between adjacent first insulating structures. Both the second and third insulating structures are connected to the first insulating structure, and there is a first opening between adjacent first insulating structures.

[0061] like Figure 2 As shown, a semiconductor initial structure 100 is provided, which includes a semiconductor substrate 110, two spaced-apart gate structures 120, and a first insulating layer 130. The first insulating layer 130 includes a first insulating structure 131, a second insulating structure 132, and a third insulating structure 133, with a first opening H1 between adjacent first insulating structures 131. The material of the first insulating layer 130 may include silicon nitride.

[0062] As an example, a first insulating structure 131, a second insulating structure 132, and a third insulating structure 133 are formed in the same process step using chemical deposition or atomic layer deposition, that is, the first insulating structure 131, the second insulating structure 132, and the third insulating structure 133 are prepared synchronously using the same material.

[0063] Step S120: Remove part of the first insulating structure 131 and the second insulating structure 132 to obtain a second insulating layer, wherein the processed first insulating structures have a second opening, and the opening size of the first opening H1 is smaller than the opening size of the second opening.

[0064] like Figure 3 As shown, as an example, an etching process, such as a dry etching process or a wet etching process, is used to etch away the second insulating structure 132 and etch away part of the first insulating structure 131 to form a processed first insulating structure 231, thereby obtaining a second insulating layer 200; wherein, the second insulating layer 200 includes a third insulating structure 133 and a processed first insulating structure 231, and the processed first insulating structure 231 has a second opening H2 between them.

[0065] For example, the opening size of the second opening H2 on the side away from the semiconductor substrate 110 can be larger than the opening size of the first opening H1, the opening size of the second opening H2 on the side closer to the semiconductor substrate 110 can be larger than the opening size of the first opening H1, and the opening size of the second opening H2 at any position in the thickness direction of the semiconductor substrate 110 can be larger than the opening size of the first opening H1. The cross-sectional shape of the second opening H2 in the direction perpendicular to the semiconductor substrate 110 can be trapezoidal, rectangular, etc.

[0066] Step S130: A dielectric layer 300 is formed on the side of the second insulating layer 200 away from the semiconductor substrate 110.

[0067] A dielectric layer 300 is formed on the side of the second insulating layer 200 away from the semiconductor substrate 110 using a chemical deposition process or an atomic layer deposition process. As an example, the material of the dielectric layer 300 includes silicon oxide.

[0068] Step S140: Remove part of the dielectric layer 300 to form a shared contact hole.

[0069] An etching process, such as dry etching or wet etching, is used to etch away part of the dielectric layer 300 to form a shared contact hole.

[0070] An unexpected effect of this application is that by removing part of the first insulating structure 131 on the periphery of the gate structure 120 and the second insulating structure 132 on the side of the gate structure 120 away from the semiconductor substrate 110, the opening size of the second opening between the processed first insulating structures 231 is larger than the opening size of the first opening between the gate structures 120. This reduces the insulating structure on the periphery of the gate structure 120, reduces the etching energy required for the insulating structure during the etching of the shared contact hole, and shortens the etching time required for the insulating structure. This increases the etching energy of the third insulating structure 133. Furthermore, in the case of misalignment during the etching of the shared contact hole, the etching opening of the third insulating structure 133 can be increased, reducing the risk of open circuit in the shared contact hole, improving the fabrication quality of the shared contact hole, and thus reducing the requirements for etching precision during the fabrication of the shared contact hole, thereby reducing the fabrication difficulty of the semiconductor device. Meanwhile, by increasing the size of the second opening, voids can be avoided during the deposition of the dielectric layer 300 on the side of the second insulating layer 200 away from the semiconductor substrate 110. This can prevent tungsten leakage in the shared contact hole, reduce the risk of short circuits in the shared contact hole, further improve the fabrication quality of the semiconductor device, enhance the reliability and stability of the semiconductor device, and increase the yield of the semiconductor device.

[0071] like Figure 4 As shown, in some embodiments, removing a portion of the first insulating structure 131 and the second insulating structure 132 to obtain the second insulating layer 200 includes: forming a sacrificial layer 400 on the side of the third insulating structure 133 away from the semiconductor substrate 110; etching a portion of the first insulating structure 131 according to the sacrificial layer 400, wherein the opening size of the second opening H2 on the side near the semiconductor substrate 110 is smaller than the opening size of the second opening H2 on the side away from the semiconductor substrate 110; and removing the sacrificial layer 400.

[0072] As an example, a sacrificial layer 400 is formed on the side of the third insulating structure 133 away from the semiconductor substrate 110, wherein the thickness dimension of the sacrificial layer 400 is smaller than the depth dimension of the second opening H2 in the thickness direction of the semiconductor substrate 110. Using the sacrificial layer 400 as a mask, the second insulating structure 132 and a portion of the first insulating structure 132 are etched away to form the second insulating layer 200 and the second opening H2; wherein the opening size of the second opening H2 on the side closer to the semiconductor substrate 110 is smaller than the opening size of the second opening H2 on the side away from the semiconductor substrate 110; the sacrificial layer 400 on the third insulating structure 133 is removed, exposing the surface of the third insulating structure 133 away from the semiconductor substrate 110. The semiconductor device fabrication method provided in this application embodiment uses the sacrificial layer 400 as a mask to protect the third insulating structure 133, avoid damage to the third insulating structure 133 during the pre-etching process of the first insulating structure 131, and further avoid damage to the semiconductor substrate 110 due to the excessively small thickness of the third insulating structure 133 during the etching process of the shared contact hole. This can improve the fabrication quality of the semiconductor device, enhance its reliability and stability, and improve its electrical performance and yield.

[0073] In some embodiments, a sacrificial layer 400 is formed on the side of the third insulating structure 133 away from the semiconductor substrate 110, including: forming an initial sacrificial layer on the side of the first insulating layer 130 away from the semiconductor substrate 110; removing a portion of the initial sacrificial layer to obtain the sacrificial layer 400, the sacrificial layer 400 being located between adjacent first insulating structures 131, and the thickness dimension of the sacrificial layer 400 being smaller than the depth dimension of the second opening in the thickness direction of the semiconductor substrate 110.

[0074] As an example, a deposition process is used to form an initial sacrificial layer on the side of the first insulating layer 130 away from the semiconductor substrate 110; wherein the initial sacrificial layer is located in the first opening H1 and extends along the sidewall of the first opening H1 to the second insulating structure 131 and the third insulating structure 133; an etching process, such as a wet etching process or a dry etching process, is used to etch the initial sacrificial layer, retaining a portion of the initial sacrificial layer located on the third insulating structure 133 in the first opening H1, to form a sacrificial layer 400; wherein the thickness dimension of the sacrificial layer 400 is smaller than the depth dimension of the second opening H2.

[0075] The semiconductor device fabrication method provided in this application embodiment, by setting the thickness of the sacrificial layer 400 to be smaller than the depth of the second opening, can utilize the height difference between the surface of the sacrificial layer 400 away from the semiconductor substrate 110 and the surface of the first insulating structure 131 away from the semiconductor substrate 110 to form a second opening H2 with a gradually decreasing opening size in the direction of the gate structure 120 pointing to the semiconductor substrate 110, thereby expanding the size of the opening between two adjacent gate structures 120.

[0076] By pre-etching the first insulating structure 131, the etching energy and time required for the first insulating structure 131 during the formation of the shared contact hole are reduced. This increases the etching energy of the third insulating structure 133, further increasing the etching opening of the third insulating structure 133 even if the shared contact hole etching alignment is inaccurate. This reduces the risk of open circuits within the shared contact hole and improves the fabrication quality of the shared contact hole. Therefore, the etching precision requirements during the fabrication of the shared contact hole can be reduced, lowering the fabrication difficulty of the semiconductor device. Simultaneously, it avoids voids generated during the deposition of the dielectric layer 300 on the side of the second insulating layer 200 away from the semiconductor substrate 110, thus preventing tungsten leakage within the shared contact hole, reducing the risk of short circuits, further improving the fabrication quality of the semiconductor device, increasing its reliability and stability, and improving its yield.

[0077] In some implementations, the material of the sacrificial layer 400 includes amorphous carbon.

[0078] It should be noted that amorphous carbon has high deposition quality and fewer voids after deposition, which can improve the formation quality of the sacrificial layer 400.

[0079] In some embodiments, a semiconductor initial structure 100 is provided, comprising: providing a semiconductor substrate 110, the semiconductor substrate 110 including a trench region and source / drain doped regions, the trench region and the source / drain doped regions being spaced apart; forming a gate insulating layer 121 on the surface of the trench region; forming a gate initial structure 122 on the side of the gate insulating layer 121 away from the semiconductor substrate 110; forming a sidewall 123 on the periphery of the gate initial structure 122, thereby obtaining a gate structure 120; wherein the gate structure 120 includes the gate initial structure 122, the sidewall 123 and the gate insulating layer 121, and the orthographic projection of two adjacent gate structures 120 toward the semiconductor substrate 110. There are two spaced-apart source / drain doped regions, which are insulated from each other, corresponding to different gate structures 120. Each source / drain doped region corresponds to one gate structure 120. A conductive structure 140 is formed on one side of the semiconductor substrate 110. The conductive structure 140 and the initial gate structure 122 are located on the same side of the semiconductor substrate 110. The conductive structure 140 is used to electrically connect the two spaced-apart source / drain doped regions located between two adjacent gate structures 120. A first insulating layer 130 is formed between the periphery of the gate structure 120, the surface of the gate structure 120 away from the semiconductor substrate 110, and the adjacent gate structure 120.

[0080] As an example, a gate insulating material layer is formed on one side of the semiconductor substrate 110 using a deposition process. The gate insulating material layer is then patterned and etched, leaving the gate insulating material layer in the trench region as the gate insulating layer 121. An initial gate structure 122 is formed on the side of the gate insulating layer 121 away from the semiconductor substrate 110 using a deposition process. Sidewalls 123 are formed around the initial gate structure 122 using a deposition process, resulting in the gate structure 120.

[0081] For example, the sidewall 123 may include a three-layer composite structure, consisting of a silicon nitride sidewall, a silicon oxide sidewall, and a silicon nitride sidewall, respectively, in the radial direction of the initial gate structure 122. The material of the conductive structure 140 includes a nickel-silicon compound.

[0082] The semiconductor device fabrication method provided in this application embodiment, by setting the gate structure 120 to be insulated from the source and drain doped regions, can drive the formation of channels in the trench region by applying driving power to the gate structure 120, so that the adjacent source and drain regions are connected. This can avoid the voltage change on the gate structure 120 from affecting the electrical performance of the semiconductor device and improve the conduction quality of the semiconductor device.

[0083] In some embodiments, a dielectric layer 300 is formed on the side of the second insulating layer 200 away from the semiconductor substrate 110, including: forming a first sub-dielectric layer on the side of the second insulating layer 200 away from the semiconductor initial structure 100, wherein the surface of the first sub-dielectric layer on the side away from the semiconductor initial structure 100 is flush with the surface of the gate structure 120 on the side away from the semiconductor substrate 110; and forming a second sub-dielectric layer on the side of the first sub-dielectric layer away from the semiconductor initial structure 100, wherein the dielectric layer 300 includes the first sub-dielectric layer and the second sub-dielectric layer.

[0084] As an example, a first sub-dielectric layer is formed on the side of the second insulating layer 200 away from the semiconductor initial structure 100 using a chemical vapor deposition process or an atomic layer deposition process. The surface of the first sub-dielectric layer away from the semiconductor initial structure 100 is flush with the surface of the gate structure 120 away from the semiconductor substrate 110. A second sub-dielectric layer is formed on the side of the first sub-dielectric layer away from the semiconductor initial structure 100 using a chemical vapor deposition process or an atomic layer deposition process, resulting in a dielectric layer 300.

[0085] For example, the second sub-dielectric layer is located on the surface of the gate structure 120 away from the semiconductor substrate 110.

[0086] The semiconductor device fabrication method provided in this application, by forming a sub-dielectric layer in two stages to obtain a dielectric layer 300, can further reduce the risk of voids in the first sub-dielectric layer within the second opening H2, further improve the formation quality of the dielectric layer 300, avoid tungsten leakage within the shared contact hole, reduce the risk of short circuits within the shared contact hole, further improve the fabrication quality of the semiconductor device, enhance the reliability and stability of the semiconductor device, and increase the yield of the semiconductor device.

[0087] For example, the first sub-dielectric layer and the second sub-dielectric layer are made of the same material, such as an oxide layer. This arrangement can increase the adhesion between the first sub-dielectric layer and the second sub-dielectric layer.

[0088] In some embodiments, removing a portion of the first insulating structure 131 and the second insulating structure 132 to obtain the second insulating layer 200 includes: removing a portion of the first insulating structure 131; and removing the second insulating structure 132 by a planarization process.

[0089] As an example, an etching process, such as dry etching or wet etching, is used to etch away part of the first insulating structure 131, forming the processed first insulating structure 231. A planarization process is then used to remove the second insulating structure 132, exposing the gate structure 120. The semiconductor device fabrication method provided in this application, by removing the second insulating structure 132 after etching the first insulating structure 131, avoids damage to the gate structure 120 caused by the etching of the first insulating structure 131. Simultaneously, the planarization process for removing the second insulating structure 132 improves the surface flatness of the gate structure 120, preventing damage to the gate structure 120, reducing the fabrication difficulty of the semiconductor device, and improving the control over the surface morphology of the semiconductor device.

[0090] In some embodiments, before forming the first sub-dielectric layer 310 on the side of the second insulating layer 200 away from the semiconductor initial structure 100, the method further includes: forming an initial dielectric layer 301 on the side of the first insulating layer 130 away from the semiconductor initial structure 100, wherein the surface of the initial dielectric layer 301 away from the semiconductor initial structure 100 extends beyond the surface of the second insulating structure 132 away from the semiconductor substrate 110. Removing the second insulating structure 132 by a planarization process includes: removing a portion of the initial dielectric layer 301 and the second insulating structure 132 by a planarization process to obtain the second insulating layer 200 and the first sub-dielectric layer 310.

[0091] As an example, an initial dielectric layer is formed on the side of the first insulating layer 130 away from the semiconductor initial structure 100 using a chemical vapor deposition process or an atomic layer deposition process.

[0092] like Figure 5 As shown, the surface of the initial dielectric layer 301 away from the semiconductor initial structure 100 can be flush with the surface of the second insulating structure 132 away from the semiconductor substrate 110.

[0093] like Figure 6 As shown, the surface of the first sub-dielectric layer 310 away from the semiconductor substrate 110 can be flush with the surface of the gate structure 120 away from the semiconductor substrate 110.

[0094] The semiconductor device fabrication method provided in this application can increase the grinding area in the planarization process by forming an initial dielectric layer 301 in the second opening H2, thereby improving the stability of the mechanical grinding of the second insulating structure 132, further enhancing the grinding effect, increasing the reliability and stability of the semiconductor device, and improving the yield of the semiconductor device.

[0095] In some embodiments, a semiconductor initial structure 100 is provided, including forming a dummy gate structure on the side of the gate insulating layer 121 of the semiconductor initial structure 100 away from the semiconductor substrate 110 using a polysilicon material. The dummy gate structure has the same dimensions as the gate initial structure 122 of the semiconductor initial structure 100.

[0096] As an example, a gate insulating material layer and a polysilicon material are sequentially formed on one side of the semiconductor substrate 110, with the polysilicon material formed on the side of the gate insulating material layer away from the semiconductor substrate 110; the polysilicon material and the gate insulating material layer are patterned, and the polysilicon material and the gate insulating material layer are etched, while the polysilicon material and the gate insulating material layer in the trench region are retained, resulting in a pseudo-gate structure composed of the remaining polysilicon material and a gate insulating layer 121 composed of the remaining gate insulating material layer.

[0097] For example, when a dummy gate structure is formed in the space where the initial gate structure 122 is located, a top sidewall structure is also provided on the surface of the dummy gate structure away from the semiconductor substrate 110, and the second insulating structure 132 is located on the side of the top sidewall structure away from the semiconductor substrate 110.

[0098] After removing part of the initial dielectric layer 301 and the second insulating structure 132 through a planarization process to obtain the second insulating layer 200 and the first sub-dielectric layer 310, the method further includes: removing the dummy gate structure; filling the space where the dummy gate structure is located with metal gate material to obtain the gate structure 120.

[0099] For example, if a pseudo-gate structure is formed in the space where the initial gate structure 122 is located, the top sidewall structure corresponding to the pseudo-gate structure can be removed by a planarization process while removing part of the initial dielectric layer 301.

[0100] It should be noted that the step of filling the metal gate material to obtain the gate structure 120 occurs before the step of forming the second sub-dielectric layer.

[0101] The semiconductor device fabrication method provided in this application embodiment uses a pseudo-gate structure to occupy space first, which can avoid damage to the gate structure 120 during the fabrication process, thereby further improving the electrical performance of the semiconductor device, improving the reliability and stability of the semiconductor device, and improving the yield of the semiconductor device.

[0102] like Figure 7 As shown, in a second aspect of the present application, a semiconductor device is provided, which is fabricated using any of the semiconductor device fabrication methods described in the first aspect above.

[0103] For example, the shared contact hole CT is used to electrically connect the gate structure 120 and the conductive structure 140, thereby enabling the gate and source / drain regions of the semiconductor device to form an electrical connection by providing contact plugs within the shared contact hole CT.

[0104] An unexpected effect of this application is that by removing part of the first insulating structure 131 on the periphery of the gate structure 120 and the second insulating structure 132 on the side of the gate structure 120 away from the semiconductor substrate 110, the opening size of the second opening between the processed first insulating structures 231 is larger than the opening size of the first opening between the gate structures 120. This reduces the insulating structure on the periphery of the gate structure 120, reduces the etching energy required for the insulating structure during the etching of the shared contact hole, and shortens the etching time required for the insulating structure. This increases the etching energy of the third insulating structure 133. Furthermore, in the case of misalignment during the etching of the shared contact hole, the etching opening of the third insulating structure 133 can be increased, reducing the risk of open circuit in the shared contact hole, improving the fabrication quality of the shared contact hole, and thus reducing the requirements for etching precision during the fabrication of the shared contact hole, thereby reducing the fabrication difficulty of the semiconductor device. Meanwhile, by increasing the size of the second opening, voids can be avoided during the deposition of the dielectric layer 300 on the side of the second insulating layer 200 away from the semiconductor substrate 110. This can prevent tungsten leakage in the shared contact hole, reduce the risk of short circuits in the shared contact hole, further improve the fabrication quality of the semiconductor device, enhance the reliability and stability of the semiconductor device, and increase the yield of the semiconductor device.

[0105] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor initial structure is provided, wherein the semiconductor initial structure includes a semiconductor substrate, a first insulating layer, and gate structures spaced apart. The first insulating layer includes a first insulating structure, a second insulating structure, and a third insulating structure. The first insulating structure is located on the periphery of the gate structure, the second insulating structure is located on the side of the gate structure away from the semiconductor substrate, and the third insulating structure is located between adjacent first insulating structures. Both the second insulating structure and the third insulating structure are connected to the first insulating structure, and a first opening is provided between adjacent first insulating structures. A portion of the first insulating structure and the second insulating structure are removed to obtain a second insulating layer, wherein the processed first insulating structure has a second opening between them, and the opening size of the first opening is smaller than the opening size of the second opening. A dielectric layer is formed on the side of the second insulating layer away from the semiconductor substrate; A portion of the dielectric layer is removed to form a shared contact hole; The second insulating layer is obtained by removing portions of the first and second insulating structures, including: A sacrificial layer is formed on the side of the third insulating structure away from the semiconductor substrate; According to the sacrificial layer, a portion of the first insulating structure is etched, wherein the opening size of the second opening on the side closer to the semiconductor substrate is smaller than the opening size of the second opening on the side farther from the semiconductor substrate; Remove the sacrificial layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a sacrificial layer on the side of the third insulating structure away from the semiconductor substrate includes: An initial sacrificial layer is formed on the side of the first insulating layer away from the semiconductor substrate; A portion of the initial sacrificial layer is removed to obtain the sacrificial layer, which is located between adjacent first insulating structures. In the thickness direction of the semiconductor substrate, the thickness dimension of the sacrificial layer is smaller than the depth dimension of the second opening.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The sacrificial layer comprises amorphous carbon.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The provision of the initial semiconductor structure includes: A semiconductor substrate is provided, the semiconductor substrate including a trench region and source / drain doped regions, the trench region being spaced apart from the source / drain doped regions; A grid insulating layer is formed on the surface of the trench region; An initial gate structure is formed on the side of the gate insulating layer away from the semiconductor substrate; A sidewall is formed on the periphery of the initial gate structure to obtain the gate structure, wherein the gate structure includes the initial gate structure, the sidewall and the gate insulating layer, and two spaced source and drain doped regions are provided between the orthogonal projections of two adjacent gate structures toward the semiconductor substrate, the source and drain doped regions corresponding to different gate structures are insulated from each other, and each source and drain doped region corresponds to one gate structure; A conductive structure is formed on one side of the semiconductor substrate, the conductive structure being located on the same side of the semiconductor substrate as the initial gate structure, the conductive structure being used to electrically connect two spaced source / drain doped regions located between two adjacent gate structures; The first insulating layer is formed between the periphery of the gate structure, the surface of the gate structure away from the semiconductor substrate, and the adjacent first insulating structure.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The sidewalls consist of a three-layer composite structure, which are silicon nitride sidewalls, silicon oxide sidewalls, and silicon nitride sidewalls in the radial direction of the initial gate structure.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a dielectric layer on the side of the second insulating layer away from the semiconductor substrate includes: A first sub-dielectric layer is formed on the side of the second insulating layer away from the initial semiconductor structure, and the surface of the first sub-dielectric layer away from the initial semiconductor structure is flush with the surface of the gate structure away from the semiconductor substrate; A second sub-dielectric layer is formed on the side of the first sub-dielectric layer away from the initial semiconductor structure, the dielectric layer comprising the first sub-dielectric layer and the second sub-dielectric layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The removal of portions of the first insulating structure and the second insulating structure to obtain a second insulating layer includes: Remove part of the first insulating structure; The second insulating structure is removed by a planarization process.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, Prior to the step of forming a first sub-dielectric layer on the side of the second insulating layer away from the initial semiconductor structure, the method further includes: An initial dielectric layer is formed on the side of the first insulating layer away from the initial semiconductor structure, and the surface of the initial dielectric layer on the side away from the initial semiconductor structure extends beyond the surface of the second insulating structure on the side away from the semiconductor substrate; The removal of the second insulating structure by planarization process includes: A planarization process is used to remove part of the initial dielectric layer and the second insulating structure to obtain the second insulating layer and the first sub-dielectric layer.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The provision of the initial semiconductor structure includes: A pseudo-gate structure is formed on the side of the gate insulating layer of the initial semiconductor structure away from the semiconductor substrate using polycrystalline silicon material. The pseudo-gate structure has the same dimensions as the initial gate structure of the initial semiconductor structure. After the step of removing part of the initial dielectric layer and the second insulating structure through a planarization process to obtain the second insulating layer and the first sub-dielectric layer, the method further includes: Remove the pseudo-gate structure; The gate structure is obtained by filling the space where the pseudo-gate structure is located with metal gate material.

10. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 9.

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