A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The application provides a semiconductor device preparation method and a semiconductor device, relates to the technical field of semiconductor devices, and can reduce the risk of disconnection in a shared contact hole. The method comprises the following steps: providing a semiconductor initial structure, which comprises an insulating layer and spaced gate initial structures, the insulating layer comprises first insulating structures and second insulating structures, the first insulating structures are located on the side of the gate initial structures, the second insulating structures are located between the two first insulating structures, and the first insulating structures have first openings therebetween; forming an etching stop layer on one side of the gate initial structures; forming a first dielectric layer on one side of the second insulating structures; removing the etching stop layer and part of the first insulating structures according to the first dielectric layer, so that the first insulating structures have second openings therebetween, and the opening size of the first openings is smaller than that of the second openings; forming a second dielectric layer on one side of the first dielectric layer and one side of the gate initial structures; and removing part of the first dielectric layer and the second dielectric layer to obtain a shared contact hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] With the advancement and development of semiconductor device technology, the requirements for the fabrication quality and efficiency of semiconductor devices are gradually increasing. For semiconductor devices with shared contact holes, the shared contact holes are used to accommodate shared contact plugs to electrically connect the gate and source / drain regions of the semiconductor device.

[0003] During the formation of a shared contact hole, after etching away the dielectric layer at the corresponding location of the shared contact hole, it is necessary to etch the etch stop layer down the gate sidewall. However, misalignment during the etching process can lead to insufficient spacing between the etch stop layers, or even prevent the etch stop layers from being etched through, affecting the fabrication quality of the shared contact hole. This increases the risk of open circuits in the shared contact hole, further increasing the fabrication difficulty of the semiconductor device, reducing its reliability and stability, and ultimately lowering its yield. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor device and a semiconductor device, which can improve the fabrication quality of shared contact holes, reduce the risk of open circuits in shared contact holes, reduce the fabrication difficulty of semiconductor devices, improve the reliability and stability of semiconductor devices, and increase the yield of semiconductor devices.

[0005] A first aspect of this application provides a method for fabricating a semiconductor device, comprising:

[0006] A semiconductor initial structure is provided, wherein the semiconductor initial structure includes a semiconductor substrate, two spaced-apart gate initial structures and an insulating layer, the insulating layer including a first insulating structure and a second insulating structure, the first insulating structure being located on the periphery of the gate initial structure, the second insulating structure being located between two adjacent first insulating structures, the first insulating structure being connected to the second insulating structure, and a first opening being provided between adjacent first insulating structures;

[0007] An etch stop layer is formed on the side of the initial gate structure away from the semiconductor substrate;

[0008] A first dielectric layer is formed on the side of the second insulating structure away from the semiconductor substrate;

[0009] Based on the first dielectric layer, the etch stop layer and part of the first insulating structure are removed, such that the processed first insulating structure has a second opening, the opening size of the first opening being smaller than the opening size of the second opening;

[0010] A second dielectric layer is formed on the surface of the first dielectric layer away from the semiconductor substrate and on the surface of the initial gate structure away from the semiconductor substrate;

[0011] A portion of the first dielectric layer and the second dielectric layer are removed to obtain a shared contact hole.

[0012] In some embodiments, prior to the step of forming an etch stop layer on the side of the initial gate structure away from the semiconductor substrate, the method further includes:

[0013] By removing a portion of the gate structure, the initial gate structure is obtained, wherein the size of the gate structure is larger than the size of the initial gate structure in the thickness direction of the semiconductor substrate.

[0014] The surface of the first insulating structure away from the semiconductor substrate after processing is flush with the surface of the initial gate structure away from the semiconductor substrate.

[0015] In some embodiments, forming an etch stop layer on the side of the initial gate structure away from the semiconductor substrate and forming a first dielectric layer on the side of the second insulating structure away from the semiconductor substrate includes:

[0016] An initial dielectric layer is formed on the side of the second insulating structure away from the semiconductor substrate, and the surface of the initial dielectric layer on the side away from the semiconductor substrate is flush with the surface of the first insulating structure on the side away from the semiconductor substrate.

[0017] An etch stop layer is formed on the side of the initial gate structure away from the semiconductor substrate, and the surface of the etch stop layer away from the semiconductor substrate is flush with the surface of the first insulating structure away from the semiconductor substrate.

[0018] A portion of the initial dielectric layer is removed to obtain the first dielectric layer, wherein the size of the first dielectric layer is smaller than the size of the initial dielectric layer in the thickness direction of the semiconductor substrate.

[0019] In some embodiments, forming an etch stop layer on the side of the initial gate structure away from the semiconductor substrate includes:

[0020] In the case where there are grooves in the initial dielectric layer, an etch stop layer is formed within the grooves.

[0021] In some embodiments, removing a portion of the initial dielectric layer to obtain the first dielectric layer includes:

[0022] The first dielectric layer is obtained by removing a portion of the initial dielectric layer according to the etch stop layer. The first dielectric layer includes a protrusion structure that corresponds to the etch stop layer in the groove.

[0023] In some embodiments, providing the initial semiconductor structure includes:

[0024] A semiconductor substrate is provided, the semiconductor substrate including a trench region and source / drain doped regions, the trench region being spaced apart from the source / drain doped regions;

[0025] A gate insulation layer is formed on the surface of the trench region;

[0026] A first gate structure is formed on the side of the gate insulating layer away from the semiconductor substrate;

[0027] A sidewall is formed on the periphery of the first gate structure to obtain the initial gate structure, wherein the initial gate structure includes the first gate structure, the sidewall and the gate insulating layer, and two spaced source and drain doped regions are provided between the orthogonal projections of two adjacent initial gate structures toward the semiconductor substrate, the source and drain doped regions corresponding to different initial gate structures are insulated from each other, and each source and drain doped region corresponds to one initial gate structure;

[0028] A conductive structure is formed on one side of the semiconductor substrate, the conductive structure being located on the same side of the semiconductor substrate as the initial gate structure, the conductive structure being used to electrically connect two spaced source / drain doped regions located between two adjacent gate structures;

[0029] The insulating layer is formed on the periphery of the sidewall and between adjacent first gate structures.

[0030] In some embodiments, forming a first gate structure on the side of the gate insulating layer away from the semiconductor substrate includes:

[0031] A second gate structure is formed on the side of the gate insulating layer away from the semiconductor substrate, wherein the size of the second gate structure is larger than the size of the first gate structure in the thickness direction of the semiconductor substrate;

[0032] By removing a portion of the second gate structure, the first gate structure is obtained.

[0033] In some embodiments, forming sidewalls around the periphery of the first gate structure to obtain the initial gate structure includes:

[0034] A dummy gate structure is formed on the side of the gate insulating layer away from the semiconductor substrate using polycrystalline silicon material, wherein the size of the dummy gate structure is equal to the size of the second gate structure in the thickness direction of the semiconductor substrate;

[0035] Sidewalls are formed around the periphery of the pseudo-gate structure;

[0036] Remove the pseudo-gate structure and fill the space where the pseudo-gate structure was located with metal gate material to obtain the second gate structure;

[0037] By removing a portion of the second gate structure, the initial gate structure is obtained.

[0038] In some embodiments, removing portions of the first dielectric layer and the second dielectric layer to obtain a shared contact hole includes:

[0039] The first dielectric layer and the second dielectric layer on the surface of the first gate initial structure away from the semiconductor substrate are removed to obtain the first contact hole;

[0040] The first dielectric layer and the second dielectric layer on the surface of the first insulating structure near the second gate initial structure of the first gate initial structure are removed to obtain the second contact hole;

[0041] Remove the first dielectric layer and the second dielectric layer from the surface of the second insulating structure near one end of the first gate initial structure to obtain a third contact hole;

[0042] The first contact hole, the second contact hole, and the third contact hole are formed synchronously and are connected to each other. The gate initial structure includes the first gate initial structure and the second gate initial structure, which are spaced apart.

[0043] A second aspect of this application provides a semiconductor device fabricated using the semiconductor device fabrication method described in any of the first aspects above.

[0044] An unexpected effect of this application is that by forming an etch stop layer on the side of the initial gate structure away from the semiconductor substrate, the surface of the initial gate structure can be protected. By forming a first dielectric layer on the side of the second insulating structure away from the semiconductor substrate and using the first dielectric layer as a mask to remove part of the first insulating structure to form a second opening, the opening size of the second opening between the processed first insulating structures is larger than the opening size of the first opening between the initial gate structures. This reduces the thickness of the first insulating structure around the initial gate structure, thereby reducing the etching energy required for the insulating structure during the etching of the shared contact hole and shortening the etching time required for the insulating structure. This increases the etching energy of the second insulating structure, and further, in the case of misalignment during the etching of the shared contact hole, it can increase the etching opening of the second insulating structure, reduce the risk of open circuit in the shared contact hole, improve the fabrication quality of the shared contact hole, and thus reduce the etching precision requirements during the fabrication of the shared contact hole, reducing the fabrication difficulty of semiconductor devices. Meanwhile, the stepwise formation of the dielectric layer can further reduce the risk of voids during the dielectric layer deposition process, avoid tungsten leakage in the shared contact hole, reduce the risk of short circuits in the shared contact hole, further improve the fabrication quality of semiconductor devices, enhance the reliability and stability of semiconductor devices, and increase the yield of semiconductor devices. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application;

[0047] Figure 2 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0048] Figure 3 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0049] Figure 4 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0050] Figure 5 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0051] Figure 6 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0052] Figure 7 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0053] Figure 8 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0054] Figure 9 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0055] Figure 10 A schematic structural diagram of a semiconductor device fabrication method provided in this application embodiment;

[0056] Figure 11 This is a schematic structural diagram of a semiconductor device provided in an embodiment of this application.

[0057] Explanation of reference numerals in the attached figures:

[0058] 100 - Initial semiconductor structure, 110 - Semiconductor substrate, 120 - Initial gate structure, 121 - Gate insulating layer, 122 - First gate structure, 123 - Sidewall, 124 - Second gate structure, 130 - Insulating layer, 131 - First insulating structure, 132 - Second insulating structure, 133 - Processed first insulating structure, 140 - Conductive structure, 150 - Gate structure, 200 - Etch stop layer, 300 - First dielectric layer, 301 - Initial dielectric layer, 400 - Second dielectric layer. Detailed Implementation

[0059] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0061] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0062] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0063] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0064] With the advancement and development of semiconductor device technology, the requirements for the fabrication quality and efficiency of semiconductor devices are gradually increasing. For semiconductor devices with shared contact holes, the shared contact holes are used to accommodate shared contact plugs to electrically connect the gate and source / drain regions of the semiconductor device.

[0065] During the formation of shared contact holes, after etching away the dielectric layer at the corresponding location of the shared contact hole, it is necessary to etch down the gate sidewalls to form an etch stop layer. However, misalignment during the etching process can lead to insufficient spacing between the etch stop layers, or even prevent the etch stop layers from being etched through. This increases the risk of open circuits in the shared contact hole, further complicating semiconductor device fabrication, reducing reliability and stability, and ultimately lowering yield. Furthermore, as the linewidth of semiconductor devices decreases, the spacing between adjacent gates also gradually decreases. Therefore, during dielectric layer deposition, deposition voids can easily form between adjacent gates, leading to tungsten leakage within the shared contact hole and causing short circuits in the contact plugs.

[0066] like Figure 1 As shown, a first aspect of this application provides a method for fabricating a semiconductor device, comprising:

[0067] Step S110: Provide a semiconductor initial structure, wherein the semiconductor initial structure includes a semiconductor substrate, two spaced-apart gate initial structures and an insulating layer, the insulating layer includes a first insulating structure and a second insulating structure, the first insulating structure is located on the periphery of the gate initial structure, the second insulating structure is located between two adjacent first insulating structures, the first insulating structure and the second insulating structure are connected, and there is a first opening between adjacent first insulating structures.

[0068] like Figure 2 As shown, a semiconductor initial structure 100 is provided. The semiconductor initial structure 100 includes a semiconductor substrate 110, two spaced-apart gate initial structures 120, and an insulating layer 130. The insulating layer 130 includes a first insulating structure 131 and a second insulating structure 132. A first opening H1 is formed between the first insulating structures 131 on the sidewalls of two adjacent gate initial structures 120. The surface of the first insulating structure 131 on the side away from the semiconductor substrate 110 extends beyond the surface of the gate initial structure 120 on the side away from the semiconductor substrate 110. The material of the insulating layer 130 may include silicon nitride.

[0069] As an example, a first insulating structure 131 and a second insulating structure 132 are formed in the same process step using a chemical deposition process or an atomic layer deposition process, that is, the first insulating structure 131 and the second insulating structure 132 are prepared simultaneously using the same material.

[0070] Step S120: An etch stop layer is formed on the side of the initial gate structure 120 away from the semiconductor substrate 110.

[0071] like Figure 3 As shown, an etch stop layer 200 is formed on the gate initial structure 120 using a chemical deposition process or an atomic layer deposition process; wherein, the etch stop layer 200 is located on the side of the gate initial structure 120 away from the semiconductor substrate 110, and the etch stop layer 200 is located inside the first insulating structure 131, that is, the first insulating structure 131 surrounds the periphery of the etch stop layer 200.

[0072] Step S130: A first dielectric layer is formed on the side of the second insulating structure 132 away from the semiconductor substrate 110.

[0073] like Figure 4 As shown, a first dielectric layer 300 is formed on the side of the second insulating structure 132 away from the semiconductor substrate 110 using deposition and etching processes, such as chemical deposition or atomic layer deposition, wet etching, and / or dry etching. The surface of the first insulating structure 131 on the side away from the semiconductor substrate 110 extends beyond the surface of the first dielectric layer 300 on the side away from the semiconductor substrate 110. As an example, the material of the first dielectric layer 300 includes silicon oxide.

[0074] Step S140: Based on the first dielectric layer, remove the etch stop layer 200 and part of the first insulating structure 131, so that the processed first insulating structure has a second opening, the opening size of the first opening H1 is smaller than the opening size of the second opening H2.

[0075] like Figure 5 As shown, as an example, using the first dielectric layer 300 as a mask, an etching process, such as a wet etching process or / and a dry etching process, is used to etch away the etch stop layer 200 on the gate initial structure 120, exposing the gate initial structure 120, and to etch away part of the first insulating structure 131 to form the processed first insulating structure 133; wherein, there is a second opening H2 between the processed first insulating structures 133 of two adjacent gate initial structures 120 sidewalls.

[0076] For example, the opening size of the second opening H2 on the side away from the semiconductor substrate 110 can be larger than the opening size of the first opening H1, the opening size of the second opening H2 on the side closer to the semiconductor substrate 110 can be larger than the opening size of the first opening H1, and the opening size of the second opening H2 at any position in the thickness direction of the semiconductor substrate 110 can be larger than the opening size of the first opening H1. The cross-sectional shape of the second opening H2 in the direction perpendicular to the semiconductor substrate 110 can be trapezoidal, rectangular, etc.

[0077] Step S150: A second dielectric layer is formed on the surface of the first dielectric layer 300 away from the semiconductor substrate 110 and on the surface of the gate initial structure 120 away from the semiconductor substrate 110.

[0078] like Figure 6 As shown, as an example, a second dielectric layer 400 is formed on the surface of the first dielectric layer 300 away from the semiconductor substrate 110 using a chemical deposition process or an atomic layer deposition process. The second dielectric layer 400 extends along the sidewall of the second opening H2 to the gate initial structure 120. That is, the second dielectric layer 400 is located on the surface of the first dielectric layer 300 away from the semiconductor substrate 110 and on the side of the gate initial structure 120 away from the semiconductor substrate 110.

[0079] Step S160: Remove part of the first dielectric layer 300 and the second dielectric layer 400 to obtain the shared contact hole CT.

[0080] As an example, an etching process, such as a dry etching process or a wet etching process, is used to etch away part of the first dielectric layer 300 and part of the second dielectric layer 400 to form a shared contact hole CT.

[0081] An unexpected effect of this application is that by forming an etch stop layer 200 on the side of the initial gate structure 120 away from the semiconductor substrate 110, the surface of the initial gate structure 120 can be protected. By forming a first dielectric layer 300 on the side of the second insulating structure 132 away from the semiconductor substrate 110, and using the first dielectric layer 300 as a mask to remove part of the first insulating structure 131 to form a second opening H2, the opening size of the second opening H2 between the processed first insulating structures 133 is larger than the opening size of the first opening H1 between the initial gate structures 120. This reduces the thickness of the first insulating structure 131 around the initial gate structure 120, thereby reducing the etching energy required for the insulating structure portion during the shared contact hole CT etching process and shortening the etching time required for the insulating structure. This increases the etching energy of the second insulating structure 132, and further, in the case of misalignment during shared contact hole CT etching, it can increase the etching opening of the second insulating structure 132, reduce the risk of open circuit within the shared contact hole CT, improve the fabrication quality of the shared contact hole CT, and thus reduce the requirements for etching precision during the fabrication of the shared contact hole CT, reducing the fabrication difficulty of semiconductor devices. Meanwhile, the stepwise formation of the dielectric layer can further reduce the risk of voids during the dielectric layer deposition process, avoid tungsten leakage in the shared contact hole CT, reduce the risk of short circuits in the shared contact hole CT, further improve the fabrication quality of semiconductor devices, enhance the reliability and stability of semiconductor devices, and increase the yield of semiconductor devices.

[0082] In some embodiments, before forming the etch stop layer 200 on the side of the gate initial structure 120 away from the semiconductor substrate 110, the method further includes: removing a portion of the gate structure 150 to obtain the gate initial structure 120, wherein the size of the gate structure 150 is larger than the size of the gate initial structure 120 in the thickness direction of the semiconductor substrate 110; and the surface of the processed first insulating structure 133 on the side away from the semiconductor substrate 110 is flush with the surface of the gate initial structure 120 on the side away from the semiconductor substrate 110.

[0083] like Figure 2 and Figure 7 As shown, a semiconductor substrate 110 is provided, and a gate structure 150 and an insulating layer 130 are formed on one side of the semiconductor substrate 110 at intervals. In the thickness direction of the semiconductor substrate 110, the surface of the gate structure 150 away from the semiconductor substrate 110 is flush with the surface of the first insulating structure 131 away from the semiconductor substrate 110. An etching process is used to etch away a portion of the thickness of the gate structure 150 between the first insulating structures 131, forming an initial gate structure 120. For example, the surface of the etch stop layer 200 away from the semiconductor substrate 110 is flush with the surface of the first insulating structure 131 away from the semiconductor substrate 110. A portion of the first insulating structure 131 is etched away, and the surface of the processed first insulating structure 133 away from the semiconductor substrate 110 is flush with the surface of the initial gate structure 120 away from the semiconductor substrate 110.

[0084] The semiconductor device fabrication method provided in this application embodiment, by first forming a gate structure 150 with a relatively large thickness, facilitates the formation of a first insulating structure 131 whose surface away from the semiconductor substrate 110 exceeds the surface of the initial gate structure 120 away from the semiconductor substrate 110. This facilitates control over the formation of the etch stop layer 200, preventing the etch stop layer 200 from covering the surface of the first insulating structure 131 and being difficult to remove, thus affecting the etching of the first insulating structure 131. Therefore, it can improve the formation quality of the second opening H2, further reduce the etching energy required for the insulating structure portion during the etching of the shared contact hole CT, increase the etching energy of the second insulating structure 132, improve the semiconductor device's resistance to misalignment during fabrication, reduce the risk of open circuits within the shared contact hole CT, improve the fabrication quality of the shared contact hole CT, further reduce the risk of voids generated during dielectric layer deposition, reduce the risk of tungsten leakage within the shared contact hole CT, reduce the risk of short circuits within the shared contact hole CT, improve the fabrication quality of the semiconductor device, enhance the reliability and stability of the semiconductor device, and increase the yield of the semiconductor device.

[0085] In some embodiments, an etch stop layer 200 is formed on the side of the initial gate structure 120 away from the semiconductor substrate 110, and a first dielectric layer 300 is formed on the side of the second insulating structure 132 away from the semiconductor substrate 110. This includes: forming an initial dielectric layer 301 on the side of the second insulating structure 132 away from the semiconductor substrate 110, wherein the surface of the initial dielectric layer 301 on the side away from the semiconductor substrate 110 is flush with the surface of the first insulating structure 131 on the side away from the semiconductor substrate 110; forming an etch stop layer 200 on the side of the initial gate structure 120 away from the semiconductor substrate 110, wherein the surface of the etch stop layer 200 on the side away from the semiconductor substrate 110 is flush with the surface of the first insulating structure 131 on the side away from the semiconductor substrate 110; and removing a portion of the initial dielectric layer 301 to obtain the first dielectric layer 300, wherein the size of the first dielectric layer 300 is smaller than the size of the initial dielectric layer 301 in the thickness direction of the semiconductor substrate 110.

[0086] like Figure 8 As shown, as an example, an initial dielectric layer 301 is formed on the side of the second insulating structure 132 away from the semiconductor substrate 110 using a chemical vapor deposition process or an atomic layer deposition process; wherein, the surface of the initial dielectric layer 301 away from the semiconductor substrate 110 is flush with the surface of the first insulating structure 131 away from the semiconductor substrate 110, and the surface of the initial dielectric layer 301 away from the semiconductor substrate 110 may be flush with the surface of the etch stop layer 200 away from the semiconductor substrate 110; an etch stop layer 200 is formed on the side of the gate initial structure 120 away from the semiconductor substrate 110.

[0087] For example, the first dielectric layer 300 can be obtained by removing the etch stop layer 200 and a portion of the initial dielectric layer 301 through a planarization process. The surface of the initial dielectric layer 301 on the side away from the semiconductor substrate 110 may extend beyond the surface of the etch stop layer 200 on the side away from the semiconductor substrate 110.

[0088] The semiconductor device fabrication method provided in this application embodiment, by setting the surface of the initial dielectric layer 301 away from the semiconductor substrate 110 to be flush with the surface of the first insulating structure 131 away from the semiconductor substrate 110, can avoid the etch stop layer 200 being formed in the first opening H1, which would make the etch stop layer 200 on the surface of the initial dielectric layer 301 difficult to remove. In the case where the etch stop layer 200 is formed on the surface of the initial dielectric layer 301, the etch stop layer 200 on the surface of the initial dielectric layer 301 can be removed by a planarization process based on the first insulating structure 131, thereby improving the fabrication quality of the etch stop layer 200. Simultaneously, it can improve the surface uniformity of the initial dielectric layer 301, further improve the formation quality of the first dielectric layer 300, further improve the preparation quality of the second opening H2, and thus, in the case of misalignment in the etching of the shared contact hole CT, increase the etching opening of the second insulating structure 132, reduce the risk of open circuit in the shared contact hole CT, improve the preparation quality of the shared contact hole CT, thereby reducing the requirements for etching precision during the preparation of the shared contact hole CT, reducing the difficulty of semiconductor device preparation, and further reducing the risk of voids generated during dielectric layer deposition, avoiding tungsten leakage in the shared contact hole CT, reducing the risk of short circuit in the shared contact hole CT, improving the preparation quality of semiconductor devices, improving the reliability and stability of semiconductor devices, and increasing the yield of semiconductor devices.

[0089] In some embodiments, an etch stop layer 200 is formed on the side of the initial gate structure 120 away from the semiconductor substrate 110, including: forming the etch stop layer 200 in the groove if there is a groove in the initial dielectric layer 301.

[0090] like Figure 9 As shown, as an example, using chemical vapor deposition or atomic layer deposition, an etch stop layer 200 is formed on the side of the initial gate structure 120 away from the semiconductor substrate 110, and the etch stop layer 200 extends onto the initial dielectric layer 301; wherein, the surface of the etch stop layer 200 away from the semiconductor substrate 110 exceeds the surface of the first insulating structure 131 away from the semiconductor substrate 110; wherein, the initial dielectric layer 301 has grooves, and the etch stop layer 200 fills the grooves; a planarization process is used to remove the portion of the etch stop layer 200 that extends beyond the first insulating structure 131, forming an etch stop layer 200 flush with the first insulating structure 131, and the etch stop layer 200 has protrusions corresponding to the grooves.

[0091] It should be noted that the opening size of the first opening H1 is relatively small, which can easily lead to deposition voids in the initial dielectric layer 301. In the case of grooves within the initial dielectric layer 301, during the removal of part of the initial dielectric layer 301, the grooves may cause over-etching of the initial dielectric layer 301, resulting in damage to the first dielectric layer 300, further damaging the second insulating structure 132, leading to a reduction in the formation quality of the shared contact hole CT, and affecting the electrical performance of the semiconductor device.

[0092] The semiconductor device fabrication method provided in this application embodiment can improve the morphological integrity of the second insulating structure 132 by filling the initial dielectric layer 301 with voids with an etch stop layer 200, further improving the etching effect of the shared contact hole CT, avoiding damage to the initial semiconductor structure 100, thereby improving the electrical performance of the semiconductor device, further improving the fabrication quality of the semiconductor device, reducing the fabrication difficulty of the semiconductor device, and increasing the yield of the semiconductor device.

[0093] In some embodiments, a portion of the initial dielectric layer 301 is removed to obtain a first dielectric layer 300, including:

[0094] A portion of the initial dielectric layer 301 is removed from the etch stop layer 200 to obtain a first dielectric layer 300. The first dielectric layer 300 includes a protrusion structure that corresponds to the etch stop layer 200 in the groove.

[0095] like Figure 10 As shown, using the etch stop layer 200 as a mask, an etching process is employed to etch away part of the initial dielectric layer 301 to form a first dielectric layer 300; wherein, the first dielectric layer 300 includes a protrusion structure corresponding to the protrusion of the etch stop layer 200.

[0096] It should be noted that, based on the phenomenon of grooves being generated within the initial medium layer 301, the locations corresponding to the grooves can be considered as areas prone to depositing voids.

[0097] The semiconductor device fabrication method provided in this application provides a method for pre-filling areas prone to deposited voids in the first opening H1 by forming a protrusion structure in the first dielectric layer 300 corresponding to the groove in the initial dielectric layer 301. This reduces the risk of voids in the second dielectric layer 400 during its formation, avoids tungsten leakage in the shared contact hole CT, reduces the risk of short circuits in the shared contact hole CT, further improves the fabrication quality of the semiconductor device, enhances its reliability and stability, and increases its yield.

[0098] In some embodiments, providing a semiconductor initial structure 100 includes: providing a semiconductor substrate 110, the semiconductor substrate 110 including a trench region and source / drain doped regions, the trench region and the source / drain doped regions being spaced apart; forming a gate insulating layer 121 on the surface of the trench region; forming a first gate structure 122 on the side of the gate insulating layer 121 away from the semiconductor substrate 110; forming a sidewall 123 on the periphery of the first gate structure 122, thereby obtaining a gate initial structure 120, wherein the gate initial structure 120 includes the first gate structure 122, the sidewall 123 and the gate insulating layer 121, and two adjacent gate initial structures 120 are oriented towards... The semiconductor substrate 110 has two spaced-apart source / drain doped regions between its orthographic projections, which are insulated from the source / drain doped regions of different gate initial structures 120. Each source / drain doped region corresponds to one gate initial structure 120. A conductive structure 140 is formed on one side of the semiconductor substrate 110. The conductive structure 140 and the gate initial structure 120 are located on the same side of the semiconductor substrate 110. The conductive structure 140 is used to electrically connect the two spaced-apart source / drain doped regions located between two adjacent gate structures 150. An insulating layer 130 is formed on the periphery of the sidewall 123 and between adjacent first gate structures 122.

[0099] As an example, a gate insulating material layer is formed on one side of the semiconductor substrate 110 using a deposition process. The gate insulating material layer is then patterned and etched, leaving the gate insulating material layer in the trench region as the gate insulating layer 121. A first gate structure 122 is formed on the side of the gate insulating layer 121 away from the semiconductor substrate 110 using a deposition process. Sidewalls 123 are formed around the first gate structure 122 using a deposition process, resulting in an initial gate structure 120.

[0100] The semiconductor device fabrication method provided in this application embodiment, by setting the initial gate structure 120 to be insulated from the source and drain doped regions, can drive the formation of channels in the trench region by applying driving power to the initial gate structure 120, so that the adjacent source and drain regions are connected. This can avoid the voltage change on the initial gate structure 120 from affecting the electrical performance of the semiconductor device and improve the conduction quality of the semiconductor device.

[0101] In some embodiments, forming a first gate structure 122 on the side of the gate insulating layer 121 away from the semiconductor substrate 110 includes: forming a second gate structure 124 on the side of the gate insulating layer 121 away from the semiconductor substrate 110, wherein the size of the second gate structure 124 is larger than the size of the first gate structure 122 in the thickness direction of the semiconductor substrate 110; and removing a portion of the second gate structure 124 to obtain the first gate structure 122.

[0102] like Figure 7 and Figure 8As shown, a deposition process is used to form a second gate structure 124 on the side of the gate insulating layer 121 away from the semiconductor substrate 110. The surface of the second gate structure 124 away from the semiconductor substrate 110 is flush with the surface of the first insulating structure 131 away from the semiconductor substrate 110. An etching process is used to etch away a portion of the thickness of the second gate structure 124, forming the remaining first gate structure 122 composed of the second gate structure 124. The size of the second gate structure 124 is larger than the size of the first gate structure 122 in the thickness direction of the semiconductor substrate 110.

[0103] The semiconductor device fabrication method provided in this application, by first forming a second gate structure 124 with a relatively large thickness, facilitates the formation of a first insulating structure 131 whose surface away from the semiconductor substrate 110 exceeds the surface of the initial gate structure 120 away from the semiconductor substrate 110, reducing the fabrication difficulty of the first insulating structure 131 and the etch stop layer 200. This, in turn, improves the formation quality of the second opening H2, enhances the fabrication quality of the shared contact hole CT, improves the reliability and stability of the semiconductor device, and increases the yield of the semiconductor device.

[0104] In some embodiments, a sidewall 123 is formed on the periphery of the first gate structure 122 to obtain an initial gate structure 120, including: forming a dummy gate structure on the side of the gate insulating layer 121 away from the semiconductor substrate 110 using polysilicon material, wherein the size of the dummy gate structure is equal to the size of the second gate structure 124 in the thickness direction of the semiconductor substrate 110; forming a sidewall 123 on the periphery of the dummy gate structure; removing the dummy gate structure and filling the space where the dummy gate structure is located with metal gate material to obtain the second gate structure 124; and removing a portion of the second gate structure 124 to obtain the initial gate structure 120.

[0105] As an example, a deposition process is used to sequentially form a gate insulating material layer and a polysilicon material on one side of a semiconductor substrate 110, with the polysilicon material formed on the side of the gate insulating material layer away from the semiconductor substrate 110. The polysilicon material and the gate insulating material layer are patterned and etched, retaining the polysilicon material and the gate insulating material layer in the trench region, resulting in a pseudo-gate structure composed of the remaining polysilicon material and a gate insulating layer 121 composed of the remaining gate insulating material layer. A deposition and etching process is used to form sidewalls 123 around the pseudo-gate structure, with the sidewalls 123 in contact with the pseudo-gate structure. An etching process is used to remove the pseudo-gate structure. A deposition process, such as chemical vapor deposition or atomic layer deposition, is used to fill the space containing the pseudo-gate structure with a metal gate material, forming a second gate structure 124. The surface of the second gate structure 124 away from the semiconductor substrate 110 is flush with the surface of the first insulating structure 131 away from the semiconductor substrate 110. An etching process is used to etch away part of the thickness of the second gate structure 124 to obtain the initial gate structure 120.

[0106] As an example, the second gate structure 124 with a certain thickness is etched away, and the sidewall 123 with a certain thickness is etched away, resulting in a sidewall 123 that is flush with the initial gate structure 120.

[0107] The semiconductor device fabrication method provided in this application embodiment uses a pseudo-gate structure to occupy space first, which can avoid damage to the initial gate structure 120 during the fabrication process, thereby further improving the electrical performance, reliability and stability of the semiconductor device, and yield of the semiconductor device.

[0108] In some embodiments, removing portions of the first dielectric layer 300 and the second dielectric layer 400 to obtain a shared contact hole includes: using an etching process to etch and remove the first dielectric layer 300 and the second dielectric layer 400 on the surface of the first gate initial structure away from the semiconductor substrate 110 to obtain a first contact hole; using an etching process to etch and remove the first dielectric layer 300 and the second dielectric layer 400 on the surface of the first insulating structure 131 near the second gate initial structure to obtain a second contact hole; using an etching process to etch and remove the first dielectric layer 300 and the second dielectric layer 400 on the surface of the second insulating structure 132 near one end of the first gate initial structure to obtain a third contact hole; wherein the first contact hole, the second contact hole, and the third contact hole are formed simultaneously and are interconnected, and the gate initial structure 120 includes a first gate initial structure and a second gate initial structure, which are spaced apart.

[0109] The semiconductor device fabrication method provided in this application embodiment can expose the initial gate structure and the source / drain region in the semiconductor substrate 110 by sequentially etching the second dielectric layer 400 and the first dielectric layer 300. This allows the source / drain region to be electrically connected to the gate by setting contact plugs in the shared contact hole CT, thereby improving the electrical performance of the semiconductor device.

[0110] like Figure 11 As shown, in a second aspect of the present application, a semiconductor device is provided, which is fabricated using any of the semiconductor device fabrication methods described in the first aspect above.

[0111] An unexpected effect of this application is that by forming an etch stop layer 200 on the side of the initial gate structure 120 away from the semiconductor substrate 110, the surface of the initial gate structure 120 can be protected. By forming a first dielectric layer 300 on the side of the second insulating structure 132 away from the semiconductor substrate 110, and using the first dielectric layer 300 as a mask to remove part of the first insulating structure 131 to form a second opening H2, the opening size of the second opening H2 between the processed first insulating structures 133 is larger than the opening size of the first opening H1 between the initial gate structures 120. This reduces the thickness of the first insulating structure 131 around the initial gate structure 120, thereby reducing the etching energy required for the insulating structure portion during the shared contact hole CT etching process and shortening the etching time required for the insulating structure. This increases the etching energy of the second insulating structure 132, and further, in the case of misalignment during shared contact hole CT etching, it can increase the etching opening of the second insulating structure 132, reduce the risk of open circuit within the shared contact hole CT, improve the fabrication quality of the shared contact hole CT, and thus reduce the requirements for etching precision during the fabrication of the shared contact hole CT, reducing the fabrication difficulty of semiconductor devices. Meanwhile, the stepwise formation of the dielectric layer can further reduce the risk of voids during the dielectric layer deposition process, avoid tungsten leakage in the shared contact hole CT, reduce the risk of short circuits in the shared contact hole CT, further improve the fabrication quality of semiconductor devices, enhance the reliability and stability of semiconductor devices, and increase the yield of semiconductor devices.

[0112] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor initial structure is provided, wherein the semiconductor initial structure includes a semiconductor substrate, an insulating layer, and a gate initial structure disposed at intervals. The insulating layer includes a first insulating structure and a second insulating structure. The first insulating structure is located on the periphery of the gate initial structure, and the second insulating structure is located between two adjacent first insulating structures. The first insulating structure and the second insulating structure are connected, and a first opening is provided between adjacent first insulating structures. An etch stop layer is formed on the side of the initial gate structure away from the semiconductor substrate; A first dielectric layer is formed on the side of the second insulating structure away from the semiconductor substrate; the surface of the first insulating structure on the side away from the semiconductor substrate extends beyond the surface of the first dielectric layer on the side away from the semiconductor substrate. Using the first dielectric layer as a mask, the etch stop layer and part of the first insulating structure are removed, so that the processed first insulating structure has a second opening, the opening size of the first opening is smaller than the opening size of the second opening; A second dielectric layer is formed on the surface of the first dielectric layer away from the semiconductor substrate and on the surface of the initial gate structure away from the semiconductor substrate; A portion of the first dielectric layer and the second dielectric layer are removed to obtain a shared contact hole.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Prior to the step of forming an etch stop layer on the side of the initial gate structure away from the semiconductor substrate, the method further includes: By removing a portion of the gate structure, the initial gate structure is obtained, wherein the size of the gate structure is larger than the size of the initial gate structure in the thickness direction of the semiconductor substrate. The surface of the first insulating structure away from the semiconductor substrate after processing is flush with the surface of the initial gate structure away from the semiconductor substrate.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming an etch stop layer on the side of the initial gate structure away from the semiconductor substrate and forming a first dielectric layer on the side of the second insulating structure away from the semiconductor substrate includes: An initial dielectric layer is formed on the side of the second insulating structure away from the semiconductor substrate, and the surface of the initial dielectric layer on the side away from the semiconductor substrate is flush with the surface of the first insulating structure on the side away from the semiconductor substrate. An etch stop layer is formed on the side of the initial gate structure away from the semiconductor substrate, and the surface of the etch stop layer away from the semiconductor substrate is flush with the surface of the first insulating structure away from the semiconductor substrate. A portion of the initial dielectric layer is removed to obtain the first dielectric layer, wherein the size of the first dielectric layer is smaller than the size of the initial dielectric layer in the thickness direction of the semiconductor substrate.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming an etch stop layer on the side of the initial gate structure away from the semiconductor substrate includes: In the case where there are grooves in the initial dielectric layer, an etch stop layer is formed within the grooves.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The step of removing a portion of the initial dielectric layer to obtain the first dielectric layer includes: The first dielectric layer is obtained by removing a portion of the initial dielectric layer according to the etch stop layer. The first dielectric layer includes a protrusion structure that corresponds to the etch stop layer in the groove.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The provision of the initial semiconductor structure includes: A semiconductor substrate is provided, the semiconductor substrate including a trench region and source / drain doped regions, the trench region being spaced apart from the source / drain doped regions; A grid insulating layer is formed on the surface of the trench region; A first gate structure is formed on the side of the gate insulating layer away from the semiconductor substrate; A sidewall is formed on the periphery of the first gate structure to obtain the initial gate structure, wherein the initial gate structure includes the first gate structure, the sidewall and the gate insulating layer, and two spaced source and drain doped regions are provided between the orthogonal projections of two adjacent initial gate structures toward the semiconductor substrate, the source and drain doped regions corresponding to different initial gate structures are insulated from each other, and each source and drain doped region corresponds to one initial gate structure; A conductive structure is formed on one side of the semiconductor substrate, the conductive structure being located on the same side of the semiconductor substrate as the initial gate structure, the conductive structure being used to electrically connect two spaced source / drain doped regions located between two adjacent gate structures; The insulating layer is formed on the periphery of the sidewall and between adjacent first gate structures.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The formation of a first gate structure on the side of the gate insulating layer away from the semiconductor substrate includes: A second gate structure is formed on the side of the gate insulating layer away from the semiconductor substrate, wherein the size of the second gate structure is larger than the size of the first gate structure in the thickness direction of the semiconductor substrate; By removing a portion of the second gate structure, the first gate structure is obtained.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The step of forming a sidewall around the periphery of the first gate structure to obtain the initial gate structure includes: A dummy gate structure is formed on the side of the gate insulating layer away from the semiconductor substrate using polycrystalline silicon material, wherein the size of the dummy gate structure is equal to the size of the second gate structure in the thickness direction of the semiconductor substrate; Sidewalls are formed around the periphery of the pseudo-gate structure; Remove the pseudo-gate structure and fill the space where the pseudo-gate structure was located with metal gate material to obtain the second gate structure; By removing a portion of the second gate structure, the initial gate structure is obtained.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of removing portions of the first dielectric layer and the second dielectric layer to obtain a shared contact hole includes: The first dielectric layer and the second dielectric layer on the surface of the first gate initial structure away from the semiconductor substrate are removed to obtain the first contact hole; The first dielectric layer and the second dielectric layer on the surface of the first insulating structure near the second gate initial structure of the first gate initial structure are removed to obtain the second contact hole; Remove the first dielectric layer and the second dielectric layer from the surface of the second insulating structure near one end of the first gate initial structure to obtain a third contact hole; The first contact hole, the second contact hole, and the third contact hole are formed synchronously and are connected to each other. The gate initial structure includes the first gate initial structure and the second gate initial structure, which are spaced apart.

10. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 9.

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