A method for manufacturing a micro light emitting diode array and a chip

Abstract

The application provides a micro light emitting diode array chip preparation method and chip, relates to the micro light emitting diode display technical field, and comprises the following steps: preparing two mask arrays on the upper surface of a micro light emitting diode epitaxial wafer, and dividing the micro light emitting diode epitaxial wafer into isolated areas, protection areas and pixel areas according to the coverage range; implementing ion implantation, so that the ion implantation impurity concentration of the isolated areas, the protection areas and the pixel areas decreases in turn; removing the two mask arrays; removing the P-type conductive layer and the light emitting layer of the non-light emitting area, and preparing a P-type electrode layer and an N-type electrode layer on the P-type conductive layer of the light emitting area and the N-type conductive layer of the non-light emitting area respectively; and cutting to obtain a micro light emitting diode array chip. The application realizes the partition ion implantation of the micro light emitting diode epitaxial wafer through a dielectric layer and a metal composite mask structure, and solves the problem that the traditional ion implantation process cannot simultaneously control the depth distribution and lateral extension of ion implantation impurities.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of micro light emitting diode display, and in particular to a preparation method of a micro light emitting diode array chip and the chip. BACKGROUND

[0002] Micro light emitting diode display technology has the characteristic of pixel self-luminous, and has broad application prospects in virtual reality / augmented reality display, consumer electronics, vehicle-mounted display, television, wearable display and large-screen display and the like application fields due to its excellent color rendering performance, high resolution, excellent reliability, low energy consumption, fast response speed and long working life.

[0003] Generally, etching process is adopted to realize pixelization of the micro light emitting diode array, but the etching process will cause structure damage and defects on the pixel sidewall, resulting in increased non-radiative recombination of carriers. In order to suppress the performance degradation caused by such damage, a complex sidewall passivation process is usually introduced to improve the photoelectric performance and reliability of the micro light emitting diode array chip.

[0004] As an optional scheme for realizing pixelization of the micro light emitting diode, ion implantation process can effectively avoid the sidewall damage caused by the traditional etching process, so as to realize pixelization of the low-damage micro light emitting diode array. However, after ion implantation, the impurities in the material are in a "pear-shaped distribution", which is difficult to accurately control the depth distribution and lateral expansion of the impurities by optimizing the implantation parameters. This leads to the problems of excessive ion implantation and damage to the quantum well structure while pursuing good insulation effect, and it is difficult to balance the pixel isolation effect and light emitting performance. Therefore, the ion implantation pixelization process still faces the challenges of process optimization and performance balance in realizing high-performance micro light emitting diode array chips. SUMMARY

[0005] The purpose of the present application is to provide a micro light emitting diode array chip preparation method and chip, which realizes the coordinated regulation of the depth distribution and lateral expansion of ion implantation impurities by using a dielectric layer and a metal composite mask structure to realize the partition ion implantation of the micro light emitting diode epitaxial wafer.

[0006] To achieve the above purpose, the present application provides the following solutions:

[0007] A micro light emitting diode array chip preparation method, comprising:

[0008] growing a buffer layer, an N-type conductive layer, a light emitting layer and a P-type conductive layer on a substrate in sequence to obtain a micro light emitting diode epitaxial wafer;

[0009] preparing a periodic dielectric layer array on the upper surface of the micro light emitting diode epitaxial wafer to obtain a first mask array;

[0010] preparing an array of metal layers with a periodic distribution on the first mask array to obtain a second mask array; the second mask array and the first mask array have the same arrangement mode, and each unit of the second mask array is located within a corresponding unit of the first mask array;

[0011] dividing the micro-LED epitaxial wafer into an isolation region, a protection region and a pixel region according to the first mask array and the second mask array; the isolation region is a region not covered by the first mask array and the second mask array, the protection region is a region only covered by the first mask array, and the pixel region is a region covered by the first mask array and the second mask array;

[0012] performing ion implantation on the micro-LED epitaxial wafer with the first mask array and the second mask array as masks, so that the ion implantation impurity concentration of the isolation region, the protection region and the pixel region decreases in turn, and the resistivity of the P-type conductive layer of the isolation region, the protection region and the pixel region decreases in turn after ion implantation;

[0013] removing the first mask array and the second mask array to obtain a micro-LED array; and dividing the micro-LED array into a non-light-emitting region and a plurality of light-emitting regions, each of the light-emitting regions comprising at least one pixel region;

[0014] removing the P-type conductive layer and the light-emitting layer of the non-light-emitting region to expose the N-type conductive layer; and preparing a P-type electrode layer and an N-type electrode layer on the P-type conductive layer of the light-emitting region and the N-type conductive layer of the non-light-emitting region, respectively;

[0015] cutting the micro-LED array to obtain a micro-LED array chip, each of the micro-LED array chips comprising one light-emitting region.

[0016] Optionally, the substrate is any one of a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon substrate, a silicon carbide substrate, a gallium oxide substrate, a gallium nitride composite template and an aluminum nitride composite template; the buffer layer is a stack of one or more of InN, GaN, AlN, InGaN and AlGaN; the N-type conductive layer is a stack of one or more of N-type conductive InN, GaN, AlN, InGaN and AlGaN; the light-emitting layer is a periodic multi-quantum well structure composed of two or more of InN, GaN, AlN, InGaN and AlGaN; and the P-type conductive layer is a stack of one or more of P-type conductive InN, GaN, AlN, InGaN and AlGaN.

[0017] Optionally, the first mask array is a dielectric layer array, and the dielectric layer array is a stack of one or more of SiO2, TiO2, ZrO2, SiN, Al2O3, AlN, Ta2O5, HfO2, ZnO, ITO. x Optionally, the second mask array is a metal layer array, and the metal layer array is a stack of one or more of Au, W, Ti, Ni, Al, Pt, Pd, Ag, Cu, and Cr.

[0018] Optionally, the size of a unit in the first mask array ranges from 0.1 to 1000 μm, and the pitch of units in the first mask array ranges from 0.1 to 1000 μm; the size of a unit in the second mask array ranges from 0.01 to 100 μm, and the pitch of units in the second mask array ranges from 0.1 to 1000 μm.

[0019] Optionally, the number of pixel regions in the light-emitting region ranges from 1 to 10. 6

[0020] Optionally, the P-type electrode layer covers all of the light-emitting region or only covers the pixel regions in the light-emitting region.

[0021] The application further provides a micro light-emitting diode array chip, which comprises a micro light-emitting diode array and an electrode layer.

[0022] The micro light-emitting diode array comprises, from top to bottom, a P-type conductive layer, a light-emitting layer, an N-type conductive layer, a buffer layer, and a substrate; the P-type conductive layer, the light-emitting layer, the N-type conductive layer, the buffer layer, and the substrate are in a mesa shape, wherein the mesa size of the P-type conductive layer and the light-emitting layer is smaller than the mesa size of the N-type conductive layer, the buffer layer, and the substrate; the P-type conductive layer comprises an isolation region, a protection region, and a pixel region; the pixel region is arranged in a periodic array, the protection region is located between the isolation region and the pixel region, and the resistivity of the isolation region, the protection region, and the pixel region decreases in turn.

[0023] The electrode layer comprises a P-type electrode layer and an N-type electrode layer; the P-type electrode layer is arranged on the P-type conductive layer and covers all of the P-type conductive layer or only covers the pixel regions in the P-type conductive layer; the N-type electrode layer is arranged on the N-type conductive layer and is distributed around the P-type conductive layer and the light-emitting layer.

[0024] Optionally, the micro light-emitting diode array chip is prepared by the aforementioned micro light-emitting diode array preparation method.

[0025] ​The application discloses the following technical effects: the application provides a preparation method and a chip of a micro light emitting diode array, and through a dielectric layer and a metal composite mask structure, an isolation area, a protection area and a pixel area are formed on the surface of a micro light emitting diode epitaxial wafer, so that the partition ion implantation of the micro light emitting diode epitaxial wafer is realized, and the problem that the traditional ion implantation process cannot simultaneously control the depth distribution and lateral extension of ion implantation impurities is solved. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1 A preparation flowchart of the micro light emitting diode array chip provided by the embodiment of the present application is shown in the figure.

[0028] Figure 2 A cross-sectional schematic view (left) and a top view schematic view (right) of the sample structure after the first mask array preparation of the embodiment of the present application are shown in the figure.

[0029] Figure 3 A cross-sectional schematic view (left) and a top view schematic view (right) of the sample structure after the second mask array preparation of the embodiment of the present application are shown in the figure.

[0030] Figure 4 A cross-sectional schematic view of the sample structure after the ion implantation process of the embodiment of the present application is shown in the figure.

[0031] Figure 5 A cross-sectional schematic view (left) and a top view schematic view (right) of the sample structure after the first mask array and the second mask array are removed in the embodiment of the present application are shown in the figure.

[0032] Figure 6 A cross-sectional schematic view (left) and a top view schematic view (right) of the sample structure after the preparation of the P-type electrode layer and the N-type electrode layer of the embodiment of the present application are shown in the figure.

[0033] Figure 7 A cross-sectional schematic view of the micro light emitting diode array chip provided by the embodiment of the present application is shown in the figure.

[0034] Explanation of reference signs:

[0035] 101-substrate, 102-buffer layer, 103-N-type conductive layer, 104-light emitting layer, 105-P-type conductive layer, 201-first mask array, 301-second mask array, 401-isolation region, 402-protection region, 403-pixel region, 501-light emitting region, 601-P-type electrode layer, 602-N-type electrode layer. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0037] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0038] Figure 1 The preparation flowchart of the micro light emitting diode array chip provided by the embodiments of the present application is shown in FIG. 1, and the present application provides a preparation method of a micro light emitting diode array chip, which comprises the following steps: Figure 1 The preparation flowchart of the micro light emitting diode array chip provided by the embodiments of the present application is shown in FIG. 1, and the present application provides a preparation method of a micro light emitting diode array chip, which comprises the following steps:

[0039] Step 100: sequentially growing a buffer layer, an N-type conductive layer, a light emitting layer and a P-type conductive layer on a substrate to obtain a micro light emitting diode epitaxial wafer;

[0040] Step 200: preparing a periodic distribution of a dielectric layer array on the upper surface of the micro light emitting diode epitaxial wafer to obtain a first mask array;

[0041] Step 300: preparing a periodic distribution of a metal layer array on the first mask array to obtain a second mask array; the second mask array and the first mask array have the same arrangement mode, and each unit of the second mask array is located within the corresponding unit of the first mask array;

[0042] Step 400: dividing the micro light emitting diode epitaxial wafer into an isolation region, a protection region and a pixel region according to the first mask array and the second mask array; the isolation region is a region not covered by the first mask array and the second mask array, the protection region is a region only covered by the first mask array, and the pixel region is a region commonly covered by the first mask array and the second mask array;

[0043] Step 500: Using the first mask array and the second mask array as masks, perform ion implantation on the micro light-emitting diode epitaxial wafer, so that the ion implantation impurity concentration in the isolation region, the protection region and the pixel region decreases sequentially, and the resistivity of the P-type conductive layer in the isolation region, the protection region and the pixel region decreases sequentially after ion implantation;

[0044] Step 600: Remove the first mask array and the second mask array to obtain a micro light-emitting diode array; divide the micro light-emitting diode array into a non-light-emitting region and a plurality of light-emitting regions, each of the light-emitting regions including at least one pixel region;

[0045] Step 700: Remove the P-type conductive layer and the light-emitting layer in the non-light-emitting area to expose the N-type conductive layer; fabricate a P-type electrode layer and an N-type electrode layer on the P-type conductive layer in the light-emitting area and the N-type conductive layer in the non-light-emitting area, respectively;

[0046] Step 800: Cut the micro LED array to obtain micro LED array chips, each of the micro LED array chips including one of the light-emitting regions.

[0047] The method for fabricating a miniature light-emitting diode array chip provided in this embodiment will be further described in detail below with reference to the accompanying drawings.

[0048] Figure 2 These are cross-sectional views (left) and top views (right) of the sample structure after the first mask array has been fabricated, as shown in this embodiment of the invention. Figure 2 As shown, a buffer layer 102, an N-type conductive layer 103, a light-emitting layer 104, and a P-type conductive layer 105 are sequentially grown on a substrate 101 to obtain a micro light-emitting diode epitaxial wafer; a periodically distributed array of dielectric layers is prepared on the upper surface of the micro light-emitting diode epitaxial wafer to obtain a first mask array 201.

[0049] Optionally, the substrate 101 is any one of a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon substrate, a silicon carbide substrate, a gallium oxide substrate, a gallium nitride composite template, and an aluminum nitride composite template; the buffer layer 102 is a stack of one or more of InN, GaN, AlN, InGaN, and AlGaN; the N-type conductive layer 103 is a stack of one or more of InN, GaN, AlN, InGaN, and AlGaN of N-type conductivity; the light-emitting layer 104 is a periodic multi-quantum well structure of two or more of InN, GaN, AlN, InGaN, and AlGaN; the P-type conductive layer 105 is a stack of one or more of InN, GaN, AlN, InGaN, and AlGaN of P-type conductivity; the first mask array 201 is a dielectric layer array, which is a stack of one or more of SiO2, TiO2, ZrO2, SiN x , Al2O3, AlN, Ta2O5, HfO2, ZnO, ITO; the unit size of the first mask array 201 ranges from 0.1 to 1000 μm, and the unit spacing of the first mask array 201 ranges from 0.1 to 1000 μm.

[0050] In this embodiment, the substrate 101 is a c-plane sapphire substrate, the buffer layer 102 is a stack of an AlN film with a thickness of 25 nm and an unintentionally doped GaN layer with a thickness of 2 μm, the N-type conductive layer 103 is an N-type GaN layer with a thickness of 2 μm, the light-emitting layer 104 is a 3-period InGaN / GaN multi-quantum well structure with a period thickness of 13 nm and a light-emitting wavelength of 625 nm, and the P-type conductive layer 105 is a P-type GaN layer with a thickness of 0.2 μm; the first mask array 201 is a SiO2 layer with a thickness of 50 nm; the unit size of the first mask array 201 is 6 μm, and the unit spacing of the first mask array 201 is 10 μm.

[0051] Figure 3 FIG. 2 shows a cross-sectional view (left) and a top view (right) of a sample structure after the preparation of the second mask array according to an embodiment of the present application, as shown in the following. Figure 3 A periodically distributed metal layer array is prepared on the first mask array 201 to obtain a second mask array 301; the second mask array 301 and the first mask array 201 have the same arrangement mode, and each unit of the second mask array 301 is located within a corresponding unit of the first mask array 201.

[0052] Optionally, the second mask array 301 is a metal layer array, the metal layer array is a stack of one or more of Au, W, Ti, Ni, Al, Pt, Pd, Ag, Cu and Cr; the unit size in the second mask array 301 ranges from 0.01 to 100 μm, and the unit spacing in the second mask array 301 ranges from 0.1 to 1000 μm.

[0053] In this embodiment, the second mask array 301 is a Ti metal layer with a thickness of 100 nm; the unit size in the second mask array 301 is 4 μm, and the unit spacing in the second mask array 301 is 10 μm.

[0054] Figure 4 A cross-sectional view of a sample structure after the ion implantation process is completed for the embodiment of the present application is shown in FIG. 4. Figure 4 As shown in FIG. 4, the micro-LED epitaxial wafer is divided into an isolation region 401, a protection region 402 and a pixel region 403 according to the first mask array 201 and the second mask array 301; the isolation region 401 is a region not covered by the first mask array 201 and the second mask array 301, the protection region 402 is a region covered only by the first mask array 201, and the pixel region 403 is a region covered by both the first mask array 201 and the second mask array 301; ion implantation is performed on the micro-LED epitaxial wafer with the first mask array 201 and the second mask array 301 as masks, so that the ion implantation impurity concentration of the isolation region 401, the protection region 402 and the pixel region 403 decreases in turn, and the P-type conductive layer resistivity of the isolation region 401, the protection region 402 and the pixel region 403 decreases in turn after ion implantation.

[0055] In this embodiment, the ion implantation process is Ar + ion implantation process, Ar + The ion dose is 4×10 13 cm -2 , and the energy is 40 keV.

[0056] Figure 5 A cross-sectional view (left) and a top view (right) of a sample structure after the first mask array and the second mask array are removed for the embodiment of the present application are shown in FIG. 5. Figure 5 As shown in FIG. 5, the first mask array and the second mask array are removed to obtain a micro-LED array; the micro-LED array is divided into a non-light-emitting region and a plurality of light-emitting regions 501, and each light-emitting region 501 includes at least one pixel region 403.

[0057] Optionally, the number of pixel regions 403 in the light-emitting region 501 ranges from 1 to 10 6One.

[0058] In this embodiment, the number of pixel regions 403 in the light emitting region 501 is four.

[0059] Figure 6 The cross-sectional view (left) and top view (right) of the sample structure after the preparation of the P-type electrode layer and N-type electrode layer are shown in FIG. 6. Figure 6 As shown in FIG. 6, the P-type conductive layer 105 and the light emitting layer in the light emitting region are removed to expose the N-type conductive layer 103; the P-type electrode layer 601 and the N-type electrode layer 602 are prepared on the P-type conductive layer 105 in the light emitting region and the N-type conductive layer 103 in the non-light emitting region, respectively.

[0060] Optionally, the P-type electrode layer 601 covers all the light emitting regions or only covers the pixel regions in the light emitting regions.

[0061] In this embodiment, the P-type electrode layer 601 is an ITO layer with a thickness of 100 nm, and the P-type electrode layer only covers the pixel regions in the light emitting regions; the N-type electrode layer 602 is a Ti / Al / Ni / Au stack with a total thickness of 0.3 μm.

[0062] The micro light emitting diode array is cut to obtain micro light emitting diode array chips, and each micro light emitting diode array chip includes one light emitting region.

[0063] Further, the embodiment also provides a micro light emitting diode array chip.

[0064] Figure 7is a cross-sectional schematic view of a micro light emitting diode array chip provided by an embodiment of the present application, and a structure of the micro light emitting diode array chip comprises: a micro light emitting diode array and an electrode layer; the micro light emitting diode array comprises, from top to bottom, a P-type conductive layer 105, a light emitting layer 104, an N-type conductive layer 103, a buffer layer 102 and a substrate 101; the P-type conductive layer 105, the light emitting layer 104, the N-type conductive layer 103, the buffer layer 102 and the substrate 101 are in a mesa shape, wherein a mesa size of the P-type conductive layer 105 and the light emitting layer 104 is smaller than a mesa size of the N-type conductive layer 103, the buffer layer 102 and the substrate 101; the P-type conductive layer 105 comprises an isolation region 401, a protection region 402 and a pixel region 403; the pixel region 403 is distributed in a periodic array, the protection region 402 is located between the isolation region 401 and the pixel region 403, and resistivities of the isolation region 401, the protection region 402 and the pixel region 403 decrease in turn; the electrode layer comprises a P-type electrode layer 601 and an N-type electrode layer 602; the P-type electrode layer is arranged on the P-type conductive layer 105 and covers all the P-type conductive layer 105 or only covers the pixel region 403 in the P-type conductive layer 105; the N-type electrode layer 602 is arranged on the N-type conductive layer 103 and is distributed around the P-type conductive layer 105 and the light emitting layer 104.

[0065] Optionally, the micro light emitting diode array chip in the embodiment is prepared by the micro light emitting diode array preparation method in the embodiment.

[0066] Optionally, the substrate 101 is any one of a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon substrate, a silicon carbide substrate, a gallium oxide substrate, a gallium nitride composite template and an aluminum nitride composite template; the buffer layer 102 is a stack of one or more of InN, GaN, AlN, InGaN and AlGaN; the N-type conductive layer 103 is a stack of one or more of N-type conductive type InN, GaN, AlN, InGaN and AlGaN; the light emitting layer 104 is a periodic multi-quantum well structure of two or more of InN, GaN, AlN, InGaN and AlGaN; and the P-type conductive layer 105 is a stack of one or more of P-type conductive type InN, GaN, AlN, InGaN and AlGaN.

[0067] In the embodiment, the substrate 101 is a c-plane sapphire substrate, the buffer layer 102 is a stack of an AlN film with a thickness of 25 nm and an unintentionally doped GaN layer with a thickness of 2 μm, the N-type conductive layer 103 is an N-type GaN layer with a thickness of 2 μm, the light-emitting layer 104 is a 3-period InGaN / GaN multi-quantum well structure with a period thickness of 13 nm and a light-emitting wavelength of 625 nm, the P-type conductive layer 105 is a P-type GaN layer with a thickness of 0.2 μm, the P-type electrode layer 601 is an ITO layer with a thickness of 100 nm, and the P-type electrode layer only covers the pixel region 403 in the P-type conductive layer 105; the N-type electrode layer 602 is a Ti / Al / Ni / Au stack with a total thickness of 0.3 μm; the array unit size of the pixel region 403 is 4 μm, and the array unit spacing of the pixel region 403 is 10 μm.

[0068] The present application has the advantages that the isolation region, the protection region and the pixel region are formed on the surface of the micro light-emitting diode epitaxial wafer by the dielectric layer and the metal composite mask structure, the partition ion implantation of the micro light-emitting diode epitaxial wafer is realized, the problem that the traditional ion implantation process cannot simultaneously control the depth distribution and the lateral extension of the ion implantation impurities is solved, and the pixel isolation effect and the light-emitting efficiency of the micro light-emitting diode array chip are improved.

[0069] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be mutually referred to.

[0070] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above embodiment descriptions are only used to help understand the method of the present application and its core idea; meanwhile, for the general technical personnel in the field, the specific implementation manners and application ranges will be changed according to the idea of the present application. In conclusion, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A method for fabricating a micro light-emitting diode array chip, characterized in that, The application relates to a micro light-emitting diode array chip and a preparation method thereof. A buffer layer, an N-type conductive layer, a light-emitting layer and a P-type conductive layer are sequentially grown on a substrate to obtain a micro light-emitting diode epitaxial wafer; A periodic array of dielectric layers is prepared on the upper surface of the micro light-emitting diode epitaxial wafer to obtain a first mask array; A periodic array of metal layers is prepared on the first mask array to obtain a second mask array; The second mask array and the first mask array have the same arrangement mode, and each unit of the second mask array is located in a corresponding unit of the first mask array; The micro light-emitting diode epitaxial wafer is divided into isolated regions, protection regions and pixel regions according to the first mask array and the second mask array; the isolated regions are regions not covered by the first mask array and the second mask array, the protection regions are regions only covered by the first mask array, and the pixel regions are regions covered by the first mask array and the second mask array; Ion implantation is performed on the micro light-emitting diode epitaxial wafer by taking the first mask array and the second mask array as masks, so that the ion implantation impurity concentration of the isolated regions, the protection regions and the pixel regions decreases in sequence, and the P-type conductive layer resistivity of the isolated regions, the protection regions and the pixel regions decreases in sequence after ion implantation; The first mask array and the second mask array are removed to obtain a micro light-emitting diode array; the micro light-emitting diode array is divided into non-light-emitting regions and a plurality of light-emitting regions, and each light-emitting region comprises at least one pixel region; The P-type conductive layer and the light-emitting layer of the non-light-emitting regions are removed to expose the N-type conductive layer; A P-type electrode layer and an N-type electrode layer are respectively prepared on the P-type conductive layer of the light-emitting regions and the N-type conductive layer of the non-light-emitting regions; The micro light-emitting diode array is cut to obtain a micro light-emitting diode array chip, and each micro light-emitting diode array chip comprises one light-emitting region.

2. The micro light emitting diode array chip preparation method of claim 1, wherein, The substrate is any one of a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon substrate, a silicon carbide substrate, a gallium oxide substrate, a gallium nitride composite template and an aluminum nitride composite template; the buffer layer is a stack of one or more of InN, GaN, AlN, InGaN and AlGaN; the N-type conductive layer is a stack of one or more of N-type conductive InN, GaN, AlN, InGaN and AlGaN; the light-emitting layer is a periodic multi-quantum well structure composed of two or more of InN, GaN, AlN, InGaN and AlGaN; and the P-type conductive layer is a stack of one or more of P-type conductive InN, GaN, AlN, InGaN and AlGaN.

3. The micro light emitting diode array chip preparation method of claim 1, wherein, The first mask array is the medium layer array, the medium layer array is a stack of one or more of SiO2, TiO2, ZrO2, SiN x , Al2O3, AlN, Ta2O5, HfO2, ZnO, ITO; the second mask array is the metal layer array, the metal layer array is a stack of one or more of Au, W, Ti, Ni, Al, Pt, Pd, Ag, Cu and Cr.

4. The micro light emitting diode array chip preparation method of claim 1, wherein, The unit size in the first mask array ranges from 0.1 to 1000 μm, and the unit spacing in the first mask array ranges from 0.1 to 1000 μm; the unit size in the second mask array ranges from 0.01 to 100 μm, and the unit spacing in the second mask array ranges from 0.1 to 1000 μm.

5. The micro light emitting diode array chip preparation method of claim 1, wherein, the number of pixel regions in the light emitting region ranges from 1 to 10 6 one.

6. The micro light emitting diode array chip preparation method of claim 1, wherein, The P-type electrode layer covers all the light-emitting regions or only the pixel regions in the light-emitting regions.

7. A micro light emitting diode array chip, characterized by, The structure comprises: a micro light-emitting diode array and an electrode layer; The micro light-emitting diode array comprises, from top to bottom, a P-type conductive layer, a light-emitting layer, an N-type conductive layer, a buffer layer and a substrate; the P-type conductive layer, the light-emitting layer, the N-type conductive layer, the buffer layer and the substrate are all in a mesa shape, wherein the mesa size of the P-type conductive layer and the light-emitting layer is smaller than that of the N-type conductive layer, the buffer layer and the substrate; the P-type conductive layer comprises an isolation region, a protection region and a pixel region; the pixel region is arranged in a periodic array, and the protection region is located between the isolation region and the pixel region; the resistivity of the isolation region, the protection region and the pixel region decreases in turn; The electrode layer comprises a P-type electrode layer and an N-type electrode layer; the P-type electrode layer is arranged on the P-type conductive layer, and covers all the P-type conductive layer or only the pixel region in the P-type conductive layer; the N-type electrode layer is arranged on the N-type conductive layer, and is distributed around the P-type conductive layer and the light-emitting layer.

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