Si-based hybrid integrated micro-led chip and preparation method

Abstract

The application discloses a Si-based hybrid integrated Micro-LED chip and a preparation method thereof. The chip takes a Si substrate as a core integrated carrier. A GaN-based blue-green light Micro-LED array is directly grown on the front surface through regional selective epitaxy. Meanwhile, an AlGaInP-based red light Micro-LED array is integrated on the wafer through wafer bonding. A CMOS driving circuit is integrated on the back surface. The p-type layer surfaces of the GaN-based blue-green light array and the AlGaInP-based red light array are covered with transparent conductive layers and composite positive electrodes. A composite negative electrode is prepared on the back surface of the Si substrate and is interconnected with the CMOS driving circuit. The application solves the problem of low efficiency of traditional GaN-based red light through an AlGaInP material system, reduces the transfer frequency, combines high thermal conductivity and compatibility, realizes efficient integration of full-color Micro-LED, and has high luminous efficiency, high yield, strong reliability and wide application compatibility, and is suitable for various full-color display scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Micro-LED chip, in particular to a Si-based hybrid integrated Micro-LED chip and a preparation method thereof, which is suitable for full-color display scenarios such as consumer electronics (such as smart phones and televisions), vehicle displays (such as instrument panels and central control screens), and medical displays (such as surgical navigation screens), and can realize large-scale preparation of high-brightness, high-yield, and low-cost full-color Micro-LED modules. BACKGROUND

[0002] Micro-LED has become the core direction of the next generation of display technology due to its high brightness (peak brightness up to 10000 ), high contrast (million levels), fast response speed (nanosecond level), and long service life (more than 100,000 hours), and other advantages; full-color display is a key requirement for the landing of Micro-LED technology. The current mainstream full-color scheme relies on GaN-based material system to prepare red, blue, and green (RGB) three primary color chips, but this scheme has three major technical bottlenecks, which seriously restrict its large-scale application.

[0003] First, the efficiency of red Micro-LED is significantly lower.

[0004] In the existing GaN-based full-color scheme, blue and green Micro-LEDs can achieve high-efficiency light emission (external quantum efficiency EQE up to 50%, 80% or more) through InGaN quantum wells, but red Micro-LEDs (emission wavelength 620-650 nm) need to introduce more than 35% of In component in InGaN quantum wells to adjust the emission wavelength. High In component leads to a serious lattice mismatch (lattice constant difference exceeds 5%) between InGaN and GaN barrier layers, and at the same time causes strong piezoelectric polarization effect, which further forms high-density dislocation defects (density up to ) and non-radiative recombination centers in the quantum well, ultimately resulting in internal quantum efficiency (IQE) of less than 20% and external quantum efficiency (EQE) of mostly less than 10% for red devices, which is much lower than that of blue and green devices, and cannot meet the brightness balance requirements of full-color display.

[0005] Although some studies have attempted to indirectly achieve red light through "quantum dot conversion" or "fluorescent powder coating", quantum dots are prone to aging, and fluorescent powder has light decay problems, and will lose 30%-50% of light efficiency, which cannot meet the high reliability requirements of Micro-LED; although AlGaInP-based materials are direct bandgap semiconductors, which are naturally suitable for preparing red devices (EQE can reach more than 30%), but in the traditional scheme, AlGaInP red chips and GaN-based blue and green chips need to be prepared on different substrates (GaAs substrate, sapphire substrate), which is difficult to realize integration on the same substrate, and has poor compatibility.

[0006] II. Multiple transfers result in low yield and high cost.

[0007] The existing full-color display scheme needs to use a "step-by-step selective transfer process" to transfer blue, green, and red chips from their respective substrates to a driving substrate (such as a Si-CMOS substrate). Each transfer needs to independently complete processes such as photomask making, high-precision alignment (error needs to be less than 1 μm), wafer bonding, detection and repair, etc. If the single transfer yield is 90%, the system yield after three transfers is only 72.9%. If the single transfer yield is 85%, the yield after three transfers is less than 62%, which is difficult to meet the needs of large-scale production. At the same time, each transfer needs a special photomask (costing tens of thousands of yuan per set), a high-precision bonding device (costing more than one million yuan per unit), and additional working hours. The equipment investment and working hours cost for three transfers is 3-4 times that of a single transfer, resulting in high costs of full-color Micro-LED modules (current cost is more than 1000 US dollars / inch).

[0008] III. Insufficient integration compatibility and stability.

[0009] In the existing scheme, blue and green chips mostly use sapphire substrates, which have a thermal conductivity of only 40 W / mK, poor heat dissipation performance, and are prone to cause chip junction temperature rise (more than 80℃), thereby reducing the light-emitting efficiency and service life. Moreover, the sapphire substrate cannot be directly interconnected with the Si-based CMOS driving circuit, and needs to be additionally connected through an "intermediate layer", increasing the integration complexity and contact resistance. In addition, the traditional transparent conductive layer mostly uses single ITO material with a fixed thickness of 150 nm. When the chip size is reduced to less than 5 μm, the sheet resistance of the ITO layer significantly increases (more than 50 Ω / □), affecting the current uniformity. The composite electrode mostly uses a "Ti / Au" structure, and the adhesion of Ti to the p-type layer is insufficient, which is prone to electrode peeling problems after long-term use.

[0010] In summary, it is crucial to develop a Micro-LED integration scheme that can balance "red light efficiency improvement, transfer process simplification, and integration compatibility optimization" to solve the current technical bottlenecks. SUMMARY

[0011] The purpose of the present application is to solve the problems of "low red light efficiency, poor multiple transfer yield, and insufficient integration compatibility" in the existing GaN-based full-color Micro-LED technology, and to provide a Si-based hybrid integrated Micro-LED chip and a preparation method.

[0012] To solve the above technical problems, the technical scheme adopted by the present application is:

[0013] A Si-based hybrid integrated Micro-LED chip, comprising a Si substrate, a GaN-based blue-green light Micro-LED array and an AlGaInP-based red light Micro-LED array integrated on the front surface of the Si substrate, and a CMOS driving circuit integrated on the back surface of the Si substrate;

[0014] The GaN-based blue-green light Micro-LED array is directly grown on the front surface of the Si substrate by regionalized selective epitaxy, and the AlGaInP-based red light Micro-LED array is integrated on the designated region of the front surface of the Si substrate by wafer bonding;

[0015] The p-type layer surfaces of the GaN-based blue-green light Micro-LED array and the AlGaInP-based red light Micro-LED array are covered with transparent conductive layers, and the transparent conductive layer surfaces are provided with composite positive electrodes;

[0016] The back surface of the Si substrate is provided with a composite negative electrode, and the CMOS driving circuit is electrically interconnected through the negative electrode.

[0017] Preferably, the GaN-based blue-green light Micro-LED array is sequentially stacked along the surface of the Si substrate with a buffer layer, an n-GaN electron-providing layer, a quantum well structure, and a p-GaN hole-providing layer, wherein x = 0.2-0.6, the buffer layer has a thickness of 200-600 nm, the n-GaN electron-providing layer has a thickness of 1-2 μm and a carrier concentration of ; the quantum well structure has 1-5 pairs, a well layer has a thickness of 1.5-4.5 nm, a GaN barrier layer has a thickness of 10-15 nm, and in the blue light quantum well, x = 0.15, and in the green light quantum well, x = 0.25; the p-GaN hole-providing layer has a thickness of 100-300 nm and a carrier concentration of .

[0018] Preferably, the AlGaInP-based red light Micro-LED array is sequentially stacked along the bonding surface with an n-type etching stop layer, an n-type GaAs ohmic contact layer, an n-type limiting layer, an InGaP / quantum well structure, a p-type spacer layer, and a p-GaP hole-providing layer; wherein, x = 0.1-0.4, y = 0.5, the n-type etching stop layer has a thickness of 100-300 nm and a carrier concentration of ; n-type GaAs ohmic contact layer thickness is 10-50nm, carrier concentration is ; =0.7-1, =0.5, n-type limiting layer thickness is 150-500nm, carrier concentration is ; =0.6-0.9, =0.5, InGaP / quantum well structure is 1-5 pairs, InGaP well layer thickness is 1.5-4.5nm, barrier layer thickness is 4-10nm; =0.8-0.9, =0.5, p-type spacer layer thickness is 30-100nm, carrier concentration is ; p-GaP hole supply layer thickness is 100-300nm, carrier concentration is .

[0019] In a preferred scheme, the transparent conductive layer is ITO, IZO or AZO transparent conductive material, the thickness is 50-300nm, and the molar ratio of indium and tin is 9:1; the composite positive electrode and the composite negative electrode are both composed of at least two metal layers, and the total thickness is 500-1500nm.

[0020] The application also provides a preparation method of a Si-based hybrid integrated Micro-LED chip, comprising the following steps:

[0021] S1, synchronously growing GaN-based blue-green light Micro-LED devices on a Si substrate by regional selective epitaxy;

[0022] S2, preparing an n-type electrode on the back of the Si substrate, and realizing interconnection of the Si-based CMOS driving circuit and the Si substrate through bonding;

[0023] S3, growing AlGaInP-based red light Micro-LED devices on a GaAs substrate by regional selective epitaxy;

[0024] S4, temporarily bonding the AlGaInP-based red light Micro-LED devices to a transfer substrate, and after removing the GaAs substrate, precisely bonding to a specified area of the Si-based CMOS substrate completed in S2;

[0025] S5, preparing a transparent conductive layer and a p-type positive electrode on the surface of the p-type layer of the GaN-based blue-green light Micro-LED devices and the AlGaInP-based red light Micro-LED devices, and completing the chip preparation.

[0026] In a preferred embodiment, step S1 specifically includes the following sub-steps:

[0027] S11 is deposited on the surface of a Si substrate using PECVD technology. The mask layer has a thickness of 100-500 nm; the reactant gas is... and , The flow rate is 1000-1500 sccm. The flow rate is 200-400 sccm, the plasma source power is 80-120 W, the deposition temperature is 200-300℃, and the deposition rate is 0.8-1.2 nm / s;

[0028] S12, in A positive photoresist with a thickness of 500-3000 nm is spin-coated onto the mask layer. After curing and UV exposure, it is developed with TMAH aqueous solution for 100-1400 s to form a strip photoresist pattern. In the strip photoresist pattern, the green light area has a size of 2-5 μm and the blue light area has a size of 8-10 μm.

[0029] S13, ICP etching technology is used to remove the patterned area. Mask layer, etching gas is , The flow rate is 20-30 sccm, the etching time is 300-500 s, and the etching rate is 1.0-1.4 nm / s. After etching, the remaining photoresist is removed using an acetone / isopropanol mixed solution to obtain a patterned Si substrate.

[0030] S14, GaN-based epitaxial layers are grown on a patterned Si substrate using MOCVD technology, and then sequentially deposited... Buffer layer, n-GaN electron-donating layer Quantum well structure and p-GaN hole-providing layer.

[0031] In a preferred embodiment, step S2 specifically includes the following sub-steps:

[0032] S21, Patterning is fabricated on the back side of the Si substrate. Mask layer; A composite metal layer is deposited on the exposed Si substrate area using evaporation or sputtering techniques at a deposition rate of 0.8-1.2 nm / s; The underlying metal layer with photoresist is removed by a lift-off process to obtain the back n-type negative electrode;

[0033] S22, deposit a bonding metal layer on the front side of the CMOS driving circuit backplane; align and bond the bonding metal layer on the back side of the Si substrate with the front side of the CMOS backplane, and bond for 10-60 minutes at 400-700℃ and 3000-9000kg pressure to form an electromechanical connection.

[0034] Preferably, step S3 specifically comprises the following sub-steps:

[0035] S31, depositing a mask layer on the surface of the GaAs substrate by PECVD technology, with a thickness of 100-500 nm;

[0036] S32, coating photoresist on the mask layer, and forming photoresist patterns corresponding to the mesa structure of the red Micro-LED after pattern processing;

[0037] S33, removing the mask layer in the patterned area by etching technology, and removing the remaining photoresist to obtain a patterned GaAs substrate;

[0038] S34, growing an AlGaInP-based epitaxial layer on the patterned GaAs substrate by MOCVD technology, and sequentially depositing an n-type GaAs buffer layer, an n-type etching stop layer, an n-type GaAs ohmic contact layer, an n-type confinement layer, an InGaP / quantum well structure, a p-type spacer layer, and a p-type GaP hole supply layer;

[0039] Preferably, step S4 specifically comprises the following sub-steps:

[0040] S41, depositing a bonding metal layer on the surface of the AlGaInP epitaxial layer and the front surface of the transfer substrate; aligning and bonding the bonding metal layers of the two, bonding at 400-700℃ and a pressure of 3000-9000kg for 10-60min; removing the GaAs substrate by wet or dry etching to obtain an AlGaInP red epitaxial layer attached to the transfer substrate;

[0041] S42, depositing a bonding metal layer on the surface of the AlGaInP red epitaxial layer and the specified area of the Si-based CMOS substrate completed in S2; aligning and bonding the two, bonding at 400-700℃ and a pressure of 3000-9000kg for 10-60min; and removing the transfer substrate by physical or chemical methods.

[0042] Preferably, step S5 specifically comprises the following sub-steps:

[0043] ​​​​​​​S51, a transparent conductive layer with a thickness of 50-300 nm is deposited on the surface of the p-type layer of the GaN-based blue-green light epitaxial layer and the AlGaInP red light epitaxial layer by evaporation or sputtering technology, and the deposition rate is 0.8-1.2 nm / s; a positive photoresist with a thickness of 1000-5000 nm is spin-coated, and after solidification and ultraviolet exposure, the photoresist is developed with TMAH aqueous solution for 160-200 s; after patterned etching, annealing is performed at 300-500 DEG C for 120-240 s;

[0044] S52, spin-coating a positive photoresist on the surface of the transparent conductive layer, solidifying and ultraviolet exposing, and then depositing a composite metal layer; removing the excess metal by a stripping process to obtain a p-type positive electrode.

[0045] Due to the use of the above technical solutions, the beneficial effects of the present application compared with the prior art are:

[0046] 1. Improve red light emission efficiency: The present application uses AlGaInP-based material system to prepare red light Micro-LED, which avoids the lattice mismatch and polarization effect problems caused by high In component in traditional GaN-based red light devices, and effectively improves the light emission efficiency of the red light device, which meets the brightness balance requirement of full-color display.

[0047] 2. Simplify the transfer process and improve yield: By using regional selective epitaxy technology, the GaN-based blue-green light Micro-LED array is grown in situ on the front surface of the Si substrate, without the need for additional transfer; only a single transfer integration is needed for the AlGaInP-based red light Micro-LED array, which greatly reduces the number of transfers in the traditional full-color scheme, simplifies the process flow, and reduces the yield loss caused by multiple transfers, thereby improving the overall system yield.

[0048] 3. Optimize integration compatibility and application flexibility: Si substrate is selected, which can be directly bonded with the CMOS driving circuit on the back surface to realize electrical interconnection without the need for additional interlayer, thereby simplifying the integration process; the transparent conductive layer supports multiple material options such as ITO, IZO, and AZO, and the composite electrode is composed of at least two metal layers, which can be flexibly adapted according to different application scenarios (such as consumer electronics and vehicle displays), thereby enhancing the application compatibility of the chip.

[0049] 4. Enhance heat dissipation performance and long-term reliability: The Si substrate has good heat conduction characteristics, which can effectively dissipate the heat generated during chip operation and reduce the performance degradation caused by high junction temperature; the adhesion between the composite electrode and the substrate and the functional layer is strong, which can reduce the risk of electrode detachment during long-term use, prolong the service life of the chip, and improve the overall reliability. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to make the technical field personnel better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should be within the scope of protection of the present application.

[0051] Figure 1 A structure schematic diagram of a Si-based hybrid integrated Micro-LED chip of the present application;

[0052] Figure 2 A schematic diagram of a GaN-based blue-green light Micro-LED array of the present application;

[0053] Figure 3 A schematic diagram of an AlGaInP-based red light Micro-LED array of the present application;

[0054] Figure 4 A flow chart of a preparation method of a Si-based hybrid integrated Micro-LED chip of the present application;

[0055] 1, Si substrate; 2, GaN-based blue-green light Micro-LED array; 3, AlGaInP-based red light Micro-LED array; 4, CMOS driving circuit; 21, buffer layer; 22, n-GaN electron supply layer; 23, quantum well structure; 24, p-GaN hole supply layer; 31, p-GaP hole supply layer; 32, p-type spacer layer; 33, InGaP / quantum well structure; 34, n-type limiting layer; 35, n-type GaAs ohmic contact layer; 36, n-type etching stop layer. DETAILED DESCRIPTION

[0056] In order to make the technical field personnel better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should be within the scope of protection of the present application.

[0057] It should be noted that the terms "first", "second" and "third" and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a specific sequential or chronological order. It is to be understood that the use of these terms is arbitrary apart from their usage to distinguish between the elements to which they are used to identify. Furthermore, the terms "comprise", "comprising", "include", "including" and the like are used herein to indicate the presence of elements, components, steps, and / or the like, but do not preclude the presence or addition of one or more other elements, components, steps, and / or the like.

[0058] In the present application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not intended to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0059] In addition, in addition to indicating the orientation or positional relationship, the above-mentioned partial terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the present application can be understood according to the specific circumstances.

[0060] In addition, the terms "mount", "set", "provided with", "connected", "linked", "sleeved" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or a monolithic structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or an internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0061] It should be noted that the embodiments and features in the embodiments in the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0062] Embodiment One

[0063] Please refer to Figures 1-3The application provides a Si-based hybrid integrated Micro-LED chip, taking a Si substrate 1 as a core integrated carrier to form a vertical structure of "front light emission and back driving", which comprises the Si substrate 1, a GaN-based blue-green light Micro-LED array 2 and an AlGaInP-based red light Micro-LED array 3 integrated on the front of the Si substrate 1, and a CMOS driving circuit 4 integrated on the back of the Si substrate 1, and the structural details of each part are as follows:

[0064] The Si substrate 1 is a <111> crystal-oriented Si substrate 1 (preferably 500-750 μm in thickness), which has a thermal conductivity of 150 , and a resistivity of <0.01 . The Si substrate 1 can provide stable mechanical support for the whole chip, act as an efficient heat dissipation channel, and directly realize electrical interconnection with the CMOS driving circuit 4 without an additional interlayer.

[0065] The GaN-based blue-green light Micro-LED array 2 is directly grown on the front of the Si substrate 1 by regional selective epitaxy technology, and is stacked in a multilayer structure from bottom to top along the surface of the Si substrate 1, which comprises a buffer layer 21, an n-GaN electron-providing layer 22, a quantum well structure 23, and a p-GaN hole-providing layer 24, wherein the Al component x of the buffer layer 21 is 0.2-0.6, and the thickness is 200-600 nm, which can effectively balance the lattice mismatch between the Si substrate 1 and the GaN-based material and reduce the dislocation defects in the epitaxial layer; the n-GaN electron-providing layer 22 is 1-2 μm in thickness, and the carrier concentration is controlled at , which can ensure efficient transmission of electrons and avoid impurity scattering caused by excessively high carrier concentration; The quantum well structure 23 is 1-5 pairs, each pair of quantum well comprising a well layer and a GaN barrier layer, wherein the well layer is 1.5-4.5 nm in thickness, and the GaN barrier layer is 10-15 nm in thickness, and for the wavelength requirements of blue light and green light, the In component in the blue light quantum well is fixed at 0.15 (corresponding to the light emission wavelength of 440-460 nm), and the In component in the green light quantum well is fixed at 0.25 (corresponding to the light emission wavelength of 520-530 nm); the p-GaN hole-providing layer 24 is 100-300 nm in thickness, and the carrier concentration is , which can realize effective injection of holes into the quantum well region.

[0066] AlGaInP-based red Micro-LED array 3: integrated in the designated area (non-overlapping with the blue-green array) on the front side of the Si substrate 1 by wafer bonding technology, stacked in order from bottom to top along the bonding surface to form a multilayer structure, specifically n-type etching stop layer 36, n-type GaAs ohmic contact layer 35, n-type limiting layer 34, InGaP quantum well structure 33, p-type spacer layer 32 and p-GaP hole supply layer 31; wherein the n-type Al composition of the etching stop layer 36 0.1-0.4, the component ratio y is fixed at 0.5, the thickness is 100-300 nm, and the carrier concentration is , which can protect the underlying red structure layer from being etched when the original GaAs substrate is removed later; the n-type GaAs ohmic contact layer 35 has a thickness of 10-50 nm and a carrier concentration of , which can reduce the contact resistance with the subsequent bonding metal layer; the n-type Al composition of the limiting layer 34 0.7-1, the component ratio is fixed at 0.5, the thickness is 150-500 nm, and the carrier concentration is , which is used to limit the overflow of carriers from the n-type side of the quantum well active region; InGaP The quantum well structure 33 is 1-5 pairs, each pair of quantum well includes an InGaP well layer and a barrier layer, wherein the InGaP well layer has a thickness of 1.5-4.5 nm, the barrier layer has a thickness of 4-10 nm, and the Al composition 0.6-0.9, the component ratio is fixed at 0.5, and this structure can achieve high-efficiency red light emission at a wavelength of 630-640 nm; the p-type Al composition of the spacer layer 32 0.8-0.9, the component ratio is fixed at 0.5, the thickness is 30-100 nm, and the carrier concentration is , which can effectively limit the overflow of carriers from the p-type side of the quantum well active region; the p-GaP hole supply layer 31 has a thickness of 100-300 nm and a carrier concentration of , which provides holes for the active region and effectively solves the problem of interface states caused by the direct contact between AlGaInP material and the subsequent transparent conductive layer.

[0067] Transparent conductive layer: covering the surface of the p-type layer of GaN-based blue-green Micro-LED array 2 and AlGaInP-based red Micro-LED array 3, the material can be selected from ITO (indium tin oxide), IZO (indium zinc oxide) or AZO (aluminum-doped zinc oxide), and the thickness is 50-300 nm, wherein when ITO is selected, the mole ratio of indium tin is fixed at 9:1, and the role of this layer is to realize uniform distribution of current on the surface of the p-type layer, while ensuring that the light transmittance in the visible light region is > 90%, avoiding shielding the light-emitting area.

[0068] Composite electrode: including a composite positive electrode and a composite negative electrode, both of which are composed of at least two metal layers (preferably a Cr / Pt / Au composite structure), and the total thickness is 500-1500 nm; wherein the composite positive electrode is prepared on the surface of the transparent conductive layer and forms good electrical contact with the transparent conductive layer; the composite negative electrode is prepared on the back of the Si substrate 1, and the CMOS driving circuit 4 on the back of the Si substrate 1 is electrically interconnected through the negative electrode, thereby realizing independent driving control of each Micro-LED pixel.

[0069] CMOS driving circuit 4: integrated on the back of the Si substrate 1, prepared by Si-based CMOS process, pixel pitch is 10-50 μm, driving voltage range is 3.3-5 V, maximum driving current is 100 μA / pixel, and corresponding driving signals can be output according to display requirements to control the on-off and brightness adjustment of blue, green and red three-primary color Micro-LEDs, and finally realize full-color display.

[0070] Example two

[0071] See Figure 4 The application also provides a preparation method of a Si-based hybrid integrated Micro-LED chip, which realizes efficient integration of three-primary color chips through four core steps of "regional epitaxy-back driving integration-red light transfer-transparent electrode preparation", and the specific steps and parameter details are as follows:

[0072] S1, synchronously epitaxially growing GaN-based blue-green Micro-LED devices on the Si substrate 1.

[0073] This step directly grows blue and green Micro-LED arrays on the front surface of the Si substrate 1 through regional selective epitaxy technology, which specifically includes four sub-steps:

[0074] S11, Mask layer deposition: using PECVD (plasma enhanced chemical vapor deposition) technology to deposit Mask layer on the surface of the Si substrate 1, and the thickness of the mask layer is 100-500 nm. During the deposition process, the reaction gas is selected from and , wherein Flow rate should be controlled at 1000-1500 sccm. The flow rate is controlled at 200-400 sccm, the plasma source power is 80-120 W, the deposition temperature is 200-300℃, and the deposition rate is 0.8-1.2 nm / s; this parameter range can guarantee... The mask layer has good density (porosity <5%) and uniformity, providing a stable masking effect for subsequent regional epitaxy.

[0075] S12, Photolithographic pattern preparation: In Positive photoresist (preferred model 5214) is spin-coated onto the mask layer, with a photoresist thickness of 500-3000 nm. The photoresist is then cured (pre-baked at 110℃ for 90-120 s), exposed to ultraviolet light (30-60 s), and developed with a TMAH (tetramethylammonium hydroxide) aqueous solution (concentration 2.38%) for 100-140 s to form a striped photoresist pattern. The striped pattern size corresponding to the green light region is 2-5 μm, and the striped pattern size corresponding to the blue light region is 8-10 μm. This size difference matches the In composition requirements of the blue and green quantum wells, increases the tensile stress introduced during GaN merging in the green light region, thereby improving the In composition of the active region and achieving green light emission.

[0076] S13, Etching and photoresist removal: ICP (Inductively Coupled Plasma) etching technology is used to remove patterned areas. Mask layer, etching gas selection The flow rate is controlled at 20-30 sccm, the etching time is 300-500 s, and the etching rate is 1.0-1.4 nm / s; right Etching selectivity ( The ratio of photoresist to Si can reach 50:1, which can avoid damage to the Si substrate during the etching process. After etching, the substrate is ultrasonically cleaned for 10-15 minutes using a mixture of acetone and isopropanol (volume ratio 1:1) to remove the remaining photoresist and obtain a patterned Si substrate.

[0077] S14, GaN-based epitaxial layer growth: GaN-based epitaxial layers were grown on patterned Si substrates using MOCVD (metal-organic chemical vapor deposition) technology. The growth process involved sequential deposition. Buffer layer 21, n-GaN electron-donating layer 22 Quantum well structure 23 and p-GaN hole-providing layer 24; wherein, The growth temperature of the buffer layer 21 is 1000-1100℃, and the growth temperature of the n-GaN electron-providing layer 22 is 1000-1050℃. The growth temperature of the quantum well structure 23 is 700-800℃ (which can avoid In component desorption), and the growth temperature of the p-GaN hole supply layer 24 is 900-950℃. The material parameters of each layer are consistent with those described in the chip structure. Finally, a GaN-based blue-green Micro-LED device is formed.

[0078] S2, an n-type electrode is prepared on the back of the Si substrate 1, and the Si-based CMOS driving circuit 4 is interconnected with the Si substrate 1 by bonding.

[0079] This step realizes the electrical-mechanical interconnection of the Si substrate 1 and the CMOS driving circuit 4, and specifically includes two sub-steps:

[0080] S21, back n-type negative electrode preparation: repeating the processes of steps S11-S13, a patterned mask layer (the through hole region of the mask layer corresponds to the mesa structure of the blue, green and red Micro-LEDs); then, an evaporation or sputtering technology is used to deposit a composite metal layer (preferably a Cr / Pt / Au structure) on the exposed Si substrate 1 region, the deposition rate is 0.8-1.2 nm / s, and the total thickness of the composite metal layer is consistent with the thickness of the composite electrode in the chip structure (500-1500 nm); after deposition, the lower metal with photoresist is removed by a lift-off process (acetone soaking for 30-60 min) to obtain a back n-type negative electrode.

[0081] S22, CMOS driving circuit 4 bonding: on the front surface of the back plate of the CMOS driving circuit 4, a composite bonding metal layer (also a Cr / Pt / Au structure, with a thickness consistent with the back negative electrode) is deposited by using the same evaporation or sputtering technology as step S21; then, the composite negative electrode on the back of the Si substrate 1 is aligned and attached to the composite bonding metal layer on the front of the CMOS back plate, and is placed in a high-pressure bonding machine to bond at a temperature of 400-700℃ and a pressure of 3000-9000kg for 10-60min, to form a stable electrical-mechanical connection and realize the interconnection of the Si substrate 1 and the CMOS driving circuit 4.

[0082] S3, AlGaInP-based red Micro-LED devices are grown on a GaAs substrate by regional selective epitaxy.

[0083] This step prepares high-efficiency red epitaxial layers on the GaAs substrate, which prepares for subsequent transfer to the Si substrate 1, and specifically includes four sub-steps:

[0084] S31, mask layer deposition: using the same PECVD technology as step S11, a mask layer is deposited on the surface of a GaAs substrate (selected in the <100> direction, with a thickness of 350-500μm) Mask layer, mask layer thickness is 100-500nm, deposition parameters are completely consistent with S11, to ensure the quality of mask layer.

[0085] S32, photoetching pattern preparation: repeat the process of step S12, spin-coat positive photoresist on the mask layer, after curing, UV exposure, development treatment, form photoresist pattern corresponding to the red light Micro-LED mesa structure, pattern size matches the size of the red light integrated area reserved on the front side of Si substrate 1 (preferably 5-10μm), to ensure the alignment accuracy in subsequent transfer.

[0086] S33, Etching and photoresist removal: repeat the ICP etching process of step S13, remove the mask layer in the patterned area , etching parameters are consistent with S13; then use acetone / isopropyl alcohol mixed solution to remove the remaining photoresist, get the patterned GaAs substrate.

[0087] S34, AlGaInP-based epitaxial layer growth: use MOCVD technology to grow AlGaInP-based epitaxial layer on the patterned GaAs substrate, the growth process deposits n-type GaAs buffer layer, n-type Etching stop layer 36, n-type GaAs ohmic contact layer 35, n-type Restriction layer 34, InGaP / Quantum well structure 33, p-type Spacer layer 32 and p-GaP hole providing layer 31; wherein the growth temperature of n-type GaAs buffer layer and n-type GaAs ohmic contact layer 35 is 620-700℃, the growth temperature of the rest of the layers is 700-780℃, the material parameters of each layer are consistent with the description in the chip structure, finally form AlGaInP-based red light Micro-LED device.

[0088] S4, temporarily bond the AlGaInP-based red light Micro-LED device to the transfer substrate, after removing the GaAs substrate, precisely bond to the designated area of the Si-based CMOS substrate completed in S2.

[0089] This step realizes the transfer integration of red light Micro-LED from GaAs substrate to Si-based CMOS substrate, which specifically includes two sub-steps:

[0090] ​S41, temporary bonding and GaAs substrate removal: first, a bonding metal layer (Cr / Pt / Au structure, thickness consistent with the composite electrode) is deposited on the surface of the AlGaInP epitaxial layer and the transfer substrate (glass substrate with a thickness of 500-700 pm and a light transmittance of >90%) using evaporation or sputtering technology; then the bonding metal layers of the two are aligned and attached, and bonded at a temperature of 400-700 °C and a pressure of 3000-9000 kg for 10-60 min to form a temporary fixing structure; then the GaAs substrate is removed by wet or dry etching: for wet etching, a mixed solution of 10% ammonia and 10% hydrogen peroxide with a volume ratio of 4:1 is prepared, and the sample is soaked for 40-60 min (etching rate of 1-2 pm / min, and the 350-500 pm thick GaAs substrate can be completely removed); for dry etching, ICP etching technology (etching gas is and mixed gas) is used, and finally the AlGaInP red light epitaxial layer attached to the glass transfer substrate is obtained.

[0091] S42, precise bonding and transfer substrate removal: first, a bonding metal layer (Cr / Pt / Au structure) is deposited on the surface of the AlGaInP red light epitaxial layer and the designated area (reserved red light integration area) of the Si-based CMOS substrate completed in step S2 using evaporation or sputtering technology; then the two are aligned and attached, and bonded at a temperature of 400-700 °C and a pressure of 3000-9000 kg for 10-60 min to form a stable bonding structure; finally, the glass transfer substrate is removed by physical or chemical methods: the physical method uses laser lift-off technology (wavelength 355 nm, power 80-120 W, and the laser energy only acts on the interface between the glass and the metal without damaging the red light epitaxial layer); the chemical method uses a hydrofluoric acid solution (concentration 5%) for 20-30 min (the etching rate of hydrofluoric acid on glass is >10 pm / min, and the glass substrate can be completely removed), and the transfer integration of the red light Micro-LED is completed.

[0092] S5, a transparent conductive layer and a p-type positive electrode are prepared on the surface of the p-type layer of the GaN-based blue-green light Micro-LED device and the AlGaInP-based red light Micro-LED device to complete the chip preparation.

[0093] This step realizes current injection and electrode interconnection, which specifically includes two sub-steps:

[0094] S51, transparent conductive layer preparation: using evaporation or sputtering technology, a transparent conductive layer is deposited on the surface of the p-type layer of the GaN-based blue-green light epitaxial layer and the AlGaInP-based red light epitaxial layer, the material (ITO, IZO or AZO) and thickness (50-300nm) of the transparent conductive layer are selected according to the chip structure described above, and the deposition rate is 0.8-1.2nm / s; after deposition, a positive photoresist (preferably model 562, thickness 1000-5000nm) is spin-coated, and after curing and ultraviolet exposure, TMAH aqueous solution is used for development for 160-200s to form a patterned mask of the transparent conductive layer; then IBE (ion beam etching) technology is used to pattern and etch the transparent conductive layer (ion source power 400-600W, etching rate 1.0-1.5nm / s) to remove the excess transparent conductive layer; finally, the chip is placed in an annealing furnace and annealed at a temperature of 300-500℃ for 120-240s to repair the damage caused during etching and improve the contact performance of the transparent conductive layer and the p-type layer (contact resistance < 10-2Ω·cm2). ).

[0095] S52, p-type positive electrode preparation: spin-coating a positive photoresist (model 5214, thickness 1500-3000nm) on the surface of the transparent conductive layer, curing and ultraviolet exposure, and then using TMAH aqueous solution for development for 120-160s to form a patterned mask of the positive electrode (the mask through hole corresponds to the position and size of the positive electrode); then, a composite metal layer (Cr / Pt / Au structure, total thickness 500-1500nm) is deposited by evaporation or sputtering technology, and the deposition rate is consistent with step S21; finally, the excess metal is removed by lift-off process (acetone soaking for 30-60min) to obtain a p-type positive electrode, realize complete electrical interconnection of the three-color Micro-LED and the CMOS driving circuit 4, and complete the preparation of the entire chip.

[0096] Example Three

[0097] The application provides a preparation method of a Si-based hybrid integrated Micro-LED chip, in particular a preparation method of a Si-based hybrid integrated Micro-LED chip using an ITO transparent conductive layer, which comprises the following steps:

[0098] I. Preparation steps:

[0099] S1, GaN-based blue-green light epitaxy: a 4-inch <111> crystal direction Si substrate 1 (thickness 500μm) is selected:

[0100] S11, 300nm of SiO2is deposited by PECVD mask layer flow rate 1200sccm, Flow 300 seem, plasma power 100 W, temperature 250 °C, rate 1 nm / s

[0101] S12, spin-coat 1500 nm positive photoresist (model 5214), form 3 μm green light area and 9 μm blue light area pattern after development;

[0102] S13, remove the patterned photoresist by ICP etching (flow 25 seem, time 400 s, rate 1.2 nm / s) , acetone cleaning to remove the photoresist;

[0103] S14, grow GaN-based epitaxial layer by MOCVD: 1050 °C deposit 400 nm buffer layer, 1020 °C deposit 1.5 μm n-GaN electron supply layer 22 (carrier concentration ), 750 °C grow 3 pairs of quantum wells (blue well layer 2.5 nm, green well layer 3.5 nm, barrier layer 12 nm), 920 °C deposit 200 nm p-GaN hole supply layer 24 (carrier concentration ).

[0104] S2, CMOS drive circuit 4 bonding:

[0105] S21, deposit Cr / Pt / Au composite negative electrode (300 nm / 300 nm / 200 nm, rate 1 nm / s) by EB (electron beam) evaporation technology, form by lift-off process;

[0106] S22, bond Si substrate 1 and 4 inch Si-based CMOS drive circuit 4 (pixel pitch 20 μm) at 400 °C, 4500 kg pressure for 30 min, measured contact resistance 4.5 Ω.

[0107] S3, AlGaInP-based red light epitaxy: select 4 inch <100> direction GaAs substrate (thickness 350 μm):

[0108] S31-S33, repeat S11-S13 process, form 5 μm red light area pattern;

[0109] S34, grow AlGaInP-based epitaxial layer by MOCVD: 650 °C deposit 200 nm n-type GaAs buffer layer (carrier concentration ), 750 °C deposit 200 nm n-type etching stop layer (carrier concentration ), 650 °C deposit 30 nm n-type GaAs ohmic contact layer 35 (carrier concentration​​ ), 750℃ deposition of 300nm n-type limiting layer (carrier concentration ), 750℃ growth of 3 pairs of InGaP / quantum well (3nm well layer, 7nm barrier layer), 750℃ deposition of 50nm p-type spacer layer (carrier concentration ), 650℃ deposition of 200nm p-GaP hole supply layer 31 (carrier concentration ).

[0110] S4, red light transfer:

[0111] S41, deposition of Cr / Pt / Au bonding layer on both the front surface of the AlGaInP epitaxial layer and the glass transfer substrate (thickness 500μm), bonding at 500℃ under a pressure of 4500kg for 30min, immersion in 10% ammonia water + 10% hydrogen peroxide (4:1) for 40min to remove the GaAs substrate;

[0112] S42, deposition of Cr / Pt / Au bonding layer on both the AlGaInP epitaxial layer and the designated area of the Si-based CMOS substrate, bonding at 450℃ under a pressure of 6000kg for 40min, laser lift-off of the glass substrate at 100W.

[0113] S5, transparent electrode preparation:

[0114] S51, deposition of 150nm ITO (indium tin molar ratio 9:1, rate 1nm / s) by EB evaporation, IBE etching (power 500W, rate 1nm / s) followed by annealing at 400℃ for 180s;

[0115] S52, deposition of Cr / Pt / Au positive electrode (300nm / 300nm / 200nm), lift-off process shaping, to obtain the final chip.

[0116] II. The performance test results are as follows:

[0117] Luminescence performance: blue light wavelength 450nm, EQE 45%; green light wavelength 525nm, EQE 42%; red light wavelength 635nm, EQE 35%;

[0118] Yield: 4-inch chip effective pixel number 10 million, yield 92%;

[0119] Reliability: after 1000 thermal cycles (-40℃ to 85℃), brightness attenuation rate 8%, electrode shedding rate 0.05%;

[0120] Cost: single chip preparation cost 3000USD (compared with traditional scheme 5000USD).

[0121] Example Four

[0122] The application provides a preparation method of a Si-based hybrid integrated Micro-LED chip, in particular to a preparation method of a Si-based hybrid integrated Micro-LED chip using an AZO transparent conductive layer, which comprises the following steps:

[0123] I. Preparation step (only the transparent conductive layer material is changed, and the rest of the parameters are consistent with example three):

[0124] S51 is changed to: using EB evaporation technology to deposit 150nm of AZO (aluminum doping amount 2%, rate 1nm / s), IBE etching parameters (power 500W, rate 1nm / s) are consistent with example three, 400℃ annealing for 180s;

[0125] The rest of the steps (S1-S4, S52) are exactly the same as example three.

[0126] II. The performance test results are as follows:

[0127] Luminous performance: blue light wavelength 450nm, EQE 44%; green light wavelength 525nm, EQE 41%; red light wavelength 635nm, EQE 33%;

[0128] Yield: 4-inch chip effective pixel number 1 million, yield 91%;

[0129] Reliability: after 1000 times of thermal cycling, the brightness attenuation rate is 7% (AZO weather resistance is better), and the electrode shedding rate is 0.04%;

[0130] Cost: AZO material cost is 1 / 2 of ITO, single piece preparation cost is reduced to 2800 dollars, and further reduced by 10%.

[0131] III. Comparative analysis of examples:

[0132] The performance difference between example three and four is mainly due to the transparent conductive layer material: the red light EQE of AZO is slightly lower than that of ITO (33% vs 35%), but the weather resistance is better, which is suitable for vehicle and other harsh environments; the comprehensive light efficiency of ITO is higher, which is suitable for consumer electronics scenarios; this result proves that the transparent conductive layer parameter range (50-300nm, supporting ITO / IZO / AZO) of the application is reasonable, which can be flexibly adjusted according to application requirements, and the scheme has strong practicability.

[0133] The present application solves the three core problems of low red light efficiency, poor yield in multiple transfer and insufficient integration compatibility of the existing GaN-based full-color Micro-LED by the hybrid integration scheme of "Si-based in-situ epitaxial blue-green light + precise transfer of AlGaInP red light", directly integrates AlGaInP red light and GaN-based blue-green light on the Si substrate 1, improves the red light EQE to more than 30%, reduces the transfer times from 3 times to 1 time, improves the system yield to more than 90%, and reduces the cost by 40%; based on the high thermal conductivity and CMOS compatibility of the Si substrate 1, the chip reliability and integration flexibility are greatly improved.

[0134] Finally, it should be noted that the above is only the preferred embodiment of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments or make equivalent replacements to some technical features, as long as they are within the spirit and principles of the present application. Any modification, equivalent replacement, improvement, etc. shall be included in the protection scope of the present application.

Claims

1. A Si-based hybrid integrated Micro-LED chip, characterized in that, It includes a Si substrate, a GaN-based blue-green micro-LED array and an AlGaInP-based red micro-LED array integrated on the front side of the Si substrate, and a CMOS driving circuit integrated on the back side of the Si substrate. The GaN-based blue-green micro-LED array is directly grown on the front side of the Si substrate through regional selective epitaxy, and the AlGaInP-based red micro-LED array is integrated on a designated area of ​​the front side of the Si substrate through wafer bonding. Both the p-type layer surfaces of the GaN-based blue-green Micro-LED array and the AlGaInP-based red Micro-LED array are covered with a transparent conductive layer. The transparent conductive layer is made of ITO, IZO, or AZO transparent conductive material, with a thickness of 50-300 nm, an indium-tin molar ratio of 9:1, and a transmittance >90% and a sheet resistance <50 Ω / □, which is used to solve the current uniformity problem of small-sized Micro-LEDs. A composite positive electrode is prepared on the surface of the transparent conductive layer. The composite positive electrode is composed of at least two metal layers with a total thickness of 500-1500 nm, which is used to solve the problem of traditional electrode detachment. A composite negative electrode is fabricated on the back side of the Si substrate. The thickness of the composite negative electrode consists of at least two metal layers with a total thickness of 500-1500 nm. Electrical interconnection is achieved between the negative electrode and the CMOS driving circuit.

2. The Si-based hybrid integrated Micro-LED chip according to claim 1, characterized in that, The GaN-based blue-green micro-LED array is sequentially stacked along the surface of the Si substrate. Buffer layer, n-GaN electron-donating layer Quantum well structure and p-GaN hole-providing layer, where x = 0.2-0.

6. The buffer layer thickness is 200-600 nm; the n-GaN electron-donating layer thickness is 1-2 μm, and the carrier concentration is... ; The quantum well structure consists of 1-5 pairs. The well layer thickness is 1.5-4.5 nm, the GaN barrier layer thickness is 10-15 nm, and the blue light quantum well... =0.15, in the green light quantum trap =0.25; the p-GaN hole-providing layer thickness is 100-300 nm, and the carrier concentration is... .

3. The Si-based hybrid integrated Micro-LED chip according to claim 1, characterized in that, The AlGaInP-based red micro-LED array has n-type LEDs stacked sequentially along the bonding surface. Etching barrier layer, n-type GaAs ohmic contact layer, n-type Confinement layer, InGaP / Quantum well structure, p-type Spacer layer and p-GaP hole-providing layer; wherein, =0.1-0.4, y=0.5, n-type The etch barrier layer thickness is 100-300 nm, and the carrier concentration is... The thickness of the n-type GaAs ohmic contact layer is 10-50 nm, and the carrier concentration is... ; =0.7-1、 =0.5, n-type The confinement layer thickness is 150-500 nm, and the carrier concentration is... ; =0.6-0.9、 =0.5, InGaP / The quantum well structure consists of 1-5 pairs, and the InGaP well layer thickness is 1.5-4.5 nm. The barrier layer thickness is 4-10 nm; =0.8-0.9、 =0.5, p-type The spacer layer thickness is 30-100 nm, and the carrier concentration is... The p-GaP hole-providing layer thickness is 100-300 nm, and the carrier concentration is... .

4. A method for fabricating a Si-based hybrid integrated Micro-LED chip according to any one of claims 1-3, characterized in that, Includes the following steps: S1, GaN-based blue-green micro-LED devices are simultaneously grown on a Si substrate through regional selective epitaxy; S2, an n-type electrode is fabricated on the back side of a Si substrate, and the Si-based CMOS driving circuit is interconnected with the Si substrate by bonding; S3, AlGaInP-based red micro-LED devices are grown on GaAs substrates by regional selective epitaxy; S4, temporarily bond the AlGaInP-based red Micro-LED device to the transfer substrate, and after removing the GaAs substrate, precisely bond it to the designated area of ​​the Si-based CMOS substrate completed in S2; S5. A transparent conductive layer and a p-type positive electrode are prepared on the p-type layer surface of the GaN-based blue-green Micro-LED device and the AlGaInP-based red Micro-LED device to complete the chip fabrication.

5. The method for fabricating a Si-based hybrid integrated Micro-LED chip according to claim 4, characterized in that, Step S1 specifically includes the following sub-steps: S11 is deposited on the surface of a Si substrate using PECVD technology. The mask layer has a thickness of 100-500 nm; Among them, the reacting gas is and , The flow rate is 1000-1500 sccm. The flow rate is 200-400 sccm, the plasma source power is 80-120 W, the deposition temperature is 200-300℃, and the deposition rate is 0.8-1.2 nm / s; S12, in A positive photoresist with a thickness of 500-3000 nm is spin-coated onto the mask layer. After curing and UV exposure, it is developed with TMAH aqueous solution for 100-1400 s to form a strip photoresist pattern. In the strip photoresist pattern, the green light area has a size of 2-5 μm and the blue light area has a size of 8-10 μm. S13, ICP etching technology is used to remove the patterned area. Mask layer, etching gas is , The flow rate is 20-30 sccm, the etching time is 300-500 s, and the etching rate is 1.0-1.4 nm / s; After etching, the remaining photoresist is removed using an acetone / isopropanol mixture to obtain a patterned Si substrate; S14, GaN-based epitaxial layers are grown on a patterned Si substrate using MOCVD technology, and then sequentially deposited... Buffer layer, n-GaN electron-donating layer Quantum well structure and p-GaN hole-providing layer.

6. The method for fabricating a Si-based hybrid integrated Micro-LED chip according to claim 4, characterized in that, Step S2 specifically includes the following sub-steps: S21, Patterning is fabricated on the back side of the Si substrate. Mask layer; A composite metal layer is deposited on the exposed Si substrate area using evaporation or sputtering techniques at a deposition rate of 0.8-1.2 nm / s; The underlying metal layer with photoresist is removed by a lift-off process to obtain the back n-type negative electrode; S22, deposit a bonding metal layer on the front side of the CMOS driving circuit backplane; align and bond the bonding metal layer on the back side of the Si substrate with the front side of the CMOS backplane, and bond for 10-60 minutes at 400-700℃ and 3000-9000kg pressure to form an electromechanical connection.

7. The method for fabricating a Si-based hybrid integrated Micro-LED chip according to claim 4, characterized in that, Step S3 specifically includes the following sub-steps: S31, deposited on the surface of a GaAs substrate using PECVD technology. The mask layer has a thickness of 100-500 nm; S32, in Photoresist is coated on the mask layer and patterned to form a photoresist pattern corresponding to the red Micro-LED mesa structure. S33, uses etching technology to remove the patterned area. Mask layer, remove remaining photoresist to obtain patterned GaAs substrate; S34, An AlGaInP-based epitaxial layer is grown on a patterned GaAs substrate using MOCVD technology, followed by the sequential deposition of an n-type GaAs buffer layer and an n-type... Etching barrier layer, n-type GaAs ohmic contact layer, n-type Confinement layer, InGaP / Quantum well structure, p-type Spacer layer and p-type GaP hole-providing layer.

8. The method for fabricating a Si-based hybrid integrated Micro-LED chip according to claim 4, characterized in that, Step S4 specifically includes the following sub-steps: S41, Deposit bonding metal layers on both the surface of the AlGaInP epitaxial layer and the front side of the transfer substrate; Align and bond the bonding metal layers of the two layers together, and bond them for 10-60 min at 400-700℃ and 3000-9000 kg pressure; Remove the GaAs substrate by wet or dry etching to obtain the AlGaInP red light epitaxial layer attached to the transfer substrate. S42, deposit bonding metal layers on the surface of the AlGaInP red light epitaxial layer and in the designated area of ​​the Si-based CMOS substrate completed in S2; align and bond the two layers together, and bond them for 10-60 minutes at 400-700℃ and 3000-9000kg pressure; remove the transfer substrate using physical or chemical methods.

9. The method for fabricating a Si-based hybrid integrated Micro-LED chip according to claim 4, characterized in that, Step S5 specifically includes the following sub-steps: S51 uses evaporation or sputtering techniques to deposit a thick transparent conductive layer on the p-type surface of both the GaN-based blue-green epitaxial layer and the AlGaInP red epitaxial layer, with a thickness of 50-300 nm and a deposition rate of 0.8-1.2 nm / s; a positive photoresist with a thickness of 1000-5000 nm is spin-coated, cured, exposed to ultraviolet light, and then developed with TMAH aqueous solution for 160-200 s; After patterning and etching, anneal at 300-500℃ for 120-240s; S52, positive photoresist is spin-coated onto the surface of the transparent conductive layer, cured, and exposed to ultraviolet light to deposit a composite metal layer; excess metal is removed by a stripping process to obtain a p-type positive electrode.

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