A sub-threshold CMOS reference source with high supply voltage rejection ratio

Abstract

The application discloses a sub-threshold CMOS reference source with high power voltage rejection ratio, and relates to the field of integrated circuits.The reference source is composed of a first-stage starting circuit, a pre-stabilization circuit, a second-stage starting circuit and a core voltage reference circuit.The first-stage starting circuit and the second-stage starting circuit ensure that the circuit enters a normal working state, and the pre-stabilization circuit provides a stable and small-ripple secondary power voltage VDDs for the core voltage reference circuit.The core voltage reference circuit adopts a multi-branch current source to improve the loop phase margin, and the combination of the two can improve the low-frequency PSRR degradation problem of the sub-threshold CMOS reference source.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to a subthreshold CMOS reference source with a high power supply voltage rejection ratio. Background Technology

[0002] Voltage references are indispensable core modules in analog, digital, and mixed-signal circuits. Their core function is to generate a stable reference voltage that is virtually unaffected by fluctuations in power supply voltage, ambient temperature, and manufacturing processes. This module is widely used in A / D converters, various sensors, IoT terminals, and wearable devices. Bandgap references are the most commonly used, but they require diodes and bipolar junction transistors (BJTs). Since the bandgap voltage of silicon is 1.2V, the circuit obviously cannot function properly when the power supply voltage is below 1.2V. Furthermore, traditional bandgap references consume a relatively high amount of power, while these devices are often designed with power consumption in the range of a few microwatts or even lower. To meet these operational requirements, MOSFET voltage references, with their key low-power characteristic, have been widely adopted in related circuit design fields.

[0003] When the gate-source voltage of a MOSFET drops below its threshold voltage, a very small drain-source current exists, known as the "subthreshold current." At this point, the MOSFET operates in the subthreshold region. The gate-source voltage of a subthreshold MOSFET has a negative temperature coefficient. Therefore, this characteristic can be utilized to replace the bipolar transistor in a traditional bandgap reference circuit with a MOSFET operating in the subthreshold region to implement a CMOS reference circuit. This reduces power consumption and overcomes the process incompatibility issues associated with bipolar transistors.

[0004] However, the bias loop bandwidth of subthreshold references is typically only tens to hundreds of hertz, and PSRR is positively correlated with the loop bandwidth. At high frequencies, PSRR drops rapidly, failing to suppress high-frequency noise on the power line, requiring additional filtering circuitry for compensation, thus increasing design complexity. Summary of the Invention

[0005] To address the issue of power supply rejection ratio (PSRR) attenuation in subthreshold CMOS reference sources at high frequencies, this invention provides a high PSRR subthreshold CMOS reference circuit. The circuit includes a first-stage startup circuit, a pre-regulator circuit, a second-stage startup circuit, and a core voltage reference circuit. Both the first-stage and second-stage startup circuits accelerate the startup process of the reference voltage source and prevent the circuit from entering a zero state after power-on; the dual-stage startup circuit increases the reliability of the circuit startup. The pre-regulator circuit provides a stable and low-noise power supply voltage VDDs for the second-stage startup circuit and the core voltage reference circuit. The core voltage reference circuit generates a zero-temperature coefficient reference voltage V. REF .

[0006] The first-stage startup circuit includes: a first capacitor C1, a second capacitor C2, a first MOSFET M1, and a second MOSFET M2. One end of the first capacitor C1 is connected to the power supply VDD, and the other end is connected to the second capacitor C2 and the gate of the first MOSFET M1. One end of the second capacitor C2 is connected to the first capacitor C1 and the gate of the first MOSFET M1, and the other end is connected to ground GND. The gate of the first MOSFET M1 is connected to the drain of the first capacitor C1, the second capacitor C2, and the second MOSFET M2; the source of the first MOSFET M1 is grounded to GND; and the drain of the first MOSFET M1 is connected to a pre-regulatory circuit. The drain of the second MOSFET M2 is connected to the gate of the first MOSFET M1, the first capacitor C1, and the second capacitor C2; the source of the second MOSFET M2 is grounded to GND; and the gate of the second MOSFET M2 is connected to the pre-regulatory circuit.

[0007] The pre-regulator circuit includes: a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, and an eleventh MOSFET M11. Specifically, the source of the third MOSFET M3 is connected to the drain of the fifth MOSFET M5, the gate of the third MOSFET M3 is connected to the gate of the fourth MOSFET M4, and the drain of the third MOSFET M3 is connected to the drain of the seventh MOSFET M7; the drain and gate of the fourth MOSFET M4 are connected together, the drain of the fourth MOSFET M4 is connected to the gate of the eleventh MOSFET M11 and the drain of the ninth MOSFET M9, the gate of the fourth MOSFET M4 is connected to the gate of the third MOSFET M3, and the source of the fourth MOSFET M4 is connected to the drain of the sixth MOSFET M6; the source of the fifth MOSFET M5 is grounded (GND), the drain of the fifth MOSFET M5 is connected to the source of the third MOSFET M3, and the gate of the fifth MOSFET M5 is connected to the gate of the sixth MOSFET M6; the source of the sixth MOSFET M6 is grounded (GND), the drain and gate of the sixth MOSFET M6 are connected together, and the drain of the sixth MOSFET M6 is connected to the source of the fourth MOSFET M4; the drain and gate of the seventh MOSFET M7 are connected together, and the seventh MOSFET M8 is connected to the drain of the seventh MOSFET M9. The drain of transistor M7 is connected to the drain of the third MOSFET M3, the gate of the seventh MOSFET M7 is connected to the gate of the eighth MOSFET M8, and the seventh MOSFET M7 is connected to the power supply VDD; the source of the eighth MOSFET M8 is connected to the power supply VDD, the gate of the eighth MOSFET M8 is connected to the gate of the seventh MOSFET M7, and the drain of the eighth MOSFET M8 is connected to the source of the ninth MOSFET M9 and the secondary power supply VDDs; the source of the ninth MOSFET M9 is connected to the second-stage startup circuit, the drain of the ninth MOSFET M9 is connected to the drain of the fourth MOSFET M4 and the gate of the eleventh MOSFET M11, and the gate of the ninth MOSFET M9 is connected to the core voltage reference circuit; the source of the tenth MOSFET M10 is connected to the secondary power supply VDDs, and the drain and gate of the tenth MOSFET M10 are connected to and connected to the source of the eleventh MOSFET M11; the gate of the eleventh MOSFET M11 is connected to the drain of the ninth MOSFET M9 and the drain of the fourth MOSFET M4, and the drain of the eleventh MOSFET M11 is grounded to GND.

[0008] The second-stage startup circuit includes: a third capacitor C3, a fourth capacitor C4, a twelfth MOSFET M12, and a thirteenth MOSFET M13. One end of the third capacitor C3 is connected to the secondary power supply VDDs, and the other end is connected to the fourth capacitor C4 and the gate of the twelfth MOSFET M12. One end of the fourth capacitor C4 is connected to the third capacitor C3 and the gate of the twelfth MOSFET M12, and the other end is connected to ground GND. The gate of the twelfth MOSFET M12 is connected to the third capacitor C3, the fourth capacitor C4, and the drain of the thirteenth MOSFET M13; the source of the twelfth MOSFET M12 is grounded to GND; and the drain of the twelfth MOSFET M12 is connected to the core voltage reference circuit. The drain of the thirteenth MOSFET M13 is connected to the gate of the twelfth MOSFET M12, the third capacitor C3, and the fourth capacitor C4; the source of the thirteenth MOSFET M13 is grounded to GND; and the gate of the thirteenth MOSFET M13 is connected to the core voltage reference circuit.

[0009] The core voltage reference circuit includes: a fifth capacitor C5, a first resistor R1, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a nineteenth MOSFET M19, a twentieth MOSFET M20, a twenty-first MOSFET M21, a twenty-second MOSFET M22, a twenty-third MOSFET M23, a twenty-fourth MOSFET M24, a twenty-fifth MOSFET M25, a twenty-sixth MOSFET M26, a twenty-seventh MOSFET M27, a twenty-eighth MOSFET M28, a twenty-ninth MOSFET M29, and a thirtieth MOSFET M30. The fifth capacitor C5 has one end connected to ground (GND), and the other end connected to the drain of the twentieth MOSFET M20, the gate of the twenty-fourth MOSFET M24, and the drain of the twenty-fifth MOSFET M25. The first resistor R1 has one end connected to ground (GND), and the other end connected to the source of the twenty-fourth MOSFET M24 and the source of the twenty-sixth MOSFET M26. The source of the fourteenth MOSFET M14 is connected to the secondary power supply VDDs, and the drain and gate of the fourteenth MOSFET M14 are connected together. The drain of the fourteenth MOSFET M14 is connected to the nineteenth MOSFET M25. The source of MOSFET M19 is connected to the source of MOSFET M19. The gate of MOSFET M19 is connected to the gates of MOSFETs M15, M16, M17, and M18. The source of MOSFET M15 is connected to the secondary power supply VDDs, and the drain of MOSFET M15 is connected to the source of MOSFET M20. The source of MOSFET M16 is connected to the secondary power supply VDDs, and the drain of MOSFET M16 is connected to the source of MOSFET M21. The 17th MOSFET... The source of MOSFET M17 is connected to the secondary power supply VDDs, and the drain of MOSFET M17 is connected to the source of MOSFET M22. The source of MOSFET M18 is connected to the secondary power supply VDDs, and the drain of MOSFET M18 is connected to the source of MOSFET M23. The source of MOSFET M19 is connected to the drain of MOSFET M14, the drain and gate of MOSFET M19 are connected together, the drain of MOSFET M19 is connected to the drain of MOSFET M24, and the gate of MOSFET M19 is connected to the twentieth MOSFET M23. The gates of MOSFET M20, M21, M22, and M23 are connected; the source of MOSFET M20 is connected to the drain of MOSFET M15, and the drain of MOSFET M20 is connected to capacitor C5, the gate of MOSFET M24, and the drain of MOSFET M25; the source of MOSFET M21 is connected to the drain of MOSFET M16, and the drain of MOSFET M21 is connected to the drain of MOSFET M26.The source of the 22nd MOSFET M22 is connected to the drain of the 17th MOSFET M17, and the source of the 22nd MOSFET M22 is connected to the drain of the 27th MOSFET M27; the source of the 23rd MOSFET M23 is connected to the drain of the 18th MOSFET M18, and the drain of the 23rd MOSFET M23 is connected to the drain of the 29th MOSFET M29; the source of the 24th MOSFET M24 is connected to the first resistor R1 and the source of the 26th MOSFET M26, and the drain of the 24th MOSFET M24 is connected to the drain of the 19th MOSFET M19. The gate of transistor M24 is connected to the drain of the twentieth MOSFET M20, the fifth capacitor C5, and the drain of the twentyth MOSFET M25; the source of the twenty-fifth MOSFET M25 is grounded (GND), and its gate is connected to the gate of the twenty-sixth MOSFET M26; the drain and gate of the twenty-sixth MOSFET M26 are connected together, its gate is connected to the gate of the twenty-fifth MOSFET M25, its drain is connected to the drain of the twenty-first MOSFET M21, and its source is connected to the twenty-fourth MOSFET M20. 4. Source and first resistor R1; the drain and gate of the 27th MOSFET M27 are connected together, the drain of the 27th MOSFET M27 is connected to the drain of the 22nd MOSFET M22, the gate of the 22nd MOSFET M22 is connected to the gate of the 27th MOSFET M27, the source of the 27th MOSFET M27 is connected to the drain of the 28th MOSFET M28 and the source of the 30th MOSFET M30; the source of the 28th MOSFET M28 is grounded (GND), and the gate of the 28th MOSFET M28 is connected to the gate of the 27th MOSFET M27; the 29th MOSFET M2... The drain and gate of transistor M29 are connected together. The drain of the 29th MOSFET M29 is connected to the drain of the 23rd MOSFET M23, the gate of the 29th MOSFET M29 is connected to the gate of the 30th MOSFET M30, and the source of the 29th MOSFET M29 is connected to the drain of the 30th MOSFET M30. The source of the 30th MOSFET M30 is connected to the drain of the 28th MOSFET M28 and the source of the 27th MOSFET M27, the drain of the 30th MOSFET M30 is connected to the source of the 29th MOSFET M29, and the gate of the 30th MOSFET M30 is connected to the gate of the 29th MOSFET M29. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0011] Figure 1 A circuit diagram of the subthreshold CMOS reference source of the present invention is shown;

[0012] Figure 2A PSRR simulation diagram of the subthreshold CMOS reference source of the present invention is shown. Detailed Implementation

[0013] This invention provides a subthreshold CMOS reference voltage source with high power supply voltage rejection ratio (PSRR) to overcome the problems of existing subthreshold CMOS reference voltage sources where the power supply voltage has a significant impact on the output reference voltage and the PSRR is low. Specifically, the subthreshold CMOS reference voltage source with high PSRR includes a first-stage startup circuit, a pre-regulator circuit, a second-stage startup circuit, and a core voltage reference circuit. The subthreshold CMOS reference voltage source of this disclosure will be described in detail below.

[0014] The first-stage startup circuit includes a first capacitor C1, a second capacitor C2, a first MOSFET M1, and a second MOSFET M2. When the circuit first starts up, the gate voltage of the second MOSFET M2 is low, and the transistor is in the off state. The gate voltage of the first MOSFET M1 is half of the power supply VDD, and the transistor turns on to trigger the seventh MOSFET M7 and the eighth MOSFET M8 of the pre-regulator circuit, causing the pre-regulator circuit to start working.

[0015] The pre-regulator circuit includes a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, and an eleventh MOSFET M11. Among them, the third MOSFET M3, fourth MOSFET M4, fifth MOSFET M5, sixth MOSFET M6, seventh MOSFET M7, and eighth MOSFET M8 form a common-source, common-gate current mirror, increasing the gate-to-ground impedance and making it difficult for low-to-medium frequency ripple to be conducted through the gate-source voltage difference, thus reducing the ripple amplification effect. Figure 1 The pre-regulator circuit generates a secondary power supply voltage VDDs for subsequent circuits, reducing the impact of the power supply voltage VDD ripple on the output reference voltage.

[0016] The second-stage startup circuit includes a third capacitor C3, a fourth capacitor C4, a twelfth MOSFET M12, and a thirteenth MOSFET M13. During circuit operation, the secondary power supply voltage VDDs charges the third capacitor C3 and the fourth capacitor C4. The gate voltage of the thirteenth MOSFET M13 is low, and the transistor is in the off state. The gate voltage of the twelfth MOSFET M12 is half of the secondary power supply voltage VDDs, and this transistor turns on, triggering the fourteenth MOSFET M14 of the core reference circuit to start the core reference circuit.

[0017] The core voltage reference circuit includes: a fifth capacitor C5, a first resistor R1, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a nineteenth MOSFET M19, a twentieth MOSFET M20, a twenty-first MOSFET M21, a twenty-second MOSFET M22, a twenty-third MOSFET M23, a twenty-fourth MOSFET M24, a twenty-fifth MOSFET M25, a twenty-sixth MOSFET M26, a twenty-seventh MOSFET M27, a twenty-eighth MOSFET M28, a twenty-ninth MOSFET M29, and a thirtieth MOSFET M30. Among these, the fourteenth MOSFET M14, the fifteenth MOSFET M15, the sixteenth MOSFET M16, the nineteenth MOSFET M19, the twentieth MOSFET M20, the twenty-first MOSFET M21, the twenty-fourth MOSFET M24, the twenty-fifth MOSFET M25, the twenty-sixth MOSFET M26, the fifth capacitor C5, and the first resistor R1 form a multi-branch reference current source. The multi-branch reference current source has three branches. The multiple branches can effectively isolate power supply noise, and at the same time, they improve system stability through the outer and inner loops, introduce zeros to cancel the low-frequency parasitic poles of the reference source, improve the loop phase margin, and thus allow for an increase in loop bandwidth. The multiple branches can generate a lower reference current, and at the same time provide a stable reference current for the subsequent reference voltage generation circuit that is less affected by the power supply voltage and independent of temperature, thereby improving the power supply voltage rejection ratio and temperature characteristics of the circuit output reference voltage.

[0018] The reference current source is obtained through the gate-source voltage difference ΔV of the 24th MOSFET M24, 25th MOSFET M25, and 26th MOSFET M26 operating in the subthreshold region. GS A reference current is generated by applying it to the first resistor R1.

[0019] Gate-source voltage V of a CMOS transistor operating in subthreshold mode GS It has a negative temperature coefficient:

[0020]

[0021]

[0022]

[0023] The first term in the above formula is the threshold voltage. For a MOSFET operating in the subthreshold region, its threshold voltage VTH changes linearly with increasing temperature and has a negative temperature coefficient. The second term V... T It increases linearly with temperature, while other values ​​are constant in the circuit, which can be regarded as V. TThe coefficient of the second term is such that it has a positive temperature coefficient. By adjusting the coefficient of the second term, the temperature-independent gate-source voltage difference ΔV can be obtained. GS A current I, independent of temperature, is obtained by adding a first resistor R1. R .

[0024]

[0025] In the core voltage reference circuit, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the twenty-second MOSFET M22, the twenty-third MOSFET M23, the twenty-seventh MOSFET M27, the twenty-eighth MOSFET M28, the twenty-ninth MOSFET M29, and the thirtieth MOSFET M30 together form the reference voltage generation circuit. The reference voltage VREF is composed of the gate-source voltages of the twenty-seventh MOSFET M27, the twenty-eighth MOSFET M28, the twenty-ninth MOSFET M29, and the thirtieth MOSFET M30 operating in the subthreshold region.

[0026]

[0027]

[0028] The first term in the above formula is the threshold voltage. For a MOSFET operating in the subthreshold region, the threshold voltage V is... TH The second term V exhibits a linear negative temperature coefficient change with increasing temperature. T It increases linearly with temperature, while other values ​​are constant in the circuit, which can be regarded as V. T The coefficient of the second term is positive, so the second term has a positive temperature coefficient. By adjusting the coefficient of the second term, a temperature-independent reference voltage V can be obtained. REF .

[0029] The fundamental reason for the low low-frequency PSRR of subthreshold CMOS reference sources is the low bias loop gain, which is greatly affected by power supply voltage fluctuations. The core method of this invention to alleviate the low PSRR of subthreshold CMOS reference sources in the low-frequency range is to introduce a pre-regulator circuit and a multi-branch current source into the reference voltage generation circuit. The regulator circuit generates a stable secondary power supply voltage VDDs for subsequent circuits, and the multi-branch current source isolates power supply noise. The fifth capacitor C5 in the multi-branch current source compensates the branch and introduces a zero-point boost loop phase margin to increase the loop bandwidth of the subthreshold CMOS reference source, thereby alleviating the problem of low-frequency PSRR degradation.

Claims

1. A subthreshold CMOS reference source with high power supply voltage rejection ratio, characterized in that, The high power supply voltage rejection ratio subthreshold CMOS reference source comprises four circuit modules: a first-stage startup circuit, a pre-regulator circuit, a second-stage startup circuit, and a core voltage reference circuit. The first-stage startup circuit and the second-stage startup circuit constitute a dual-stage startup to ensure that the circuit enters a normal working state. After startup is completed, the two-stage startup circuits automatically shut down. The function of the pre-regulator circuit is to convert the wide-range fluctuating input voltage VDD into a stable intermediate supply voltage VDDs; The core voltage reference circuit includes a reference current source and a reference voltage generation circuit. The reference current source generates a temperature-independent reference current, which is replicated to the reference voltage generation circuit via a current mirror to produce a reference voltage V with zero temperature coefficient. REF .

2. The subthreshold CMOS reference source according to claim 1, characterized in that, The pre-regulator circuit includes: a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, and an eleventh MOSFET M11; the source of the third MOSFET M3 is connected to the drain of the fifth MOSFET M5, the gate of the third MOSFET M3 is connected to the gate of the fourth MOSFET M4, and the drain of the third MOSFET M3 is connected to the drain of the seventh MOSFET M7; the drain and gate of the fourth MOSFET M4 are connected together, the drain of the fourth MOSFET M4 is connected to the gate of the eleventh MOSFET M11 and the drain of the ninth MOSFET M9, and the source of the fourth MOSFET M4 is connected to the drain of the sixth MOSFET M6; the source of the fifth MOSFET M5 is grounded (GND), and the gate of the fifth MOSFET M5 is connected to the sixth MOSFET M6. Gate; the source of the sixth MOSFET M6 is grounded to GND, and the drain and gate of the sixth MOSFET M6 are connected together; the drain and gate of the seventh MOSFET M7 are connected together, and the gate of the seventh MOSFET M7 is connected to the gate of the eighth MOSFET M8, and the seventh MOSFET M7 is connected to the power supply VDD; the source of the eighth MOSFET M8 is connected to the power supply VDD, and the drain of the eighth MOSFET M8 is connected to the source of the ninth MOSFET M9 and the secondary power supply VDDs; the drain of the ninth MOSFET M9 is connected to the gate of the eleventh MOSFET M11, and the gate of the ninth MOSFET M9 is connected to the core voltage reference circuit as the first output terminal of the pre-regulator circuit; the source of the tenth MOSFET M10 is connected to the secondary power supply VDDs, and the drain and gate of the tenth MOSFET M10 are connected to and connected to the source of the eleventh MOSFET M11; the drain of the eleventh MOSFET M11 is grounded to GND.

3. The subthreshold CMOS reference source according to claim 1, characterized in that, The pre-regulator circuit generates a secondary power supply voltage VDDs for subsequent circuits, reducing the impact of the power supply voltage VDD ripple on the output reference voltage.

4. The subthreshold CMOS reference source according to claim 1, characterized in that, The core voltage reference circuit includes: a fifth capacitor C5, a first resistor R1, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a nineteenth MOSFET M19, a twentieth MOSFET M20, a twenty-first MOSFET M21, a twenty-second MOSFET M22, a twenty-third MOSFET M23, a twenty-fourth MOSFET M24, a twenty-fifth MOSFET M25, a twenty-sixth MOSFET M26, a twenty-seventh MOSFET M27, a twenty-eighth MOSFET M28, a twenty-ninth MOSFET M29, and a thirtieth MOSFET M30; One end of the fifth capacitor C5 is connected to ground (GND), and the other end of the fifth capacitor C5 is connected to the drain of the twentieth MOSFET M20, the gate of the twenty-fourth MOSFET M24, and the drain of the twenty-fifth MOSFET M25. One end of the first resistor R1 is connected to ground (GND), and the other end of the first resistor R1 is connected to the source of the twenty-fourth MOSFET M24 and the source of the twenty-sixth MOSFET M26. The source of the fourteenth MOSFET M14 is connected to the secondary power supply VDDs, the drain and gate of the fourteenth MOSFET M14 are connected together, the drain of the fourteenth MOSFET M14 is connected to the source of the nineteenth MOSFET M19, and the gate of the fourteenth MOSFET M19 is connected to the gates of the fifteenth MOSFET M15, the sixteenth MOSFET M16, and the seventeenth MOSFET M17. The gate of the eighteenth MOSFET M18 is connected to the secondary power supply VDDs; the source of the fifteenth MOSFET M15 is connected to the secondary power supply VDDs, and the drain of the fifteenth MOSFET M15 is connected to the source of the twentieth MOSFET M20; the source of the sixteenth MOSFET M16 is connected to the secondary power supply VDDs, and the drain of the sixteenth MOSFET M16 is connected to the source of the twenty-first MOSFET M21; the source of the seventeenth MOSFET M17 is connected to the secondary power supply VDDs, and the drain of the seventeenth MOSFET M17 is connected to the source of the twenty-second MOSFET M22; the source of the eighteenth MOSFET M18 is connected to the secondary power supply VDDs, and the drain of the eighteenth MOSFET M18 is connected to the source of the twenty-third MOSFET M23; the gate and drain of the nineteenth MOSFET M19 are connected together. The drain of M19 is connected to the drain of the 24th MOSFET M24; the gate of the 19th MOSFET M19 is connected to the gates of the 20th MOSFET M20, the 21st MOSFET M21, the 22nd MOSFET M22, and the 23rd MOSFET M23; the drain of the 20th MOSFET M20 is connected to the fifth capacitor C5, the gate of the 24th MOSFET M24, and the drain of the 25th MOSFET M25; the drain of the 21st MOSFET M21 is connected to the drain of the 26th MOSFET M26; the source of the 22nd MOSFET M22 is connected to the drain of the 27th MOSFET M27; the drain of the 23rd MOSFET M23 is connected to the drain of the 29th MOSFET M29; the 25th MOSFET M2...

5. The source of MOSFET M25 is grounded to GND. The gate of MOSFET M25 is connected to the gate of MOSFET M26. The drain and gate of MOSFET M26 are connected together. The drain and gate of MOSFET M27 are connected together. The gate of MOSFET M27 is connected to the gate of MOSFET M28. The source of MOSFET M27 is connected to the drain of MOSFET M28 and the source of MOSFET M30. The source of MOSFET M28 is grounded to GND. The drain and gate of MOSFET M29 are connected together. The gate of MOSFET M29 is connected to the gate of MOSFET M30. The source of MOSFET M29 is connected to the drain of MOSFET M30.

5. The subthreshold CMOS reference source according to claim 6, characterized in that, The fourteenth MOSFET M14, the fifteenth MOSFET M15, the sixteenth MOSFET M16, the nineteenth MOSFET M19, the twentieth MOSFET M20, the twenty-first MOSFET M21, the twenty-fourth MOSFET M24, the twenty-fifth MOSFET M25, the twenty-sixth MOSFET M26, the fifth capacitor C5, and the first resistor R1 form a multi-branch reference current source. The drain current of the twenty-fourth MOSFET M24 is the reference current generated by the reference current source. The multi-branch reference current source isolates the reference core from the power supply, reducing the interference of voltage noise on the reference current. It also utilizes the newly added branches to construct low-frequency, high-gain negative feedback, improving the loop's ability to suppress power supply voltage fluctuations. This effectively solves the problem of poor PSRR in the low-frequency band of subthreshold CMOS reference sources.

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