Aging prediction method for ASIC special password intelligent chip

Abstract

The invention discloses an ASIC special password intelligent chip aging prediction method, and relates to the field of chip aging prediction, and the method comprises the steps: carrying out the feature fusion coding through obtaining chip power supply wiring layer data and collecting environment parameters, obtaining an aging sensitivity feature vector, carrying out the fractional order aging dynamics modeling based on the aging sensitivity feature vector, and carrying out the aging prediction. Performing chip aging state prediction based on the chip aging state change equation to obtain an aging track prediction sequence, extracting an aging sensitivity feature vector component and the aging track prediction sequence to perform residual life probability evaluation, and obtaining a residual life cumulative distribution function; on the basis of the residual life cumulative distribution function, uncertainty analysis is carried out on chip aging prediction to obtain a two-factor risk index, a coupling aging rule between hardware structure weakness and environmental stress is grasped, real aging sensitive points of the chip can be accurately reflected, and accurate reference can be provided for preventive maintenance of the chip.

Description

Technical Field

[0001] This invention relates to the field of chip aging prediction, specifically to an aging prediction method for ASIC-specific cryptographic smart chips. Background Technology

[0002] Existing aging prediction methods for dedicated cryptographic smart chips in ASICs suffer from a single feature dimension. They focus only on the chip's hardware structural parameters, such as power network routing or logic unit layout, while ignoring the dynamic effects of environmental stresses such as temperature fluctuations and voltage ripple. They only consider static environmental data such as temperature and current, failing to comprehensively consider hardware topology characteristics such as clock tree load distribution and logic unit utilization. They cannot grasp the coupled aging patterns between hardware structural weaknesses and environmental stresses, and the extracted features are one-sided, failing to accurately reflect the chip's true aging sensitivity points.

[0003] There are also obvious shortcomings in modeling and risk assessment. The modeling uses an integer-order dynamic model, which assumes that aging is a short-term memory process. However, it does not take into account the long-term dependence characteristics of the cryptographic chip caused by the accumulation of current ripple and the superposition of voltage fluctuations in high-frequency encryption operations. This leads to a large deviation in the prediction of long-term aging trajectory. At the same time, the risk assessment is crude, using a single lifetime threshold for judgment. It cannot quantify the failure risk boundary under different probabilities, nor does it take into account the potential risks under extreme operating conditions. In particular, it does not adequately consider the dynamic load changes of the cryptographic chip in encryption mode and standby mode. The threshold is set fixedly, and the aging risk obtained is far from the actual operating conditions, which cannot provide an accurate reference for the chip's preventive maintenance.

[0004] To address the aforementioned shortcomings, a technical solution is provided. Summary of the Invention

[0005] To address the technical problems raised in the background section, this invention is proposed. Embodiments of this invention provide an aging prediction method for ASIC-specific cryptographic smart chips.

[0006] The objective of this invention can be achieved through the following technical solution: an aging prediction method for ASIC-specific cryptographic smart chips, comprising the following steps:

[0007] Step S100: Obtain chip power wiring layer data and collected environmental parameters, perform feature fusion encoding, and obtain aging sensitivity feature vector;

[0008] Step S200: Perform fractional-order aging dynamics modeling based on the aging sensitivity feature vector to obtain the chip aging state change equation;

[0009] Step S300: Predict the chip aging state based on the chip aging state change equation to obtain the aging trajectory prediction sequence;

[0010] Step S400: Extract the aging sensitivity feature vector components and aging trajectory prediction sequence to perform remaining lifetime probability assessment and obtain the remaining lifetime cumulative distribution function;

[0011] Step S500: Based on the cumulative distribution function of remaining lifetime, perform uncertainty analysis on chip aging prediction to obtain a two-factor risk index.

[0012] Furthermore, the aging sensitivity feature vector analysis steps are as follows:

[0013] Digital temperature sensors are deployed in key areas of the chip to collect and process junction temperatures in real time, thereby obtaining a working temperature sequence.

[0014] Collect the core power supply voltage and calculate the instantaneous deviation between the core power supply voltage and the nominal voltage to obtain the voltage fluctuation sequence;

[0015] The current in the power supply circuit is measured and the AC component of the power supply circuit current is extracted. The root mean square value is then calculated to obtain the current ripple sequence.

[0016] An environmental time-series data vector is constructed by synchronizing the operating temperature sequence, voltage fluctuation sequence, and current ripple sequence with timestamps.

[0017] After tensorizing the topological impedance parameter set, it is normalized and then concatenated to obtain a static feature vector. The environmental time series data vector is input into the sliding window processor to generate a time-varying feature sequence. The static feature vector and the dynamic feature sequence are input into the gated cyclic encoder, and cross-domain feature fusion is performed through the gating mechanism to obtain the aging sensitivity feature vector.

[0018] Furthermore, the analysis steps for the topological impedance parameter set are as follows:

[0019] Based on the power routing layer data of the chip layout, a three-dimensional chip power network topology is established with power pads as input nodes, standard cell power connection points as terminal nodes, and metal traces as connection edges. The resistance values ​​between nodes are obtained through four-probe measurement technology. Based on the resistance values ​​between nodes, the admittance matrix is ​​established through node analysis. The equivalent resistance between any two nodes is obtained by solving the linear equation system, and the power network resistance matrix is ​​constructed.

[0020] Static timing analysis tools are used to extract the position information of the trigger clock pins at the end of the clock tree, calculate the load capacitance of the clock endpoints, and generate the clock tree load vector by grouping by clock domain.

[0021] The total number of available logical units is calculated using the layout and routing data, the number of instantiated logical units is counted, and the logical unit utilization rate is calculated based on the total number of available logical units and the number of instantiated logical units.

[0022] The power network resistance matrix, clock tree load vector, and logic cell utilization constitute the topology impedance parameter set.

[0023] Furthermore, the analysis steps for the chip aging state change equation are as follows:

[0024] The aging sensitivity feature vector is transformed linearly to obtain the initial aging degree. The aging sensitivity feature vector is then input into a temporal convolutional network to extract the time-varying diffusion coefficient through dilated convolutional layers. Finally, the aging sensitivity feature vector is input into a two-layer perceptron to output the Hearst exponent.

[0025] Initial aging degree, time-varying diffusion coefficient, and Hearst exponent constitute the ternary aging core parameter set;

[0026] A fractional Brownian motion model of chip aging is created based on a ternary aging kernel parameter set. The chip aging fractional Brownian motion model is expanded by total differential through fractional Itoh lemma functions to obtain the chip aging state change equation.

[0027] Furthermore, the aging trajectory prediction sequence analysis steps are as follows:

[0028] The chip aging state change equation is expanded to obtain the chip aging linear term, chip aging subvariance term, and chip aging fractional term. The chip aging linear term is expanded by first-order Taylor to obtain the linear degradation mapping matrix. The chip aging subvariance term is calculated by second-order moment to obtain the noise amplification matrix. The chip aging fractional term is weighted by Grünwald-Letnikov history to obtain the memory effect mapping matrix. The linear degradation mapping matrix, noise amplification matrix, and memory effect mapping matrix are superimposed to obtain the state transition matrix. The linear degradation mapping matrix is ​​multiplied by the time-varying diffusion coefficient to obtain the noise control matrix. The state transition matrix and the noise control matrix constitute the discrete aging state transition parameter set.

[0029] Based on the discrete aging state transition parameter set, a discrete state equation for chip aging is created. For each future prediction step, a state recursion calculation is performed. During the iteration, the aging degree component is extracted from the two-dimensional discrete state vector to form an aging trajectory prediction sequence.

[0030] Furthermore, the two-dimensional discrete state vector analysis steps are as follows:

[0031] The chip aging state change equation is reconstructed into a continuous-time state vector, which includes the current aging degree and continuous fractional derivative terms. The continuous fractional derivative terms are discretized using the Grünwald-Letnikov fractional discretization method to obtain fractional difference terms. Substituting the fractional difference terms into the continuous-time state vector yields a two-dimensional discrete state vector.

[0032] Furthermore, the analysis steps for the cumulative distribution function of remaining lifetime are as follows:

[0033] The aging degree at each future moment in the aging trajectory prediction sequence is modeled as a Gaussian distribution using the posterior covariance matrix of fractional Kalman filtering. The probability density function of the Gaussian distribution is then integrated with the time-varying failure threshold using tail probability to obtain the probability of aging degree exceeding the threshold. The path-dependent joint probability of the probability of aging degree exceeding the threshold is then calculated to obtain the conditional probability of first crossing. The conditional probability of first crossing is then accumulated and integrated over time to obtain the cumulative distribution function of remaining lifetime.

[0034] Furthermore, the time-varying threshold function analysis steps are as follows:

[0035] The first 64 dimensions of the aging sensitivity feature vector are extracted, and the basic failure threshold is calculated through linear transformation. The last 64 dimensions of the aging sensitivity feature vector are input into a time-aware fully connected network to output the threshold offset that changes over time. The basic failure threshold and the time-varying threshold offset are linearly calculated to obtain the time-varying threshold function.

[0036] Furthermore, the steps for the two-factor risk index analysis are as follows:

[0037] Within a set confidence level and probability upper limit, sampling points are selected at equal intervals, and the lifetime value corresponding to each sampling point is calculated by interpolation using the inverse function of the cumulative distribution function of remaining lifetime.

[0038] The conditional value of risk is obtained by calculating the lifetime value corresponding to each sampling point;

[0039] Combining conditional value of risk and risk boundary value yields a two-factor risk index.

[0040] Furthermore, the risk boundary value analysis steps are as follows:

[0041] Monotonic cubic spline interpolation is performed on the cumulative distribution function of remaining lifetime to generate a continuously differentiable interpolation function;

[0042] Set a confidence level, initialize the search interval based on a continuously differentiable interpolation function, calculate the first inner sub-point and the second inner sub-point using the endpoints of the search interval and the golden section point, calculate the difference between the first inner sub-point and the confidence level using the interpolation function to obtain the first evaluation function value, and calculate the difference between the second inner sub-point and the confidence level to obtain the second evaluation function value.

[0043] If the absolute value of the first evaluation function is less than the set threshold, the corresponding inner point is output as the risk boundary value; otherwise, the search interval is updated based on the sign of the product of the first and second evaluation function values, and iterated until the interval length is less than the set threshold, and the risk boundary value is output.

[0044] Compared with the prior art, the beneficial effects of the present invention are:

[0045] 1. This invention obtains an aging sensitivity feature vector by acquiring chip power routing layer data and collecting environmental parameters for feature fusion encoding. Based on the aging sensitivity feature vector, fractional-order aging dynamics modeling is performed to obtain the chip aging state change equation. Based on the chip aging state change equation, chip aging state prediction is performed to obtain an aging trajectory prediction sequence. The aging sensitivity feature vector components and the aging trajectory prediction sequence are extracted to perform remaining lifetime probability assessment to obtain the remaining lifetime cumulative distribution function. This invention not only focuses on the chip's hardware structural parameters, such as power network routing or logic unit layout, but also considers the dynamic impact of environmental stresses such as temperature fluctuations and voltage ripple. It takes into account environmental data such as temperature and current, and can comprehensively consider hardware topology characteristics such as clock tree load distribution and logic unit utilization. It grasps the coupled aging law between hardware structural weaknesses and environmental stresses, and can accurately reflect the chip's true aging sensitivity points.

[0046] 2. This invention analyzes the uncertainty of chip aging prediction based on the residual lifetime cumulative distribution function, and obtains a two-factor risk index. The model adopts an aging fractional Brownian motion model, which can take into account the long-term dependence characteristics of current ripple accumulation and voltage fluctuation superposition in high-frequency encryption operations of cryptographic chips. The long-term aging trajectory prediction deviation is accurate. At the same time, the risk assessment can quantify the failure risk boundary under different probabilities and can also consider the potential risks under extreme operating conditions. In particular, it comprehensively considers the dynamic load changes of cryptographic chips in encryption mode and standby mode. The obtained aging risk is consistent with the actual operating conditions and can provide an accurate reference for the preventive maintenance of chips. Attached Figure Description

[0047] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The following drawings are not drawn to scale according to the actual size, but are intended to show the main idea of ​​the present invention.

[0048] Figure 1 This is a flowchart of the method of the present invention;

[0049] Figure 2 This is a flowchart of step S100 of the present invention;

[0050] Figure 3 This is a flowchart of step S500 of the present invention. Detailed Implementation

[0051] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are also within the scope of protection of the present invention.

[0052] like Figure 1 As shown, an aging prediction method for ASIC-specific cryptographic smart chips includes the following steps:

[0053] Step S100: Obtain chip power wiring layer data and collected environmental parameters, perform feature fusion encoding, and obtain aging sensitivity feature vector;

[0054] Specifically, environmental parameters collected include chip temperature, voltage, and current data;

[0055] Step S200: Perform fractional-order aging dynamics modeling based on the aging sensitivity feature vector to obtain the chip aging state change equation;

[0056] Step S300: Predict the chip aging state based on the chip aging state change equation to obtain the aging trajectory prediction sequence;

[0057] Step S400: Extract the aging sensitivity feature vector components and aging trajectory prediction sequence to perform remaining lifetime probability assessment and obtain the remaining lifetime cumulative distribution function;

[0058] Step S500: Based on the cumulative distribution function of remaining lifetime, perform uncertainty analysis on chip aging prediction to obtain a two-factor risk index;

[0059] like Figure 2 As shown, the specific analysis of step S100 is as follows:

[0060] Based on the power routing layer data of the chip layout, a three-dimensional chip power network topology is established with power pads as input nodes, standard cell power connection points as terminal nodes, and metal traces as connection edges. The resistance values ​​between nodes are obtained through four-probe measurement technology. Based on the resistance values ​​between nodes, the admittance matrix is ​​established through node analysis. The equivalent resistance between any two nodes is obtained by solving the linear equation system, and the power network resistance matrix is ​​constructed.

[0061] Static timing analysis tools are used to extract the position information of the trigger clock pins at the end of the clock tree, calculate the load capacitance of the clock endpoints, and generate the clock tree load vector by grouping by clock domain.

[0062] The total number of available logical units is calculated using the layout and routing data, the number of instantiated logical units is counted, and the logical unit utilization rate is calculated based on the total number of available logical units and the number of instantiated logical units.

[0063] The power network resistance matrix, clock tree load vector, and logic cell utilization constitute the topology impedance parameter set.

[0064] Specifically, based on the power routing layer data of the chip layout, a three-dimensional chip power network topology is established, using power pads as input nodes, standard cell power connection points as terminal nodes, and metal traces as connection edges. Based on this topology, a constant current is injected into selected nodes using four-probe measurement technology to measure the voltage difference between adjacent nodes. Resistance values ​​are calculated using Ohm's law. Based on the resistance values ​​between nodes, an admittance matrix is ​​established using nodal analysis. Solving the linear equations yields the equivalent resistance between any two nodes, thus constructing the power network resistance matrix R. grid ∈R U×U This is a symmetric positive definite matrix describing the equivalent resistance relationship between any two nodes in a chip power network. U represents the total number of nodes in the power network (including power pad input nodes and standard cell terminal nodes). The row / column indices correspond to the node numbers (e.g., row w and column d represent the relationship between node w and node d). Matrix elements r... wd , representing the equivalent resistance value between power nodes w and d; the gate-level netlist is parsed using static timing analysis tools to extract the flip-flop clock pin location information at the end of the clock tree; combined with the parasitic parameter extraction results, the load capacitance of each end node is calculated, including metal interconnect capacitance and gate input capacitance; end nodes belonging to the same clock domain are grouped according to the clock domain definition file; and the total load capacitance c of each clock domain o is calculated. o =∑(Cwire+Cgate), generating the clock tree load vector, where T represents the transpose of the matrix, and the quantization table c o The drive load requirements of the o-th clock domain are shown; the total area of ​​the programmable logic region and the area of ​​the basic logic cells in the standard cell library are obtained from the placement and routing database, the total number of available logic cells is calculated (equal to the total area of ​​the programmable logic region divided by the area of ​​the basic logic cells), the netlist instances are traversed, the number of instantiated logic cells is counted, and the number of instantiated logic cells is divided by the total number of available logic cells to obtain the logic cell utilization rate, a scalar value, which is in the range of [0,1]; the topology impedance parameter set S={R grid C ck U log}, where U log It represents the utilization rate of logic units, provides a hardware topology basis for subsequent feature fusion, the resistance matrix reflects the power supply stability, the load vector represents the timing critical path pressure, and the utilization rate indicates the distribution of functional module aging risk.

[0065] It should be noted that the calculation steps for metal interconnect capacitance and gate input capacitance are as follows: Based on the physical coordinates of the flip-flop clock pins in the layout, the total length L of the metal traces from the clock source to each pin is calculated using the Manhattan distance algorithm. Combined with the unit length capacitance parameter Cunit provided in the process documentation (including interlayer capacitance Ca and edge capacitance Cf), the metal interconnect capacitance Cwire is calculated using the formula Cwire = L × (Ca + 2Cf). Simultaneously, the input capacitance model parameters of the flip-flop cells are extracted from the standard cell library. The corresponding gate input capacitance reference value Cgate0 is selected based on the drive strength level, and then calculated using the load scaling factor formula. Voltage correlation correction is performed, where q is the process correlation coefficient, ultimately yielding the accurate gate input capacitance value Cgate, where V DD Vth represents the power supply voltage, the positive power supply voltage when the chip is working, and Vth represents the threshold voltage, the critical gate-source voltage at which the MOSFET moves from the cutoff region to the saturation region.

[0066] Digital temperature sensors are deployed in key areas of the chip to collect and process junction temperatures in real time, thereby obtaining a working temperature sequence.

[0067] Collect the core power supply voltage and calculate the instantaneous deviation between the core power supply voltage and the nominal voltage to obtain the voltage fluctuation sequence;

[0068] The current in the power supply circuit is measured and the AC component of the power supply circuit current is extracted. The root mean square value is then calculated to obtain the current ripple sequence.

[0069] An environmental time-series data vector is constructed by synchronizing the operating temperature sequence, voltage fluctuation sequence, and current ripple sequence with timestamps.

[0070] Specifically, digital temperature sensors are deployed in key areas of the chip (specifically, the arithmetic unit, memory unit, and I / O interface). A thermistor array is used to monitor the junction temperature in real time at a sampling frequency of 1kHz (where junction temperature is the actual operating temperature of the PN junction or active region inside the electronic device, and is a key parameter for measuring the device's heat dissipation state). After conversion by an on-chip ADC, the data from multiple sensors are weighted and averaged (weights are allocated according to the power density of the region) to obtain an accurate operating temperature sequence T(t). The core power supply voltage Vcore(t) (core power supply refers to the voltage provided by the internal logic cores of the chip (such as CPU, GPU, encryption engine, etc.)) is sampled at the same frequency by a 12-bit ADC built into the power management unit, and its instantaneous deviation from the nominal voltage Vnom is calculated. The voltage fluctuation sequence ΔV(t) = Vcore(t) - Vnom represents the voltage fluctuation. At the same time, a current probe is used to measure the power supply circuit current I(t), and the AC component is extracted by a digital bandpass filter (passband range 0.1-100MHz) and its root mean square value is calculated. The current ripple sequence δI(t) is obtained (where I AC (t τ The ) represents the AC component of the current, extracted by a digital bandpass filter, suppressing DC bias; G represents the number of sampling window points; τ represents the sampling point index; t τ The sampling time is used as the quantization value of the current ripple. Finally, the three signals are synchronized with timestamps to construct the environmental time-series data vector E(t)=[T(t),ΔV(t),δI(t)] T Temperature reflects thermal stress accumulation, voltage fluctuation indicates power supply stability, and current ripple is related to electromigration aging rate. These three factors together constitute the set of key environmental parameters that affect chip aging.

[0071] After tensorizing the topological impedance parameter set, it is normalized and then concatenated to obtain a static feature vector. The environmental time series data vector is input into the sliding window processor to generate a time-varying feature sequence. The static feature vector and the dynamic feature sequence are input into the gated cyclic encoder, and cross-domain feature fusion is performed through the gating mechanism to obtain a 128-dimensional aging sensitivity feature vector.

[0072] Specifically, the topological impedance parameter set is tensorized, where the power network resistance matrix is ​​flattened into an eigenvector, the clock tree load vector is reduced to dimensionality using principal component analysis, and the logic unit utilization is expanded into a regional distribution histogram. These three are then concatenated after min-max normalization to form a static eigenvector. The environmental time-series data vector is input into a sliding window processor, which calculates the statistical characteristics (including mean, variance, peak factor, and kurtosis) of each channel within a 1ms time window, generating a time-varying feature sequence. The static eigenvector and dynamic feature sequence are then input into a gated recurrent unit (GRU) encoder. This encoder contains a three-layer, 128-unit GRU network, achieving cross-domain feature fusion through a gating mechanism: updating the gate's historical state retention ratio, resetting the gate to adjust the new feature fusion weights, and finally outputting the hidden state to adjust the new feature fusion weights. The final output hidden state is mapped to a 128-dimensional aging sensitivity feature vector through a fully connected layer. This vector integrates the relationship between hardware topology characteristics and environmental dynamic response, with the first 64 dimensions encoding the aging sensitivity structure and the last 64 dimensions representing the environmental stress accumulation effect, providing a highly discriminative feature representation for subsequent aging modeling.

[0073] Specifically, step S200 is analyzed as follows:

[0074] The aging sensitivity feature vector is transformed linearly to obtain the initial aging degree. The aging sensitivity feature vector is then input into a temporal convolutional network to extract the time-varying diffusion coefficient through dilated convolutional layers. Finally, the aging sensitivity feature vector is input into a two-layer perceptron to output the Hearst exponent.

[0075] Initial aging degree, time-varying diffusion coefficient, and Hearst exponent constitute the ternary aging core parameter set;

[0076] Specifically, the aging sensitivity feature vector is input into a fully connected neural network for feature decoupling. The initial aging degree A0 is calculated from the first 64 dimensions of the structural aging feature components, specifically obtained through linear transformation: A0 = W A ·F 1:64 +b A Weight matrix W A and bias b A The mapping relationship between the initial degradation state of the chip and the hardware topology is learned through pre-training, F 1:64 This represents the first 64 dimensions of the aging sensitivity feature vector, which are structural aging feature components. The time-varying diffusion coefficient is dynamically generated by the dynamic feature components. The aging sensitivity feature vector components F... 65:128 Input a temporal convolutional network (TCN), and extract the time-varying diffusion coefficient through dilated convolutional layers. Where s represents the continuous-time variable, the current time step, and h represents the convolution kernel index, h = 0, 1, 2, ..., H0, ω h The convolution kernel weights are learnable parameters (training and updating). φ(·) represents the cubic spline basis function, and its output coefficients are positively correlated with the aging rate. Δt represents the time step. The Hearst exponent H is calculated through a gating mechanism: first, the full-feature aging sensitivity feature vector F is input into a two-layer perceptron, h = ReLU(W). h F+b h ), where F represents the aging sensitivity feature vector, ReLU represents the activation function, and W h This represents the first layer weight, b. h This represents the first layer bias, followed by constraints from the Sigmoid activation function. To the interval (0,1), where W H This represents the weights of the second layer, b. H The second layer bias is indicated by H, which quantifies the long-range dependence of the aging process. When H > 0.5, it represents persistent aging (historical degradation accelerates future degradation), and when H < 0.5, it indicates anti-persistent aging (historical degradation slows down future degradation). The ternary aging kernel parameter set (A0, σ(s), H) is used. A0 reflects the inherent aging tendency of the structure, σ(s) controls the intensity of degradation fluctuations under environmental stress, and H determines the memory characteristics of the aging path. Together, they constitute the core parameter set for chip degradation dynamics modeling.

[0077] A fractional Brownian motion model of chip aging is created based on a ternary aging kernel parameter set. The fractional Brownian motion model of chip aging is expanded by total differential through fractional Itoh lemma function to obtain the chip aging state change equation.

[0078] Specifically, the fractional-order Brownian motion model for chip aging includes: Where A tThis indicates the degree of chip aging, the cumulative degradation over time t, in dB. H (s) represents the fractional Brownian motion differential, driving the random noise of aging. The fractional Itō lemma functions include: Where f(A) t ) represents the aging state function, df(A) t () represents the total differential of the function f. and The function f represents the pair of A t First-order partial derivatives and function f with respect to A t The second-order partial derivative, (dA) t ) 2 Denotes the second variation of the differential, (dA) t ) 2 =σ 2 (t)dt 2H , This represents the Riemann-Liouville fractional derivative. Γ represents the gamma function, u is the integration variable, and represents any intermediate state point within the integration interval [0, At]. t ) H Denotes the H-order differential variation, (dA) t ) H =σ H (t)(dB H (t)) H .

[0079] Specifically, step S300 is analyzed as follows:

[0080] The chip aging state change equation is reconstructed into a continuous-time state vector, which includes the current aging degree and continuous fractional derivative terms. The continuous fractional derivative terms are discretized using the Grünwald-Letnikov fractional discretization method to obtain fractional difference terms. Substituting the fractional difference terms into the continuous-time state vector yields a two-dimensional discrete state vector.

[0081] The chip aging state change equation is expanded to obtain the chip aging linear term, chip aging subvariance term, and chip aging fractional term. The chip aging linear term is expanded by first-order Taylor to obtain the linear degradation mapping matrix. The chip aging subvariance term is calculated by second-order moment to obtain the noise amplification matrix. The chip aging fractional term is weighted by Grünwald-Letnikov history to obtain the memory effect mapping matrix. The linear degradation mapping matrix, noise amplification matrix, and memory effect mapping matrix are superimposed to obtain the state transition matrix. The linear degradation mapping matrix is ​​multiplied by the time-varying diffusion coefficient to obtain the noise control matrix. The state transition matrix and the noise control matrix constitute the discrete aging state transition parameter set.

[0082] Based on the discrete aging state transition parameter set, a chip aging discrete state equation is created. For each future prediction step, a state recursion calculation is performed. During the iteration, the aging degree component is extracted from the two-dimensional discrete state vector to form an aging trajectory prediction sequence.

[0083] Specifically, the continuous-time state vector is Represent the current aging level and the fractional derivative term (historical path dependency), respectively; the fractional difference term is... Where H represents the Hearst exponent, k represents the current time step number, and j represents the historical time step number. Denotes the coefficient of a fractional binomial. A k-j The aging degree is represented by Δt at the kj-th historical time step, where Δt represents the discretized sampling time interval. H A k Represents fractional difference terms, a two-dimensional discrete state vector. The linear term, the subvariable term, and the fractional term of chip aging are respectively: and The linear degenerate mapping matrix is α represents the linear degradation rate, and β is the noise amplification matrix. σ(k) represents the time-varying diffusion coefficient, where Memory effect mapping matrix Where γ represents the memory coupling strength. State transition matrix The noise control matrix A = K1σ(k), the state transition matrix, and the noise control matrix constitute the discrete aging state transition parameter set M = {K, A}, where the state transition matrix ∈ R. 2*2 Encoding aging state transition logic, noise control matrix ∈ R 2*1 The intensity of environmental noise injection is controlled, and both fully preserve the dynamic characteristics of the discrete state equations of continuous chip aging.

[0084] Get the current status of the chip Create the discrete state equation for chip aging as X k+n =KX k+n-1 +Aω k Where n represents each future prediction step n = 1, 2, ..., N1, ω k+n Represents discretized noise, ω k+n It follows the order N(0,(Δt)). 2H This simulation addresses the impact of random environmental disturbances on the aging process, where N represents a normal (Gaussian) distribution. For each future prediction step, a state recursion calculation is performed, extracting the aging degree component B from the state vector in each iteration. k+n =Xk+n [1], Output the ordered set {B} k+1 B k+2 ,...,B k+N This constitutes an aging trajectory prediction sequence, the generation mechanism of which deeply integrates 1) fractional-order memory effect (through Δ... H A k 1) Implementation of historical state weighting); 2) Environmental stress fluctuations (through noise term Aω) k 3) Nonlinear propagation of degradation path (determined by state transition matrix K), ultimately achieving high-precision prediction of future aging trajectory.

[0085] Specifically, step S400 is analyzed as follows:

[0086] The first 64 dimensions of the aging sensitivity feature vector are extracted, and the basic failure threshold is calculated through linear transformation. The last 64 dimensions of the aging sensitivity feature vector are input into the time-aware fully connected network to output the threshold offset that changes with time. The basic failure threshold and the time-varying threshold offset are linearly calculated to obtain the time-varying threshold function.

[0087] Specifically, the first 64 dimensions of the aging sensitivity feature vector are extracted, and then linearly transformed. Calculate the basic failure threshold Where the weight matrix W g1 and bias b g1 F was learned through pre-training 1:64 The first 64 dimensions of the aging sensitivity feature vector represent the structural aging feature components. The last 64 dimensions of the aging sensitivity feature vector are input into the time-aware fully connected network ΔA. th (t)=TANN(F 65:128 ,t), where TANN represents a time-aware fully connected network. This network includes a timestamp embedding layer and gated activation units, and outputs a threshold offset ΔA that varies over time. th (t) is obtained by linearly calculating the basic failure threshold and the time-varying threshold offset to obtain the time-varying threshold function. The scaling factor χ is dynamically adjusted by the chip's operating mode (e.g., χ = 1.2 in encryption operation mode to increase threshold sensitivity, χ = 0.8 in standby mode to decrease sensitivity, and χ = 1 in other modes). The time-varying threshold function's spatial dimension reflects the distribution of hardware topological weaknesses, the time dimension predicts future environmental stress, and the operating condition dimension responds to key changes in the task. The final output is a failure threshold surface that strictly matches the spatiotemporal characteristics of the aging trajectory prediction sequence.

[0088] The aging degree at each future moment in the aging trajectory prediction sequence is modeled as a Gaussian distribution using the posterior covariance matrix of fractional Kalman filtering. The probability density function of the Gaussian distribution is integrated with the time-varying failure threshold to obtain the probability of aging degree exceeding the threshold. The path-dependent joint probability of the probability of aging degree exceeding the threshold is calculated to obtain the conditional probability of first crossing. The conditional probability of first crossing is accumulated and integrated over time to obtain the cumulative distribution function of remaining lifetime.

[0089] Specifically, the Gaussian distribution utilizes the multi-step prediction mechanism of fractional-order Kalman filtering, propagating the posterior covariance matrix of the current time step forward to each future prediction time step t through the state transition matrix. n Let n represent each prediction step in the future, n = 1, 2, ..., N1. During this process, uncertainties caused by process noise are simultaneously injected. Then, the variance component corresponding to the predicted aging degree is extracted from the posterior covariance matrix obtained from the propagation. This variance value quantifies the prediction uncertainty caused by environmental disturbances and model errors. Using the predicted aging degree values ​​in the prediction sequence as the mean and the variance calculated from the propagation as the uncertainty measure, a Gaussian distribution model is established for the predicted value at each future time. Where u n , These are the mean of the predicted aging degree (i.e., the predicted value itself) and the standard deviation of the predicted aging degree (from the posterior covariance matrix), respectively. This distribution reveals the probability distribution characteristics of the predicted aging degree around its estimated value. Its standard deviation increases with the increase of the prediction time span, accurately reflecting the accumulation of uncertainty in long-term predictions. The probability density function of the Gaussian distribution... f B (x) represents the Gaussian probability density function for predicting the degree of aging, describing the instantaneous risk density at x, and the probability of the degree of aging exceeding the threshold. Where A th (k+n) represents the time-varying threshold function for the next n prediction steps, p n 、P(B k+n ≥A th (k+n) represents the probability that the aging degree exceeds the time-varying threshold function, and the conditional probability of the first crossing. Where q n Let P represent the probability that the chip first exceeds the failure threshold in step n, where P represents the probability measure, ∩ represents the event intersection operation, and B represents the probability of the chip first exceeding the failure threshold in step n. k+m <A th (k+m) represents historical events that did not exceed the threshold, and the aging level at step m is lower than the threshold. Specifically... in For steps 1 to n-1, the probability of "aging degree not exceeding the threshold" at each step (the product of the probabilities of multiple independent events) is corr(B k+m B k+nThe ) represents the correlation coefficient for predicting the degree of aging. (K n-m ) 11 It is the element in the first row and first column of the state transition matrix K raised to the power of nm (because the state vector is two-dimensional, the aging component is taken), λ is the correlation adjustment coefficient, which adjusts the influence of historical state associations on the final probability (obtained through training), and the conditional probability of the first crossing is accumulated and integrated over the time axis to obtain the cumulative distribution function of the remaining lifetime. q h Let p represent the conditional probability of the first crossing at step p, where p = 1, 2, ..., n, t n t represents an absolute point in time. n =k+n, accurately reflecting the accumulation process of chip failure risk.

[0090] like Figure 3 As shown, the specific analysis of step S500 is as follows:

[0091] Monotonic cubic spline interpolation is performed on the cumulative distribution function of remaining lifetime to generate a continuously differentiable interpolation function;

[0092] Set a confidence level, initialize the search interval based on a continuously differentiable interpolation function, calculate the first inner sub-point and the second inner sub-point using the endpoints of the search interval and the golden section point, calculate the difference between the first inner sub-point and the confidence level using the interpolation function to obtain the first evaluation function value, and calculate the difference between the second inner sub-point and the confidence level to obtain the second evaluation function value.

[0093] If the absolute value of the first evaluation function is less than the set threshold, the corresponding inner point is output as the risk boundary value; otherwise, the search interval is updated based on the sign of the product of the first and second evaluation function values, and iterated until the interval length is less than the set threshold, and the risk boundary value is output.

[0094] Specifically, based on the discrete data points in the cumulative remaining lifetime distribution function, the average rate of change of the cumulative probability between adjacent points over time is calculated. Specific constraints are applied to these rates of change to ensure that the trends of adjacent segments complement each other to maintain overall monotonicity, while limiting the adjustment range of the rate of change to avoid distortion of the interpolation function. Subsequently, based on the constrained and corrected rate of change, a piecewise cubic polynomial is constructed to ensure smooth connection between adjacent data points. This ultimately generates an interpolation function that strictly fits the original discrete data, is continuously differentiable, and strictly monotonically increasing, accurately reflecting the cumulative remaining lifetime distribution. The entire process uses the Fritsch-Carlson algorithm to control the slope and polynomial, ensuring the interpolation effect meets requirements, resulting in a continuously differentiable interpolation function FRUL′(t). A confidence level of a = 0.95 is set, and the initial... The initial search interval [b, c] is set such that the interpolation function values ​​at both ends are less than and greater than the confidence level (satisfying FRUL′(b) < 0.95 < FRUL′(c), where b is the minimum value among all discrete time points, and c is the first discrete point with a "cumulative probability ≥ 99%", ensuring that the interval contains the lifetime corresponding to a 95% probability). A golden section search is performed, calculating the first inner bisector l1 = c - 0.618(cb) and the second inner bisector l2 = b + 0.618(cb). The difference between the first inner bisector and the confidence level is calculated using the interpolation function to obtain the first evaluation function value f1 = FRUL′(l1) - 0.95. The difference between the second inner bisector and the confidence level is calculated to obtain the second evaluation function value f2 = FRUL′(l2) - 0.95. If the absolute value of the first evaluation function value is less than the set threshold |f1| < 10, the search is considered complete. -6 The corresponding internal division point is output as the risk boundary value VR. 95％ =l1; otherwise, update the search interval based on the sign of the product of the first and second evaluation function values ​​f1f2<0 (if f1>0, then c=l2; if f2<0, then b=l1), iterating until the interval length is less than the set threshold cb<10. - 6. The final output is the risk boundary value VR. 95％ The output at this time is the midpoint value of the search interval [b,c] with a 95% probability. The risk boundary value is the maximum remaining lifespan of the chip that can work safely (in hours), and its physical meaning directly corresponds to the time threshold for preventive maintenance.

[0095] Within a set confidence level and probability upper limit, sampling points are selected at equal intervals, and the lifetime value corresponding to each sampling point is calculated by interpolation using the inverse function of the cumulative distribution function of remaining lifetime.

[0096] The conditional value of risk is obtained by calculating the lifetime value corresponding to each sampling point;

[0097] Combining conditional value of risk and risk boundary value yields a two-factor risk index;

[0098] Specifically, 1000 points are sampled at equal intervals within the probability interval [0.95, 1], and the corresponding lifetime value t is solved by inverse function interpolation. z =FRUL -1 (p z ), where z represents the sampling point number, p z The conditional value of risk is obtained by applying Romberg numerical integral with adaptive weights and lifetime values ​​to represent the sequence of sampling points. Z is the total number of sampling points, ω z The weighting coefficients are adaptively determined by the Romberg algorithm, making the integral result closer to the true value. Conditional Value at Risk (VaR) quantifies the average remaining lifetime in the worst-case 5% failure scenario. (VR is a two-factor risk indicator.) 95％ CVR 95％}

[0099] Specifically, based on the power routing layer data of the chip layout, a 3D chip power network topology is established. A power network resistance matrix is ​​constructed using four-probe measurement technology and node analysis. Using static timing analysis tools and layout data, clock tree load vectors and logic cell utilization are generated, forming a topology impedance parameter set. Sensors are deployed in key areas of the chip to collect and process operating temperature, voltage fluctuations, and current ripple sequences, constructing an environmental timing data vector. The topology impedance parameter set is tensorized and normalized to obtain a static feature vector. The environmental timing data vector is processed through a sliding window to generate a time-varying feature sequence. These two are then input into a gated cyclic encoder for fusion, yielding an aging sensitivity feature vector. Using this vector, a ternary aging kernel parameter set is obtained through linear transformation, a temporal convolutional network, and a two-layer perceptron. An aging fractional-order Brownian motion model is created, and after discretization and state recursion, an aging trajectory prediction sequence is obtained. The time-varying threshold function is calculated by extracting the aging sensitivity feature vector components and combining them with the aging trajectory prediction sequence. The remaining lifetime cumulative distribution function is obtained through Gaussian distribution modeling and probability integration. Then, the conditional risk value is obtained through sampling and integration. This value, together with the risk boundary value, forms a two-factor risk index, enabling accurate prediction of chip aging and providing a basis for preventive maintenance. This ensures the accuracy and reliability of the prediction, reflects the correlation between chip hardware topology, environmental stress, and aging risk, and supports the full life cycle reliability management of cryptographic smart chips.

[0100] The foregoing description is illustrative of the invention and should not be construed as limiting it. Although several exemplary embodiments of the invention have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. It should be understood that the foregoing description is illustrative of the invention and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the claims and their equivalents.

Claims

1. A method for predicting the aging of an ASIC-specific cryptographic smart chip, characterized in that, Includes the following steps: Step S100: Obtain chip power wiring layer data and collected environmental parameters, perform feature fusion encoding, and obtain aging sensitivity feature vector; Step S200: Perform fractional-order aging dynamics modeling based on the aging sensitivity feature vector to obtain the chip aging state change equation; Step S300: Predict the chip aging state based on the chip aging state change equation to obtain the aging trajectory prediction sequence; Step S400: Extract the aging sensitivity feature vector components and aging trajectory prediction sequence to perform remaining lifetime probability assessment and obtain the remaining lifetime cumulative distribution function; Step S500: Based on the cumulative distribution function of remaining lifetime, perform uncertainty analysis on chip aging prediction to obtain a two-factor risk index.

2. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 1, characterized in that, The steps for analyzing the aging sensitivity feature vector are as follows: Digital temperature sensors are deployed in key areas of the chip to collect and process junction temperatures in real time, thereby obtaining a working temperature sequence. Collect the core power supply voltage and calculate the instantaneous deviation between the core power supply voltage and the nominal voltage to obtain the voltage fluctuation sequence; The current in the power supply circuit is measured and the AC component of the power supply circuit current is extracted. The root mean square value is then calculated to obtain the current ripple sequence. An environmental time-series data vector is constructed by synchronizing the operating temperature sequence, voltage fluctuation sequence, and current ripple sequence with timestamps. After tensorizing the topological impedance parameter set, it is normalized and then concatenated to obtain a static feature vector. The environmental time series data vector is input into the sliding window processor to generate a time-varying feature sequence. The static feature vector and the dynamic feature sequence are input into the gated cyclic encoder, and cross-domain feature fusion is performed through the gating mechanism to obtain the aging sensitivity feature vector.

3. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 2, characterized in that, The analysis steps for the topological impedance parameter set are as follows: Based on the power routing layer data of the chip layout, a three-dimensional chip power network topology is established with power pads as input nodes, standard cell power connection points as terminal nodes, and metal traces as connection edges. The resistance values ​​between nodes are obtained through four-probe measurement technology. Based on the resistance values ​​between nodes, the admittance matrix is ​​established through node analysis. The equivalent resistance between any two nodes is obtained by solving the linear equation system, and the power network resistance matrix is ​​constructed. Static timing analysis tools are used to extract the position information of the trigger clock pins at the end of the clock tree, calculate the load capacitance of the clock endpoints, and generate the clock tree load vector by grouping by clock domain. The total number of available logical units is calculated using the layout and routing data, the number of instantiated logical units is counted, and the logical unit utilization rate is calculated based on the total number of available logical units and the number of instantiated logical units. The power network resistance matrix, clock tree load vector, and logic cell utilization constitute the topology impedance parameter set.

4. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 1, characterized in that, The analysis steps for the chip aging state change equation are as follows: The aging sensitivity feature vector is transformed linearly to obtain the initial aging degree. The aging sensitivity feature vector is then input into a temporal convolutional network to extract the time-varying diffusion coefficient through dilated convolutional layers. Finally, the aging sensitivity feature vector is input into a two-layer perceptron to output the Hearst exponent. Initial aging degree, time-varying diffusion coefficient, and Hearst exponent constitute the ternary aging core parameter set; A fractional Brownian motion model of chip aging is created based on a ternary aging kernel parameter set. The chip aging fractional Brownian motion model is expanded by total differential through fractional Itoh lemma functions to obtain the chip aging state change equation.

5. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 1, characterized in that, The steps for analyzing the aging trajectory prediction sequence are as follows: The chip aging state change equation is expanded to obtain the chip aging linear term, chip aging subvariance term, and chip aging fractional term. The chip aging linear term is expanded by first-order Taylor to obtain the linear degradation mapping matrix. The chip aging subvariance term is calculated by second-order moment to obtain the noise amplification matrix. The chip aging fractional term is weighted by Grünwald-Letnikov history to obtain the memory effect mapping matrix. The linear degradation mapping matrix, noise amplification matrix, and memory effect mapping matrix are superimposed to obtain the state transition matrix. The linear degradation mapping matrix is ​​multiplied by the time-varying diffusion coefficient to obtain the noise control matrix. The state transition matrix and the noise control matrix constitute the discrete aging state transition parameter set. Based on the discrete aging state transition parameter set, a discrete state equation for chip aging is created. For each future prediction step, a state recursion calculation is performed. During the iteration, the aging degree component is extracted from the two-dimensional discrete state vector to form an aging trajectory prediction sequence.

6. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 5, characterized in that, The steps of the two-dimensional discrete state vector analysis are as follows: The chip aging state change equation is reconstructed into a continuous-time state vector, which includes the current aging degree and continuous fractional derivative terms. The continuous fractional derivative terms are discretized using the Grünwald-Letnikov fractional discretization method to obtain fractional difference terms. Substituting the fractional difference terms into the continuous-time state vector yields a two-dimensional discrete state vector.

7. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 1, characterized in that, The analysis steps for the cumulative distribution function of remaining lifetime are as follows: The aging degree at each future moment in the aging trajectory prediction sequence is modeled as a Gaussian distribution using the posterior covariance matrix of fractional Kalman filtering. The probability density function of the Gaussian distribution is then integrated with the time-varying failure threshold using tail probability to obtain the probability of aging degree exceeding the threshold. The path-dependent joint probability of the probability of aging degree exceeding the threshold is then calculated to obtain the conditional probability of first crossing. The conditional probability of first crossing is then accumulated and integrated over time to obtain the cumulative distribution function of remaining lifetime.

8. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 1, characterized in that, The time-varying threshold function analysis steps are as follows: The first 64 dimensions of the aging sensitivity feature vector are extracted, and the basic failure threshold is calculated through linear transformation. The last 64 dimensions of the aging sensitivity feature vector are input into a time-aware fully connected network to output the threshold offset that changes over time. The basic failure threshold and the time-varying threshold offset are linearly calculated to obtain the time-varying threshold function.

9. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 1, characterized in that, The steps for the two-factor risk index analysis are as follows: Within a set confidence level and probability upper limit, sampling points are selected at equal intervals, and the lifetime value corresponding to each sampling point is calculated by interpolation using the inverse function of the cumulative distribution function of remaining lifetime. The conditional value of risk is obtained by calculating the lifetime value corresponding to each sampling point; Combining conditional value of risk and risk boundary value yields a two-factor risk index.

10. The aging prediction method for an ASIC-specific cryptographic smart chip according to claim 9, characterized in that, The risk boundary value analysis steps are as follows: Monotonic cubic spline interpolation is performed on the cumulative distribution function of remaining lifetime to generate a continuously differentiable interpolation function; Set a confidence level, initialize the search interval based on a continuously differentiable interpolation function, calculate the first inner sub-point and the second inner sub-point using the endpoints of the search interval and the golden section point, calculate the difference between the first inner sub-point and the confidence level using the interpolation function to obtain the first evaluation function value, and calculate the difference between the second inner sub-point and the confidence level to obtain the second evaluation function value. If the absolute value of the first evaluation function is less than the set threshold, the corresponding inner point is output as the risk boundary value; otherwise, the search interval is updated based on the sign of the product of the first and second evaluation function values, and iterated until the interval length is less than the set threshold, and the risk boundary value is output.

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