A register overflow optimization method, device and storage medium

Abstract

Embodiments of the present application provide a register overflow optimization method and device and a storage medium, applied to the chip technical field, in the method, for each virtual register in a target program, based on the physical register type supported by the instruction operand where the virtual register is located, a corresponding target register class is selected from N candidate register classes, N is greater than 1; a first physical register in the target register class is allocated to the virtual register; when a register overflow occurs, a target register is selected from the allocated multiple first physical registers, and the instruction operand saved in the target register is overflowed to a second physical register in the other N-1 candidate register classes. Compared with overflowing the instruction operand to the memory to generate read and write operations on the memory, the present application overflows to different types of physical registers, generates read and write operations on the physical registers, relieves the pressure of the registers, reduces the performance overhead of overflowing to the memory, and improves the register allocation efficiency.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a register overflow optimization method, device and storage medium. Background Technology

[0002] During program compilation, physical registers are allocated to virtual registers (i.e., variables or temporary values) in the program to indirectly realize the storage and processing of data in physical registers. Among them, virtual registers are temporary logical registers generated by the compiler.

[0003] In related technologies, chips often support different types of physical registers. In register allocation tasks, the corresponding register class is first set during instruction selection, and then the physical registers in the register class are allocated to the virtual registers in the program. When there are not enough physical registers in the register type, the instruction operands in the allocated physical registers are overflowed into memory to free up the physical register; when the instruction operands are needed, they are read from memory again.

[0004] The above scheme requires writing instruction operands to memory and reading instruction operands from memory. The efficiency of reading and writing memory is often low, and the overhead of overflowing into memory is large. Summary of the Invention

[0005] This invention provides a register overflow optimization method, device, and storage medium to reduce the performance overhead caused by instruction operands overflowing into memory.

[0006] On the one hand, embodiments of this application provide a register overflow optimization method, the method comprising:

[0007] For each virtual register in the target program, based on the physical register type supported by the operand of the instruction where the virtual register is located, a corresponding target register class is selected from N candidate register classes, where N is greater than 1;

[0008] Allocate the first physical register in the target register class to the virtual register;

[0009] When a register overflow occurs, a target register is selected from the multiple allocated first physical registers, and the instruction operands stored in the target register are overflowed into the second physical registers in the other N-1 candidate register classes.

[0010] On one hand, embodiments of this application provide a register overflow optimization apparatus, the apparatus comprising:

[0011] The selection module is used to select the corresponding target register class from N candidate register classes for each virtual register in the target program, based on the physical register type supported by the instruction operand where the virtual register is located; where N is greater than 1.

[0012] The allocation module is used to allocate the first physical register in the target register class to the virtual register;

[0013] The overflow module is used to select a target register from a plurality of allocated first physical registers when a register overflow occurs, and to overflow the instruction operands stored in the target register to a second physical register in one of the other N-1 candidate register classes.

[0014] Optionally, the selection module is specifically used for:

[0015] The candidate register class that matches the physical register type supported by the operand of the instruction and whose number of available registers meets the preset allocation conditions is selected as the target register class.

[0016] Optionally, the overflow module is specifically used for:

[0017] Based on the priorities of the N-1 candidate register classes, a first overflow register class is selected from the N-1 candidate register classes. The priority of the candidate register class is negatively correlated with the delay of the candidate register class.

[0018] When the first overflow register class contains a second physical register that is in an available state, the instruction operands stored in the target register are overflowed into the second physical register.

[0019] Optionally, the overflow module is specifically used for:

[0020] Select the candidate register class with the highest priority from the N-1 candidate register classes as the first overflow register class.

[0021] Optionally, the overflow module is further configured to:

[0022] When the first overflow register class does not contain a second physical register that is in an available state, the first overflow register class is excluded from the N-1 candidate register classes;

[0023] The remaining candidate register classes are traversed iteratively until a second physical register in a usable state is found; each iteration includes the following steps:

[0024] Based on the priority of each of the remaining candidate register classes, an overflow register class is selected from the remaining candidate register classes;

[0025] When the overflow register class contains a second physical register that is in an available state, the instruction operands stored in the target register are overflowed into the second physical register;

[0026] When the candidate overflow register class does not contain a second physical register that is in an available state, the overflow register class selected in this round is excluded from the remaining candidate register classes, and the next round of iteration begins.

[0027] Optionally, the overflow module is further configured to:

[0028] The instruction operand is read from the second physical register, and the operation in the target program is executed based on the instruction operand to obtain the operation result.

[0029] Optionally, the register overflow optimization device further includes: a post-processing module;

[0030] The post-processing module is specifically used for:

[0031] Peephole optimization is performed on the transfer instruction, which is used to overflow the instruction operand into the second physical register and read the instruction operand from the second physical register.

[0032] On one hand, embodiments of this application provide a computer device, including:

[0033] Memory, used to store program instructions;

[0034] The chip is used to run program instructions stored in the memory and execute the steps of the above-described data register overflow optimization method according to the obtained program.

[0035] On one hand, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer to perform the steps of the above-described register overflow optimization method.

[0036] On one hand, embodiments of this application provide a computer program product, including a computer program stored on a computer-readable storage medium, the computer program including program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the above-described register overflow optimization method.

[0037] In this embodiment, for each virtual register in the target program, based on the physical register type supported by the instruction operand of the virtual register, a corresponding target register class is selected from N candidate register classes, and a first physical register in the target register class is allocated to the virtual register. When the number of available physical registers in the target register class is insufficient, a register overflow occurs. A target register is selected from the multiple allocated first physical registers, and the instruction operand stored in the target register overflows to a second physical register in one of the other N-1 candidate register classes. Compared to overflowing the instruction operand to memory and generating read / write operations for memory, this application overflows the instruction operand to other types of physical registers, thus generating only read / write operations for physical registers. Read / write operations for physical registers are much faster than read / write operations for memory, thereby greatly reducing performance overhead and improving the efficiency of register allocation while reducing register allocation pressure. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a chip architecture provided in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of a register overflow optimization method provided in an embodiment of this application;

[0041] Figure 3 A flowchart illustrating a register overflow optimization method provided in an embodiment of this application;

[0042] Figure 4 This is a schematic diagram of a register overflow optimization device provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0045] refer to Figure 1 This is a structural diagram of a chip applicable to an embodiment of this application. The chip 100 includes at least a plurality of execution units 101 and memory 102. The memory 102 may be high-bandwidth memory (HBM) or other types of memory.

[0046] Each execution unit 101 includes multiple physical registers 103. The physical registers 103 are "temporary docking points" for data when it is processed by the execution unit 101; the execution unit 101 is used to execute the data and / or instructions in the physical registers 103.

[0047] In addition to the structure described above, the chip 100 in this application may also include other structures, and this application does not specifically limit such structures.

[0048] In some embodiments, the chip 100 in this application may be an artificial intelligence chip.

[0049] During the compilation phase, for each virtual register in the target program, the central processing unit selects the corresponding target register class from N candidate register classes based on the physical register type supported by the instruction operand of the virtual register; then, the virtual register is allocated to the first physical register in the target register class; when a register overflow occurs, the target register is selected from the multiple allocated first physical registers, and the instruction operand stored in the target register overflows to the second physical register in the other N-1 candidate register classes.

[0050] During the execution phase, the execution unit 101 reads the corresponding instruction operands from the physical register 103 and performs calculation operations (such as addition and multiplication operations) in the target program based on the instruction operands to obtain the operation results; instead of reading the instruction operands from the memory 102 and performing calculation operations based on the instruction operands, it greatly reduces the performance overhead of instruction operands overflowing into memory and improves the efficiency of register allocation.

[0051] Chip 100 can be: Graphics Processing Unit (GPU), General-purpose computing on graphics processing units (GPGPU), Domain Specific Architecture (DSA), etc.

[0052] In the context of related technologies, during program compilation, Low Level Virtual Machine (LLVM) instruction selection is the core process by which the compiler backend converts intermediate representations (LLVM IR) into target machine instructions. Its goal is to select appropriate machine instructions for each intermediate representation operation (i.e., IR operation). This process requires consideration of the characteristics of the target architecture, such as the number of physical registers and instruction set limitations.

[0053] Specifically, LLVM typically uses a selection DAG (Directed Acyclic Graph) based on pattern matching to implement instruction selection. The specific steps include:

[0054] Step 1: Construct a selection directed acyclic graph based on intermediate representation operations, preserving the dependencies between operations and the type information of values.

[0055] For example, intermediate representation operations include:

[0056] %0 = add i32 %a, %b (calculate a+b);

[0057] %1 = sub i32 %c, %d (calculate cd);

[0058] %2 = mul i32 %0, %1 (Calculate (a+b)) (cd));

[0059] In this context, %a, %b, %c, %d, %0, %1, and %2 represent virtual registers; i32 represents operand type; and add, sub, and mul represent opcodes / operation instructions.

[0060] By constructing a directed acyclic graph (DAG) from the intermediate representation operations, that is, converting opcodes into nodes and data flow directions into edges, we obtain the following: Figure 2 The selection shown is a directed acyclic graph. Figure 2 In this process, a+b and cd are calculated first, and then the results are multiplied. It should be noted that during the construction of the directed acyclic graph, local directed acyclic graph optimization is performed, that is, the structure is simplified and adapted to hardware characteristics through operations such as constant folding and redundant operation elimination.

[0061] Step 2 involves validating the directed acyclic graph and optimizing the validated directed acyclic graph.

[0062] Specifically, this ensures that all operations and types in the directed acyclic graph (DAG) are supported by the target architecture, eliminating architecture-incompatible operations. Type legalization involves: if the target architecture does not support the operand type in an intermediate representation operation (e.g., x86-32 does not support operand type i128), then the operand type is split into types supported by x86-32, such as i128 being split into i64. Operation legalization involves: if the target architecture does not support a certain operation instruction, such as the udiv instruction, then the udiv operation instruction is replaced with a library function call, such as udivsi3. In addition, target-specific constraints are included; for example, if memory operation addresses must be aligned, then alignment checks or adjustment instructions need to be added to the DAG.

[0063] Next, the following optimization operations are performed on the legalized directed acyclic graph: common subexpression elimination, such as merging identical sub-directed acyclic graphs; strength reduction, such as replacing computationally expensive operations with functionally equivalent but less computationally expensive operations; constant propagation, such as directly embedding constants into operations; and goal-specific optimization operations.

[0064] Step 3: Map the DAG nodes in the optimized directed acyclic graph to the specific instructions of the target architecture through pattern matching, and generate a machine instruction sequence containing virtual registers.

[0065] Specifically, in the target architecture's .td file, each machine instruction is defined as a pattern. Starting from the leaf nodes of the DAG (such as virtual registers or constants), the parent nodes are matched from bottom to top to find a sub-directed acyclic graph that perfectly matches the machine instruction pattern. If multiple machine instructions can match the same sub-directed acyclic graph (e.g., add has multiple addressing modes), the optimal instruction is selected using a cost model (e.g., fewer cycles, fewer registers used). After a successful match, the corresponding DAG child node is replaced with a machine instruction node, ultimately generating a DAG composed of machine instructions. Then, the DAG after instruction selection is topologically sorted to ensure that the instruction execution order conforms to the dependencies. The machine instructions are added to the basic block one by one according to the sorting result, and virtual registers are allocated as operands.

[0066] Step 4: Handle any remaining details from the instruction selection process to prepare for subsequent stages (such as register allocation and instruction scheduling).

[0067] Specifically, it inserts pseudo-instructions necessary for the target architecture into the machine instruction sequence, such as IMPLICIT DEF indicating uninitialized registers; verifies the validity of the machine instruction sequence; and records debugging information of the machine instructions.

[0068] For example, by performing steps 2, 3, and 4 on the intermediate representation operations described above, the following sequence of machine instructions is obtained:

[0069] %2:tlr = ADDS_rrr %1:tlr, %0:tlr, / .v1.b32.lo / 0, implicit wm1;

[0070] %5:tlr = SUBS_rrr %4:tlr, %3:tlr, / .v1.b32.lo / 0, implicit wm1;

[0071] %6:tlr = MULS_rrr %2:tlr, %5:tlr, / .v1.b32.lo / 0, implicit wm1;

[0072] Here, %0, %1, %2, %3, %4, %5, and %6 represent virtual registers; tlr uses a separator as a suffix to characterize the physical register class corresponding to the virtual register, and tlr is a general-purpose register; / .v1.b32.lo / 0, implicit wm1 is metadata related to the target architecture, used to accurately describe the operational attributes, hardware constraints, and implicit dependencies of machine instructions, ensuring that the instructions can be correctly parsed and executed by the hardware.

[0073] When allocating registers for virtual registers in the aforementioned machine instruction sequence, the instruction selection process prioritizes physical register classes with available registers, based on the constraints set for each virtual register. These physical register classes are then allocated to the virtual registers in the program. However, once a register class, such as the general-purpose register class TLR, is selected, if there are insufficient available physical registers in that class, the instruction operands stored in the allocated physical registers will overflow onto the stack memory. When the virtual registers are needed later, they are loaded back from the stack memory into available physical registers within the previously selected physical register class. This process involves writing (store) virtual registers into memory and loading (load) them back from memory. Memory read / write operations are significantly slower than physical register read / write operations, resulting in substantial performance overhead and impacting instruction cache efficiency.

[0074] In view of this, this application is based on Figure 1 The chip architecture diagram shown illustrates a register overflow optimization method applicable to various scenarios, such as image processing, speech processing, and text processing. The physical meaning of register overflow optimization can differ depending on the application scenario.

[0075] For example, in a text processing scenario, the data in the virtual register during register overflow optimization can be text data used in tasks such as text generation and text recognition.

[0076] For example, in a speech processing scenario, the data in the virtual register during register overflow optimization can be speech data used in tasks such as speech enhancement, speech recognition, and speech synthesis.

[0077] For example, in image processing scenarios, the data in the virtual registers used in register overflow optimization can be image data used in tasks such as image preprocessing, image segmentation, and object detection.

[0078] It should be noted that in this application, "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated.

[0079] The following section details the process of a register overflow optimization method. (See attached image) Figure 3 This method is performed by a computer device, which includes... Figure 1 The method, as shown in the diagram, includes the following steps:

[0080] Step 301: For each virtual register in the target program, select the corresponding target register class from N candidate register classes based on the physical register type supported by the operand of the instruction where the virtual register is located.

[0081] Specifically, N is a positive integer greater than 1. Virtual registers are abstract containers used by the compiler to store intermediate results in the intermediate code during program compilation; they do not actually exist in the hardware. Physical registers are actual registers that exist in the chip and their number is fixed. The candidate register class includes multiple physical registers of the same type.

[0082] In this embodiment, based on different uses or different hardware addresses of physical registers, N candidate register classes are defined; for example, general-purpose registers, floating-point registers, and special-purpose registers. General-purpose registers can be used to store integers; floating-point registers are used to store floating-point instructions; special-purpose registers include various register classes with specific functions, such as vector registers. Register allocation involves mapping the address of a virtual register to a physical register.

[0083] For any candidate register class, define the supported data types, register sequences, alignment constraints, and allocatability information. Register sequences refer to the multiple specific physical registers in the candidate register class, represented by register numbers or names. Alignment constraints refer to the memory alignment constraints when storing data in the candidate register class; for example, in GPR32 register class processing, addresses must be aligned to 4 bytes. Allocatability can be defined as either the entire candidate register class not participating in register allocation, or a subset of physical registers within the register class not participating in register allocation.

[0084] In some embodiments, the candidate register class that matches the physical register type supported by the operand of the instruction and whose number of available registers meets the preset allocation conditions is selected as the target register class.

[0085] Specifically, in the compiler's intermediate representation, each instruction operand containing a virtual register has a supported physical register type, which is related to the data type of the instruction operand itself; for example, 32-bit integers, single-precision floating-point numbers, etc.

[0086] The preset allocation conditions that the number of available registers must satisfy can be set according to the actual situation; for example, the preset allocation condition can be that the number of available registers is the largest; or the number of available registers is the second largest; or there can be at least one available register; of course, there can be other forms of allocation conditions, which are not specifically limited in this application.

[0087] For example, the number of virtual registers to be mapped is 4, and the data type is 32-bit integer. If the general-purpose register class has the most available registers among the candidate register classes that support the above data type, then the general-purpose register class will be used as the target register class.

[0088] In this embodiment, the corresponding target register class is selected by the physical register type supported by the instruction operand where the virtual register is located and the number of available registers in the register class, which reduces the search cost during allocation and improves the efficiency of register allocation; by limiting the number or data type of available registers, the compiler can generate legal instructions, improve the accuracy of register allocation, and avoid program crashes caused by mismatched data types of physical registers during program execution.

[0089] Step 302: Allocate the first physical register in the target register class to the virtual register.

[0090] Specifically, the first physical register available in the target register class selected in step 301 is assigned to the virtual register, that is, the address of the virtual register is mapped to the selected first physical register.

[0091] Step 303: When a register overflow occurs, select a target register from the multiple allocated first physical registers, and overflow the instruction operands stored in the target register to the second physical registers in the other N-1 candidate register classes.

[0092] Specifically, register overflow refers to the following: when there are insufficient available physical registers in the selected target register class, virtual registers in the target program that have not been allocated a first physical register can be mapped to second physical registers in other candidate register classes; or, a target register in the target program that has been allocated a first physical register and meets preset conditions can be identified, and then the instruction operands stored in the target register can overflow to second physical registers in other candidate register classes. The target register is then released and allocated as a usable register to other virtual registers in the target program that have not been allocated a first physical register. In practical applications, one or more target registers can be selected according to the actual situation. For each target register, a second physical register can be selected from the other N-1 candidate register classes, and the instruction operands stored in the target register can overflow to the corresponding selected second physical register.

[0093] Specifically, the preset conditions can be: the target register with the longest lifespan; at least one target register with a lifespan greater than a preset threshold; the target register with the fewest accesses within a certain period; the target register that can reduce overflow costs, for example, if the first physical register with the most frequent use of stored data overflows, the overhead caused by subsequent reloading is higher, so the first physical register with the most frequent use of stored data will not be selected as the target register; or the target register that has the most interference and conflict with the data stored in other physical registers, etc., which are all judgment conditions that are conducive to register allocation. This application does not make specific limitations on these conditions.

[0094] In practical applications, instruction operands are overflowed into the second physical register via the mov instruction, and instruction operands are read from the second physical register.

[0095] In some embodiments, certain non-general register classes are often only available to specific instructions, meaning that some instructions can only use certain register classes. This imposes many restrictions and results in high maintenance costs.

[0096] In this embodiment of the application, the instruction operands stored in the target register are overflowed into the second physical register by the mov instruction. The candidate register class of the second physical register can be different from the target register class of the target register. That is, the mov instruction can break the restriction that some instructions can only use a specified register class, thereby reducing maintenance costs.

[0097] For example, the instruction operands corresponding to multiplication instructions support register class 1; when it is necessary to allocate physical registers for the instruction operands corresponding to other multiplication instructions, and the number of available registers in register class 1 is insufficient, the instruction operands in the first physical register with a lifetime greater than the preset duration and already allocated are overflowed to the second physical register through the mov instruction. The second physical register can be an available register in register class 2.

[0098] In some embodiments, a first overflow register class is selected from the N-1 candidate register classes based on their respective priorities. The priority of the candidate register class is negatively correlated with the latency of the candidate register class. When the first overflow register class contains a second physical register that is in an available state, the instruction operands stored in the target register are overflowed into the second physical register.

[0099] Specifically, the priority of each candidate register class is set according to its own read / write latency attribute; that is, the candidate register class with the smaller read / write latency has the higher priority.

[0100] The highest priority candidate register class can be selected from N-1 candidate register classes as the first overflow register class; alternatively, other priority candidate register classes can be selected from N-1 candidate register classes as the first overflow register class. This application does not impose any specific limitations on this.

[0101] Different candidate register classes have different latency overheads. When the target register class is insufficient, the candidate register class with lower latency is preferred to be used first, thus satisfying the requirement that a certain type of register is only used when the register pressure is relatively high.

[0102] After selecting the first overflow register class, the instruction operands stored in the target register are written into the second physical register in the first overflow register class that is in an available state.

[0103] In this embodiment, for each virtual register in the target program, based on the physical register type supported by the instruction operand of the virtual register, a corresponding target register class is selected from N candidate register classes, and a first physical register in the target register class is allocated to the virtual register. When the number of available physical registers in the target register class is insufficient, a register overflow occurs. A target register is selected from the multiple allocated first physical registers, and the instruction operand stored in the target register overflows to a second physical register in one of the other N-1 candidate register classes. Compared to overflowing the instruction operand to memory and generating read / write operations for memory, this application overflows the instruction operand to other types of physical registers, thus generating only read / write operations for physical registers. Read / write operations for physical registers are much faster than read / write operations for memory, thereby greatly reducing performance overhead and improving the efficiency of register allocation, reducing register allocation pressure.

[0104] In some embodiments, when the first overflow register class does not contain a second physical register in a usable state, the first overflow register class is excluded from N-1 candidate register classes; the remaining candidate register classes are traversed iteratively until a second physical register in a usable state is found; wherein each iteration process includes the following steps:

[0105] Based on the priority of each of the remaining candidate register classes, an overflow register class is selected from the remaining candidate register classes; when the overflow register class contains a second physical register that is in an available state, the instruction operands stored in the target register are overflowed into the second physical register.

[0106] If the candidate overflow register class does not contain a second physical register that is in an available state, the overflow register class selected in this round is excluded from the remaining candidate register classes, and the next round of iteration begins.

[0107] In some embodiments, during register allocation, the physical register class specified during instruction selection is preferentially selected based on the number of available registers. However, in related technologies, if the current machine instruction requires the allocation of multiple physical registers with consecutive sequence numbers, and the specified preferred physical register class does not contain multiple physical registers with consecutive sequence numbers and available numbers, the instruction operands stored in the allocated physical registers will overflow into memory. In reality, the specified preferred physical register class may contain physical registers with non-consecutive sequence numbers and available numbers, resulting in these physical registers being idle and leading to poor register allocation results.

[0108] Based on this, in this embodiment, if multiple virtual registers need to allocate multiple physical registers with consecutive sequence numbers, and the target register class cannot meet this requirement, a register overflow occurs. Since the instruction operands stored in the allocated target registers are temporarily overflowing into other candidate register classes outside the target register class when a register overflow occurs, and the `mov` instruction does not require overflowing instruction operands into multiple physical registers with consecutive sequence numbers, the overflow is performed at the granularity of a single physical register to available physical registers in other candidate register classes. One instruction operand may correspond to one or more consecutive physical registers.

[0109] For example, setting up four virtual registers requires four consecutive physical registers. The target register class has allocable physical registers numbered 0-15; however, previous instructions have already used physical registers numbered 0-3, 5-10, and 12-15, meaning the currently available physical registers are registers numbered 4 and 11. This cannot meet the requirement of four consecutive physical registers for the virtual registers, thus causing a register overflow. A first overflow register class is selected from the remaining candidate register classes. If only one physical register in the first overflow register class is available, the instruction operand of one of the four virtual registers is overflowed into that physical register.

[0110] Select a second overflow register class from the remaining candidate register classes. If the second overflow register class includes three physical registers with non-contiguous sequence numbers that are available, then overflow the remaining three instruction operands from the above four instruction operands into the three physical registers with non-contiguous sequence numbers in the second overflow register class.

[0111] In this embodiment, when multiple virtual registers that need to allocate multiple physical registers with consecutive sequence numbers experience register overflow, the overflow is granularly distributed to available physical registers in other candidate register classes. This not only solves the problem of increased overhead caused by instruction operands overflowing into memory, but also allows for flexible adjustment of the use of physical registers in the target register class and other candidate register classes by leveraging register overflow. This fully utilizes the gaps in other register classes (i.e., the remaining single physical registers), thereby maximizing the utilization of each candidate register class.

[0112] Secondly, when selecting the candidate register class from among N candidate register classes that matches the physical register type supported by the instruction operand where the virtual register is located and whose number of available registers meets the preset allocation conditions, it may result in a large number of machine instructions being allocated to the same target register class. However, when a register overflow occurs in the target register class, the instruction operands stored in the target register can overflow to other candidate register classes. This flexibly distributes the allocation pressure of the target register class to other candidate registers, greatly alleviating the pressure of register allocation.

[0113] In some embodiments, instruction operands are read from a second physical register, and operations in the target program are executed based on the instruction operands to obtain the operation result.

[0114] Specifically, after the instruction operand overflows into the second physical register, when a subsequent instruction needs to use the instruction operand, the instruction operand is read from the second physical register and written into an available register of the target register class; then the instruction operand is read from the available register to perform the calculation and obtain the operation result.

[0115] In this embodiment, since the arithmetic unit can only directly operate on the specified target register class, when a subsequent instruction needs to use the instruction operand, the instruction operand is read from the second physical register and written back to the target register class. This ensures a smooth transition of data in the hardware, enables different physical registers to work together, improves the performance of high-speed register access, and improves the consistency of resource management during program execution.

[0116] In some embodiments, peephole optimization is performed on the transfer instruction, which is used to overflow the instruction operand into a second physical register and to read the instruction operand from the second physical register.

[0117] Specifically, the move instruction is abbreviated as mov instruction. Peephole optimization is a local optimization technique in compiler optimization. In the back-end stage of the compilation process, by analyzing a continuous sequence of instructions (called a peephole or window, usually containing 2-4 instructions), redundant, inefficient, or simplifiable instructions in the continuous sequence of instructions are combined or merged to improve code quality and execution efficiency without changing the program semantics.

[0118] After selecting a second physical register for the instruction operand, multiple mov instructions are obtained, such as the mov instruction that overflows the instruction operand from the first physical register to the second physical register, and the mov instruction that reads the instruction operand from the second physical register when it is needed later.

[0119] By employing copy propagation optimization, multiple `mov` instructions and their corresponding computational operation instructions are merged into a single instruction. It should be noted that copy propagation optimization is one optimization method within peephole optimization; this application can also employ other optimization methods within peephole optimization to achieve instruction merging, and this application does not impose specific limitations on these methods.

[0120] For example, let's retrieve the `mov` instruction 1, `mov` instruction 2, and the first addition instruction. The first `mov` instruction is: `mov ir1, r0`, which copies the instruction operand stored in physical register `r0` to physical register `ir1`. The second `mov` instruction is: `mov r2, ir1`, which reloads the instruction operand stored in physical register `ir1` back into physical register `r2`. The first addition instruction is: `add r3, r2, r1`, which adds the instruction operand stored in physical register `r2` to the instruction operand stored in physical register `r1`, and writes the result to physical register `r3`.

[0121] Since the instruction operands stored in physical register r2 originate from physical register ir1, and the instruction operands stored in physical register ir1 originate from physical register r0, r2 in the first addition instruction can be replaced with r0 to obtain the second addition instruction: add r3, r0, r1. In other words, the above mov instruction 1: mov ir1, r0, mov instruction 2: mov r2, ir1, and the first addition instruction: add r3, r2, r1 can be optimized to obtain the second addition instruction.

[0122] In this embodiment, after selecting the second physical register, the multiple mov instructions generated by the register overflow are optimized by peephole. This achieves the technical effect of saving resources by optimizing local instructions without changing the program semantics, thereby reducing redundant operations and improving instruction execution efficiency.

[0123] Based on the same technical concept, this application provides a schematic diagram of the structure of a register overflow optimization device, such as... Figure 4 As shown, the register overflow optimization device 400 includes:

[0124] Selection module 401 is used to select the corresponding target register class from N candidate register classes for each virtual register in the target program, based on the physical register type supported by the instruction operand where the virtual register is located; N is greater than 1.

[0125] Allocation module 402 is used to allocate the first physical register in the target register class to the virtual register;

[0126] The overflow module 403 is used to select a target register from a plurality of allocated first physical registers when a register overflow occurs, and to overflow the instruction operands stored in the target register to a second physical register in one of the other N-1 candidate register classes.

[0127] Optionally, the selection module 401 is specifically used for:

[0128] The candidate register class that matches the physical register type supported by the instruction operand where the virtual register is located, and whose number of available registers meets the preset allocation conditions, is selected as the target register class.

[0129] Optionally, the overflow module 403 is specifically used for:

[0130] Based on the priorities of the N-1 candidate register classes, a first overflow register class is selected from the N-1 candidate register classes. The priority of the candidate register class is negatively correlated with the delay of the candidate register class.

[0131] When the first overflow register class contains a second physical register that is in an available state, the instruction operands stored in the target register are overflowed into the second physical register.

[0132] Optionally, the overflow module 403 is specifically used for:

[0133] Select the candidate register class with the highest priority from the N-1 candidate register classes as the first overflow register class.

[0134] Optionally, the overflow module 403 is further configured to:

[0135] When the first overflow register class does not contain a second physical register that is in an available state, the first overflow register class is excluded from the N-1 candidate register classes;

[0136] The remaining candidate register classes are traversed iteratively until a second physical register in a usable state is found; each iteration includes the following steps:

[0137] Based on the priority of each of the remaining candidate register classes, the second overflow register class is selected from the remaining candidate register classes;

[0138] When the second overflow register class contains a second physical register that is in an available state, the instruction operands stored in the target register are overflowed into the second physical register;

[0139] When the candidate overflow register class does not contain a second physical register that is in an available state, the overflow register class selected in this round is excluded from the remaining candidate register classes, and the next round of iteration begins.

[0140] Optionally, the overflow module 403 is further configured to:

[0141] The instruction operand is read from the second physical register, and the operation in the target program is executed based on the instruction operand to obtain the operation result.

[0142] Optionally, the register overflow optimization device 400 further includes: a post-processing module 404;

[0143] The post-processing module 404 is specifically used for:

[0144] Peephole optimization is performed on the transfer instruction, which is used to overflow the instruction operand into the second physical register and read the instruction operand from the second physical register.

[0145] In this embodiment, for each virtual register in the target program, based on the physical register type supported by the instruction operand of the virtual register, a corresponding target register class is selected from N candidate register classes, and a first physical register in the target register class is allocated to the virtual register. When the number of available physical registers in the target register class is insufficient, a register overflow occurs. A target register is selected from the multiple allocated first physical registers, and the instruction operand stored in the target register overflows to a second physical register in one of the other N-1 candidate register classes. Compared to overflowing the instruction operand to memory and generating read / write operations for memory, this application overflows the instruction operand to other types of physical registers, thus generating only read / write operations for physical registers. Read / write operations for physical registers are much faster than read / write operations for memory, thereby greatly reducing performance overhead and improving the efficiency of register allocation, reducing register allocation pressure.

[0146] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 5 As shown, it includes at least one chip 100 and a memory 501 connected to at least one chip 100. In this embodiment, the specific connection medium between the chip 100 and the memory 501 is not limited. Figure 5 Taking the connection between chip 100 and memory 501 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0147] In this embodiment of the application, the memory 501 stores instructions that can be executed by at least one chip 100. By executing the instructions stored in the memory 501, at least one chip 100 can perform the steps of the above-described register overflow optimization method.

[0148] Chip 100 serves as the control center of the computer device, connecting to various parts of the device via various interfaces and lines. It optimizes attention mechanism computation by running or executing instructions stored in memory 501 and accessing data stored in memory 501. Optionally, chip 100 may include one or more processing units. Chip 100 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into chip 100. In some embodiments, chip 100 and memory 501 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0149] Chip 100 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0150] Memory 501, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 501 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 501 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. Memory 501 in the embodiments of this application may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0151] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the above-described register overflow optimization method.

[0152] Based on the same inventive concept, this application provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions that, when executed by a computer device, cause the computer device to perform the steps of the above-described register overflow optimization method.

[0153] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0154] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0155] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0156] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0157] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A register overflow optimization method, characterized in that, include: For each virtual register in the target program, based on the physical register type supported by the operand of the instruction where the virtual register is located, a corresponding target register class is selected from N candidate register classes, where N is greater than 1; Allocate the first physical register in the target register class to the virtual register; When a register overflow occurs, a target register is selected from a plurality of allocated first physical registers, and the instruction operands stored in the target register are overflowed to a second physical register in one of the other N-1 candidate register classes. This includes: selecting a first overflow register class from the N-1 candidate register classes based on the priority of each of the candidate register classes, wherein the priority of the candidate register class is negatively correlated with the read / write latency attribute of the candidate register class. When the first overflow register class contains a second physical register that is in an available state, the instruction operands stored in the target register are overflowed into the second physical register; when the first overflow register class does not contain a second physical register that is in an available state, the first overflow register class is excluded from the N-1 candidate register classes; the remaining candidate register classes are traversed in an iterative manner until a second physical register that is in an available state is obtained.

2. The method as described in claim 1, characterized in that, The step of selecting a target register class from N candidate register classes based on the physical register types supported by the instruction operands containing the virtual register includes: The candidate register class that matches the physical register type supported by the instruction operand where the virtual register is located, and whose number of available registers meets the preset allocation conditions, is selected as the target register class.

3. The method as described in claim 1, characterized in that, The step of selecting a first overflow register class from the N-1 candidate register classes based on their respective priorities includes: Select the candidate register class with the highest priority from the N-1 candidate register classes as the first overflow register class.

4. The method as described in claim 1, characterized in that, Each iteration process includes the following steps: Based on the priority of the remaining candidate register classes, the overflow register class is selected from the remaining candidate register classes; When the overflow register class contains a second physical register that is in an available state, the instruction operands stored in the target register are overflowed into the second physical register; When the overflow register class does not contain a second physical register that is in an available state, the overflow register class selected in this round is excluded from the remaining candidate register classes, and the next round of iteration begins.

5. The method according to any one of claims 1 to 4, characterized in that, After the instruction operands stored in the target register overflow into the second physical register among the other N-1 candidate register classes, the method further includes: The instruction operand is read from the second physical register, and the operation in the target program is executed based on the instruction operand to obtain the operation result.

6. The method as described in claim 5, characterized in that, After the instruction operands stored in the target register overflow into the second physical register among the other N-1 candidate register classes, the method further includes: Peephole optimization is performed on the transfer instruction, which is used to overflow the instruction operand into the second physical register and read the instruction operand from the second physical register.

7. A computer device comprising a memory, a chip, and a computer program stored on the memory and running on the chip, characterized in that, When the chip executes the computer program, it implements the steps of the method as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, It stores a computer program that is executed by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the method as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, The computer program product includes a computer program stored on a computer-readable storage medium, the computer program including program instructions that, when executed by a computer device, cause the computer device to perform the steps of the method as described in any one of claims 1 to 6.

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