SiC MOSFET device, manufacturing method and chip

Abstract

The embodiment of the invention provides a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, a manufacturing method and a chip, and the device comprises an N-epitaxial layer which is arranged at one side of an N + substrate; a current spreading layer; the P-type base region is arranged in the current expansion layer; the N + region is arranged in the P-type base region; the first grooves are formed in the side walls of the two sides of the current expansion layer; the second groove is formed in the current expansion layer; two side walls of the second groove are connected with the P-type base region and the N + region; and the grid polycrystalline silicon is arranged on a part of the upper surface of the N + region, a part of the upper surface of the P-type base region connected with the part of the upper surface of the N + region, and a part of the upper surface of the current expansion layer connected with the part of the upper surface of the P-type base region. During reverse conduction, the conduction voltage drop of the channel diode is far lower than the conduction voltage drop of the body diode, so that the channel diode is conducted more than the parasitic body diode, the conduction voltage drop of the device during reverse follow current can be reduced through the channel diode, and the problem that the follow current loss of the body diode is large is solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a SiC MOSFET device, manufacturing method, and chip. Background Technology

[0002] With the widespread application of wide-bandgap semiconductor materials in power devices, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are gradually becoming an important choice for next-generation high-efficiency power electronic devices due to their excellent material properties, such as high breakdown electric field, high thermal conductivity, and low on-resistance. Currently, SiC MOSFET devices, due to their structural characteristics, integrate a diode structure (i.e., a parasitic body diode) within their body, enabling reverse freewheeling. However, the body diode suffers from significant freewheeling losses. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a SiC MOSFET device, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0004] To address the aforementioned problems, this invention discloses a SiC MOSFET device, the device comprising:

[0005] N+ substrate;

[0006] An N- epitaxial layer is disposed on one side of the N+ substrate;

[0007] A current spreading layer is disposed above the N-epipolar layer;

[0008] A P-type base region is disposed within the current spreading layer;

[0009] The N+ region is located within the P-type base region;

[0010] The first trench is provided on both sidewalls of the current spreading layer;

[0011] A second trench is disposed within the current spreading layer; the two sidewalls of the second trench are connected to the P-type base region and the N+ region;

[0012] A gate polysilicon, disposed on a portion of the upper surface of the N+ region, a portion of the upper surface of the P-type base region connected to the portion of the upper surface of the N+ region, and a portion of the upper surface of the current spreading layer connected to the portion of the upper surface of the P-type base region;

[0013] An oxide layer is disposed on the sidewalls and bottom of the first trench and the second trench, and encapsulates the gate polysilicon.

[0014] Optionally, the device further includes:

[0015] A P-type buried layer is disposed at the bottom of the second trench and located within the current spreading layer.

[0016] Optionally, the device further includes:

[0017] P-type pillar regions are located on both sidewalls of the N-epipolar layer and the current spreading layer.

[0018] Optionally, the first groove is located within the P-shaped column area.

[0019] Optionally, the device further includes:

[0020] The source metal is disposed above the oxide layer and the N+ region;

[0021] The drain metal is located on the other side of the N+ substrate.

[0022] Optionally, the P-type buried layer extends into the N-epipolar layer.

[0023] Accordingly, this invention discloses a method for manufacturing a SiC MOSFET device, used to manufacture the aforementioned SiC MOSFET device, the method comprising:

[0024] Provide N+ substrate;

[0025] An N- epitaxial layer is epitaxially grown on one side of the N+ substrate;

[0026] A current spreading layer is epitaxially grown above the N-epitaxial layer;

[0027] P-type ions are implanted into the current-spreading layer to form a P-type base region;

[0028] N-type ions are implanted into the P-type base region to form two symmetrically distributed N+ regions;

[0029] An oxide layer is formed on the upper surfaces of the current spreading layer, the P-type base region, and the N+ region; a gate polysilicon is deposited on the oxide layer; the oxide layer and the gate polysilicon are etched, leaving the oxide layer and the gate polysilicon on a portion of the upper surface of the N+ region, a portion of the upper surface of the P-type base region connected to the portion of the upper surface of the N+ region, and a portion of the upper surface of the current spreading layer connected to the portion of the upper surface of the P-type base region;

[0030] An oxide layer is deposited on the upper surface of the current spreading layer, the gate polysilicon, the N+ region, and the P-type base region; the oxide layer is etched, leaving the oxide layer surrounding the gate polysilicon and its upper surface intact;

[0031] Etching is performed on the two sidewalls of the current spreading layer to form two symmetrically distributed first trenches;

[0032] A second trench is formed by etching within the P-type base region and the current spreading layer; the sidewalls of the second trench are connected to the N+ region.

[0033] An oxide layer is formed on the sidewalls and bottom of the first and second trenches, on the oxide layer and on the upper surface of the N+ region; the oxide layer is etched, retaining the oxide layer on the sidewalls and bottom of the first and second trenches and on the upper surface of the oxide layer.

[0034] Optionally, the method further includes:

[0035] Ion implantation is performed at the bottom of the second trench to form a P-type buried layer; the P-type buried layer is located within the current spreading layer.

[0036] Optionally, before etching the two sidewalls of the current spreading layer to form two symmetrically distributed first trenches, the method further includes:

[0037] Two symmetrically distributed third trenches are etched on the sidewalls of the current spreading layer and the N-epitaxial layer.

[0038] The third trench is filled with P-type silicon carbide to form two symmetrically distributed P-type column regions.

[0039] Optionally, etching is performed on the two sidewalls of the current spreading layer to form two symmetrically distributed first trenches, including:

[0040] Etching is performed within the P-shaped pillar region to form two symmetrically distributed first trenches.

[0041] Optionally, the method further includes:

[0042] A source metal is formed above the oxide layer and the N+ region;

[0043] On the other side of the N+ substrate, a drain metal is formed.

[0044] Optionally, the P-type buried layer extends into the N-epipolar layer.

[0045] Optionally, after ion implantation is performed at the bottom of the second trench to form a P-type buried layer, the method further includes:

[0046] A sacrificial oxide layer is formed on the sidewalls and bottom of the first trench, the sidewalls of the first trench, the upper surface of the P-type buried layer, the upper surface of the oxide layer, and the upper surface of the N+ region.

[0047] Remove the sacrificial oxide layer.

[0048] Accordingly, this invention discloses a chip including the SiC MOSFET device described above.

[0049] The embodiments of the present invention have the following advantages:

[0050] The SiC MOSFET device of this invention includes an N+ substrate; an N- epitaxial layer disposed on one side of the N+ substrate; a current spreading layer disposed above the N- epitaxial layer; a P-type base region disposed within the current spreading layer; an N+ region disposed within the P-type base region; a first trench disposed on both sidewalls of the current spreading layer; a second trench disposed within the current spreading layer; the sidewalls of the second trench are connected to the P-type base region and the N+ region; a gate polysilicon disposed on a portion of the upper surface of the N+ region, a portion of the upper surface of the P-type base region connected to the portion of the upper surface of the N+ region, and a portion of the upper surface of the current spreading layer connected to the portion of the upper surface of the P-type base region; and an oxide layer disposed on the sidewalls and bottom of the first and second trenches, and encapsulating the gate polysilicon. A channel diode is formed by an N+ region, a P-type base region, and a current spreading layer. During reverse conduction, the forward voltage drop of the channel diode is much lower than that of the body diode. Therefore, the channel diode conducts before the parasitic body diode. Thus, the forward voltage drop of the device during reverse freewheeling can be reduced by using a channel diode, which optimizes the problem of large freewheeling losses in the body diode. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the structure of a SiC MOSFET device according to an embodiment of the present invention;

[0052] Figure 2 This is a schematic diagram of another SiC MOSFET device according to an embodiment of the present invention;

[0053] Figure 3 This is a schematic diagram of a SiC MOSFET device layout design according to an embodiment of the present invention;

[0054] Figure 4 This is a schematic diagram of a device structure corresponding to a SiC MOSFET device layout design according to an embodiment of the present invention;

[0055] Figure 5 This is a schematic diagram of another device structure corresponding to a SiC MOSFET device layout design according to an embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram of another device structure corresponding to a SiC MOSFET device layout design according to an embodiment of the present invention;

[0057] Figure 7This is a schematic diagram of another SiC MOSFET device layout design according to an embodiment of the present invention;

[0058] Figure 8 This is a schematic diagram of the device structure corresponding to another SiC MOSFET device layout design according to an embodiment of the present invention;

[0059] Figure 9 This is a schematic diagram of the body diode and channel diode of a SiC MOSFET device according to an embodiment of the present invention;

[0060] Figure 10 This is a schematic diagram of the current flow direction of a SiC MOSFET device during reverse freewheeling according to an embodiment of the present invention;

[0061] Figure 11 This is a schematic diagram of the equivalent circuit of a SiC MOSFET device according to an embodiment of the present invention;

[0062] Figure 12 This is a schematic diagram of the conduction band energy distribution of a SiC MOSFET device according to an embodiment of the present invention;

[0063] Figure 13 This is a schematic diagram of another SiC MOSFET device according to an embodiment of the present invention;

[0064] Figure 14 This is a flowchart illustrating the steps of a SiC MOSFET device manufacturing method according to an embodiment of the present invention;

[0065] Figure 15 This is a schematic diagram of the structure of a SiC MOSFET device manufactured according to an embodiment of the present invention;

[0066] Figure 16 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention;

[0067] Figure 17 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention;

[0068] Figure 18 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention;

[0069] Figure 19 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention;

[0070] Figure 20 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention;

[0071] Figure 21 This is a schematic diagram of another SiC MOSFET device fabrication according to an embodiment of the present invention.

[0072] Reference numerals: N+ substrate 10, N- epitaxial layer 11, current spreading layer 12, P-type base region 13, N+ region 14, first trench 15, second trench 16, gate polysilicon 17, oxide layer 18, P-type buried layer 19, P-type pillar region 20, source metal 21, drain metal 22, body diode 23, channel diode 24. Detailed Implementation

[0073] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0074] With the widespread application of wide-bandgap semiconductor materials in power devices, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are gradually becoming an important choice for next-generation high-efficiency power electronic devices due to their excellent material properties, such as high breakdown electric field, high thermal conductivity, and low on-resistance. Currently, SiC MOSFET devices, due to their structural characteristics, integrate a diode structure (i.e., a parasitic body diode) within their body, enabling reverse freewheeling. However, the body diode suffers from significant freewheeling losses.

[0075] One of the core concepts of this invention is that a channel diode is formed by an N+ region, a P-type base region, and a current spreading layer. During reverse conduction, since the forward voltage drop of the channel diode is much lower than that of the body diode, the channel diode conducts before the parasitic body diode. Therefore, the forward voltage drop of the device during reverse freewheeling can be reduced by using the channel diode, thus optimizing the problem of large freewheeling losses in the body diode.

[0076] Reference Figure 1 The diagram illustrates a structural schematic of a SiC MOSFET device according to an embodiment of the present invention, which may specifically include the following structure:

[0077] N+ substrate 10.

[0078] The N+ substrate 10 is an N-type doped substrate used to grow epitaxial layers and can also quickly cut off the electric field, similar to the field cutoff layer of an IGBT (Insulated Gate Bipolar Transistor).

[0079] The N- epitaxial layer 11 is disposed on one side of the N+ substrate 10.

[0080] The N-epitaxy layer 11 (N-EPI) is an N-epitaxy layer with a concentration lower than that of the N+ substrate. It is N-type doped and similar to the N-type drift region of an IGBT.

[0081] The current spreading layer 12 is disposed above the N-epieptaxial layer 11.

[0082] The current spreading layer (CSL) is N-type doped, with a higher doping concentration than the N-epitaxial layer, which can reduce the JFET (Junction Field-Effect Transistor) effect. In semiconductor device design, the JFET effect refers to a JFET-like operating mechanism that occurs in certain structures. It involves controlling the width of the conductive channel through a reverse-biased PN junction, thereby affecting current flow. This effect is sometimes an undesirable parasitic effect, which can lead to increased on-resistance, uneven current density distribution, degraded device performance, and increased switching losses. Therefore, in device design, it is necessary to reduce the JFET effect to optimize the overall device performance.

[0083] The P-type base region 13 is located within the current spreading layer 12.

[0084] The P-type base region 13 (P-Body) is P-type doped, and the channel is formed here.

[0085] N+ region 14 is located within P-type base region 13.

[0086] N+ region 14 is formed by a large dose of N-type injection, which provides electrons when the MOSFET is forward-biased. Forward-biased means that the drain is connected to a high level and the source is connected to a low level.

[0087] The first trench 15 is provided on both sides of the current spreading layer 12.

[0088] The second trench 16 is disposed within the current spreading layer 12; the two sidewalls of the second trench 16 are connected to the P-type base region 13 and the N+ region 14.

[0089] The gate polysilicon 17 is disposed on a portion of the upper surface of the N+ region 14, a portion of the upper surface of the P-type base region 13 connected to the portion of the upper surface of the N+ region 14, and a portion of the upper surface of the current spreading layer 12 connected to the portion of the upper surface of the P-type base region 13.

[0090] Gate 17 is made of polysilicon and is where the gate metal is connected in the layout design.

[0091] An oxide layer 18 is disposed on the sidewalls and bottom of the first trench 15 and the second trench 16, and encapsulates the gate polysilicon 17.

[0092] The oxide layer 18 serves as a barrier and insulation layer.

[0093] The SiC MOSFET device of this invention includes an N+ substrate; an N- epitaxial layer disposed on one side of the N+ substrate; a current spreading layer disposed above the N- epitaxial layer; a P-type base region disposed within the current spreading layer; an N+ region disposed within the P-type base region; a first trench disposed on both sidewalls of the current spreading layer; a second trench disposed within the current spreading layer; the sidewalls of the second trench are connected to the P-type base region and the N+ region; a gate polysilicon disposed on a portion of the upper surface of the N+ region, a portion of the upper surface of the P-type base region connected to the portion of the upper surface of the N+ region, and a portion of the upper surface of the current spreading layer connected to the portion of the upper surface of the P-type base region; and an oxide layer disposed on the sidewalls and bottom of the first and second trenches, and encapsulating the gate polysilicon. A channel diode is formed by an N+ region, a P-type base region, and a current spreading layer. During reverse conduction, the forward voltage drop of the channel diode is much lower than that of the body diode. Therefore, the channel diode conducts before the parasitic body diode. Thus, the forward voltage drop of the device during reverse freewheeling can be reduced by using a channel diode, which optimizes the problem of large freewheeling losses in the body diode.

[0094] Reference Figure 2 The diagram illustrates a structural schematic of another SiC MOSFET device according to an embodiment of the present invention. The device further includes:

[0095] The P-type buried layer 19 is located at the bottom of the second trench 16 and within the current spreading layer 12.

[0096] The P-type buried layer 19 (P-Shielding Region, PSR) is P-type doped and can form a PN junction with the N-epitaxial layer 11. The P-type buried layer 19 can adjust the internal electric field distribution of the device under breakdown voltage. Its main function is to significantly reduce the electric field strength near the gate trench corner, thereby increasing the device's reliability. The structural distribution of the P-type buried layer 19 in the SiC MOSFET device can be changed through layout design. By adjusting the PSR distribution, the current path of the SiC MOSFET device can be optimized, thereby improving short-circuit performance.

[0097] In this embodiment of the invention, the device further includes:

[0098] P-type pillar regions 20 are located on both sides of the N-epipolar layer 11 and the current spreading layer 12.

[0099] The P-type pillar region 20 is P-type doped and is located on both sides of the N-epitaxial layer 11 and the current spreading layer 12, forming a superjunction structure. The superjunction structure can improve the breakdown voltage of the device and reduce the on-resistance.

[0100] In this embodiment of the invention, the first groove 15 is provided within the P-shaped column area 20.

[0101] The first trench 15 is disposed on both sides of the current spreading layer 12. When the device also includes a P-type pillar region 20, and the P-type pillar region 20 is disposed on both sides of the N-epitaxial layer 11 and the current spreading layer 12, the first trench 15 is disposed in the P-type pillar region 20. The first trench 15 can be connected to the source metal through the oxide layer 18.

[0102] In this embodiment of the invention, the device further includes:

[0103] Source metal 21 is disposed above oxide layer 18 and N+ region 14;

[0104] Drain metal 22 is disposed on the other side of N+ substrate 10.

[0105] The source metal 21, N+ region 14, P-type base region 13 and current spreading layer 12 together form a channel diode (MCD). The source metal 21, which is in contact with SiC, can form a Schottky contact with SiC, and the drain metal 22 can form an ohmic contact with SiC.

[0106] Reference Figure 3 The diagram illustrates a SiC MOSFET device layout design according to an embodiment of the present invention. The black bars represent trench etching, and the gray rectangles (divided into long and short types) represent P-type buried layers arranged in an array. The three lines AA', BB', and CC' in the diagram correspond to three different device structures.

[0107] Reference Figure 4 This diagram illustrates a device structure corresponding to a SiC MOSFET device layout design according to an embodiment of the present invention. Figure 4 For the corresponding Figure 3 Device structure of the AA' line. (Refer to...) Figure 5 This diagram illustrates another device structure corresponding to a SiCMOSFET device layout design according to an embodiment of the present invention. Figure 4 For the corresponding Figure 3 Device structure of the middle BB' line. (Refer to...) Figure 6 This diagram illustrates another device structure corresponding to a SiC MOSFET device layout design according to an embodiment of the present invention. Figure 6 For the corresponding Figure 3 The device structure of the CC' line. It can be seen that the device structure is strongly correlated with the distribution of the P-type buried layer, due to... Figure 3 The device structure corresponding to the CC' line has no current path. Therefore, this layout design can not only reduce the saturation current when the device is turned on, but also effectively change the current path and improve the short-circuit withstand performance of the device.

[0108] Reference Figure 7This diagram illustrates another SiC MOSFET device layout design according to an embodiment of the present invention. In this layout design, there is no trench etching at the CC' line. (Refer to...) Figure 8 This diagram illustrates a schematic of the device structure corresponding to another SiC MOSFET device layout design according to an embodiment of the present invention. Figure 8 For the corresponding Figure 7 The device structure at the CC' line is also feasible, as is the device structure without trench etching at the CC' line.

[0109] Reference Figure 9 This diagram illustrates a schematic of the body diode and channel diode of a SiC MOSFET device according to an embodiment of the present invention. The P-type base region 13 and the current spreading layer 12 form the body diode 23. The channel diode 24 is enclosed in a black dashed box. The channel diode 24 consists of a source metal 21, an N+ region 14, a P-type base region 13, and a current spreading layer 12. The solid line portion within the black dashed box represents the circuit symbol of the channel diode 24. Because the surface of the P-type buried layer 19 has an oxide layer 18, the P-type buried layer 19 does not directly contact the source metal 21. Therefore, during reverse freewheeling, the P-type buried layer 19 and the N-epipolar layer 11 do not form a body diode. Although the P-type base region 13 does not directly contact the source metal 21, the P-type base region 13, the N+ region 14, and the current spreading layer 12 form an NPN transistor. Electrons in the current spreading layer 12 need to overcome the potential barrier height of a body diode to reach the source metal 21 through the P-type base region 13. A body diode is a PN junction formed by a P-type semiconductor and an N-type semiconductor, and this PN junction can conduct when reverse freewheeling current is applied.

[0110] Reference Figure 10 This diagram illustrates the current flow direction of a SiC MOSFET device in reverse freewheeling mode according to an embodiment of the present invention. The current flow direction is opposite to the electron current. VG is grounded, VD is grounded, and VS is connected to a high level. The device is in a unipolar conduction mode in reverse freewheeling mode. The specific working principle of the channel diode 24 is as follows: After a certain high level is applied to the source metal 21, the P-type base region 13 on the sidewall of the second trench 16 will form a channel. After the channel is open, since the voltage at the source metal 21 terminal is driven by the voltage, the electron current will flow through the drain metal 22, the N-epipolar layer 11, the current extension layer 12, the P-type base region 13 channel, the N+ region 14, and the source metal 21.

[0111] Reference Figure 11The diagram shows an equivalent circuit diagram of a SiC MOSFET device according to an embodiment of the present invention. In this diagram, RDrift is the resistance of the N- epitaxial layer 11, RSub is the resistance of the N+ substrate 10, and RJFET is the resistance of the JFET region. The JFET region is composed of two P-type doped layers and one N-type doped layer. In this embodiment of the present invention, the JFET region is composed of a P-type buried layer 19, a current spreading layer 12, and a P-type pillar region 20. The resistance of the JFET is related to the length, doping, and width of the JFET region. Figure 11 This can be used to explain why the channel diode 24 conducts before the parasitic body diode 23 during reverse conduction. Figure 11 It can be seen that the body diode 23 and the channel diode 24 are connected in parallel. When reverse conduction occurs, the source metal 21Source is at a high level. Therefore, when the voltage applied to the source metal 21Source is greater than the forward voltage drop of the channel diode 24 and less than the forward voltage drop of the body diode 23, the entire SiC MOSFET is in the reverse conduction state.

[0112] Reference Figure 12 This diagram illustrates the conduction band energy distribution of a SiC MOSFET device according to an embodiment of the present invention. When the gate polysilicon 17 is grounded or has a negative voltage, the drain metal 22 is connected to a low level, and the source metal 21 is connected to a high level, the device is in a reverse conduction / freewheeling state. When the device is in a reverse conduction state, for electrons in the current spread layer 12 to flow through the P-type base region 13 and the source metal 21, they need to overcome the barrier height of the channel diode 24 formed by the current spread layer 12 and the P-type base region 13 (white line B-B' in the diagram). At the interface between the P-type base region 13 and the source trench oxide layer, due to the downward bending of the surface energy band, electrons only need to overcome a lower barrier to form a conductive channel to enter the source metal 21 (black line A-A' in the diagram). At this time, the surface of the P-type buried layer 19 is in a depletion state with a very low hole density, thus forming an electron current, which is unipolar conduction. The depletion state means the surface band bends downwards, and electrons accumulate at the bottom of the conduction band where it bends downwards, while holes move away from that area. When a high voltage is applied to the source metal, the downward bending of the surface band further increases, and more electrons accumulate at the bend. Therefore, the channel diode 24 will conduct before the body diode 23. In addition, the conduction of the body diode 23 is bipolar conduction. Due to the stacking faults in the silicon carbide epitaxial wafer, electrons and holes recombine in the drift region, releasing energy and activating the stacking faults, which reduces the device's conductivity and reliability.

[0113] When the gate polysilicon 17 is grounded or has a negative voltage, the drain metal 22 is connected to a high level, and the source metal 21 is grounded, i.e., when the device is in a forward blocking state, a lateral electric field modulation effect is generated in the drift region. This causes some carriers to be depleted laterally, and the originally tilted electric field distribution in the vertical direction is approximately flattened, thus increasing the forward breakdown voltage of the device. In addition, the P-type buried layer 19 will cut off most of the electric field lines at the drain, reducing the electric field strength at the bottom of the gate trench and improving the reliability of the device.

[0114] By adjusting the distribution of the PSR in conjunction with the device structure, the current path can be effectively changed, thereby improving the device's short-circuit withstand performance. The SiC superjunction MOSFET with integrated channel diode in this embodiment of the invention offers certain advantages in device reliability, reverse conduction voltage drop, and short-circuit withstand performance.

[0115] Reference Figure 13 The diagram shows a schematic of another SiC MOSFET device according to an embodiment of the invention, in which the P-type buried layer 19 extends into the N-epitaxial layer 11. Figure 13 Excluding the P-type column region 20, the P-type buried layer 19 extends into the N-epilayer 11, and the deeper layers can play a role similar to a semi-superjunction.

[0116] The SiC superjunction MOSFET structure with integrated channel diode in this invention optimizes the problems of high freewheeling loss and bipolar degradation in body diodes, and also improves the short-circuit performance of SiC MOSFET devices to a certain extent. Through structural design, a channel diode is integrated inside the SiC MOSFET device. From the perspective of potential barriers, its reverse freewheeling performance is optimized without affecting the device's forward conduction performance. While ensuring high gate oxide reliability, the on-state voltage drop during reverse freewheeling can be reduced. Furthermore, by modifying the structural distribution of the P-type buried layer in the SiC MOSFET device through layout design, and by adjusting the PSR distribution, the current path of the SiC MOSFET device can be optimized, thereby improving short-circuit performance.

[0117] Reference Figure 14 The diagram illustrates a step-by-step flowchart of a SiC MOSFET device manufacturing method according to an embodiment of the present invention, which may specifically include the following steps:

[0118] Step 101, provide an N+ substrate.

[0119] Step 102: An N- epitaxial layer is epitaxially grown on one side of the N+ substrate.

[0120] Step 103: An epitaxial current spreading layer is formed on top of the N-epitaxy layer.

[0121] Step 104: P-type ions are implanted into the current spreading layer to form a P-type base region.

[0122] Step 105: Inject N-type ions into the P-type base region to form two symmetrically distributed N+ regions.

[0123] Reference Figure 15 An N+ type semiconductor, i.e., an N+ substrate 10, is used as the substrate material. An N- epitaxial layer 11 and a current spreading layer 12 are sequentially grown on the N+ substrate 10. A P-type base region 13 is formed within the current spreading layer 12 by ion implantation, and an N+ region 14 is formed within the P-type base region 13 by ion implantation. The N+ region 14 is symmetrically distributed around the centerline of the P-type base region 13. Due to the special properties of SiC material, 1 to 5 ion implantation cycles are required to form the P-type base region 13 and the N+ region 14.

[0124] Step 106: An oxide layer is formed on the upper surfaces of the current spreading layer, the P-type base region, and the N+ region; gate polysilicon is deposited on the oxide layer; the oxide layer and the gate polysilicon are etched, leaving the oxide layer and gate polysilicon on a portion of the upper surface of the N+ region, a portion of the upper surface of the P-type base region connected to the portion of the upper surface of the N+ region, and a portion of the upper surface of the current spreading layer connected to the portion of the upper surface of the P-type base region.

[0125] Reference Figure 16 ,exist Figure 15 Based on this, a high-quality oxide layer of several hundred angstroms is generated on the upper surfaces of the current spreading layer, the P-type base region, and the N+ region using a dry oxygen thermal oxidation method. Dry oxygen thermal oxidation is one of the commonly used methods for generating oxide layers in semiconductor device fabrication. This method typically uses pure oxygen as an oxidant, which reacts with the silicon wafer surface at high temperature to form a high-quality silicon dioxide (SiO2) layer on the silicon wafer surface. The oxide layer generated by dry oxygen thermal oxidation has high density and good electrical insulation properties, and is therefore widely used in the manufacture of key components such as the gate oxide layer in MOS (metal-oxide-semiconductor) devices.

[0126] Next, gate polysilicon 17 is deposited on the oxide layer by LPCVD (Low Pressure Chemical Vapor Deposition), and dry etching is used to form the final gate polysilicon 17, namely, the oxide layer 18 and gate polysilicon 17 remaining on the partial upper surface of the N+ region, the partial upper surface of the P-type base region connected to the partial upper surface of the N+ region, and the partial upper surface of the current spreading layer connected to the partial upper surface of the P-type base region.

[0127] Low-pressure chemical vapor deposition (LPCVD) is a commonly used technique for depositing thin films in semiconductor manufacturing. LPCVD operates at relatively low pressures, which helps reduce collisions between gas molecules, resulting in more uniform film deposition and higher quality. Dry etching is a crucial step for patterning polysilicon gates. After the gate region is defined by photolithography, dry etching removes unwanted polysilicon material, forming a gate structure with high precision and good morphology control.

[0128] Step 107: Deposit an oxide layer on the upper surface of the current spreading layer, the gate polysilicon, the N+ region, and the P-type base region; etch the oxide layer, retaining the oxide layer surrounding the gate polysilicon and its upper surface.

[0129] An oxide layer 18 is deposited on the upper surface of the current spreading layer, the gate polysilicon, the N+ region and the P-type base region. The oxide layer 18 is an interlayer dielectric (ILD). The interlayer dielectric is etched to retain the interlayer dielectric layer surrounding the gate polysilicon 17 and its upper surface.

[0130] Interlayer dielectric layers are mainly used to isolate conductive lines at different levels, such as polysilicon gates and metal interconnects, to prevent unnecessary electrical connections between them and to provide structural support.

[0131] Step 108: Etching is performed on the two sidewalls of the current spreading layer to form two symmetrically distributed first trenches.

[0132] Step 109: Etch within the P-type base region and the current spreading layer to form a second trench; the sidewalls of the second trench are connected to the N+ region.

[0133] Reference Figure 17 ,exist Figure 16 Based on this, and in conjunction with a mask, plasma etching / dry etching techniques are used to etch and form the first trench 15 and the second trench 16.

[0134] Step 110: Form an oxide layer on the sidewalls and bottom of the first trench and the second trench, on the oxide layer and the upper surface of the N+ region; etch the oxide layer while retaining the oxide layer on the sidewalls and bottom of the first trench and the second trench, and on the upper surface of the oxide layer.

[0135] Reference Figure 18An oxide layer 18 is formed on the sidewalls and bottom of the first trench 15 and the second trench 16, on the interlayer dielectric layer and the upper surface of the N+ region 14. This oxide layer 18 is a gate oxide layer. The gate oxide layer above the N+ region 14 is dry etched, leaving the gate oxide layer above the interlayer dielectric layer on the sidewalls and bottom of the first trench 15 and the second trench 16.

[0136] In this embodiment of the invention, after etching in step 109 within the P-type base region and the current spreading layer to form the second trench, the method further includes:

[0137] Ion implantation is performed at the bottom of the second trench to form a P-type buried layer; the P-type buried layer is located within the current spreading layer.

[0138] Reference Figure 19 ,exist Figure 17 Based on this, ion implantation is performed at the bottom of the second trench 16 to form a P-type buried layer. Due to the special properties of SiC material, 1 to 5 ion implantations are performed at this location.

[0139] In this embodiment of the invention, before etching the two sidewalls of the current spreading layer in step 108 to form two symmetrically distributed first trenches, the method further includes:

[0140] Two symmetrically distributed third trenches are etched on the sidewalls of the current spreading layer and the N-epitaxial layer.

[0141] The third trench is filled with P-type silicon carbide to form two symmetrically distributed P-type column regions.

[0142] Reference Figure 20 ,exist Figure 16 Based on this, a dielectric layer LPTEOS (with) is first deposited. There are also The specific thickness is uncertain, as long as it can be used to form a window for etching trenches. The trench window is first etched on the dielectric layer LPTEOS using a trench mask. The etched dielectric layer LPTEOS area will expose SiC. Then, based on this window, the trench is etched on the SiC using plasma etching / dry etching technology. P-type pillar regions 20 are formed in the trench by filling with P-type SiC. After the filling is completed, the dielectric layer LPTEOS is removed.

[0143] In an embodiment of the invention, etching is performed on the two sidewalls of the current spreading layer to form two symmetrically distributed first trenches, including:

[0144] Etching is performed within the P-shaped pillar region to form two symmetrically distributed first trenches.

[0145] After forming the P-type pillar region 20, the P-type pillar region 20 is etched to form the first trench 15.

[0146] In this embodiment of the invention, the method further includes:

[0147] A source metal is formed above the oxide layer and the N+ region;

[0148] On the other side of the N+ substrate, a drain metal is formed.

[0149] Reference Figure 21 ,exist Figure 20 Based on this, source metal 21 and drain metal 22 are formed by deposition or sputtering. The source metal 21, which is in contact with SiC, needs to form a Schottky contact with SiC, and the drain metal 22 needs to form an ohmic contact with SiC.

[0150] In this embodiment of the invention, the P-type buried layer extends into the N-epipolar layer.

[0151] Reference Figure 13 Excluding the P-type column region 20, the P-type buried layer 19 is set deeper, extending into the N-epterion layer 11. The deeper P-type buried layer 19 can play a role similar to a semi-superjunction.

[0152] In this embodiment of the invention, after ion implantation is performed at the bottom of the second trench to form a P-type buried layer, the method further includes:

[0153] A sacrificial oxide layer is formed on the sidewalls and bottom of the first trench, the sidewalls of the first trench, the upper surface of the P-type buried layer, the upper surface of the oxide layer, and the upper surface of the N+ region.

[0154] Remove the sacrificial oxide layer.

[0155] A high-quality sacrificial oxide layer of several hundred angstroms is generated on the sidewalls and bottom of the first trench 15, the sidewalls of the second trench 16, the upper surface of the P-type buried layer 19, the upper surface of the oxide layer 18, and the upper surface of the N+ region 14 using a dry oxygen thermal oxidation method. The sacrificial oxide layer is then removed by etching to remove the interface damage caused by implantation and etching.

[0156] A sacrificial oxide layer is a layer of silicon dioxide grown on the surface of a silicon wafer through methods such as thermal oxidation. However, it is not part of the final device structure and is removed in subsequent processes. Its main purpose is to improve the surface quality of silicon or remove surface defects / contamination. Sacrificial oxide layers can clean surfaces and repair defects. Silicon wafer surfaces often have lattice damage (such as scratches, ion implantation damage) and adsorb contaminants (metal ions, organic matter, etc.). Growing a sacrificial oxide layer can "wrap" these defects within the oxide layer, significantly improving the quality of the exposed silicon surface after removal. It can also adsorb impurity metal ions. At high temperatures, certain metal impurities easily diffuse and accumulate at the oxide-silicon interface. A sacrificial oxide layer can "extract" these metals, thus purifying the silicon material. Furthermore, it reduces interface state density. High-quality gate oxide layers require low interface state density; sacrificial oxide layer pretreatment can reduce interface defects between the final oxide layer and silicon.

[0157] The SiC MOSFET device of this invention includes an N+ substrate; an N- epitaxial layer disposed on one side of the N+ substrate; a current spreading layer disposed above the N- epitaxial layer; a P-type base region disposed within the current spreading layer; an N+ region disposed within the P-type base region; a first trench disposed on both sidewalls of the current spreading layer; a second trench disposed within the current spreading layer; the sidewalls of the second trench are connected to the P-type base region and the N+ region; a gate polysilicon disposed on a portion of the upper surface of the N+ region, a portion of the upper surface of the P-type base region connected to the portion of the upper surface of the N+ region, and a portion of the upper surface of the current spreading layer connected to the portion of the upper surface of the P-type base region; and an oxide layer disposed on the sidewalls and bottom of the first and second trenches, and encapsulating the gate polysilicon. A channel diode is formed by an N+ region, a P-type base region, and a current spreading layer. During reverse conduction, the forward voltage drop of the channel diode is much lower than that of the body diode. Therefore, the channel diode conducts before the parasitic body diode. Thus, the forward voltage drop of the device during reverse freewheeling can be reduced by using a channel diode, which optimizes the problem of large freewheeling losses in the body diode.

[0158] This invention also discloses a chip, including the SiC MOSFET device described above.

[0159] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0160] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0161] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0162] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0163] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0164] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0165] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0166] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0167] The SiC MOSFET device, manufacturing method, and chip provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A SiC MOSFET device, characterized in that, The device includes: N+ substrate; An N- epitaxial layer is disposed on one side of the N+ substrate; A current spreading layer is disposed above the N-epipolar layer; A P-type base region is disposed within the current spreading layer; The N+ region is located within the P-type base region; The first trench is provided on both sidewalls of the current spreading layer; A second trench is disposed within the current spreading layer; the two sidewalls of the second trench are connected to the P-type base region and the N+ region; A gate polysilicon, disposed on a portion of the upper surface of the N+ region, a portion of the upper surface of the P-type base region connected to the portion of the upper surface of the N+ region, and a portion of the upper surface of the current spreading layer connected to the portion of the upper surface of the P-type base region; An oxide layer is disposed on the sidewalls and bottom of the first trench and the second trench, and encapsulates the gate polysilicon.

2. The SiC MOSFET device according to claim 1, characterized in that, The device also includes: A P-type buried layer is disposed at the bottom of the second trench and located within the current spreading layer.

3. The SiC MOSFET device according to claim 2, characterized in that, The device also includes: P-type pillar regions are located on both sidewalls of the N-epipolar layer and the current spreading layer.

4. The SiC MOSFET device according to claim 3, characterized in that, The first groove is located within the P-shaped column area.

5. The SiC MOSFET device according to claim 1, characterized in that, The device also includes: The source metal is disposed above the oxide layer and the N+ region; The drain metal is located on the other side of the N+ substrate.

6. The SiC MOSFET device according to claim 2, characterized in that, The P-type buried layer extends into the N-epipolar layer.

7. A method for manufacturing a SiC MOSFET device, characterized in that, The method for manufacturing a SiC MOSFET device as described in any one of claims 1-6 comprises: Provide N+ substrate; An N- epitaxial layer is epitaxially grown on one side of the N+ substrate; A current spreading layer is epitaxially grown above the N-epitaxial layer; P-type ions are implanted into the current-spreading layer to form a P-type base region; N-type ions are implanted into the P-type base region to form two symmetrically distributed N+ regions; An oxide layer is formed on the upper surfaces of the current spreading layer, the P-type base region, and the N+ region; a gate polysilicon is deposited on the oxide layer; the oxide layer and the gate polysilicon are etched, leaving the oxide layer and the gate polysilicon on a portion of the upper surface of the N+ region, a portion of the upper surface of the P-type base region connected to the portion of the upper surface of the N+ region, and a portion of the upper surface of the current spreading layer connected to the portion of the upper surface of the P-type base region; An oxide layer is deposited on the upper surface of the current spreading layer, the gate polysilicon, the N+ region, and the P-type base region; the oxide layer is etched, leaving the oxide layer surrounding the gate polysilicon and its upper surface intact; Etching is performed on the two sidewalls of the current spreading layer to form two symmetrically distributed first trenches; A second trench is formed by etching within the P-type base region and the current spreading layer; the sidewalls of the second trench are connected to the N+ region. An oxide layer is formed on the sidewalls and bottom of the first and second trenches, on the oxide layer and on the upper surface of the N+ region; the oxide layer is etched, retaining the oxide layer on the sidewalls and bottom of the first and second trenches and on the upper surface of the oxide layer.

8. The method for manufacturing a SiC MOSFET device according to claim 7, characterized in that, The method further includes: Ion implantation is performed at the bottom of the second trench to form a P-type buried layer; the P-type buried layer is located within the current spreading layer.

9. The method for manufacturing a SiC MOSFET device according to claim 8, characterized in that, Before etching the two sidewalls of the current spreading layer to form two symmetrically distributed first trenches, the method further includes: Two symmetrically distributed third trenches are etched on the sidewalls of the current spreading layer and the N-epitaxial layer. The third trench is filled with P-type silicon carbide to form two symmetrically distributed P-type column regions.

10. The method for manufacturing a SiC MOSFET device according to claim 9, characterized in that, The etching is performed on the two sidewalls of the current spreading layer to form two symmetrically distributed first trenches, including: Etching is performed within the P-shaped pillar region to form two symmetrically distributed first trenches.

11. The method for manufacturing a SiC MOSFET device according to claim 7, characterized in that, The method further includes: A source metal is formed above the oxide layer and the N+ region; On the other side of the N+ substrate, a drain metal is formed.

12. The method for manufacturing a SiC MOSFET device according to claim 8, characterized in that, The P-type buried layer extends into the N-epipolar layer.

13. The method for manufacturing a SiC MOSFET device according to claim 8, characterized in that, After ion implantation is performed at the bottom of the second trench to form a P-type buried layer, the method further includes: A sacrificial oxide layer is formed on the sidewalls and bottom of the first trench, the sidewalls of the first trench, the upper surface of the P-type buried layer, the upper surface of the oxide layer, and the upper surface of the N+ region. Remove the sacrificial oxide layer.

14. A chip, characterized in that, Including the SiC MOSFET device as described in any one of claims 1 to 6 above.

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