A unidirectional ultra-low voltage electrostatic protection device

Abstract

The application provides a one-way ultra-low voltage electrostatic protection device, which comprises a TVS main device and a low-voltage trigger unit, the TVS main device comprises an N-type heavily doped substrate and a P-type epitaxial layer, the P-type epitaxial layer is provided with a first P+ heavily doped active region, an N+ heavily doped active region and a second P+ heavily doped active region, the first P+ heavily doped active region, the N+ heavily doped active region and the second P+ heavily doped active region cooperatively form an NPN-type triode, the lower surface of the N-type heavily doped substrate is connected with an I / O port one, the N+ heavily doped active region and the second P+ heavily doped active region are connected with an I / O port two, the low-voltage trigger unit is arranged between the I / O port one and the first P+ heavily doped active region, and the low-voltage trigger unit can quickly forward bias and conduct the PN junction formed by the first P+ heavily doped active region and the N+ heavily doped active region. The application has the beneficial effect of reducing the opening voltage of the electrostatic protection device.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection devices, specifically to a unidirectional ultra-low voltage ESD protection device. Background Technology

[0002] In real-world applications of electronic devices, electrostatic discharge (ESD) and electrical overstress (EOS) are unavoidable phenomena. These phenomena not only lead to functional failures and reduced product reliability, but in extreme cases, can even cause permanent damage. To address the protection requirements against ESD and EOS, placing a transient voltage suppressor (TVS) at the front end of the protected chip or circuit is an effective method. TVS offers excellent surge and electrostatic discharge capabilities, forming a highly efficient electrostatic protection barrier for downstream circuits or chips.

[0003] Common electrostatic discharge (ESD) and surge protection devices include avalanche diodes (Zeners), PIN diodes, PNP devices, NPN devices, and silicon controlled rectifiers (SCRs). Among these, NPN devices offer stronger current discharge capability and lower clamping voltage compared to Zeners, PIN diodes, and PNP devices. Furthermore, compared to SCRs, NPN devices have a shallower snapback depth, effectively preventing latch-up. In summary, NPN devices are highly ideal for TVS and ESD protection, and vertical NPN devices, due to their higher power density, have become the preferred choice for design.

[0004] However, for some ultra-low voltage applications, such as AI (Artificial Intelligence) chips, traditional vertical NPN transistors are somewhat inadequate, mainly due to their relatively high trigger voltage. Furthermore, limited by the properties of silicon, simply optimizing the manufacturing process cannot effectively reduce the turn-on voltage of vertical NPN transistors.

[0005] For example, Figure 1(a) shows a general connection diagram of an NPN ESD & TVS device, which is typically used as a TVS element and connected between the I / O or power port and ground. The collector of the NPN is connected to a high potential, while the emitter and base are connected to low potentials. Figure 1(b) shows a schematic diagram of a typical vertical unidirectional NPN device, which utilizes epitaxial and deep trench isolation processes. When a positive static charge or surge occurs at the I / O or power port, the NPN collector junction avalanche occurs, turning on the NPN; conversely, when a negative charge occurs at the I / O or power port, the reverse diode channel turns on. However, this traditional vertical NPN device still suffers from a high trigger voltage, making it difficult to effectively protect low-voltage chips. Therefore, this method is insufficient to meet user needs. Summary of the Invention

[0006] To address the problems in the prior art, this invention provides a unidirectional ultra-low voltage electrostatic discharge (ESD) protection device. By incorporating an N-type heavily doped substrate, a P-type epitaxial layer, a first P+ heavily doped active region, an N+ heavily doped active region, a second P+ heavily doped active region, and a low-voltage triggering unit within the low-capacitance ESD protection device, effective ESD surge discharge can be achieved. This significantly reduces the turn-on voltage of the ESD protection device, thereby effectively protecting the low-voltage chip. This solves the problem of high trigger voltage and difficulty in effectively protecting low-voltage chips in existing vertical unidirectional NPN devices.

[0007] This invention provides a unidirectional ultra-low voltage electrostatic discharge (ESD) protection device, comprising a TVS main device and a low-voltage triggering unit. The TVS main device includes an N-type heavily doped substrate and a P-type epitaxial layer arranged from bottom to top. The P-type epitaxial layer contains a first P+ heavily doped active region, an N+ heavily doped active region, and a second P+ heavily doped active region. The tops of the first P+ heavily doped active region, the top of the N+ heavily doped active region, and the top of the second P+ heavily doped active region are flush with the upper surface of the P-type epitaxial layer. The first P+ heavily doped active region, the N+ heavily doped active region, and the second P+ heavily doped active region are all flush with the upper surface of the P-type epitaxial layer. The active regions cooperate to form an NPN transistor. The lower surface of the heavily doped N-type substrate can be connected to I / O port one. The N+ heavily doped active region and the second P+ heavily doped active region can be connected to I / O port two. The low-voltage trigger unit is disposed between I / O port one and the first P+ heavily doped active region. The low-voltage trigger unit can quickly forward bias and conduct the PN junction formed by the first P+ heavily doped active region and the N+ heavily doped active region, thereby conducting the NPN transistor to form a main current discharge path between the heavily doped N-type substrate and the P-type epitaxial layer.

[0008] In a further improvement, the P-type epitaxial layer is further provided with an isolation deep trench. The isolation deep trench cooperates with the first P+ heavily doped active region, the N+ heavily doped active region, and the second P+ heavily doped active region. The top of the isolation deep trench is flush with the upper surface of the P-type epitaxial layer, and the bottom of the isolation deep trench passes through the P-type epitaxial layer and extends into the N-type heavily doped substrate.

[0009] In a further improvement to the present invention, the low-voltage triggering unit is a Zener diode, or a series-connected diode, or a series-connected field-effect transistor with its drain and gate shorted, or a series-connected bipolar junction transistor with its base and collector shorted, and the structure of the low-voltage triggering unit includes a horizontal distribution structure and a vertical distribution structure.

[0010] The present invention is further improved in that when I / O port one is a power port, I / O port two is a ground port; when I / O port one is a ground port, I / O port two is a power port.

[0011] In a further improvement to the present invention, the filling material in the isolation deep trench is silicon dioxide, silicon nitride, or High-K.

[0012] In a further improvement, the low-voltage triggering unit is disposed within the N-type heavily doped substrate. The low-voltage triggering unit includes an integrated P+ heavily doped active region and an integrated N+ heavily doped Zener diode arranged from top to bottom. The bottom of the integrated P+ heavily doped active region is electrically connected to the top of the integrated N+ heavily doped Zener diode, and the top of the integrated P+ heavily doped active region is electrically connected to the first P+ heavily doped active region. The integrated P+ heavily doped active region and the integrated N+ heavily doped Zener diode form a PN junction. Adjusting the doping concentration of the integrated N+ heavily doped Zener diode can change the breakdown voltage of the low-voltage triggering unit. The integrated N+ heavily doped Zener diode is manufactured using an ion implantation process.

[0013] The present invention is further improved in that the doping concentration of the integrated N+ heavily doped Zener diode is C1, and the value of C1 is in the range of 10. 18 cm -3 ≤C1≤10 19 cm -3 .

[0014] The present invention is further improved in that the low-voltage triggering unit includes a first Zener P+ heavily doped active region, a Zener N+ heavily doped active region, and a second Zener P+ heavily doped active region disposed within the P-type epitaxial layer. The tops of the first Zener P+ heavily doped active region, the top of the Zener N+ heavily doped active region, and the top of the second Zener P+ heavily doped active region are all flush with the upper surface of the P-type epitaxial layer. The first Zener P+ heavily doped active region is electrically connected to the second Zener P+ heavily doped active region and the first P+ heavily doped active region. The top of the Zener N+ heavily doped active region is connected to the I / O port. A corresponding P+ heavily doped Zener diode is located at the bottom of the Zener N+ heavily doped active region. The P+ heavily doped Zener diode and the Zener N+ heavily doped active region form a PN junction. Adjusting the doping concentration of the P+ heavily doped Zener diode can change the breakdown voltage of the low-voltage trigger unit. The P+ heavily doped Zener diode is manufactured using an ion implantation process, and its doping concentration is C2, with a value ranging from 10. 18 cm -3 ≤C2≤10 19 cm -3 .

[0015] This invention is further improved in that the low-voltage triggering unit includes an independent P-type heavily doped substrate and an independent P-type epitaxial layer arranged from bottom to top. The bottom of the independent P-type heavily doped substrate is electrically connected to the bottom of the N-type heavily doped substrate. The independent P-type epitaxial layer contains a corresponding independent N+ heavily doped active region and an independent P+ heavily doped Zener diode. The top of the independent N+ heavily doped active region is flush with the upper surface of the independent P-type epitaxial layer. The independent N+ heavily doped active region is electrically connected to the first P+ heavily doped active region. The independent N+ heavily doped active region and the independent P+ heavily doped Zener diode form a PN junction. Adjusting the doping concentration of the independent P+ heavily doped Zener diode can change the breakdown voltage of the low-voltage triggering unit. The independent P+ heavily doped Zener diode is manufactured using an ion implantation process. The doping concentration of the independent P+ heavily doped Zener diode is C3, and the value of C2 ranges from 10. 18 cm -3 ≤C3≤10 19 cm -3 .

[0016] In a further improvement to the present invention, the TVS main device can be an avalanche diode, a field-effect transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, or a silicon controlled rectifier, and the structure of the TVS main device includes a horizontal distribution structure and a vertical distribution structure.

[0017] Compared with the prior art, the beneficial effects of the present invention are: it provides a unidirectional ultra-low voltage electrostatic discharge (ESD) protection device based on a novel structure. By setting an N-type heavily doped substrate, a P-type epitaxial layer, a first P+ heavily doped active region, an N+ heavily doped active region, a second P+ heavily doped active region, and a low-voltage triggering unit within the low-capacitance ESD protection device, the low-voltage triggering unit can quickly forward bias and conduct the PN junction formed by the first P+ heavily doped active region and the N+ heavily doped active region, thereby conducting the NPN transistor to form a main current discharge path between the N-type heavily doped substrate and the P-type epitaxial layer. This enables effective ESD surge discharge and significantly reduces the turn-on voltage of the ESD protection device, achieving a minimum turn-on voltage of 3V. This effectively protects low-voltage chips and solves the problem of high trigger voltage and difficulty in effectively protecting low-voltage chips in existing vertical unidirectional NPN devices. Attached Figure Description

[0018] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1(a) is a schematic diagram of a common connection method for an existing NPN type ESD & TVS device;

[0020] Figure 1(b) is a schematic diagram of the structure of a typical longitudinal unidirectional NPN device.

[0021] Figure 2(a) is a schematic diagram of a first embodiment of the unidirectional ultra-low voltage electrostatic protection device of the present invention;

[0022] Figure 2(b) is a schematic diagram of the structure of a first embodiment of the unidirectional ultra-low voltage electrostatic protection device of the present invention;

[0023] Figure 2(c) is a schematic diagram of the packaging structure of a first embodiment of the unidirectional ultra-low voltage electrostatic protection device of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of a second embodiment of the unidirectional ultra-low voltage electrostatic protection device of the present invention;

[0025] Figure 4(a) is a schematic diagram of the structure of Embodiment 3 of the unidirectional ultra-low voltage electrostatic protection device of the present invention;

[0026] Figure 4(b) is a schematic diagram of the packaging structure of Embodiment 3 of the unidirectional ultra-low voltage electrostatic protection device of the present invention;

[0027] Figure 5(a) is a schematic diagram of the structure of Embodiment 4 of the unidirectional ultra-low voltage electrostatic protection device of the present invention;

[0028] Figure 5(b) is a schematic diagram of the packaging structure of Embodiment 4 of the unidirectional ultra-low voltage electrostatic protection device of the present invention.

[0029] In the figure, 200 - N-type heavily doped substrate, 201 - P-type epitaxial layer, 202 - isolation deep trench, 203 - first P+ heavily doped active region, 204 - N+ heavily doped active region, 250 - second P+ heavily doped active region, 210 - I / O port one, 240 - I / O port two, 230 - low voltage trigger unit, 303 - first Zener P+ heavily doped active region, 304 - Zener N+ heavily doped active region, 305 - P+ heavily doped Zener diode, 306 - second Zener P+ heavily doped active region, 400 - independent P-type heavily doped substrate, 401 - independent P-type epitaxial layer, 402 - independent N+ heavily doped active region, 403 - independent P+ heavily doped Zener diode, 502 - integrated P+ heavily doped active region, 503 - integrated N+ heavily doped Zener diode. Detailed Implementation

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used herein and in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects and not to describe a particular order.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0033] like Figures 2(a)-2(c)The image shows an embodiment of the unidirectional ultra-low voltage electrostatic discharge (ESD) protection device of the present invention. This unidirectional ESD protection device includes a TVS main device and a low-voltage triggering unit. The TVS main device includes an N-type heavily doped substrate and a P-type epitaxial layer arranged from bottom to top. The P-type epitaxial layer contains a first P+ heavily doped active region, an N+ heavily doped active region, and a second P+ heavily doped active region. The tops of the first P+ heavily doped active region, the N+ heavily doped active region, and the second P+ heavily doped active region are flush with the upper surface of the P-type epitaxial layer. The first P+ heavily doped active region, the N+ heavily doped active region, and the second P+ heavily doped active region are all flush with the upper surface of the P-type epitaxial layer. The doped active region and the second P+ heavily doped active region work together to form an NPN transistor. The lower surface of the N-type heavily doped substrate can be connected to I / O port one, and the N+ heavily doped active region and the second P+ heavily doped active region can be connected to I / O port two. A low-voltage trigger unit is located between I / O port one and the first P+ heavily doped active region. The low-voltage trigger unit can quickly forward bias and conduct the PN junction formed by the first P+ heavily doped active region and the N+ heavily doped active region, thereby conducting the NPN transistor to form a main current discharge path between the N-type heavily doped substrate and the P-type epitaxial layer. The low-voltage triggering unit is disposed within an N-type heavily doped substrate. The low-voltage triggering unit includes an integrated P+ heavily doped active region 502 and an integrated N+ heavily doped Zener diode 503 arranged from top to bottom. The bottom of the integrated P+ heavily doped active region 502 is electrically connected to the top of the integrated N+ heavily doped Zener diode 503, and the top of the integrated P+ heavily doped active region 502 is electrically connected to the first P+ heavily doped active region. The integrated P+ heavily doped active region 502 and the integrated N+ heavily doped Zener diode 503 form a PN junction. Adjusting the doping concentration of the integrated N+ heavily doped Zener diode 503 can change the breakdown voltage of the low-voltage triggering unit. The integrated N+ heavily doped Zener diode 503 is manufactured using an ion implantation process, and the doping concentration of the integrated N+ heavily doped Zener diode 503 is C1, with a value ranging from 10. 18 cm -3 ≤C1≤10 19 cm -3The main TVS device can be an avalanche diode, a field-effect transistor, an NPN bipolar junction transistor, a PNP bipolar junction transistor, or a silicon controlled rectifier (SCR). The TVS main device structure includes both horizontal and vertical distribution structures. In this embodiment, a compact, integrated device layout is achieved. The "low-voltage trigger unit" uses a vertical Zener diode structure (P+ / N-Zener). Furthermore, the entire device does not employ epitaxial growth or deep trench isolation processes. This allows the power supply port on the back of the chip to be directly connected to the "low-voltage trigger unit" via the substrate without additional external interconnects. When a positive static charge or surge occurs at the I / O or power port, the low-voltage trigger path is shown by the blue dashed line in Figure 2(b), successfully reducing the turn-on voltage of the entire TVS chip. Finally, only one electrode (ground port) exists on the upper surface of the entire chip, significantly simplifying the packaging structure, as shown in Figure 2(c). In this case, only one wire bonding is needed to complete the packaging.

[0034] Figure 2 shows a second embodiment of the unidirectional ultra-low voltage electrostatic discharge (ESD) protection device of the present invention. This unidirectional ESD protection device includes an N-type heavily doped substrate 200 and a P-type epitaxial layer 201 arranged from bottom to top. The P-type epitaxial layer 201 contains an isolation trench 202, a first P+ heavily doped active region 203, an N+ heavily doped active region 204, and a second P+ heavily doped active region 250. The top of the isolation trench 202 is flush with the upper surface of the P-type epitaxial layer 201, and the bottom of the isolation trench 202 passes through the P-type epitaxial layer 201 and extends into the N-type heavily doped substrate 200. The first P+ heavily doped active region 203, the N+ heavily doped active region 204, and the second P+ heavily doped active region 250 cooperate to form a complete system. An NPN transistor has an N-type heavily doped substrate 200 whose lower surface can be connected to I / O port 210. The N+ heavily doped active region 204 and the second P+ heavily doped active region 250 can be connected to I / O port 240. A low-voltage trigger unit 230 is provided between I / O port 210 and the first P+ heavily doped active region 203 to conduct I / O port 210 and the first P+ heavily doped active region 203. The low-voltage trigger unit 230 can quickly forward bias and conduct the PN junction formed by the first P+ heavily doped active region 203 and the N+ heavily doped active region 204, thereby conducting the NPN transistor to form a main current discharge path between the N-type heavily doped substrate 200 and the P-type epitaxial layer 201. In this embodiment, by adding a low-voltage trigger unit 230 to the vertically oriented NPN transistor, the rapid conduction of the NPN transistor is assisted, achieving effective electrostatic surge discharge. Its working mechanism is as follows: When a positive static electricity or surge occurs at I / O port 210, the low-voltage trigger unit 230 is turned on first, and current is injected into the emitter of the NPN transistor along path ①, lowering the barrier height and making the PN junction forward biased and conducting. Subsequently, the NPN transistor can be turned on, forming the main current discharge path ②; when a negative charge occurs at I / O port 210, the reverse diode channel is turned on, and the current is discharged from the discharge path ③. The low-voltage trigger unit 230 can be composed of various devices, such as Zener diodes, series diodes, series field-effect transistors (in which case the drain and gate are shorted), and series bipolar junction transistors (in which case the base and collector are shorted). There are no restrictions on the connection polarity of the low-voltage trigger unit 230, and the structure of the low-voltage trigger unit includes horizontal distribution structure and vertical distribution structure. When I / O port 210 is a power port and I / O port 240 is a ground port; when I / O port 210 is a ground port and I / O port 240 is a power port. The filling material in the isolation trench 202 is silicon dioxide, silicon nitride, or High-K.

[0035] like Figure 3 (a) and Figure 3(b) shows the structural schematic diagram and packaging schematic diagram of Embodiment 3 of the unidirectional ultra-low voltage electrostatic protection device of the present invention. Compared with Embodiment 1, this embodiment concretizes the "low voltage triggering unit 230" as a Zener diode. The low voltage triggering unit 230 includes a first Zener P+ heavily doped active region 303, a Zener N+ heavily doped active region 304, and a second Zener P+ heavily doped active region 306 disposed in the P-type epitaxial layer 201. The top of the first Zener P+ heavily doped active region 303, the top of the Zener N+ heavily doped active region 304, and the top of the second Zener P+ heavily doped active region 306 are all flush with the upper surface of the P-type epitaxial layer 201. 3 is electrically connected to the second P+ heavily doped active region 306 and the first P+ heavily doped active region 203. The top of the Zener N+ heavily doped active region 304 is connected to I / O port 210. A matching P+ heavily doped Zener diode 305 is provided at the bottom of the Zener N+ heavily doped active region 304. The P+ heavily doped Zener diode 305 and the Zener N+ heavily doped active region 304 form a PN junction. Adjusting the doping concentration of the P+ heavily doped Zener diode 305 can change the breakdown voltage of the low-voltage trigger unit 230. The P+ heavily doped Zener diode 305 is manufactured by ion implantation process, and the doping concentration of the P+ heavily doped Zener diode 305 is C1, with a value ranging from 10. 18 cm -3 ≤C1≤10 19 cm -3 In this embodiment, to achieve a lower trigger voltage, the Zener diode requires an additional P-type Zener diode implantation process, i.e., implantation to generate a P+ heavily doped Zener diode 305. By adjusting the doping concentration of the P+ heavily doped Zener diode 305, Zener breakdown of the PN junction can be achieved. For silicon processes, a minimum turn-on voltage of approximately 3V can be achieved. The electrode distribution in this embodiment is as follows: there is a ground port and a power port on the upper surface of the chip, and a power port on the back of the chip. The packaging steps in this embodiment are as follows: first, the chip is fixed to a base island with conductive adhesive, and then the power port on the upper surface of the chip is connected to the base island by wire bonding. Then, the ground port on the upper surface of the chip is connected to another base island by wire bonding to complete the packaging. In addition to the wire bonding process, the above packaging structure can also be achieved by flip-chip technology.

[0036] Figures 4(a) and 4(b) show the structural schematic diagram and packaging structure schematic diagram of Embodiment 4 of the unidirectional ultra-low voltage electrostatic protection device of the present invention, respectively. Compared with Embodiment 2, in this embodiment, the "low voltage trigger unit 230" is physically separated from the main NPN transistor. These two chips are manufactured independently and then encapsulated to achieve the effect of "electrostatic protection device with low trigger voltage". The low voltage trigger unit 230 includes an independent P-type heavily doped substrate 400 and an independent P-type epitaxial layer 401 arranged from bottom to top. The bottom of the independent P-type heavily doped substrate 400 is electrically connected to the bottom of the N-type heavily doped substrate 200. The independent P-type epitaxial layer 401 contains a corresponding independent N+ heavily doped active region 402 and an independent P+ heavily doped Zener diode 403. The top of the independent N+ heavily doped active region 402 is flush with the upper surface of the independent P-type epitaxial layer 401. The N+ doped active region 402 is electrically connected to the first P+ heavily doped active region 203. The independent N+ heavily doped active region 402 and the independent P+ heavily doped Zener diode 403 form a PN junction. Adjusting the doping concentration of the independent P+ heavily doped Zener diode 403 can change the breakdown voltage of the low-voltage trigger unit 230. The independent P+ heavily doped Zener diode 403 is manufactured by ion implantation. The doping concentration of the independent P+ heavily doped Zener diode 403 is C2, and the value of C2 ranges from 10. 18 cm -3 ≤C1≤10 19 cm -3 In this embodiment, the advantage lies in the flexibility to select various "low-voltage trigger units 230" for encapsulation, resulting in greater design flexibility. Specifically, the "low-voltage trigger unit 230" in this embodiment uses a vertical Zener diode chip. The chip's upper surface has a "cathode port" connected to the N-type side of the Zener diode, i.e., the independent N+ heavily doped active region 402; while the lower surface has an "anode port" connected to the P-type side of the Zener diode, i.e., the independent P-type heavily doped substrate 400. On the other hand, for the main NPN transistor in this embodiment, an "internal port" needs to be reserved on the upper surface for encapsulation. The encapsulation steps of this embodiment are as follows: two chips are fixed to the same base island using conductive adhesive, and the cathode port of the Zener diode chip is short-circuited to the internal port of the main NPN transistor chip via wire bonding. Furthermore, the ground port of the main NPN transistor chip is connected to another base island via wire bonding, thus completing the encapsulation.

[0037] The manufacturing process of the unidirectional ultra-low voltage electrostatic protection device of the present invention is applicable to various common integrated circuit manufacturing processes, such as nanoscale complementary metal oxide semiconductor (CMOS) process, three-dimensional fin field-effect transistor (FinFET) or gate-all-around transistor (GAA) process, or silicon-on-insulator (SOI) process, etc.

[0038] As can be seen from the above, the present invention provides a unidirectional ultra-low voltage electrostatic discharge (ESD) protection device. By setting an N-type heavily doped substrate, a P-type epitaxial layer, a first P+ heavily doped active region, an N+ heavily doped active region, a second P+ heavily doped active region, and a low-voltage triggering unit within the low-capacitance ESD protection device, the low-voltage triggering unit can quickly forward bias and conduct the PN junction formed by the first P+ heavily doped active region and the N+ heavily doped active region, thereby conducting the NPN transistor to form a main current discharge path between the N-type heavily doped substrate and the P-type epitaxial layer. This enables effective ESD surge discharge and significantly reduces the turn-on voltage of the ESD protection device, achieving a minimum turn-on voltage of 3V. This effectively protects low-voltage chips and solves the problem of high trigger voltage and difficulty in effectively protecting low-voltage chips in existing vertical unidirectional NPN devices.

[0039] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A unidirectional ultra-low voltage electrostatic protection device, characterized by: The TVS main device includes an N-type heavily doped substrate and a P-type epitaxial layer arranged from bottom to top, the P-type epitaxial layer is provided with a first P+ heavily doped active region, an N+ heavily doped active region and a second P+ heavily doped active region, the top of the first P+ heavily doped active region, the top of the N+ heavily doped active region, the top of the second P+ heavily doped active region and the upper surface of the P-type epitaxial layer are flush, the first P+ heavily doped active region, the N+ heavily doped active region and the second P+ heavily doped active region cooperatively form an NPN-type triode, the lower surface of the N-type heavily doped substrate is connected with an I / O port one, the N+ heavily doped active region and the second P+ heavily doped active region are connected with an I / O port two, the low-voltage trigger unit is arranged between the I / O port one and the first P+ heavily doped active region, the low-voltage trigger unit can quickly forward bias the PN junction formed by the first P+ heavily doped active region and the N+ heavily doped active region, and then turn on the NPN-type triode to form a main current discharge path between the N-type heavily doped substrate and the P-type epitaxial layer.

2. The unidirectional ultra-low voltage electrostatic protection device of claim 1, wherein: The P-type epitaxial layer is further provided with an isolation deep trench, the isolation deep trench cooperates with the first P+ heavily doped active region, the N+ heavily doped active region and the second P+ heavily doped active region, the top of the isolation deep trench is flush with the upper surface of the P-type epitaxial layer, and the bottom of the isolation deep trench penetrates through the P-type epitaxial layer and extends into the N-type heavily doped substrate.

3. The unidirectional ultra-low voltage electrostatic protection device of claim 2, wherein: The low-voltage trigger unit is a Zener diode, a series of diodes, a series of field effect tubes with short-circuited drain and gate, or a series of bipolar junction transistors with short-circuited base and collector, and the structure of the low-voltage trigger unit includes horizontal distribution structure and vertical distribution structure.

4. The unidirectional ultra-low voltage electrostatic protection device of claim 3, wherein: When the I / O port one is a power port, the I / O port two is a ground port; when the I / O port one is a ground port, the I / O port two is a power port.

5. The unidirectional ultra-low voltage electrostatic protection device of claim 4, wherein: The filling material in the isolation deep trench is silicon dioxide, silicon nitride or High-K.

6. The unidirectional ultra-low voltage electrostatic protection device of claim 5, wherein: The low-voltage trigger unit is arranged in the N-type heavily doped substrate, and includes an integrated P+ heavily doped active region and an integrated N+ heavily doped Zener diode arranged from top to bottom, the bottom of the integrated P+ heavily doped active region is electrically connected with the top of the integrated N+ heavily doped Zener diode, the top of the integrated P+ heavily doped active region is electrically connected with the first P+ heavily doped active region, the integrated P+ heavily doped active region and the integrated N+ heavily doped Zener diode form a PN junction, adjusting the doping concentration of the integrated N+ heavily doped Zener diode can change the breakdown voltage of the low-voltage trigger unit, and the manufacturing method of the integrated N+ heavily doped Zener diode is ion implantation process.

7. The unidirectional ultra-low voltage electrostatic protection device of claim 6, wherein: The doping concentration of the integrated N+ heavily doped Zener diode is C1, and the value range of C1 is 10 18 cm -3 ≤C1≤10 19 cm -3 .

8. The unidirectional ultra-low voltage electrostatic protection device of claim 5, wherein: The low-voltage trigger unit comprises a first Zener P+ heavily doped active region, a Zener N+ heavily doped active region and a second Zener P+ heavily doped active region arranged in the P-type epitaxial layer, the top of the first Zener P+ heavily doped active region, the top of the Zener N+ heavily doped active region and the top of the second Zener P+ heavily doped active region are flush with the upper surface of the P-type epitaxial layer, the first Zener P+ heavily doped active region is electrically connected with the second Zener P+ heavily doped active region and the first P+ heavily doped active region, the top of the Zener N+ heavily doped active region is connected with the I / O port, the bottom of the Zener N+ heavily doped active region is provided with a matched P+ heavily doped Zener diode, the P+ heavily doped Zener diode and the Zener N+ heavily doped active region form a PN junction, the doping concentration of the P+ heavily doped Zener diode can change the breakdown voltage of the low-voltage trigger unit, the manufacturing method of the P+ heavily doped Zener diode is ion implantation process, the doping concentration of the P+ heavily doped Zener diode is C2, the value range of C2 is 10 18 cm -3 ≤C2≤10 19 cm -3 .

9. The unidirectional ultra-low voltage electrostatic protection device of claim 5, wherein: The low-voltage trigger unit comprises an independent P-type heavily doped substrate and an independent P-type epitaxial layer arranged from bottom to top, the bottom of the independent P-type heavily doped substrate is electrically connected with the bottom of the N-type heavily doped substrate, and the independent P-type epitaxial layer is provided with a matched independent N+ heavily doped active region and an independent P+ heavily doped Zener diode, the top of the independent N+ heavily doped active region is flush with the upper surface of the independent P-type epitaxial layer, the independent N+ heavily doped active region is electrically connected with the first P+ heavily doped active region, the independent N+ heavily doped active region and the independent P+ heavily doped Zener diode form a PN junction, the doping concentration of the independent P+ heavily doped Zener diode can change the breakdown voltage of the low-voltage trigger unit, the independent P+ heavily doped Zener diode is manufactured by ion implantation process, the doping concentration of the independent P+ heavily doped Zener diode is C3, the value range of C2 is 10 18 cm -3 ≤C3≤10 19 cm -3 .

10. The unidirectional ultra-low voltage electrostatic protection device, according to any one of claims 6-9, wherein: The TVS main device can be an avalanche diode, a field effect tube, an NPN bipolar junction transistor, a PNP bipolar junction transistor and a silicon controlled rectifier, and the structure of the TVS main device includes a horizontal distribution structure and a vertical distribution structure.

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