Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module. The preparation method comprises the following steps that a tunneling oxide layer, a p + doped amorphous silicon carbide layer and a p + doped amorphous silicon layer are sequentially arranged on the back face of a silicon substrate in the direction away from the silicon substrate; grooves which are distributed at intervals and penetrate through the p + doped amorphous silicon layer are formed in the p + doped amorphous silicon layer, then channels are formed in the junctions of the grooves and the p + doped amorphous silicon layer, the tunneling oxide layer is divided into a P region and an N region, the p + doped amorphous silicon carbide layer and the p + doped amorphous silicon layer are arranged on the P region, and the p + doped amorphous silicon carbide layer is arranged on the N region; performing crystallization treatment, so that the p + doped amorphous silicon carbide layer and the p + doped amorphous silicon layer on the P region are respectively converted into a p + doped polycrystalline silicon carbide layer and a p + doped polycrystalline silicon layer, and the p + doped amorphous silicon carbide layer on the N region is converted into an n + doped polycrystalline silicon carbide layer; and performing post-treatment to obtain the solar cell.

Description

[0001] This application claims priority to Chinese Patent Application 2024117170395 (filed on November 27, 2024, entitled "A Solar Cell and a Method for Preparing the Same and a Photovoltaic Module"). Technical Field

[0002] This invention belongs to the field of photovoltaic module manufacturing technology, specifically relating to a solar cell, its preparation method, and a photovoltaic module. Background Technology

[0003] Emitter-and-passivated (PERC) cells are currently the mainstream battery technology on the market. Mass-produced PERC cells can achieve an efficiency of approximately 23.5%, but increasing the efficiency to above 24% is quite challenging. Interlocking back contact (IBC) cells, due to the absence of shading on the front, can achieve efficiencies above 24.5%. With the addition of a passivation contact structure, the efficiency can exceed 26%. However, the fabrication process for IBC cells is complex, preventing its widespread mass production. Currently, the next generation of PERC battery technology is generally considered to be N-type tunneling oxide passivated contact (TOPCon) cells, heterojunction cells, and IBC cell technology. IBC cell technology can be stacked with TOPCon or heterojunction structures, such as to construct TBC back contact solar cells (TOPCon-IBC cells), combining the tunneling oxide passivation contact of TOPCon technology with the interlocking back contact structure of IBC technology, which can further improve battery efficiency. Current TBC battery technologies are mostly fabricated by deposition or printing masks plus wet etching or printing paste diffusion. However, wet etching is a complex process, and printing paste can cause pollution problems to some extent. The process is also complicated, making it difficult to improve battery efficiency.

[0004] Therefore, how to simplify the process while further improving the photoelectric conversion efficiency of solar cells is an urgent technical problem to be solved. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a solar cell, its fabrication method, and a photovoltaic module. The fabrication method provided by this invention features a simple process, a large process window, and strong mass production capability. During the crystallization process, the p+-doped amorphous layer on the P-region is transformed into a p+-doped polycrystalline layer, while the p+-doped amorphous silicon carbide layer on the N-region can be directly transformed into an n+-doped polycrystalline silicon carbide layer. This achieves the formation of n-type and p-type tunneling passivation contact structures in one step, reducing the impact of the primary environment on the tunneling oxide layer.

[0006] To achieve this objective, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a method for preparing a solar cell, the method comprising the following steps:

[0008] On the back side of the silicon substrate, a tunneling oxide layer, a p+-doped amorphous silicon carbide layer, and a p+-doped amorphous silicon layer are arranged sequentially in the direction away from the silicon substrate.

[0009] Grooves are formed on the p+ doped amorphous silicon layer, spaced apart and penetrating the p+ doped amorphous silicon layer. Then, a channel is formed at the junction of the grooves and the p+ doped amorphous silicon layer, dividing the tunneling oxide layer into P-regions and N-regions. The p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are arranged on the P-region, and the p+ doped amorphous silicon carbide layer is arranged on the N-region.

[0010] A crystallization process is performed, which transforms the p+-doped amorphous silicon carbide layer and the p+-doped amorphous silicon carbide layer located in the P region into a p+-doped polycrystalline silicon carbide layer and a p+-doped polycrystalline silicon carbide layer, respectively, and transforms the p+-doped amorphous silicon carbide layer in the N region into an n+-doped polycrystalline silicon carbide layer.

[0011] Post-processing is performed to obtain the solar cell.

[0012] The fabrication method provided by this invention is simple, has a large process window, and is highly producible. During the crystallization process, the p+-doped amorphous layer on the P-region is transformed into a p+-doped polycrystalline layer, while the p+-doped amorphous silicon carbide layer on the N-region can be directly transformed into an n+-doped polycrystalline silicon carbide layer. This allows for the one-step formation of n-type and p-type tunneling passivation contact structures, reducing the impact of the primary environment on the tunneling oxide layer. Furthermore, the fabrication method utilizes channel formation to isolate the P / N regions, preventing them from becoming conductive in subsequent processes. In addition, the solar cell fabricated using the method provided by this invention exhibits excellent photoelectric conversion efficiency.

[0013] Preferably, the methods for forming the tunneling oxide layer, the p+-doped amorphous silicon carbide layer, and the p+-doped amorphous silicon layer are each independently plasma-enhanced chemical vapor deposition.

[0014] Preferably, the tunneling oxide layer material comprises silicon oxide.

[0015] Preferably, the thickness of the tunneling oxide layer is 0.5nm-2.5nm, and more preferably 1nm-2.5nm.

[0016] Preferably, the dopant concentration in the p+-doped amorphous silicon carbide layer is 3 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 .

[0017] Preferably, the thickness of the p+ doped amorphous silicon carbide layer is 30nm-100nm.

[0018] Preferably, the dopant concentration in the p+-doped amorphous silicon layer is 3 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 .

[0019] Preferably, the thickness of the p+ doped amorphous silicon layer is 50nm-200nm.

[0020] Preferably, the method for forming the groove includes: forming a first mask layer on the outer surface of the p+ doped amorphous silicon layer, and sequentially performing patterned laser windowing and etching processes.

[0021] Preferably, the thickness of the first mask layer is 20nm-100nm.

[0022] Preferably, the laser used for patterned laser windowing includes an ultraviolet picosecond laser or a green picosecond laser.

[0023] Preferably, the etchant used for the etching process includes any one or a combination of at least two of KOH, NaOH, or TMAH.

[0024] Preferably, the width of the groove is 100μm-1000μm.

[0025] Preferably, the method for forming the trench includes: sequentially forming an n+ doped amorphous silicon layer and a second mask layer on one side surface of the silicon substrate where the groove is formed, and sequentially performing patterned laser windowing and etching processes.

[0026] Preferably, the thickness of the n+ doped amorphous silicon layer is 30nm-100nm.

[0027] Preferably, the material of the second mask layer includes silicon oxide.

[0028] Preferably, the thickness of the second mask layer is 10nm-50nm.

[0029] Preferably, the width of the channel is 10μm-60μm.

[0030] Preferably, the crystallization process includes sequential phosphorus diffusion and oxidation annealing processes.

[0031] Preferably, the temperature of the phosphorus diffusion is 800℃-900℃.

[0032] Preferably, the atmosphere for the oxidative annealing treatment is an oxygen-containing atmosphere.

[0033] Preferably, the temperature of the oxidation annealing treatment is 900℃-1000℃.

[0034] Preferably, the front side of the silicon substrate has a textured surface.

[0035] Preferably, after phosphorus diffusion, a phosphorus-dopated light doped layer is formed on the front side of the silicon substrate.

[0036] Preferably, the surface phosphorus concentration of the phosphorus-doped layer is 5 × 10⁻⁶. 17 cm -3 -5×10 20 cm -3 .

[0037] Preferably, the post-processing steps include:

[0038] A back passivation layer and a back antireflection layer are sequentially stacked on one side of the silicon substrate where the n+ doped polycrystalline silicon carbide layer is formed, and a front passivation layer and a front antireflection layer are sequentially stacked on the front side of the silicon substrate.

[0039] A first back metal electrode and a second back metal electrode are formed in the P region and the N region, respectively, such that one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer, such that one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer.

[0040] Preferably, the method for forming the back passivation layer and the front passivation layer includes thermal oxidation or atomic layer deposition.

[0041] Preferably, the method for forming the back antireflection layer and the front antireflection layer includes plasma-enhanced chemical vapor deposition.

[0042] Preferably, the materials of the back passivation layer and the front passivation layer include silicon oxide and / or aluminum oxide.

[0043] Preferably, the materials of the back antireflection layer and the front antireflection layer include any one or a combination of at least two of silicon nitride, silicon oxynitride, or silicon oxide.

[0044] Preferably, the thickness of the back passivation layer and the front passivation layer is 2nm-10nm.

[0045] Preferably, the thickness of the back antireflective layer and the front antireflective layer is 60nm-150nm.

[0046] Preferably, the steps of forming the first back metal electrode and the second back metal electrode include sequential metallization and sintering processes.

[0047] Preferably, the materials of the first back metal electrode and the second back metal electrode include silver and / or aluminum.

[0048] Preferably, after the sintering treatment, a photoinjection annealing step is also performed.

[0049] In a second aspect, the present invention provides a solar cell, which is prepared using the preparation method described in the first aspect.

[0050] Thirdly, the present invention provides a photovoltaic module, the photovoltaic module comprising the solar cell described in the second aspect.

[0051] Compared with the prior art, the present invention has the following beneficial effects:

[0052] (1) The preparation method provided by the present invention is simple, has a large process window, and is highly producible.

[0053] (2) In the preparation method provided by the present invention, the P / N region is isolated by forming a channel, which can prevent the P / N region from forming a conductive path in the subsequent process; in addition, the front and back passivation layers are formed for the undiffused areas of the interval, which effectively reduces the interface recombination and ensures the passivation effect.

[0054] (3) In the preparation method provided by the present invention, the P-type amorphous silicon carbide in contact with the n+ doped amorphous silicon layer can be directly transformed into the n+ doped polycrystalline silicon carbide layer during the oxidation annealing process, thereby forming the n-type and p-type tunneling passivation contact structure in one step, reducing the impact of the primary environment on the tunneling oxide layer.

[0055] (4) The solar cells prepared by the preparation method provided by the present invention have excellent photoelectric conversion efficiency. Attached Figure Description

[0056] Figure 1 This is a process flow diagram of the fabrication process of a solar cell provided in one embodiment of the present invention.

[0057] Figure 2 This is a schematic diagram of the battery structure after step (1) of the fabrication process of the solar cell provided in Embodiment 1 of the present invention.

[0058] Figure 3a This is a schematic diagram of the cell structure after patterned laser windowing in step (2) of the solar cell fabrication process provided in Embodiment 1 of the present invention.

[0059] Figure 3b This is a schematic diagram of the battery structure after step (2) of the fabrication process of the solar cell provided in Embodiment 1 of the present invention.

[0060] Figure 4This is a schematic diagram of the battery structure after step (3) of the fabrication process of the solar cell provided in Embodiment 1 of the present invention.

[0061] Figure 5a This is a schematic diagram of the cell structure after laser windowing in step (4) of the solar cell fabrication process provided in Embodiment 1 of the present invention.

[0062] Figure 5b This is a schematic diagram of the battery structure after step (4) of the fabrication process of the solar cell provided in Embodiment 1 of the present invention.

[0063] Figure 6 This is a schematic diagram of the battery structure after step (5) of the fabrication process of the solar cell provided in Embodiment 1 of the present invention.

[0064] Figure 7 This is a schematic diagram of the battery structure after step (6) of the fabrication process of the solar cell provided in Embodiment 1 of the present invention.

[0065] Figure 8a This is a schematic diagram of the surface-modified battery structure described in step (7) of the solar cell fabrication process provided in Embodiment 1 of the present invention.

[0066] Figure 8b This is a schematic diagram of the battery structure after step (7) of the fabrication process of the solar cell provided in Embodiment 1 of the present invention.

[0067] Among them, 1-n-type silicon wafer; 2-phosphorus light doped layer; 3-front passivation layer; 4-front antireflection layer; 5-tunneling oxide layer; 6'-p+ doped amorphous silicon carbide layer; 6-p+ doped polycrystalline silicon carbide layer; 7'-p+ doped amorphous silicon layer; 7-p+ doped polycrystalline silicon layer; 8'-n+ phosphorus doped amorphous silicon layer; 8-n+ doped polycrystalline silicon carbide layer; 9-back passivation layer; 10-back antireflection layer; 11-first back metal electrode; 12-second back metal electrode; 13-first mask layer; 14-second mask layer; 15-PSG layer. Detailed Implementation

[0068] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0069] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0070] In one embodiment, the present invention provides a method for fabricating a solar cell, the process flow diagram of which is shown below. Figure 1 As shown, the preparation method includes the following steps:

[0071] S101. A tunneling oxide layer, a p+-doped amorphous silicon carbide layer, and a p+-doped amorphous silicon layer are arranged sequentially on the back side of the silicon substrate in a direction away from the silicon substrate.

[0072] S102. Grooves are formed on the p+ doped amorphous silicon layer, spaced apart and penetrating the p+ doped amorphous silicon layer. Then, a channel is formed at the junction of the grooves and the p+ doped amorphous silicon layer to divide the tunneling oxide layer into a P region and an N region. The p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are arranged on the P region, and the p+ doped amorphous silicon carbide layer is arranged on the N region.

[0073] S103. Perform crystallization treatment, so that the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer located on the P region are transformed into a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer, respectively, and the p+ doped amorphous silicon carbide layer on the N region is transformed into an n+ doped polycrystalline silicon carbide layer.

[0074] S104. Perform post-processing to obtain the solar cell.

[0075] The fabrication method provided by this invention is simple, has a large process window, and is highly producible. During the crystallization process, the p+-doped amorphous layer on the P-region is transformed into a p+-doped polycrystalline layer, while the p+-doped amorphous silicon carbide layer on the N-region can be directly transformed into an n+-doped polycrystalline silicon carbide layer. This allows for the one-step formation of n-type and p-type tunneling passivation contact structures, reducing the impact of the primary environment on the tunneling oxide layer. Furthermore, the fabrication method utilizes channel formation to isolate the P / N regions, preventing them from becoming conductive in subsequent processes. In addition, the solar cell fabricated using the method provided by this invention exhibits excellent photoelectric conversion efficiency.

[0076] In some embodiments, the silicon substrate is an n-type silicon wafer. For example, the n-type silicon wafer is a double-sided polished n-type silicon wafer.

[0077] In some embodiments, the tunneling oxide layer, the p+-doped amorphous silicon carbide layer, and the p+-doped amorphous silicon layer are all formed by plasma-enhanced chemical vapor deposition (PECVD).

[0078] In some embodiments, the material of the tunneling oxide layer includes silicon oxide.

[0079] In some embodiments, the thickness of the tunneling oxide layer is 0.5nm-2.5nm, for example, it can be 0.5nm, 1nm, 1.5nm, 2nm or 2.5nm, preferably 1nm-2.5nm.

[0080] It should be noted that the doping element in the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer can be boron.

[0081] In some embodiments, the dopant concentration in the p+-doped amorphous silicon carbide layer is 3 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 For example, it could be 3×10 19 cm -3 5×10 19 cm -3 1×10 20 cm -3 3×10 20 cm -3 Or 5×10 20 cm -3 wait.

[0082] Furthermore, the thickness of the p+ doped amorphous silicon carbide layer is 30nm-100nm, for example, it can be 30nm, 50nm, 70nm or 90nm, etc.

[0083] Furthermore, the p+ doped amorphous silicon carbide layer is a single-layer film or at least two-layer films.

[0084] Preferably, the at least two layers comprise an intrinsic layer and a doped layer, wherein the doped layer comprises a lightly doped layer and / or a heavily doped layer.

[0085] Furthermore, the doping element concentration in the p+-doped amorphous silicon layer is 3 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 For example, it could be 3×10 19 cm-3 5×10 19 cm -3 1×10 20 cm -3 3×10 20 cm -3 Or 5×10 20 cm -3 wait.

[0086] Furthermore, the thickness of the p+ doped amorphous silicon layer is 50nm-200nm, for example, it can be 50nm, 100nm, 150nm or 200nm.

[0087] Furthermore, the method for forming the groove includes: forming a first mask layer on the outer surface of the p+ doped amorphous silicon layer, and sequentially performing patterned laser windowing and etching processes.

[0088] In this invention, when forming the grooves, a patterned laser window is used to remove the first mask layer above a portion of the p+ doped amorphous silicon layer, exposing the p+ doped amorphous silicon layer. Then, an etching process is used to remove the exposed p+ doped amorphous silicon layer, forming grooves that are spaced apart on the p+ doped amorphous silicon layer and penetrate the p+ doped amorphous silicon layer. After the grooves are formed, cleaning is performed, and the first mask layer that was not removed by the laser needs to be retained during cleaning.

[0089] Furthermore, the material of the first mask layer includes silicon oxide.

[0090] Furthermore, the thickness of the first mask layer is 20nm-100nm, for example, it can be 20nm, 40nm, 60nm, 80nm or 100nm.

[0091] Furthermore, the laser used for the patterned laser windowing includes an ultraviolet picosecond laser or a green picosecond laser.

[0092] Furthermore, the etchant used for the etching process includes any one or a combination of at least two of KOH, NaOH, or TMAH.

[0093] Furthermore, the width of the groove is 100μm-1000μm, for example, it can be 100μm, 300μm, 500μm, 700μm, 900μm or 1000μm.

[0094] Further, the method for forming the trench includes: sequentially forming an n+ doped amorphous silicon layer and a second mask layer on the surface of the silicon substrate on one side where the groove is formed, and then sequentially performing patterned laser windowing and etching processes. For example, the laser used in the patterned laser windowing process can be an ultraviolet picosecond laser or a green laser, etc., and the etching process can be wet etching, etc. It should be noted that the doping element in the n+ doped amorphous silicon layer can be phosphorus.

[0095] After forming the groove, an n+-doped amorphous silicon layer and a second mask layer are sequentially formed on the back side of the silicon substrate. The n+-doped amorphous silicon layer covers the surface of the first mask and the side of the groove, covers the side of the groove of the p+-doped amorphous silicon layer, and covers the surface of the groove of the p+-doped amorphous silicon carbide layer. That is, the n+-doped amorphous silicon layer covers the side of the groove, and the n+-doped amorphous silicon layer and the p+-doped amorphous silicon layer are in contact on the side of the groove. Then, a patterned laser is used to open a window to remove the second mask layer at the PN junction, specifically removing the n+-doped amorphous silicon layer and the p+-doped amorphous silicon layer at the groove. The side contact area and the second mask layer above it are then etched away. Finally, the layers at the patterned laser window are etched away to expose the tunneling oxide layer, forming a channel. One side of the channel is a P-region, which is equipped with the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer, the first mask layer, the n+ doped amorphous silicon layer, and the second mask layer. The other side is an N-region, which is equipped with the p+ doped amorphous silicon carbide layer, the n+ doped amorphous silicon layer, and the second mask layer, so that P / N are completely separated. Then, annealing is performed to prevent P / N from diffusing and forming a conductor during the annealing process, thus ensuring the passivation effect.

[0096] Furthermore, the doping concentration of the doping element in the n+ doped amorphous silicon layer is 4 × 10⁻⁶. 20 -2×10 21 cm -3 For example, it could be 4×10 20 cm -3 6×10 20 cm -3 8×10 20 cm -3 1×10 21 cm -3 Or 2×10 21 cm -3 wait.

[0097] In this invention, the n+-doped amorphous silicon layer in the N-region directly covers the p+-doped amorphous silicon carbide layer. Since the doping element concentration of the n+-doped amorphous silicon layer is higher than that of the p+-doped amorphous silicon carbide layer by an order of magnitude, during crystallization, due to the difference in doping element concentration, the high concentration of doping elements in the n+-doped amorphous silicon layer diffuses into the p+-doped amorphous silicon carbide layer. This causes the doping element concentration of the n+-doped amorphous silicon layer in the p+-doped amorphous silicon carbide layer to gradually increase, eventually making the doping element of the n+-doped amorphous silicon layer dominant in the p+-doped amorphous silicon carbide layer. This results in the formation of an n+-doped polycrystalline silicon carbide layer from the p+-doped amorphous silicon carbide layer, thus enabling the formation of n-type and p-type tunneling passivation contact structures in one step.

[0098] Furthermore, the thickness of the n+ doped amorphous silicon layer is 30nm-100nm, for example, it can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm, etc.

[0099] Furthermore, the n+ doped amorphous silicon layer is a single-layer film or at least two-layer films.

[0100] Furthermore, the at least two layers of film include an intrinsic layer and a doped layer, wherein the doped layer includes a lightly doped layer and / or a heavily doped layer.

[0101] Furthermore, the growth method of the n+ doped amorphous silicon layer is PECVD.

[0102] Furthermore, the material of the second mask layer includes silicon oxide.

[0103] Furthermore, the thickness of the second mask layer is 10nm-50nm, for example, it can be 10nm, 20nm, 30nm, 40nm or 50nm, etc.

[0104] Furthermore, the width of the channel is 10μm-60μm, for example, it can be 10μm, 20μm, 30μm, 40μm, 50μm or 60μm, etc.

[0105] Furthermore, the crystallization process includes sequential phosphorus diffusion and oxidation annealing treatments.

[0106] In this invention, the crystallization process begins with phosphorus diffusion. Since the doping element of the n+ doped amorphous silicon layer can be phosphorus, the p+ doped amorphous silicon carbide layer forms an n+ doped polycrystalline silicon carbide layer under the diffusion effect of phosphorus diffusion and the phosphorus doping element in the n+ doped amorphous silicon layer. After phosphorus diffusion and oxidation annealing, the n+ doped amorphous silicon layer forms a PSG layer. After crystallization, the PSG layer is removed (when removing the PSG layer, the film layer in the channel is completely etched, and even part of the silicon substrate in the channel itself is etched away. Therefore, after removing the PSG layer, the silicon substrate in the channel is thinner than the silicon substrate in other locations), forming an n-type and p-type tunneling passivation contact structure.

[0107] Furthermore, the phosphorus source used in the phosphorus expansion process includes phosphorus oxychloride.

[0108] Furthermore, the temperature of the phosphorus diffusion is 800℃-900℃, for example, it can be 800℃, 820℃, 840℃, 860℃, 880℃ or 900℃, etc.

[0109] Furthermore, the atmosphere for the oxidation annealing treatment is an oxygen-containing atmosphere.

[0110] Furthermore, the gas in the oxygen-containing atmosphere includes oxygen and an inert gas. For example, the inert gas may be nitrogen.

[0111] Furthermore, the oxidation annealing temperature is 900℃-1000℃, for example, it can be 900℃, 920℃, 940℃, 960℃, 980℃, or 1000℃. In this invention, if the oxidation annealing temperature is too low, the activation will be insufficient, the doping amount will be too low, the contact will be poor, and the passivation will be poor; if the oxidation annealing temperature is too high, the doping amount will be too high, leading to the destruction of the tunneling layer.

[0112] Furthermore, the front side of the silicon substrate has a textured surface.

[0113] Furthermore, after phosphorus diffusion, a phosphorus-dopated light doped layer is formed on the front side of the silicon substrate.

[0114] Furthermore, the surface phosphorus concentration of the phosphorus-doped layer is 5 × 10⁻⁶. 17 cm -3 -5×10 20 cm -3 For example, it could be 5×10 17 cm -3 5×10 18 cm -3 5×10 19 cm -3 Or 5×10 20 cm -3 Etc., preferably 1×10 18 -1×1020 cm -3 wait.

[0115] Furthermore, the post-processing steps include:

[0116] A back passivation layer and a back antireflection layer are sequentially stacked on one side of the silicon substrate where the n+ doped polycrystalline silicon carbide layer is formed, and a front passivation layer and a front antireflection layer are sequentially stacked on the front side of the silicon substrate.

[0117] A first back metal electrode and a second back metal electrode are formed in the P region and the N region, respectively, such that one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer, such that one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer.

[0118] This invention targets the non-diffused regions to form passivation through thermal oxidation, while thermal oxidation is performed on both the front and back sides of the silicon substrate, effectively reducing interfacial recombination.

[0119] Furthermore, the methods for forming the back passivation layer and the front passivation layer include thermal oxidation or atomic layer deposition (ALD).

[0120] Furthermore, the method for forming the back antireflection layer and the front antireflection layer includes plasma-enhanced chemical vapor deposition.

[0121] Furthermore, the materials of the back passivation layer and the front passivation layer include silicon oxide and / or aluminum oxide.

[0122] Furthermore, the materials of the back antireflection layer and the front antireflection layer include any one or a combination of at least two of silicon nitride, silicon oxynitride, or silicon oxide.

[0123] Furthermore, the thickness of the back passivation layer and the front passivation layer is 2nm-10nm, for example, it can be 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm, etc.

[0124] Furthermore, the thickness of the back antireflection layer and the front antireflection layer is 60nm-150nm, for example, it can be 60nm, 80nm, 100nm, 110nm, 130nm or 150nm, etc., preferably 60-100nm.

[0125] Furthermore, the steps of forming the first back metal electrode and the second back metal electrode include sequential metallization and sintering processes.

[0126] Furthermore, the metallization process includes any one of screen printing, laser transfer, or electroplating.

[0127] Furthermore, the peak temperature of the sintering treatment is 650-750℃, for example, it can be 650℃, 700℃ or 750℃, etc.

[0128] Furthermore, the materials of the first back metal electrode and the second back metal electrode include silver and / or aluminum.

[0129] Furthermore, after the sintering process, a photoinjection annealing step is performed.

[0130] In another embodiment, the present invention provides a solar cell prepared by the preparation method described above.

[0131] The solar cell includes a silicon substrate. A tunneling oxide layer is discontinuously distributed on the back side of the silicon substrate along a direction away from the silicon substrate. The tunneling oxide layer is divided into several P regions and several N regions, and the P regions and N regions are arranged alternately. A p+ doped layer is disposed on the several P regions. The p+ doped layer includes a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer along a direction away from the tunneling oxide layer. An n+ doped polycrystalline silicon carbide layer is disposed on the several N regions along a direction away from the tunneling oxide layer.

[0132] A back passivation layer and a back antireflection layer are provided on the side surface of the p+ doped polycrystalline silicon layer away from the tunneling oxide layer and on the side surface of the n+ doped polycrystalline silicon carbide layer away from the tunneling oxide layer.

[0133] A first groove is partially formed in the back passivation layer and the back antireflection layer disposed on the p+ doped polysilicon layer. A first back metal electrode is disposed in the first groove, and one end of the first back metal electrode forms an ohmic contact with the p+ doped polysilicon layer, while the other end extends out of the back antireflection layer. A second groove is partially formed in the back passivation layer and the back antireflection layer disposed on the n+ doped polysilicon carbide layer. A second back metal electrode is disposed in the second groove, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polysilicon carbide layer, while the other end extends out of the back antireflection layer.

[0134] For example, the solar cell is a TBC back-contact solar cell.

[0135] Preferably, the front side of the silicon substrate is provided with a phosphorus light doping layer, a front passivation layer and a front antireflection layer in sequence along the direction away from the silicon substrate.

[0136] Preferably, the front side of the silicon substrate has a textured surface.

[0137] Preferably, the silicon substrate is an n-type silicon wafer.

[0138] Preferably, the resistivity of the n-type silicon wafer is 0.3Ω·cm-7Ω·cm, for example, it can be 0.3Ω·cm, 0.5Ω·cm, 1Ω·cm, 2Ω·cm, 3Ω·cm, 4Ω·cm, 5Ω·cm, 6Ω·cm or 7Ω·cm, etc., and preferably 0.5-3.5Ω·cm.

[0139] Preferably, the diffusion sheet resistance of the phosphorus light doped layer is 200Ω / sq-500Ω / sq, for example, it can be 200Ω / sq, 300Ω / sq, 400Ω / sq or 500Ω / sq.

[0140] In another embodiment, the present invention provides a photovoltaic module comprising the solar cells described above.

[0141] The numerical range described in this invention includes not only the point values ​​listed above, but also any point values ​​within the numerical ranges not listed above. Due to space limitations and for the sake of brevity, this invention will not exhaustively list all the specific point values ​​included in the range.

[0142] Example 1

[0143] like Figure 2 As shown in Figure 8, this embodiment provides a method for fabricating a solar cell, the method comprising the following steps:

[0144] (1) Growth of p+ doped layer: An n-type silicon wafer 1 with a resistivity of 1.5 Ω·cm is subjected to alkaline polishing to remove the mechanical damage layers on both sides. Then, it is cleaned using the RCA cleaning method. Subsequently, a non-discontinuous tunneling oxide layer 5, a p+ doped amorphous silicon carbide layer 6', a p+ doped amorphous silicon layer 7', and a first mask layer 13 are sequentially grown on the back side of the n-type silicon wafer 1 using the PECVD method. Figure 2 As shown.

[0145] The p+-doped amorphous silicon carbide layer and the p+-doped amorphous silicon layer are collectively referred to as the p+-doped layer; the uninterrupted tunneling oxide layer is made of silicon oxide and has a thickness of 1.5 nm; the dopant element in the uninterrupted p+-doped amorphous silicon carbide layer is boron, with a doping concentration of 1 × 10⁻⁶. 20 cm -3 The silicon carbide layer has a thickness of 60 nm, consisting of a 20 nm thick intrinsic amorphous silicon carbide layer and a 40 nm thick p-type lightly doped amorphous silicon carbide layer; the uninterrupted p+ doped amorphous silicon carbide layer is doped with boron at a doping concentration of 1 × 10⁻⁶. 20 cm -3 The total thickness is 120nm; the first mask layer 13 is made of silicon oxide and has a thickness of 40nm.

[0146] (2) Grooving: The first mask layer 13 is patterned and laser-windowed using an ultraviolet picosecond laser to expose the p+-doped amorphous silicon layer 7'. The battery structure after patterning and laser-windowing is shown in the figure. Figure 3a As shown, the laser-windowed area is etched using KOH to remove the p+-doped amorphous silicon layer 7', exposing the p+-doped amorphous silicon carbide layer 6', forming spaced grooves with a width of 600 μm. The battery structure obtained after step (2) is shown in the figure. Figure 3b As shown.

[0147] (3) Growth of n+ doped layer: Using PECVD, an n+ phosphorus doped amorphous silicon layer 8' with a thickness of 50 nm and a second mask layer 14 with a thickness of 20 nm are grown sequentially on the surface of the first mask layer 13 after step (1), the surface of the p+ doped amorphous silicon carbide layer 6' in the groove, and the side of the groove. The battery structure obtained after step (3) is shown in the figure. Figure 4 As shown.

[0148] The second mask layer 14 is made of silicon oxide; the n+ phosphorus-doped amorphous silicon layer 8' is doped with phosphorus at a concentration of 1×10⁻⁶. 21 cm -3 .

[0149] (4) Setting up trenches and texturing: Laser windowing of the second mask layer 14 is performed on the side and top of the P / N region junction using a 532nm wavelength laser. The battery structure diagram after laser windowing of the second mask layer 14 is shown in the figure. Figure 5a As shown, the n+ phosphorus-doped amorphous silicon layer 8' and the p+ doped amorphous silicon carbide layer 6' at the laser window are wet-etched to form a 30μm wide channel to disconnect and isolate the P / N region. At the same time, the front side of the n-type silicon wafer 1 is texturized and cleaned. The battery structure obtained after step (4) is shown in the figure. Figure 5b As shown.

[0150] The channel has a P-region on one side, which contains the p+ doped amorphous silicon carbide layer 6', p+ doped amorphous silicon layer 7', first mask layer 13, n+ doped amorphous silicon layer 8', and second mask layer 14. The channel also has an N-region on the other side, which contains the p+ doped amorphous silicon carbide layer 6', n+ doped amorphous silicon layer 8', and second mask layer 14.

[0151] (5) Crystallization treatment: At 840℃, phosphorus oxychloride is used as the phosphorus source to perform phosphorus diffusion on the n-type silicon wafer 1 after texturing in step (2), thereby forming a phosphorus-dopated lightly doped layer 2 on the front side. Then, oxidation annealing treatment is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is gradient annealing, including a first-stage annealing at 910℃ and a second-stage annealing at 940℃, so that the p+ doped amorphous silicon carbide layer 6' and p+ doped amorphous silicon layer 7' in the P-region on the back side are crystallized. The n+ phosphorus-doped amorphous silicon layer 8' is transformed into a p+ doped polycrystalline silicon carbide layer 6, a p+ doped polycrystalline silicon layer 7, and a PSG layer 15, respectively. Simultaneously, the p+ doped amorphous silicon carbide layer 6', which is connected to the n+ phosphorus-doped amorphous silicon carbide layer 8' in the N region, is transformed into an n+ doped polycrystalline silicon carbide layer 8. Furthermore, the first mask layer 13 and the second mask layer 14 are also transformed into PSG layers 15, and a PSG layer 15 is also formed on the surface of the front phosphorus-doped light layer 2. The battery structure obtained after step (5) is shown in the figure. Figure 6 As shown;

[0152] The phosphorus concentration on the surface of phosphorus-doped layer 2 is 1×10⁻⁶. 19 cm -3 .

[0153] (6) PSG layer removal: The PSG layers 15 on the front and back sides are removed using hydrofluoric acid. Part of the n-type silicon wafer in the trench is also removed. Then, RCA cleaning is performed. The battery structure diagram obtained after step (6) is shown below. Figure 7 As shown, the P region has p+ doped polycrystalline silicon carbide layer 6 and p+ doped polycrystalline silicon carbide layer 7 arranged therein, and the N region has n+ doped polycrystalline silicon carbide layer 8 arranged therein.

[0154] (7) Surface modification and electrode fabrication: A front passivation layer 3 and a back passivation layer 9, with a thickness of 3.5 nm and made of silicon oxide, were grown on the front and back sides of the n-type silicon wafer 1 after the treatment in step (6) using a thermal oxidation method. Subsequently, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer were sequentially grown on the passivation layers on the front and back sides of the n-type silicon wafer 1 using a PECVD method as the front antireflection layer 4 and the back antireflection layer 10, respectively. A schematic diagram of the battery structure obtained after surface modification is shown below. Figure 8a As shown.

[0155] Then, silver paste is printed on the N-region and P-region of the back side of the n-type silicon wafer 1 by screen printing to form patterned metal electrodes. The metal electrodes are then subjected to contact treatment at 750°C to obtain the first back metal electrode 11 and the second back metal electrode 12. One end of the first back metal electrode 11 forms an ohmic contact with the p+ doped polycrystalline silicon layer 7, and one end of the second back metal electrode 12 forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer 8. Then, a photo-injection annealing method is used for post-processing to finally obtain the solar cell.

[0156] This embodiment provides a solar cell, the structural schematic diagram of which is shown below. Figure 8b As shown, the solar cell includes an n-type silicon wafer 1. A tunneling oxide layer 5 is discontinuously distributed on the back side of the n-type silicon wafer 1 along the direction away from the n-type silicon wafer 1. The tunneling oxide layer 5 is divided into several P regions and several N regions, and the P regions and N regions are arranged alternately. A p+ doped layer is disposed on the several P regions. The p+ doped layer includes a p+ doped polycrystalline silicon carbide layer 6 and a p+ doped polycrystalline silicon layer 7 along the direction away from the tunneling oxide layer 5. An n+ doped polycrystalline silicon carbide layer 8 is disposed on the several N regions along the direction away from the tunneling oxide layer 5.

[0157] The doping element in the n+-doped polycrystalline silicon carbide layer 8 includes phosphorus, with a doping concentration of 1×10⁻⁶. 21 cm -3 The thickness is 60nm, and the n+ doped polycrystalline silicon carbide layer 8 has the same thickness as the p+ doped polycrystalline silicon carbide layer 6.

[0158] A back passivation layer 9 and a back antireflection layer 10 are provided on the surface of the p+ doped polysilicon layer 7 away from the tunneling oxide layer 5, the discontinuity region (i.e., the channel) between the P-region tunneling oxide layer and the N-region tunneling oxide layer, and the surface of the n+ doped polysilicon carbide layer 8 away from the tunneling oxide layer 5. The back passivation layer 9 is made of silicon oxide and has a thickness of 3.5 nm. The back antireflection layer 10 includes a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer and has a thickness of 100 nm.

[0159] A first groove is partially formed in the back passivation layer 9 and the back antireflection layer 10 disposed on the p+ doped polysilicon layer 7. A first back metal electrode 11 is disposed in the first groove, and one end of the first back metal electrode 11 forms an ohmic contact with the p+ doped polysilicon layer 7, while the other end extends out of the back antireflection layer 10. A second groove is partially formed in the back passivation layer 9 and the back antireflection layer 10 disposed on the n+ doped polysilicon carbide layer 8. A second back metal electrode 12 is disposed in the second groove, and one end of the second back metal electrode 12 forms an ohmic contact with the n+ doped polysilicon carbide layer 8, while the other end extends out of the back antireflection layer 10. The material of the first back metal electrode 11 is silver, and the material of the second back metal electrode 12 is silver.

[0160] The front side of the n-type silicon wafer 1 has a textured structure. Along the direction away from the n-type silicon wafer 1, a phosphorus light doping layer 2, a front passivation layer 3, and a front antireflection layer 4 are sequentially disposed on the front side. Among them, the diffusion sheet resistance of the phosphorus light doping layer 2 is 400Ω / sq, and the junction depth is 100nm. The front antireflection layer 4 includes a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 80nm.

[0161] Example 2

[0162] This embodiment provides a method for preparing a solar cell, the method comprising the following steps:

[0163] (1) An n-type silicon wafer with a resistivity of 1 Ω·cm is subjected to alkaline polishing to remove the mechanical damage layers on the front and back sides. Then, it is cleaned by RCA cleaning. Subsequently, a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer are grown sequentially on the back side of the n-type silicon wafer by PECVD.

[0164] The tunneling oxide layer is made of silicon oxide and has a thickness of 0.5 nm; the p+ doped amorphous silicon carbide layer is doped with boron and has a doping concentration of 3 × 10⁻⁶. 19 cm -3 The thickness is 30 nm; the dopant element in the p+ doped polysilicon layer is boron, and the doping concentration is 3 × 10⁻⁶. 19 cm -3 The thickness of the first mask layer is 50nm; the material of the first mask layer is silicon oxide, with a thickness of 20nm.

[0165] (2) The first mask layer is patterned by using an ultraviolet picosecond laser to open a window, exposing the p+ doped amorphous silicon layer. The laser-opened area is then etched with KOH to remove the p+ doped amorphous silicon layer and expose the p+ doped amorphous silicon carbide layer, forming a groove with an interval distribution. The width of the groove is 100 μm.

[0166] (3) Using the PECVD method, an n+ phosphorus-doped amorphous silicon layer with a thickness of 30 nm and a second mask layer with a thickness of 10 nm are sequentially grown on the surface of the first mask layer after the treatment in step (1), the surface of the p+ doped amorphous silicon carbide layer in the groove, and the side of the groove.

[0167] The second mask layer is made of silicon oxide; the n+ phosphorus-doped amorphous silicon layer is doped with phosphorus at a concentration of 4 × 10⁻⁶. 20 cm -3 .

[0168] (4) A 532nm wave laser is used to open a window on the second mask layer at the junction of the P / N region and on the side and above. The n+ phosphorus-doped amorphous silicon layer and the p+ doped amorphous silicon carbide layer at the laser window are wet etched to form a 10μm wide channel to disconnect and isolate the P / N region. At the same time, the front side of the n-type silicon wafer is texturized and cleaned.

[0169] The channel is located on one side as a P-region, which contains a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer, a first mask layer, an n+ doped amorphous silicon layer, and a second mask layer. The channel is located on the other side as an N-region, which contains a p+ doped amorphous silicon carbide layer, an n+ doped amorphous silicon layer, and a second mask layer.

[0170] (5) At 800°C, phosphorus oxychloride is used as the phosphorus source to perform phosphorus diffusion on the n-type silicon wafer after texturing in step (2), thereby forming a phosphorus diffusion light doped layer on the front side. Then, oxidation annealing is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is gradient annealing, including a first-stage annealing at 900°C and a second-stage annealing at 970°C, so that the p+ doped amorphous silicon carbide layer, p+ doped amorphous silicon layer and n+ phosphorus doped amorphous silicon layer in the P region on the back side are transformed into p+ doped polycrystalline silicon carbide layer, p+ doped polycrystalline silicon layer and PSG layer, respectively. At the same time, the p+ doped amorphous silicon carbide layer in the N region connected to the n+ phosphorus doped amorphous silicon layer is transformed into an n+ doped polycrystalline silicon carbide layer. In addition, the first mask layer and the second mask layer are also transformed into PSG layers, and a PSG layer is also formed on the surface of the phosphorus diffusion light doped layer on the front side.

[0171] The phosphorus concentration on the surface of the phosphorus-doped layer is 5 × 10⁻⁶. 17 cm -3 .

[0172] (6) The PSG layers on the front and back sides are removed by using hydrofluoric acid. Some n-type silicon wafers in the channel are also removed. Then, the RCA cleaning method is used for cleaning. At this time, the P region is arranged with p+ doped polycrystalline silicon carbide layer and p+ doped polycrystalline silicon layer, and the N region is arranged with n+ doped polycrystalline silicon carbide layer.

[0173] (7) A passivation layer with a thickness of 2 nm and made of silicon oxide is grown on the front and back sides of the n-type silicon wafer after the treatment in step (4) by thermal oxidation method. Then, a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer are grown on the passivation layer on the front and back sides of the n-type silicon wafer by PECVD method as anti-reflection layers.

[0174] Then, silver paste is printed on the N-region and silver-aluminum paste is printed on the P-region of the back of the n-type silicon wafer after the treatment in step (5) by screen printing to form patterned metal electrodes. Then, the metal electrodes are subjected to contact treatment at 730°C to obtain the first back metal electrode and the second back metal electrode. One end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer. Then, the solar cell is finally obtained by photo-injection annealing.

[0175] This embodiment provides a solar cell, which includes an n-type silicon wafer. A discontinuously distributed tunneling oxide layer is disposed on the back side of the n-type silicon wafer along a direction away from the n-type silicon wafer. The tunneling oxide layer is divided into several P-regions and several N-regions, which are arranged alternately. A p+ doped layer is disposed on each of the several P-regions. The p+ doped layer includes a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer along a direction away from the tunneling oxide layer. An n+ doped polycrystalline silicon carbide layer is disposed on each of the several N-regions along a direction away from the tunneling oxide layer.

[0176] The doping element in the n+-doped polycrystalline silicon carbide layer includes phosphorus, with a doping concentration of 4 × 10⁻⁶. 20 cm -3 The thickness is 30nm, and the n+ doped polycrystalline silicon carbide layer has the same thickness as the p+ doped polycrystalline silicon carbide layer.

[0177] A back passivation layer and a back antireflection layer are provided on the surface of the p+ doped polycrystalline silicon layer away from the tunneling oxide layer, the discontinuity region (i.e., the channel) between the P-region tunneling oxide layer and the N-region tunneling oxide layer, and the surface of the n+ doped polycrystalline silicon carbide layer away from the tunneling oxide layer. The back passivation layer is made of aluminum oxide and has a thickness of 2 nm. The back antireflection layer includes a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer and has a thickness of 60 nm.

[0178] A first groove is partially formed in the back passivation layer and the back antireflection layer disposed on the p+ doped polycrystalline silicon layer. A first back metal electrode is disposed in the first groove, and one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, while the other end extends out of the back antireflection layer. A second groove is partially formed in the back passivation layer and the back antireflection layer disposed on the n+ doped polycrystalline silicon carbide layer. A second back metal electrode is disposed in the second groove, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, while the other end extends out of the back antireflection layer. The material of the first back metal electrode is silver, and the material of the second back metal electrode is silver.

[0179] The front side of the n-type silicon wafer has a textured structure. Along the direction away from the n-type silicon wafer, a phosphorus light doping layer, a front passivation layer, and a front antireflection layer are sequentially arranged on the front side. The diffusion sheet resistance of the phosphorus light doping layer is 500 Ω / sq. The front antireflection layer includes a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 60 nm.

[0180] Example 3

[0181] This embodiment provides a method for preparing a solar cell, the method comprising the following steps:

[0182] (1) An n-type silicon wafer with a resistivity of 2 Ω·cm is subjected to alkaline polishing to remove the mechanical damage layers on the front and back sides. Then, it is cleaned by RCA cleaning. Subsequently, a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer are grown sequentially on the back side of the n-type silicon wafer by PECVD.

[0183] The tunneling oxide layer is made of silicon oxide and has a thickness of 3 nm; the p+ doped amorphous silicon carbide layer is doped with boron and has a doping concentration of 5 × 10⁻⁶. 20 cm -3 The thickness is 100 nm; the dopant element in the p+ doped polysilicon layer is boron, and the doping concentration is 5 × 10⁻⁶. 20 cm -3 The thickness of the first mask layer is 200nm; the material of the first mask layer is silicon oxide, with a thickness of 100nm.

[0184] (2) The first mask layer is patterned by ultraviolet picosecond laser to expose the p+ doped amorphous silicon layer, and the laser windowed area is etched by KOH to remove the first mask layer and the p+ doped amorphous silicon layer in the laser windowed area, exposing the p+ doped amorphous silicon carbide layer, forming a groove with an interval distribution, the width of which is 1000μm.

[0185] (3) Using the PECVD method, an n+ phosphorus-doped amorphous silicon layer with a thickness of 100 nm and a second mask layer with a thickness of 50 nm are sequentially grown on the surface of the first mask layer after the treatment in step (1), the surface of the p+ doped amorphous silicon carbide layer in the groove, and the side of the groove.

[0186] The second mask layer is made of silicon oxide; the n+ phosphorus-doped amorphous silicon layer is doped with phosphorus at a concentration of 2 × 10⁻⁶. 21 cm -3 .

[0187] (4) Laser windowing is performed on the side and top of the P / N region junction using a 532nm wave laser, and wet etching is performed on the n+ phosphorus-doped amorphous silicon layer and p+ doped amorphous silicon carbide layer at the laser window to form a 60μm wide channel to disconnect and isolate the P / N region. At the same time, the front side of the n-type silicon wafer is texturized and cleaned.

[0188] The channel is located on one side as a P-region, which contains a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer, a first mask layer, an n+ doped amorphous silicon layer, and a second mask layer. The channel is located on the other side as an N-region, which contains a p+ doped amorphous silicon carbide layer, an n+ doped amorphous silicon layer, and a second mask layer.

[0189] (5) At 900°C, phosphorus oxychloride is used as the phosphorus source to perform phosphorus diffusion on the n-type silicon wafer after texturing in step (2), thereby forming a phosphorus diffusion light doped layer on the front side. Then, oxidation annealing is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is gradient annealing, including a first-stage annealing at 930°C and a second-stage annealing at 1000°C, so that the p+ doped amorphous silicon carbide layer, p+ doped amorphous silicon layer and n+ phosphorus doped amorphous silicon layer in the P region on the back side are transformed into p+ doped polycrystalline silicon carbide layer, p+ doped polycrystalline silicon layer and PSG layer, respectively. At the same time, the p+ doped amorphous silicon carbide layer in the N region connected to the n+ phosphorus doped amorphous silicon layer is transformed into an n+ doped polycrystalline silicon carbide layer. In addition, the first mask layer and the second mask layer are also transformed into PSG layers, and a PSG layer is also formed on the surface of the phosphorus diffusion light doped layer on the front side.

[0190] The phosphorus concentration on the surface of the phosphorus-doped layer is 5 × 10⁻⁶. 20 cm -3 .

[0191] (6) The PSG layers on the front and back sides are removed by using hydrofluoric acid. Some n-type silicon wafers in the channel are also removed. Then, the RCA cleaning method is used to remove the first mask layer. At this time, the P region is arranged with p+ doped polycrystalline silicon carbide layer and p+ doped polycrystalline silicon layer, and the N region is arranged with n+ doped polycrystalline silicon carbide layer.

[0192] (7) A passivation layer with a thickness of 10 nm and made of silicon oxide is grown on the front and back sides of the n-type silicon wafer after the treatment in step (4) by thermal oxidation method. Then, a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer are grown on the passivation layer on the front and back sides of the n-type silicon wafer by PECVD method as anti-reflection layers.

[0193] Then, silver paste is printed on the N-region and silver-aluminum paste is printed on the P-region of the back of the n-type silicon wafer after the treatment in step (5) by screen printing to form patterned metal electrodes. Then, the metal electrodes are subjected to contact treatment at 520°C to obtain the first back metal electrode and the second back metal electrode. One end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer. Then, the TBC back contact solar cell is finally obtained by photo-injection annealing.

[0194] This embodiment provides a solar cell, which includes an n-type silicon wafer. A tunneling oxide layer is discontinuously distributed on the back side of the n-type silicon wafer along a direction away from the n-type silicon wafer. The tunneling oxide layer is divided into several P-regions and several N-regions, which are arranged alternately. A p+ doped layer is disposed on each of the P-regions, and the p+ doped layer includes a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer along a direction away from the tunneling oxide layer. An n+ doped polycrystalline silicon carbide layer is disposed on each of the N-regions along a direction away from the tunneling oxide layer.

[0195] The doping element in the n+-doped polycrystalline silicon carbide layer includes phosphorus, with a doping concentration of 2 × 10⁻⁶. 21 cm -3 The thickness is 100nm; the n+ doped polycrystalline silicon carbide layer and the p+ doped polycrystalline silicon carbide layer have the same thickness.

[0196] A back passivation layer and a back antireflection layer are provided on the surface of the p+ doped polysilicon layer away from the tunneling oxide layer, the discontinuity region (i.e., the channel) between the P-region tunneling oxide layer and the N-region tunneling oxide layer, and the surface of the n+ doped polysilicon carbide layer away from the tunneling oxide layer. The back passivation layer is made of silicon oxide and has a thickness of 10 nm. The back antireflection layer includes a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer and has a thickness of 90 nm.

[0197] A first groove is partially formed in the back passivation layer and the back antireflection layer disposed on the p+ doped polycrystalline silicon layer. A first back metal electrode is disposed in the first groove, and one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, while the other end extends out of the back antireflection layer. A second groove is partially formed in the back passivation layer and the back antireflection layer disposed on the n+ doped polycrystalline silicon carbide layer. A second back metal electrode is disposed in the second groove, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, while the other end extends out of the back antireflection layer. The material of the first back metal electrode is silver, and the material of the second back metal electrode is silver.

[0198] The front side of the n-type silicon wafer has a textured structure. Along the direction away from the n-type silicon wafer, a phosphorus light-doped layer, a front passivation layer, and a front anti-reflection layer are sequentially arranged on the front side. The diffusion sheet resistance of the phosphorus light-doped layer is 200 Ω / sq. The back anti-reflection layer includes a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness of 90 nm.

[0199] Example 4

[0200] The difference between this embodiment and Embodiment 1 is that the thickness of the tunneling oxide layer is 5 nm.

[0201] The remaining preparation methods and parameters are consistent with those in Example 1.

[0202] Example 5

[0203] The difference between this embodiment and Embodiment 1 is that the total thickness of the p+ doped polycrystalline silicon carbide layer is 20 nm.

[0204] The remaining preparation methods and parameters are consistent with those in Example 1.

[0205] Example 6

[0206] The difference between this embodiment and Embodiment 1 is that the total thickness of the p+ doped polycrystalline silicon carbide layer is 120 nm.

[0207] The remaining preparation methods and parameters are consistent with those in Example 1.

[0208] Example 7

[0209] The difference between this embodiment and Embodiment 1 is that the thickness of the p+ doped polycrystalline silicon layer is 30 nm.

[0210] The remaining preparation methods and parameters are consistent with those in Example 1.

[0211] Example 8

[0212] The difference between this embodiment and Embodiment 1 is that the thickness of the p+ doped polysilicon layer is 220 nm.

[0213] The remaining preparation methods and parameters are consistent with those in Example 1.

[0214] Example 9

[0215] The difference between this embodiment and embodiment 1 is that the temperature of the oxidation annealing treatment in step (5) is 800°C.

[0216] The remaining preparation methods and parameters are consistent with those in Example 1.

[0217] Example 10

[0218] The difference between this embodiment and embodiment 1 is that the temperature of the oxidation annealing treatment in step (5) is 1200℃.

[0219] The remaining preparation methods and parameters are consistent with those in Example 1.

[0220] Comparative Example 1

[0221] The difference between this comparative example and Example 1 is that the growth of the p+ doped amorphous silicon layer is not performed in step (1).

[0222] The remaining preparation methods and parameters are consistent with those in Example 1.

[0223] Comparative Example 2

[0224] The difference between this comparative example and Example 1 is that the growth of a p+ doped amorphous silicon carbide layer is not performed in step (1).

[0225] The remaining preparation methods and parameters are consistent with those in Example 1.

[0226] Comparative Example 3

[0227] The difference between this comparative example and Example 1 is that wet etching is not performed in step (4).

[0228] The remaining preparation methods and parameters are consistent with those in Example 1.

[0229] Performance testing

[0230] The photoelectric performance of the TBC back-contact solar cells prepared in the above embodiments and comparative examples was tested under the following conditions: light intensity 1000 W / m². 2 The test temperature was 25±2℃.

[0231] The test results are shown in Table 1.

[0232] Table 1

[0233]

[0234]

[0235] analyze:

[0236] As can be seen from the above, the TBC back-contact solar cell provided by the present invention solves the problems of low efficiency caused by the recombination of metal electrodes and silicon substrate interfaces, as well as the problem of leakage current between PN junctions, and has excellent photoelectric conversion efficiency.

[0237] As can be seen from Examples 1 and 4, if the thickness of the tunneling oxide layer is too thick, the doping concentration of the P-region and N-region into the silicon substrate will be too low, resulting in high series resistance and poor contact.

[0238] As can be seen from Examples 1 and 5-6, if the thickness of the p+ doped polycrystalline silicon carbide layer is too small, the metal electrodes in the P and N regions are easily burned through, directly contacting the silicon substrate, damaging the tunneling layer, and affecting passivation and contact; if the thickness of the p+ doped polycrystalline silicon carbide layer is too large, the parasitic absorption is high and the current is low.

[0239] As can be seen from Examples 1 and 7-8, if the thickness of the p+ doped polysilicon layer is too small, the metal electrodes in the P region are easily burned through, directly contacting the silicon substrate, damaging the tunneling layer, and affecting passivation and contact; if the thickness of the p+ doped polysilicon layer is too large, the parasitic absorption is high and the current is low.

[0240] As can be seen from Examples 1 and 9-10, if the oxidation annealing temperature is too low, the activation is insufficient, the doping amount is too low, and the contact is poor; if the oxidation annealing temperature is too high, the doping is too heavy, the doping element penetrates through, the tunneling layer is destroyed, and the passivation is poor.

[0241] As can be seen from Example 1 and Comparative Example 1, if a p+ doped polysilicon layer is not provided, the metal electrodes in the P region are easily burned through, directly contacting the silicon substrate, damaging the tunneling layer, and affecting passivation and contact.

[0242] As can be seen from Example 1 and Comparative Example 2, if a p+ doped polycrystalline silicon carbide layer is not provided, the metal electrodes in the P and N regions are easily burned through, directly contacting the silicon substrate, damaging the tunneling layer, and affecting passivation and contact.

[0243] As can be seen from Example 1 and Comparative Example 3, if the sidewalls of the n+ doped polycrystalline silicon carbide layer and the p+ doped layer are tightly bonded, the P region and the N region are directly connected, and electrons and holes recombine directly, resulting in extremely low efficiency.

[0244] The applicant declares that the present invention is illustrated by the above embodiments, but the present invention is not limited to the above process steps, that is, it does not mean that the present invention must rely on the above process steps to be implemented. Those skilled in the art should understand that any improvements to the present invention, equivalent substitutions of the raw materials used in the present invention, addition of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that, The preparation method includes the following steps: On the back side of the silicon substrate, a tunneling oxide layer, a p+-doped amorphous silicon carbide layer, and a p+-doped amorphous silicon layer are arranged sequentially in the direction away from the silicon substrate. Grooves are formed on the p+ doped amorphous silicon layer, spaced apart and penetrating the p+ doped amorphous silicon layer. Then, a channel is formed at the junction of the grooves and the p+ doped amorphous silicon layer to divide the tunneling oxide layer into a P region and an N region. The p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are arranged on the P region, and the p+ doped amorphous silicon carbide layer is arranged on the N region. Crystallization treatment is performed so that the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer located on the P region are transformed into a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer, respectively, and the p+ doped amorphous silicon carbide layer on the N region is transformed into an n+ doped polycrystalline silicon carbide layer. Post-processing is performed to obtain the solar cell.

2. The preparation method according to claim 1, characterized in that, The methods for forming the tunneling oxide layer, the p+-doped amorphous silicon carbide layer, and the p+-doped amorphous silicon layer are each independently plasma-enhanced chemical vapor deposition. Preferably, the material of the tunneling oxide layer includes silicon oxide; Preferably, the thickness of the tunneling oxide layer is 0.5 nm-2.5 nm, and more preferably 1 nm-2.5 nm; Preferably, the dopant concentration in the p+-doped amorphous silicon carbide layer is 3 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 ; Preferably, the thickness of the p+ doped amorphous silicon carbide layer is 30nm-100nm; Preferably, the dopant concentration in the p+-doped amorphous silicon layer is 3 × 10⁻⁶. 19 cm -3 -5×10 20 cm -3 ; Preferably, the thickness of the p+ doped amorphous silicon layer is 50nm-200nm.

3. The preparation method according to claim 1 or 2, characterized in that, The method for forming the groove includes: forming a first mask layer on the outer surface of the p+ doped amorphous silicon layer, and performing patterned laser windowing and etching processes in sequence; Preferably, the thickness of the first mask layer is 20nm-100nm; Preferably, the laser used for the patterned laser windowing includes an ultraviolet picosecond laser or a green picosecond laser; Preferably, the etchant used for the etching process includes any one or a combination of at least two of KOH, NaOH, or TMAH; Preferably, the width of the groove is 100μm-1000μm.

4. The preparation method according to any one of claims 1-3, characterized in that, The method for forming the trench includes: sequentially forming an n+ doped amorphous silicon layer and a second mask layer on one side surface of the silicon substrate where the groove is formed, and sequentially performing patterned laser windowing and etching processes; Preferably, the doping concentration of the dopant element in the n+ doped amorphous silicon layer is 4 × 10⁻⁶. 20 -2×10 21 cm -3 ; Preferably, the thickness of the n+ doped amorphous silicon layer is 30nm-100nm; Preferably, the material of the second mask layer includes silicon oxide; Preferably, the thickness of the second mask layer is 10nm-50nm; Preferably, the width of the channel is 10μm-60μm.

5. The preparation method according to any one of claims 1-4, characterized in that, The crystallization process includes sequential phosphorus diffusion and oxidation annealing processes; Preferably, the temperature of the phosphorus diffusion is 800℃-900℃; Preferably, the atmosphere for the oxidative annealing treatment is an oxygen-containing atmosphere; Preferably, the temperature of the oxidation annealing treatment is 900℃-1000℃.

6. The preparation method according to claim 5, characterized in that, The front side of the silicon substrate has a textured surface; Preferably, after phosphorus diffusion, a phosphorus-dopated light doped layer is formed on the front side of the silicon substrate; Preferably, the surface phosphorus concentration of the phosphorus-doped layer is 5 × 10⁻⁶. 17 cm -3 -5×10 20 cm -3 ; Preferably, the post-processing steps include: A back passivation layer and a back antireflection layer are sequentially stacked on one side of the silicon substrate where the n+ doped polycrystalline silicon carbide layer is formed, and a front passivation layer and a front antireflection layer are sequentially stacked on the front side of the silicon substrate. A first back metal electrode and a second back metal electrode are formed in the P region and the N region, respectively, such that one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer, such that one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer.

7. The preparation method according to claim 6, characterized in that, The methods for forming the back passivation layer and the front passivation layer include thermal oxidation or atomic layer deposition. Preferably, the method for forming the back antireflection layer and the front antireflection layer includes plasma-enhanced chemical vapor deposition. Preferably, the materials of the back passivation layer and the front passivation layer include silicon oxide and / or aluminum oxide; Preferably, the materials of the back antireflection layer and the front antireflection layer include any one or a combination of at least two of silicon nitride, silicon oxynitride, or silicon oxide; Preferably, the thickness of the back passivation layer and the front passivation layer is 2nm-10nm; Preferably, the thickness of the back antireflective layer and the front antireflective layer is 60nm-150nm.

8. The preparation method according to claim 6 or 7, characterized in that, The steps of forming the first back metal electrode and the second back metal electrode include sequential metallization and sintering processes. Preferably, the materials of the first back metal electrode and the second back metal electrode include silver and / or aluminum; Preferably, after the sintering treatment, a photoinjection annealing step is also performed.

9. A solar cell, characterized in that, The solar cell is prepared using the preparation method described in any one of claims 1-8.

10. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell as described in claim 9.

Images