Low-voltage contact cabinet fault solution generation method and system

Abstract

The invention relates to the technical field of scheme generation, in particular to a low-voltage contact cabinet fault solution generation method and system. The method comprises the following steps of: obtaining main bus section division in the low-voltage contact cabinet and segmentation positions of a circuit breaker and an isolating switch in the cabinet, and sequentially performing power-off segmentation processing on each bus section to obtain bus section power supply isolation position data; acquiring position information and power-off state data of each breakpoint based on bus section power supply isolation position data; and according to the position information of each breakpoint, analyzing the hardware structure operation state of the incoming and outgoing line end of each bus section, and obtaining the operation parameters of the inductance hardware. According to the invention, through accurate power-off segmentation, dynamic hardware monitoring, intelligent fault diagnosis and closed-loop verification, the fine defects of inaccurate fault positioning, insufficient monitoring, poor diagnosis linkage and lack of verification feedback in the prior art are solved, and the intelligence and reliability of fault solution of the low-voltage contact cabinet are improved.

Description

Technical Field

[0001] This invention relates to the field of solution generation technology, and in particular to a method and system for generating solutions for low-voltage communication cabinet failures. Background Technology

[0002] In the early stages, fault handling relied mainly on manual inspections and experience-based judgment, which was inefficient and lacked accuracy. With advancements in sensor and communication technologies, online monitoring systems were introduced to collect key parameters such as current and voltage in real time, providing a data foundation for fault detection. Subsequently, rule-based expert systems were widely used, analyzing collected data through pre-set fault models to improve the accuracy of fault location. In the era of big data and artificial intelligence, machine learning and deep learning algorithms are used to model historical fault data, further enhancing fault prediction and automatic diagnosis capabilities. Simultaneously, the integration of IoT technology has enabled remote monitoring and intelligent maintenance of equipment status. However, the internal neutral wire loop structure of ring main units is complex, with diverse loop lengths and wiring methods. Traditional verification methods struggle to accurately capture minute anomalies in different segments of the loop, easily leading to misjudgments or missed detections. Furthermore, traditional verification methods often only determine whether a loop is abnormal, lacking precise identification of specific fault locations, increasing the difficulty and time cost of fault diagnosis. Summary of the Invention

[0003] Therefore, it is necessary to provide a method and system for generating low-voltage interconnection cabinet fault solutions to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, a method for generating a low-voltage interconnection cabinet fault solution is provided, the method comprising the following steps: Step S1: Obtain the division of the main busbar segments in the low-voltage interconnection cabinet and the segment positions of the circuit breakers and disconnect switches inside the cabinet. Perform power-off segmentation processing on each busbar segment in sequence to obtain the power isolation position data of the busbar segment. Based on the power isolation position data of the busbar segment, collect the position information and power-off status data of each breakpoint. Step S2: Analyze the hardware structure operation status of each busbar segment's incoming and outgoing terminals based on the location information of each breakpoint to obtain the inductor hardware operation parameters; use the power-off state data to perform neutral loop verification on the inductor hardware operation parameters to obtain the neutral loop verification results. Step S3: Construct a fault diagnosis model; input the neutral wire loop verification result into the fault diagnosis model for fault matching calculation to generate preliminary fault diagnosis results; intelligently associate the fault diagnosis results with the preset fault handling strategy library and maintenance tool list to generate a faulty component replacement plan; Step S4: Send the replacement plan for the faulty parts to the maintenance terminal through the HMI in the cabinet, and repeat steps S2 and S3 at preset time intervals to verify the fault resolution of the low-voltage communication cabinet until a successful fault resolution verification result is generated.

[0005] This invention employs segmented de-energization processing of main busbar sections, circuit breakers, and disconnectors to ensure accurate isolation of each busbar section, thereby enhancing the safety of maintenance and repair. Based on de-energization isolation data, the location information and de-energization status of each breakpoint are dynamically collected, enabling real-time monitoring of the hardware operating status at the busbar section's inlet and outlet terminals, thus enhancing the reliability of the basic data for fault diagnosis. Neutral loop verification of the inductive hardware operating parameters using de-energization status data effectively detects electrical loop anomalies, improving sensitivity to potential hazards and avoiding missed detections and misjudgments. The verification results are input into the fault diagnosis model for matching calculations, combined with a fault handling strategy library and maintenance tool list, to achieve automated and intelligent fault identification and repair plan generation, reducing manual judgment errors and workload. Replacement plans for faulty components are transmitted to the maintenance terminal through a human-machine interface, and the fault diagnosis steps are repeated at preset time intervals to ensure the effectiveness of fault handling measures, promptly verify the fault resolution effect, and improve the reliability and stability of system maintenance. This method effectively reduces the risk of electric shock and the probability of fault propagation through refined power-off control, intelligent fault diagnosis, and closed-loop verification, while optimizing the operation and maintenance process and saving time and labor costs. Therefore, this invention, through precise power-off segmentation, dynamic hardware monitoring, intelligent fault diagnosis, and closed-loop verification, addresses the subtle shortcomings of existing technologies, such as inaccurate fault location, insufficient monitoring, poor diagnostic linkage, and lack of verification feedback, thereby improving the intelligence and reliability of low-voltage interconnection cabinet fault resolution.

[0006] Preferably, step S1 includes the following steps: Step S11: Obtain the structural drawings of the low-voltage tie cabinet, and identify and analyze the structural drawings of the low-voltage tie cabinet to extract the main busbar segment division information and the installation positions of circuit breakers and disconnect switches in each segment, so as to obtain the main busbar structure division data. Step S12: Generate a power outage control operation sequence based on the positions of the circuit breaker and disconnector, and perform segmented processing in conjunction with the main bus structure data to obtain the power outage processing instruction set data; Step S13: Control each bus section to perform power outage segmentation operation according to the power outage processing instruction set data, record the power outage execution point of each bus section, and generate bus section power isolation position data; Step S14: Number the breakpoints in the power isolation location data of the bus section, collect the physical location information corresponding to each isolation point, and generate breakpoint location information data; Step S15: Perform on-site power outage status detection on the breakpoint location information data, record the conduction status and voltage status of each breakpoint, and generate power outage status data.

[0007] This invention intelligently identifies and analyzes the structural drawings of low-voltage interconnection cabinets, automatically extracting the main busbar segment divisions and the installation locations of circuit breakers and disconnectors. This significantly improves the accuracy and efficiency of structural information acquisition, avoiding the errors and tediousness of traditional manual identification. Based on equipment location and busbar segmentation data, it automatically generates a power-off control operation sequence, ensuring orderly and systematic power-off operations, reducing operational risks, and improving the safety and controllability of power-off segments. Power-off segmentation is controlled through a power-off processing instruction set, precisely executing power-off operations and recording the power-off execution points of each busbar segment in detail, ensuring traceability and accuracy of power-off isolation implementation. Each disconnection point is numbered, and its corresponding physical location information is collected, achieving standardized management of disconnection points, facilitating subsequent maintenance, inspection, and fault location, and improving the systematic nature and management efficiency of on-site operations. The continuity and voltage status of each disconnection point are monitored in real time, generating power-off status data to ensure the authenticity and effectiveness of power-off operations, promptly detecting anomalies, and ensuring the safe operation of the low-voltage interconnection cabinet. Complete and accurate information on the power isolation location, breakpoint location, and power outage status of the bus section provides solid data support for subsequent analysis of inductive hardware operating parameters, neutral wire loop verification, and fault diagnosis models, thereby improving the reliability of overall fault detection and handling.

[0008] Preferably, step S13 includes the following steps: Step S131: Parse the power outage processing instruction set data and extract the target power outage instruction for each bus segment. Each instruction includes the power outage node number, power outage sequence number, and maximum allowed switching time, where the maximum switching time ranges from 50ms to 500ms. Step S132: Drive the circuit breaker and disconnector actuators on the bus section according to the instruction control signal to perform the power-off segmentation operation; the circuit breaker contact complete disconnection time is required to be less than 100ms, the disconnector mechanical action time is not more than 300ms, and the control system sampling frequency for the execution status is not less than 1kHz. Step S133: After the power-off action is completed, record the physical location data corresponding to the power-off operation in real time, including the bus segment number, execution device ID, phase line position, spatial coordinate position, and record the execution time; perform integrity checks and position uniqueness verification on the recorded physical location data. If there are more than one unclosed point on the same bus segment, or if any power-off point fails to respond within the specified time limit, it is marked as an abnormal isolation point and entered into the alarm record. Step S134: Integrate the information of the non-abnormal isolation points of each bus section with their corresponding physical location data to generate bus section power isolation location data.

[0009] This invention analyzes the power outage processing instruction set, extracting detailed power outage node numbers, power outage sequences, and maximum allowable switching times to achieve scientific planning and time control of power outage actions, ensuring efficiency and safety during the power outage process. The circuit breaker contact opening time is strictly controlled within 100ms, the mechanical action time of the isolating switch does not exceed 300ms, and the control system sampling frequency reaches 1kHz, ensuring rapid and real-time monitoring of the power outage execution device, reducing the risk of misoperation and delay. Detailed records and time-marking of the specific physical location, execution device ID, phase line, and spatial coordinates of the power outage operation are maintained, combined with integrity checks and location uniqueness verification to ensure the accuracy and traceability of the power outage execution data. The system automatically identifies abnormal situations such as multiple unclosed breaks or power outage points failing to respond within timeout periods on the same busbar segment, triggering alarms promptly to prevent the spread of potential safety hazards and improve the system's safety protection level. Non-abnormal isolation points are integrated with their corresponding physical location information to form clearly structured and accurate power isolation location data, providing a solid data foundation for subsequent power outage status monitoring and fault diagnosis. The entire process is based on command-driven and status feedback, combined with high-frequency sampling and automatic verification, to achieve a high degree of automation and intelligence in power-off operations, significantly reducing the risk of manual intervention and improving operational efficiency.

[0010] Preferably, step S2, analyzing the hardware structure operation status of each busbar segment's inlet and outlet ends based on the location information of each breakpoint, includes: Based on the location information of each breakpoint, the incoming and outgoing ends are identified, and the incoming and outgoing ends corresponding to each busbar segment are selected to generate the busbar segment incoming and outgoing end positioning data. The busbar terminal contact resistance is detected by measuring the positioning data of the busbar section's incoming and outgoing ends using a micro-ohmmeter, and terminal contact resistance data is generated. The busbar section's incoming and outgoing line end positioning data is used to collect busbar contact temperature data. The temperature of each contact is read through infrared or contact sensors to generate terminal temperature data. The signal of the energized indicator device in the positioning data of the bus section's incoming and outgoing ends is read, the indication status of each phase is analyzed, and energized status indication data is generated. Secondary signal sampling is performed on the current transformers in the positioning data of the busbar section's incoming and outgoing ends to record the current, voltage, and phase sequence outputs and generate current transformer output data; The positioning data of the busbar section's incoming and outgoing ends are used to identify the status of the disconnecting switches, collect the status of the mechanical interlocking detection contacts, and generate the disconnecting switch interlocking position data. By jointly analyzing terminal contact resistance data, terminal temperature data, energized status indication data, transformer output data, and isolation switch interlocking position data, the operating parameter data of the inductor hardware is generated.

[0011] This invention analyzes breakpoint location information data to accurately identify the corresponding incoming and outgoing terminals for each busbar segment, laying the foundation for subsequent hardware operation status monitoring and improving overall identification accuracy. It uses a micro-ohmmeter to measure terminal contact resistance and combines infrared and contact sensors to collect terminal temperature data, comprehensively assessing the electrical and thermal status of the contacts, effectively identifying potential poor contact and abnormal heating, and preventing faults. Signal acquisition from energized indicators and transformers is performed, analyzing phase indication status, current, voltage, and phase sequence output to dynamically reflect the electrical load and energization status of the busbar segment, ensuring real-time visualization and accurate monitoring of the operating status. The status of the mechanical interlocking contacts of disconnect switches is collected, reflecting the position and interlocking status of the disconnect switches in real time, preventing misoperation and equipment damage, and improving the safety protection level of system operation. Multi-dimensional data such as terminal contact resistance, temperature, energized indicators, transformer output, and interlocking status are fused and analyzed to form comprehensive hardware operation parameter data, improving the accuracy and completeness of the input data for the fault diagnosis model. By systematically and multidimensionally collecting and analyzing hardware status, potential anomalies can be identified early, supporting intelligent fault diagnosis, reducing the workload of manual inspections, and improving maintenance response speed and overall system reliability.

[0012] Preferably, step S2, which uses power-off state data to perform neutral loop verification on the operating parameters of the inductive hardware, includes: Perform potential synchronization verification of electrical nodes in busbar segments on power outage status data, identify whether there is abnormal potential drift at non-breakpoint segments, and generate abnormal potential drift data. The grounding connectivity of the inductive hardware operating parameter data is compared to determine whether there is an illegal interconnection between the neutral point of the busbar incoming and outgoing terminals and the PE line, and neutral point grounding anomaly data is generated. Dynamic modeling of parasitic paths in the neutral wire loop is performed on the operating parameters of the inductive hardware under power-off conditions to obtain parasitic path modeling data; The neutral loop response voltage curve caused by the release of residual capacitance during the instantaneous interruption of the parasitic path modeling data is analyzed to quantify potential undesigned neutral paths in the loop and generate neutral filament parasitic channel index data. By using the parasitic channel index data of the neutral wire to fuse and compare the abnormal data of potential drift and the abnormal data of neutral point grounding, the integrity, abnormal path and safety level of the neutral wire circuit are comprehensively judged, and the neutral wire loop verification result data is generated.

[0013] This invention effectively identifies abnormal potential drift at non-disconnection points by performing potential synchronization verification on power-off state data, thus avoiding electrical faults and safety hazards caused by potential anomalies. By comparing grounding connectivity, it determines whether there are illegal grounding connections at the neutral points of the busbar inlet and outlet, promptly detecting neutral point grounding anomalies, ensuring the safety and standardization of the grounding system, and reducing the risk of electric shock. Dynamic modeling of the parasitic path of the neutral wire loop is performed on the operating parameters of the inductive hardware under power-off conditions, enabling dynamic quantification and monitoring of parasitic paths and enhancing the ability to identify complex electrical phenomena. By analyzing the neutral circuit response voltage curve caused by the release of instantaneous residual capacitance in the parasitic path, potential undesigned neutral paths are accurately quantified, enhancing the ability to identify hidden faults and improving system safety. By fusing and comparing the neutral wire parasitic channel index with abnormal potential drift data and grounding anomaly data, a comprehensive assessment of the neutral wire loop is achieved, accurately identifying abnormal paths and safety risks, and providing a scientific basis for maintenance decisions. Based on multi-dimensional dynamic modeling and fusion analysis, the neutral wire loop verification process is made intelligent, reducing human error and ensuring the stable operation of electrical systems and personnel safety.

[0014] Preferably, the neutral loop response voltage curve caused by the release of residual capacitance during the instantaneous interruption of the parasitic path modeling data is analyzed, and potential undesigned neutral paths in the loop are quantified, including: The time window of the parasitic path modeling data is clipped to extract the voltage response segment at the moment of power failure and generate transient voltage waveform data. Calculate the rate of change of transient voltage waveform data and extract the locations of rapid voltage changes to generate voltage mutation feature data; Residual capacitance release curves are constructed based on voltage mutation characteristic data, and residual capacitance response data are generated. Using residual capacitance response data, the structure of the neutral loop path is determined, abnormal closed branches are identified, and non-designed path data is generated. The parasitic path influence score is calculated based on non-designed pathway data, and neutral filament parasitic channel index data is generated.

[0015] This invention focuses on the voltage response segment at the moment of power failure by using time window clipping to generate transient voltage waveform data, effectively capturing key fault transient signals and improving the timeliness and accuracy of anomaly detection. It calculates the rate of change of the transient voltage waveform to accurately locate the location of rapid voltage changes and extracts voltage mutation feature data, providing a quantitative basis for anomaly judgment. Based on the voltage mutation characteristics, a residual capacitance response curve is constructed to accurately reflect the capacitance release process during power failure, contributing to a deeper understanding of the electrical behavior of parasitic paths in the neutral circuit. The residual capacitance response data is used to judge the neutral circuit path structure, quickly identifying abnormal closed branches and promptly discovering undesigned paths to prevent the continued development of hidden faults. By scoring the undesigned path data, a parasitic path impact index is generated, providing a scientific and quantitative reference for subsequent safety assessments and maintenance decisions. The overall method combines time series analysis and electrical structure judgment to enhance the ability to discover undesigned neutral paths, effectively ensuring the stability of electrical systems and personnel safety.

[0016] Preferably, step S3, which involves intelligently associating the fault diagnosis results with a preset fault handling strategy library and maintenance tool list, includes: The fault diagnosis results are classified and identified, the component name and fault type corresponding to the fault are extracted, and the fault component feature data are generated. Based on the characteristic data of the faulty components, the system retrieves matching processing entries from the fault handling strategy library to generate candidate fault handling strategy data. Extract the required maintenance tool tags from the candidate fault handling strategy data, perform tool adaptation filtering in the maintenance tool list, and generate tool availability data; By combining candidate fault handling strategy data with tool availability data, a suitability score is calculated to select the best handling solution path and generate optimal strategy matching data. Based on the optimal strategy matching data, an executable replacement plan for faulty components is generated, including the replacement parts, execution steps, and required tool configurations.

[0017] This invention categorizes and identifies fault diagnosis results, accurately extracting the corresponding component names and fault types, providing clear and structured foundational data for subsequent handling strategy matching. Based on fault component characteristic data, it automatically retrieves fault handling strategy libraries, quickly obtaining candidate handling entries, significantly shortening the time from fault analysis to repair plan generation, and improving response speed. It extracts maintenance tool tags and filters available tools, achieving compatibility between fault handling strategies and maintenance tools, ensuring the executability of repair plans and the convenience of on-site operation. By comprehensively considering candidate strategies and tool availability data, it performs compatibility scoring, automatically selecting the optimal fault handling path, improving the rationality and implementation effectiveness of the plan. Based on the optimal strategy matching results, it outputs specific replacement component information, execution steps, and required tool configurations, guiding maintenance personnel to complete fault handling efficiently and in a standardized manner. The entire process achieves automatic association and optimization from fault diagnosis to repair plan, reducing manual intervention and errors, lowering maintenance costs, and improving equipment operational reliability.

[0018] Preferably, step S4 includes the following steps: Step S41: The replacement plan for the faulty parts is encoded and converted, and then packaged into command data according to the display format of the HMI in the cabinet; the command data is transmitted to the maintenance terminal through the HMI in the cabinet, and the maintenance terminal receives and confirms the data. Step S42: Receive confirmation data through the maintenance terminal and re-collect power outage status data and induction hardware operating parameters of the current low-voltage interconnection cabinet according to the preset time interval, and generate periodic diagnostic trigger data; Step S43: Repeat step S2 using periodic diagnostic trigger data to generate a new round of inductive hardware operating parameters; repeat step S3 based on the new round of inductive hardware operating parameters to generate the neutral wire loop verification results and fault status judgment data for this round. Step S44: Perform consistency judgment on the neutral wire loop verification results and fault status judgment data of multiple consecutive rounds. If the continuous detection results are normal, generate a successful fault resolution verification result.

[0019] This invention encodes and encapsulates maintenance plans into instruction data that conforms to the display format of the cabinet's human-machine interface (HMI), ensuring the standardization and accuracy of information transmission and improving the convenience and reliability of maintenance operations. Instructions are transmitted to the maintenance terminal via the HMI, and confirmation data is obtained from the maintenance terminal, ensuring accurate delivery of maintenance instructions and improving the coordination and transparency of the maintenance process. Based on the confirmation data from the maintenance terminal, power outage status and inductive hardware operating parameters are automatically collected at preset time intervals, enabling continuous monitoring after fault repair and ensuring real-time updates of equipment status. Periodic diagnostic trigger data is used to repeatedly execute hardware operating parameter collection and fault diagnosis, forming a closed-loop fault detection and verification mechanism to ensure that faults are truly resolved. Consistency judgment is performed on the results of multiple rounds of neutral wire loop verification and fault status determination data to confirm the stability and effectiveness of fault repair, avoiding omissions and recurrences. The entire process is highly automated, reducing the burden of repeated manual testing and judgment, shortening the maintenance cycle, and improving the safety and stability of system operation.

[0020] Preferably, step S44 includes the following steps: Step S441: Perform consistency judgment on the neutral wire loop verification results and fault status judgment data of multiple consecutive rounds, and classify the status of each round of verification results. The normal state is defined as the loop resistance value is between 0.1Ω and 1.0Ω, and the fault judgment flag is "no fault". Step S442: Perform multiple rounds of result consistency judgment. If the result is judged to be normal for N consecutive rounds, the verification is considered to have passed; otherwise, it is judged to be abnormal and the subsequent fault handling process is triggered. N is 3 to 5 rounds, and the verification time interval is set to 5 to 30 seconds. Step S443: After the verification pass conditions are met, generate the fault resolution success verification result data, including the verification round, verification timestamp, average loop resistance and standard deviation, and upload the result to the fault management system.

[0021] This invention ensures the scientific accuracy of status determination by clearly classifying the results of each round of verification based on loop resistance values ​​and fault judgment flags, avoiding the impact of single anomalies on the overall judgment. A verification time interval of 5 to 30 seconds is set for N consecutive rounds (3-5 rounds) of verification. Consistency judgment across multiple rounds effectively eliminates occasional errors and interference, ensuring robust and reliable verification conclusions. Cases of consecutive verification failures are promptly identified as abnormal states, automatically initiating a fault handling mechanism to improve system fault response speed and reduce potential safety risks. Upon successful verification, verification result data containing the verification round number, timestamp, and loop resistance statistics (average and standard deviation) is generated, enabling scientific recording and tracking of the fault resolution process. Successful fault resolution verification results are automatically uploaded to the fault management system, promoting centralized management and historical tracking of maintenance data, improving operational transparency and management efficiency. The overall method, through standardization, multi-round verification, and automated data processing, enhances the intelligence and reliability of the verification process, ensuring the safe and stable operation of the electrical system.

[0022] This specification provides a low-voltage interconnection cabinet fault solution generation system for executing the aforementioned low-voltage interconnection cabinet fault solution generation method. The low-voltage interconnection cabinet fault solution generation system includes: The breakpoint analysis module is used to obtain the division of the main busbar segments in the low-voltage tie cabinet and the segment positions of the circuit breakers and disconnect switches in the cabinet. It sequentially performs power-off segmentation processing on each busbar segment to obtain the power isolation position data of the busbar segment. Based on the power isolation position data of the busbar segment, it collects the position information and power-off status data of each breakpoint. The loop verification module is used to analyze the hardware structure operation status of each busbar segment's incoming and outgoing terminals based on the location information of each breakpoint, and obtain the operating parameters of the inductor hardware; it uses the power-off state data to perform neutral wire loop verification on the operating parameters of the inductor hardware, and obtains the neutral wire loop verification result. The fault diagnosis module is used to build a fault diagnosis model; input the neutral wire loop verification results into the fault diagnosis model to perform fault matching calculations and generate preliminary fault diagnosis results; intelligently associate the fault diagnosis results with the preset fault handling strategy library and maintenance tool list to generate replacement plans for faulty parts. The diagnostic verification module is used to send the replacement plan for the faulty parts to the maintenance terminal through the human-machine interface inside the cabinet, and repeat steps S2 and S3 at preset time intervals to verify the fault resolution of the low-voltage communication cabinet until a successful fault resolution verification result is generated.

[0023] The beneficial effects of this invention lie in its ability to automatically acquire the main busbar segment division and the positions of circuit breakers and disconnectors, sequentially complete the power outage segmentation operation, and generate accurate busbar segment power isolation position data and breakpoint status information, laying a solid foundation for subsequent monitoring and diagnosis. Based on the breakpoint location information, the system systematically analyzes the hardware status of the busbar segment's incoming and outgoing terminals, combines power outage status data to perform neutral loop verification, reflects the integrity of the electrical circuit in real time, promptly captures potential anomalies, and improves fault detection capabilities. A fault diagnosis model is constructed and loop verification results are input to achieve intelligent fault matching. Combined with a fault handling strategy library and maintenance tool list, targeted component replacement plans are automatically generated, significantly improving fault location and handling efficiency. Maintenance plans are distributed to the maintenance terminal through the cabinet's human-machine interface, automatically repeating detection and diagnosis based on preset time intervals to continuously verify the fault resolution effect, ensure maintenance quality, and reduce the risk of recurrence. The overall system integrates four major functional modules: breakpoint analysis, loop verification, fault diagnosis, and maintenance verification, achieving automatic data acquisition, intelligent analysis, and closed-loop feedback, greatly improving maintenance efficiency, reducing manual intervention and misjudgment, and ensuring stable and safe equipment operation. The system generates detailed power isolation, operating status, fault diagnosis, and verification data, supporting fault history tracking and maintenance decisions, and improving the scientific nature and transparency of operation and maintenance management. Therefore, this invention, through precise power outage segmentation, dynamic hardware monitoring, intelligent fault diagnosis, and closed-loop verification, addresses the subtle shortcomings of existing technologies, such as inaccurate fault location, insufficient monitoring, poor diagnostic linkage, and lack of verification feedback, thereby improving the intelligence and reliability of low-voltage interconnection cabinet fault resolution. Attached Figure Description

[0024] Figure 1 A flowchart illustrating the steps involved in generating a solution for a low-voltage interconnection cabinet failure. Figure 2 for Figure 1 A detailed flowchart illustrating the implementation steps of step S1. Figure 3 for Figure 1 A detailed flowchart illustrating the implementation steps of step S4. Figure 4 This is a real-life image of the low-voltage interconnection cabinet structure. The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0026] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0027] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] To achieve the above objectives, please refer to Figures 1 to 4 A method for generating a low-voltage interconnection cabinet fault solution, the method comprising the following steps: Step S1: Obtain the division of the main busbar segments in the low-voltage interconnection cabinet and the segment positions of the circuit breakers and disconnect switches inside the cabinet. Perform power-off segmentation processing on each busbar segment in sequence to obtain the power isolation position data of the busbar segment. Based on the power isolation position data of the busbar segment, collect the position information and power-off status data of each breakpoint. Step S2: Analyze the hardware structure operation status of each busbar segment's incoming and outgoing terminals based on the location information of each breakpoint to obtain the inductor hardware operation parameters; use the power-off state data to perform neutral loop verification on the inductor hardware operation parameters to obtain the neutral loop verification results. Step S3: Construct a fault diagnosis model; input the neutral wire loop verification result into the fault diagnosis model for fault matching calculation to generate preliminary fault diagnosis results; intelligently associate the fault diagnosis results with the preset fault handling strategy library and maintenance tool list to generate a faulty component replacement plan; Step S4: Send the replacement plan for the faulty parts to the maintenance terminal through the HMI in the cabinet, and repeat steps S2 and S3 at preset time intervals to verify the fault resolution of the low-voltage communication cabinet until a successful fault resolution verification result is generated.

[0029] In the embodiments of this invention, please refer to Figure 4The system acquires structural topology data of the main busbar segment 101 in the low-voltage tie cabinet using a high-precision busbar status acquisition unit configured on-site. This data includes the physical connection number, logical connection relationship, and segmentation rules of the busbar segment. Electronic tags or location coding devices are used to physically locate each circuit breaker 102 and disconnector 103 within the cabinet, recording the on / off status and installation location information of each device. Based on this data, and according to a preset busbar segmentation strategy, sequential power-off operations are performed on each busbar segment. Each time a power-off operation is completed, the status acquisition interface is called to read the power isolation position, and this information is recorded in real-time in the main control system via the communication network. The generated busbar segment power isolation position data includes the power-off start time, breakpoint location information, isolation device number, and electrical... Voltage Status Label. After power failure, based on the power isolation location data, voltage detection modules and displacement sensors installed at the breakpoints collect the three-dimensional spatial coordinates and power failure status of each breakpoint to determine whether there is residual voltage or incomplete grounding. Breakpoint location information data and power failure status data are generated and uploaded to the system platform for archiving and subsequent verification and analysis. Based on the breakpoint location information collected in step S1, the corresponding switching equipment, sensors, and other inductive hardware devices at the incoming and outgoing ends of each busbar segment are located. By reading the data storage of the internal control chip of the device, the operating parameters of each device are obtained, including but not limited to current value, voltage fluctuation range, insulation status, grounding status, and metal casing potential, and are uniformly organized into inductive hardware data. Operating parameters. Using power-off state data, a neutral loop verification is performed on each hardware operating parameter. This verification logic includes: determining whether there is a non-zero potential difference between multiple grounding points; detecting whether there are abnormal leakage or return paths in the neutral loop; and analyzing whether there are abnormal characteristics such as high-frequency spike interference or noise frequency distribution in the phase-neutral voltage amplitude. The verification method compares whether key parameters such as the current loop direction and loop resistance at the hardware end form a complete closed loop. Finally, a neutral loop verification result is generated, which includes multiple dimensions such as whether the verification passed or failed, the node number with abnormal loops, the estimated leakage current value, and the waveform anomaly coefficient. Based on the neutral loop verification result obtained in step S2, a fault diagnosis model is constructed. This model... A dual-channel reasoning approach combining rule matching and feature extraction is employed: the rule channel, based on existing electrical fault logic maps, sets multiple sets of logic conditions for common issues such as neutral wire closed-loop faults, return current overloads, and grounding anomalies; the feature channel extracts high-dimensional indicators such as frequency features and leakage amplitude peaks from the verification results through pattern recognition. The neutral wire loop verification results are input into the fault diagnosis model, and through combined judgment and Bayesian inference algorithms, corresponding preliminary fault diagnosis results are generated, including suspected fault type, affected area, and associated equipment number. Subsequently, the fault diagnosis results are matched against a pre-set fault handling strategy library within the system. The strategy library includes processing steps, tool models, required operation time, and manpower allocation for each type of fault.The system automatically retrieves the strategy list most relevant to the current fault type and generates a replacement plan for the faulty parts by combining the maintenance tool list. Specifically, it includes the recommended equipment number, part model, list of required tools and equipment, and replacement operation instructions.

[0030] As an example of the present invention, reference is made to Figure 2 As shown, in this example, step S1 includes: Step S11: Obtain the structural drawings of the low-voltage tie cabinet, and identify and analyze the structural drawings of the low-voltage tie cabinet to extract the main busbar segment division information and the installation positions of circuit breakers and disconnect switches in each segment, so as to obtain the main busbar structure division data. Step S12: Generate a power outage control operation sequence based on the positions of the circuit breaker and disconnector, and perform segmented processing in conjunction with the main bus structure data to obtain the power outage processing instruction set data; Step S13: Control each bus section to perform power outage segmentation operation according to the power outage processing instruction set data, record the power outage execution point of each bus section, and generate bus section power isolation position data; Step S14: Number the breakpoints in the power isolation location data of the bus section, collect the physical location information corresponding to each isolation point, and generate breakpoint location information data; Step S15: Perform on-site power outage status detection on the breakpoint location information data, record the conduction status and voltage status of each breakpoint, and generate power outage status data.

[0031] In this embodiment of the invention, structural drawings of low-voltage interconnection cabinets are retrieved from the low-voltage power distribution system archive management database. These drawings should include multiple perspectives such as front views, side views, and functional wiring diagrams, and file formats include, but are not limited to, DWG, DXF, and PDF. An industrial-grade CAD parsing engine is used to analyze the structure of the drawing files, identifying equipment symbols, busbar routing, component numbers, and annotation text in the layers. A combination of image recognition and a dedicated OCR algorithm for electrical drawings is used to identify the main busbar routing paths marked in the drawings and extract the start and end numbers of each busbar segment. Further analysis of the standard graphic symbols and configuration information of circuit breakers (such as DW and DZ types) and disconnectors (such as GN and HS types) in the drawings identifies the actual installation positions and functional location labels of each component on the busbar. Finally, main busbar segment division information and corresponding circuit breaker and disconnector location information are generated and stored in the structural analysis database as main busbar structural division data. Based on the spatial coordinates of the circuit breakers and disconnectors identified in step S11 and their topological relationship with the busbar segments, a logical busbar segmentation model is constructed using a topology mapping method. Using a depth-first search algorithm or a topology traversal algorithm, key disconnection points suitable for electrical isolation on each bus segment are identified, thereby generating a power-off operation control strategy. Each power-off operation sequence should include: target disconnection point number, control device number, action type (open / close), execution time sequence, and whether linkage operation is required. The power-off control operation sequence is fused with bus segment division information to generate power-off processing instruction set data. The instruction set format uses structured data storage, with each instruction entry including power-off sequence number, device action instruction (e.g., disconnector switch X101 open), bus segment number, expected execution time window, and instruction number, for subsequent execution of the power-off operation by the automated control system. The control system interface of the interconnection cabinet is called to send the power-off processing instruction set data generated in step S12 to the field control device one by one. This control device should support communication protocols such as Modbus or IEC 61850 to realize remote operation control of circuit breakers and disconnectors. The system controls the target circuit breaker or disconnector to operate sequentially according to the control command sequence, while recording the execution status in real time. After each power outage command is executed, the system records the current executing device number, action feedback status (whether the execution was successful), bus segment number, and power outage timestamp, generating the power outage execution point information for that bus segment. All execution point information constitutes complete bus segment power isolation location data. This data includes: bus segment number, breakpoint number, acting device model, execution status flag, power outage time, and power outage confirmation signal feedback status, used for subsequent breakpoint location and status detection. The bus segment power isolation location data generated in step S13 is numbered, assigning a unique breakpoint number to each valid breakpoint. The numbering format can be set to "bus segment number + serial number", such as "L1-01", "L2-03", etc., to ensure consistency of the location index.Subsequently, the low-voltage interconnection cabinet equipment installation database and construction completion data were retrieved to obtain the physical coordinate data corresponding to the installation location of each piece of equipment. Using a laser rangefinder or electrical mapping equipment (such as a GIS scanner), the breakpoints within the cabinet were measured and located on-site, collecting the three-dimensional coordinates (in millimeters) of the center point of each breakpoint, the height of the equipment panel, and the relative distance between adjacent components. Finally, breakpoint location information data was generated. This data, indexed by the breakpoint number, recorded fields such as location coordinates (X, Y, Z), the busbar segment to which it belongs, the equipment surface direction, and the installation level, serving as the input basis for power outage detection. Based on the physical location of the breakpoints obtained in step S14, a multi-functional electrical tester (such as a three-phase voltmeter and a continuity tester) was used to detect the power outage status of each breakpoint. The detection steps included: first, measuring the voltage at the breakpoint, ensuring that a voltage value less than 1V was considered a power outage; second, performing a continuity test, applying a small voltage across the target breakpoint to determine if a closed loop exists; if the resistance was higher than 1MΩ, it was considered an open loop. Each detection action is associated with a corresponding breakpoint number, and information such as measured values, measurement time, tester number, and whether any abnormality is detected is recorded in real time, ultimately generating power-off status data. This data includes fields such as: breakpoint number, voltage value, current value, conduction status, and whether the power-off condition is met, serving as key inputs for subsequent loop verification and fault diagnosis.

[0032] Preferably, step S13 includes the following steps: Step S131: Parse the power outage processing instruction set data and extract the target power outage instruction for each bus segment. Each instruction includes the power outage node number, power outage sequence number, and maximum allowed switching time, where the maximum switching time ranges from 50ms to 500ms. Step S132: Drive the circuit breaker and disconnector actuators on the bus section according to the instruction control signal to perform the power-off segmentation operation; the circuit breaker contact complete disconnection time is required to be less than 100ms, the disconnector mechanical action time is not more than 300ms, and the control system sampling frequency for the execution status is not less than 1kHz. Step S133: After the power-off action is completed, record the physical location data corresponding to the power-off operation in real time, including the bus segment number, execution device ID, phase line position, spatial coordinate position, and record the execution time; perform integrity checks and position uniqueness verification on the recorded physical location data. If there are more than one unclosed point on the same bus segment, or if any power-off point fails to respond within the specified time limit, it is marked as an abnormal isolation point and entered into the alarm record. Step S134: Integrate the information of the non-abnormal isolation points of each bus section with their corresponding physical location data to generate bus section power isolation location data.

[0033] In this embodiment of the invention, the power outage processing instruction set data generated in the preceding steps is imported into the execution task scheduling module of the power distribution cabinet control system. This data structure is a structured command set, with each instruction containing the following fields: power outage node number (e.g., M1-DP03), power outage sequence number (e.g., S003), and maximum switching time (e.g., 200ms). First, each bus segment number is categorized and organized to construct a mapping table between the bus segment and its associated power outage instructions. During parsing, the maximum switching time field is validated to ensure it falls within the range of 50ms to 500ms; instructions exceeding this range are automatically discarded and marked as illegal. Each instruction is sorted internally by its sequence number in ascending order for subsequent sequential execution control. The processing results are cached in the power outage execution scheduling queue as an instruction execution chain for the power outage operation scheduling control module to call and execute. The control system, based on the sorted execution queue from step S131, issues each power outage instruction to the corresponding control channel one by one. If the control device for the power outage node is a circuit breaker (such as the DW series), the disconnection mechanism is directly activated by an electrical control trigger signal, and the start response time is recorded. The control system monitors the circuit breaker contact opening time in real time to ensure that disconnection is completed within 100ms. If the control device is a disconnecting switch (such as the GN series or HS series), the switch action mechanism is activated by an electromagnetic drive or motor mechanism, and a mechanical action timer is started simultaneously to ensure that its action time is less than 300ms. The system sampling period is not less than 1kHz, that is, at least one status sample is acquired every millisecond to determine whether the device has reached the final disconnection state. If the state is not switched within the maximum allowed switching time, the device response is marked as timed out. All control signal execution is implemented using a PLC controller, which, combined with the action feedback signal of the disconnection device, auxiliary contact signal, and status indicator light acquisition, constitutes a closed-loop feedback logic for the execution state. After each power outage command completes its action feedback, the system immediately calls the position recording module to collect the physical location information of the power outage point. Location information includes, but is not limited to: the bus segment number (e.g., L1), the executing device ID (e.g., CBX05), the phase line (e.g., phase A), the three-dimensional spatial coordinates within the control cabinet (e.g., X=520mm, Y=180mm, Z=1400mm), and the power-off operation timestamp. All recorded information is stored in a unified data table structure, and data integrity verification is performed. First, the uniqueness of the bus segment interruption point location is verified, ensuring that no more than two unclosed node markers appear. Second, the time response is verified to ensure it is completed within the predefined maximum switching time. If any interruption point response times out or the recorded location conflicts repeatedly, it is immediately marked as an "abnormal isolation point," and the abnormal information is sent to the fault monitoring subsystem, recording the abnormal point number, cause, time, current status, etc. The system uses an anomaly detection rule table to perform rule comparison on the collected data, ensuring that each interruption point information has a unique identifier and is in a physically independent location, avoiding logical overlap or coordinate conflicts.All power outage execution records marked as "non-abnormal isolation points" in step S133 are treated as qualified data items and categorized and organized according to bus segment number. The isolation point information for each bus segment includes the breakpoint number, device ID, spatial coordinates, disconnection time, phase line identifier, and the type of operating device (circuit breaker / disconnector). The integrated data is output as "Bus Segment Power Isolation Location Data" on a bus segment basis and written to the system isolation status database. This data will serve as the basic data source for subsequent breakpoint location information collection and power outage status detection, supporting the intelligent operation and maintenance system of the interconnection cabinet to achieve dynamic status monitoring of breakpoints and traceable management of the power outage process.

[0034] Preferably, step S2, analyzing the hardware structure operation status of each busbar segment's inlet and outlet ends based on the location information of each breakpoint, includes: Based on the location information of each breakpoint, the incoming and outgoing ends are identified, and the incoming and outgoing ends corresponding to each busbar segment are selected to generate the busbar segment incoming and outgoing end positioning data. The busbar terminal contact resistance is detected by measuring the positioning data of the busbar section's incoming and outgoing ends using a micro-ohmmeter, and terminal contact resistance data is generated. The busbar section's incoming and outgoing line end positioning data is used to collect busbar contact temperature data. The temperature of each contact is read through infrared or contact sensors to generate terminal temperature data. The signal of the energized indicator device in the positioning data of the bus section's incoming and outgoing ends is read, the indication status of each phase is analyzed, and energized status indication data is generated. Secondary signal sampling is performed on the current transformers in the positioning data of the busbar section's incoming and outgoing ends to record the current, voltage, and phase sequence outputs and generate current transformer output data; The positioning data of the busbar section's incoming and outgoing ends are used to identify the status of the disconnecting switches, collect the status of the mechanical interlocking detection contacts, and generate the disconnecting switch interlocking position data. By jointly analyzing terminal contact resistance data, terminal temperature data, energized status indication data, transformer output data, and isolation switch interlocking position data, the operating parameter data of the inductor hardware is generated.

[0035] In this embodiment of the invention, the breakpoint location information data generated in the preceding steps is imported into the busbar structure analysis module of the system. This data includes information such as breakpoint number, location coordinates, and the ID of the busbar segment to which it belongs. Through spatial distribution rules and main busbar topology association rules, combined with the power distribution structure configuration at both ends of the busbar segment, the incoming and outgoing ends of each busbar segment are identified. A matching algorithm based on relative coordinate distance and equipment connection relationships is used to classify the power distribution circuit numbers to which each endpoint belongs, identifying the direction from the main busbar input as the incoming end and the load side direction as the outgoing end. The positioning data of the busbar segment's incoming and outgoing ends is output, and the equipment type (such as cable joint, circuit breaker connection port, etc.) and specific physical location number of each end are recorded. The intelligent testing unit is scheduled to sequentially perform contact resistance detection on all busbar terminal positions marked in the incoming and outgoing end positioning data. A high-precision double-arm bridge micro-ohmmeter (accuracy class not less than ±0.5%) is used to perform a four-wire method contact resistance test on both ends of the terminals. A constant DC excitation current (generally set to 50A) is applied, and the voltage drop is read to calculate the contact resistance value (in microohms) at each test point. Each measurement needs to be repeated three times and the average value is taken to eliminate the influence of instantaneous interference. All measured values ​​are compared with the equipment's preset contact resistance standard threshold (e.g., ≤150μΩ), and the results are recorded and output as a terminal contact resistance data table. An infrared thermometer or embedded thermistor is used to perform temperature acquisition operations at the busbar section's inlet and outlet terminals. The measurement environment requires a power outage of at least 5 minutes or the use of an electrical isolation testing device to ensure temperature measurement safety. Each test point is measured three times consecutively, with a 2-second interval, and the average value is taken. The temperature measurement accuracy is not less than ±1℃. The system will perform difference analysis between the read temperature value and the current room temperature to determine if there are any abnormal heat points. Temperature data is uniformly recorded as terminal temperature data in degrees Celsius and archived and stored according to node number. The three-phase energized indicators (such as high-voltage phase comparators, indicator light groups, or indicator contacts) installed at the incoming and outgoing ends of each busbar section are located. The energized status signals of phases A, B, and C are read using a PLC or distributed I / O acquisition module. The acquisition format is a 1-bit binary signal (1 indicates energized, 0 indicates de-energized). A status refresh detection is performed on each signal, and the stable state signal result is recorded. Simultaneously, the sampling timestamp and device number are marked, and a energized status indication data table is generated. Secondary signal sampling is performed on the current transformers (CTs) and voltage transformers (PTs) installed at the incoming and outgoing ends of the busbars. The three-phase current values, voltage values, and phase sequence information (such as ABC forward or reverse sequence) are collected using a standard sampling module or a portable electrical parameter tester. The sampling accuracy requirement is current error ≤ ±0.5% and voltage error ≤ ±1%. The amplitude and phase angle information of each phase channel are recorded, and inter-phase difference analysis is performed. The data is uniformly archived as transformer output data, with test channel number and timestamp identifier. The mechanical interlock detection device for disconnecting switches is invoked to collect status signals for each disconnecting switch.Specifically, the status of the disconnector switch (DPS) is determined by detecting the normally open and normally closed combination states of the auxiliary contacts. A three-channel dry contact status acquisition module collects the contact on / off states (logic value 1 or 0), compares the detection results with the standard status table set in the control diagram, and determines whether there are interlocking errors or mechanical jamming. The output is the DPS interlocking position data, and anomalies are marked. Terminal contact resistance data, terminal temperature data, energized status indication data, transformer output data, and DPS interlocking position data are input to the inductive hardware status analysis module. The module uses a preset multi-parameter status fusion rule library for joint calculation. This process includes: resistance-temperature collaborative judgment (e.g., high resistance + temperature rise indicates poor contact), voltage-phase sequence matching (e.g., voltage imbalance + phase sequence abnormality indicates transformer abnormality), and then combining the consistency of switch states and the correspondence between energized and unenergized states to generate a comprehensive structural status evaluation result. The final output is a structured output table of operating parameters of the inductor hardware, which includes node number, status label, anomaly level, cause field, etc., for subsequent neutral wire loop verification analysis and fault location operations.

[0036] Preferably, step S2, which uses power-off state data to perform neutral loop verification on the operating parameters of the inductive hardware, includes: Perform potential synchronization verification of electrical nodes in busbar segments on power outage status data, identify whether there is abnormal potential drift at non-breakpoint segments, and generate abnormal potential drift data. The grounding connectivity of the inductive hardware operating parameter data is compared to determine whether there is an illegal interconnection between the neutral point of the busbar incoming and outgoing terminals and the PE line, and neutral point grounding anomaly data is generated. Dynamic modeling of parasitic paths in the neutral wire loop is performed on the operating parameters of the inductive hardware under power-off conditions to obtain parasitic path modeling data; The neutral loop response voltage curve caused by the release of residual capacitance during the instantaneous interruption of the parasitic path modeling data is analyzed to quantify potential undesigned neutral paths in the loop and generate neutral filament parasitic channel index data. By using the parasitic channel index data of the neutral wire to fuse and compare the abnormal data of potential drift and the abnormal data of neutral point grounding, the integrity, abnormal path and safety level of the neutral wire circuit are comprehensively judged, and the neutral wire loop verification result data is generated.

[0037] In this embodiment of the invention, after the low-voltage interconnection cabinet performs a power outage, the system acquires the electrical node potential information of the breakpoints and non-breakpoints of each bus segment in the power outage status data, including the voltage measurements of the three phases and the neutral line. By constructing a global potential distribution map of the bus segment, the system performs potential synchronization verification on the remaining positions in the same bus segment except for the breakpoints, observing whether there is any abnormal potential drift at the non-breakpoints. For example, if a neutral point that should be at "zero potential" has measurement data exceeding a preset offset threshold (e.g., ±5V), it is determined to be a potential anomaly. The system marks the identified abnormal points and outputs the potential drift anomaly data, including the node number, offset amplitude, and corresponding timestamp. The connection relationship between the neutral point position and the corresponding PE line in the inductive hardware operating parameter data is input into the grounding topology comparison module. This module calls the standard grounding rules of the low-voltage power distribution system for comparison and verification to determine whether there is any illegal interconnection behavior between the neutral line and the PE line. The comparison logic includes: whether an N-PE short circuit occurs at a non-protective grounding point, whether there is a multi-point grounding path at the neutral point, and whether a loop structure is formed. The analysis output identifies the node number and grounding type of the illegal grounding location at the neutral point, organizes it into neutral point grounding anomaly data, and includes a logical link description of the illegal connection path. In the power-off state, the scheduling inductive current testing submodule reads the dynamic voltage change process between the neutral line and the phase line at the instant of power failure. This data is input into the neutral wire loop parasitic modeling module, and combined with the capacitance effect model and the derivation of the conduction residual path, an electrical simulation network structure is constructed for the existing non-designed neutral loop. The modeling process considers factors such as distributed parasitic capacitance, inductive coupling, cable laying sequence, and shielding mesh. The system will generate parasitic path modeling data, which includes dynamic response voltage curves, path logic diagrams, and transient time constants. Using the aforementioned modeling data, the response analysis of the residual voltage curves at each point of the neutral line at the instant of power failure is performed, and the response waveform amplitude, oscillation frequency, and settling time at the initial stage of capacitor release are extracted. By comparing the fitted modeling curve with the standard parasitic path curve, the probability of parasitic pathways existing in the path segment, coupling strength, and path length influence factors are calculated. These are then synthesized into a quantitative index, outputting neutral filament parasitic channel index data, which includes the channel strength value, anomaly level classification, and risk label for each analyzed path. The neutral filament parasitic channel index data is used as a core reference indicator and compared with potential drift anomaly data and neutral point grounding anomaly data. The fusion logic includes: if a potential anomaly segment has a high channel index value and its neutral point exhibits grounding violations, it is judged as having a serious neutral filament loop structure anomaly; if the parasitic channel index value is low and the grounding anomaly is not obvious, it is judged as a slight deviation.The system uses a logical weighting and confidence fusion algorithm to output the neutral loop verification results, which include: the neutral loop integrity level of each busbar segment (e.g., normal, suspicious, abnormal); the abnormal path number; recommended handling strategies (e.g., rewiring, installing a neutral disconnector, inspecting the grounding node); and safety level assessment suggestions (e.g., allow operation, limited-time inspection, immediate shutdown). These results will be input into the subsequent fault diagnosis model to support fault location and maintenance optimization of the low-voltage interconnection cabinet.

[0038] Of particular importance, dynamic modeling of the parasitic path in the neutral wire loop for the operating parameters of the inductive hardware under power-off conditions also includes: The residual potential at the grounding point is sampled for the operating parameters of the inductive hardware under power failure, and the neutral point potential disturbance data is extracted. Time window sliding analysis is performed on the neutral point potential disturbance data to extract the rising edge and decay characteristics of the disturbance response and generate transient disturbance characteristic data. By jointly fitting the transient characteristic data of the disturbance with the contact resistance data of the bus terminal at the moment of power failure, a loop coupling excitation function model is constructed, and equivalent loop excitation model data is generated. Based on the equivalent loop excitation model data, a piecewise nonlinear loop fitting method is applied to perform capacitive coupling modeling on the neutral filament path, generating an initial parasitic path structure model. The voltage response was simulated and backtested using the initial parasitic path structure model combined with the actual structural topology. After the error was converged and optimized, the final parasitic path modeling data was formed.

[0039] In this embodiment of the invention, high-resolution residual potential sampling is performed on the relevant hardware grounding points of the bus section under power-off conditions: the sampling frequency is set to no less than 10kHz to ensure the capture of minute potential fluctuations at the moment of power failure; the transient potential disturbance change of the neutral point under power failure conditions is extracted, and the output is neutral point potential disturbance data; each neutral point potential sampling needs to synchronously record the corresponding bus section number, isolation point location, and sampling timestamp. For the neutral point potential disturbance data, the system uses a time window sliding analysis method for feature extraction: the sliding window duration is recommended to be set to 10ms~50ms, with a step size of 1ms; features such as the rising edge, peak point, attenuation slope, and recovery time of the potential disturbance within each window are extracted; the output is disturbance transient feature data describing the transient response behavior. The extracted disturbance transient feature data is jointly fitted with the bus terminal contact resistance data measured at the moment of power failure: a loop coupling excitation function model is constructed using the response coupling relationship between the two; the model adopts a piecewise nonlinear fitting method to capture short-time high-frequency response; the fitting output is equivalent loop excitation model data that can be used for simulation modeling. Using an equivalent loop excitation model as input, a piecewise nonlinear modeling method is employed to model the coupled branches existing in the neutral filament path, with particular consideration given to the synergistic effect of capacitive coupling and inductive response. The output forms a preliminary parasitic path structure model, including branch nodes, capacitance parameters, and coupling relationships. This model is used to describe potential undesigned closed paths or electrical shunt structures within the neutral filament. Finally, the parasitic path structure model is combined with the known structural topology of the interconnection cabinet, and voltage response simulation backtesting is performed. The simulation results are compared with the actual collected disturbance data for error analysis. If the simulation error exceeds a set threshold (e.g., within 10%), the model parameters are automatically reverted, and convergence optimization is performed. This iteration is repeated until the error between the simulation results and the measured data converges. The final output is the error-optimized parasitic path modeling data, which can be used for subsequent neutral filament integrity assessment, abnormal path identification, and loop safety level determination.

[0040] Preferably, the neutral loop response voltage curve caused by the release of residual capacitance during the instantaneous interruption of the parasitic path modeling data is analyzed, and potential undesigned neutral paths in the loop are quantified, including: The time window of the parasitic path modeling data is clipped to extract the voltage response segment at the moment of power failure and generate transient voltage waveform data. Calculate the rate of change of transient voltage waveform data and extract the locations of rapid voltage changes to generate voltage mutation feature data; Residual capacitance release curves are constructed based on voltage mutation characteristic data, and residual capacitance response data are generated. Using residual capacitance response data, the structure of the neutral loop path is determined, abnormal closed branches are identified, and non-designed path data is generated. The parasitic path influence score is calculated based on non-designed pathway data, and neutral filament parasitic channel index data is generated.

[0041] In this embodiment of the invention, a time window pruning operation is performed on the voltage time-series curves in the parasitic path modeling data. The pruning range is based on the power-off control signal trigger point, taking a reserved stable segment forward (e.g., 10ms) and extending backward to the point where the parasitic response basically ends (e.g., 100ms), extracting the complete voltage response segment containing residual capacitance release characteristics, and generating transient voltage waveform data. This data retains the voltage fluctuation details on each observation path for subsequent dynamic analysis. First-order difference calculation is performed on the transient voltage waveform data to obtain the voltage change rate per unit time. Through a threshold judgment method, abrupt change points exceeding a set upper limit (e.g., more than 20V per millisecond) are selected, and the time of occurrence of the abrupt change, the voltage jump amplitude, and the recovery trend before and after the waveform are extracted to form voltage abrupt change characteristic data. This data can reflect whether there is strong coupling or nonlinear conduction behavior during the parasitic capacitance release process. Based on the voltage abrupt change characteristic data, a local waveform fitting interval is established with the abrupt change point as the center, and an exponential decay model is used for fitting to obtain the residual capacitance release curve. The curve includes parameters such as initial voltage peak, decay rate, and response duration. The system comprehensively analyzes the amplitude and duration of this curve to determine the strength of the capacitive effect and outputs residual capacitance response data to determine whether there are energy storage parasitic element paths in the neutral wire circuit. Using the response time and waveform characteristics in the residual capacitance response data, the neutral circuit structure is analyzed through reverse reasoning. If certain circuit paths still exhibit prolonged, asymmetrical voltage responses after power failure, the system determines that the path has an abnormal closed structure, such as illegal parallel branches or redundant conducting elements, through path mapping. The analysis results are output as non-design path data, including node numbers of suspected paths, path topology descriptions, and quantitative values ​​of response indicators. For each non-design path data point, the system scores it based on factors such as residual capacitance response strength, voltage mutation degree, and the number of abnormal paths. A weighted model is used to calculate the parasitic path influence score of the circuit, which is then compared and normalized with other normal paths. The final output is the neutral filament parasitic channel index data, which includes: the channel index value for each path (0-100 points); the channel anomaly level (e.g., slight, moderate, severe); a sorted list of impact levels; a path structure diagram; and associated anomaly information. This index data provides quantitative support for neutral filament loop verification and can be used to assist in determining the level of power outage safety and loop integrity.

[0042] Of particular importance, step S3, which involves building the fault diagnosis model, also includes: A fault diagnosis model is constructed, with multi-dimensional input parameters including neutral wire loop resistance, current, voltage, and ambient temperature. Specifically, the loop resistance is set between 0.05Ω and 5.00Ω, with a resolution of no less than 0.01Ω; the loop current ranges from 0A to 100A, with an accuracy of ±0.5A; the phase voltage ranges from 180V to 260V; and the ambient temperature ranges from -20℃ to +85℃, with an accuracy of ±1℃. The model algorithm can employ support vector machines, multilayer perceptrons, or convolutional neural networks, with 2 to 5 layers and 32 to 128 neurons per layer. The activation function can be ReLU, Tanh, or Sigmoid. During training, at least 1000 historical fault sample data points should be included, each containing at least 5 feature fields. The model output matching similarity threshold is set within the range of 0.75 to 0.95.

[0043] In this embodiment of the invention, during the initial stage of fault diagnosis model construction, the sources of the multidimensional input parameters required by the model are first clarified, and their specific data ranges and accuracy requirements are set. These include: neutral wire loop resistance: range of 0.05Ω to 5.00Ω, requiring a sampling resolution of not less than 0.01Ω; loop current: range of 0A to 100A, sampling accuracy of ±0.5A; phase voltage: range of 180V to 260V; ambient temperature: range of -20℃ to +85℃, sampling accuracy of ±1℃. All of the above parameters are obtained through field sensing devices or data acquisition systems, and data standardization processing (such as normalization or Z-score standardization) is performed for unified scale conversion of the model input. Based on the real-time performance and generalization capabilities required by the diagnostic system, a suitable model algorithm is selected as the core algorithm of the fault diagnosis model. Optional algorithms include: Support Vector Machine (SVM): suitable for classification problems with moderate sample size and high feature dimensionality; Multilayer Perceptron (MLP): employs a 2-5 layer fully connected neural network structure, with 32-128 neurons per layer, and ReLU or Tanh activation functions; Convolutional Neural Network (CNN): when the input samples have temporal or two-dimensional distribution features, a 1D or 2D convolutional structure can be used, with a depth not exceeding 5 layers and the number of neurons per layer controlled within 64, using ReLU or Sigmoid activation functions. The model structure design should balance computational efficiency and model capacity. The output layer should be a multi-class or binary classification structure (e.g., normal, minor anomaly, severe fault), and the Softmax function should be used to output matching similarity. At least 1000 fault sample data points should be extracted from the historical operation records of the low-voltage interconnection cabinet system as the model training dataset. Each sample should include the following feature fields: neutral wire loop resistance value; loop current value; three-phase phase voltage; ambient temperature; and extended fields such as loop voltage fluctuation or interference signal response. After cleaning, handling missing values, and removing outliers, the sample data is divided into training and validation sets, typically in an 8:2 ratio. During training, the cross-entropy loss function and the Adam optimizer are used for backpropagation optimization. After model training, performance metrics are evaluated, including: accuracy, precision, recall, and match similarity (predicted value confidence). The match similarity output range is set between 0.75 and 0.95; if the confidence of the model's output predicted value is higher than a set threshold (e.g., 0.85), the fault mode match is considered successful; otherwise, manual assistance is required. For samples below the threshold but suspected of being faulty, confidence ranking and comparison with nearest neighbor samples can assist in judgment, improving the overall accuracy and coverage of the diagnostic system. The trained and validated fault diagnosis model is modularly embedded into the communication cabinet control system. Real-time data streams from the neutral loop are received through a preset input data channel, automatically completing the model inference process.Output fault category, fault level, and matching similarity score for subsequent replacement suggestions and maintenance reminders. Model inference time should be controlled within 300ms to ensure rapid response to electrical faults and support real-time online updates and incremental learning to adapt to changes in field conditions.

[0044] Preferably, step S3, which involves intelligently associating the fault diagnosis results with a preset fault handling strategy library and maintenance tool list, includes: The fault diagnosis results are classified and identified, the component name and fault type corresponding to the fault are extracted, and the fault component feature data are generated. Based on the characteristic data of the faulty components, the system retrieves matching processing entries from the fault handling strategy library to generate candidate fault handling strategy data. Extract the required maintenance tool tags from the candidate fault handling strategy data, perform tool adaptation filtering in the maintenance tool list, and generate tool availability data; By combining candidate fault handling strategy data with tool availability data, a suitability score is calculated to select the best handling solution path and generate optimal strategy matching data. Based on the optimal strategy matching data, an executable replacement plan for faulty components is generated, including the replacement parts, execution steps, and required tool configurations.

[0045] In this embodiment of the invention, the fault diagnosis results generated in step S3 are parsed, and the results are structured according to a rule model or tag dictionary. The component names (such as disconnect switches, busbar terminals, current transformers, etc.) and specific fault types (such as poor contact, overheating, signal abnormalities, etc.) associated with the diagnostic content are extracted, forming standardized "component + fault type" combinations to generate fault component feature data for subsequent strategy matching. Using the fault component feature data as keywords or indexes, intelligent matching and retrieval are performed in a preset fault handling strategy library. Each record in the strategy library includes the handleable component type, fault manifestation, handling steps, replacement scheme, and precautions. The matching process can use keyword Boolean combination, vector semantic similarity comparison, etc., to filter out all relevant entries and generate candidate fault handling strategy data. The tags of the required maintenance tools listed in the candidate fault handling strategy data are extracted, including tool name, specifications, and operating requirements. Subsequently, a step-by-step adaptation and filtering is performed on the maintenance tool list to determine whether each tool is available in the current environment or whether there are compatible alternatives, generating tool availability data. This data includes tool availability identifiers, deployment paths, and recommended compatibility options. Candidate fault handling strategy data is matched with corresponding tool availability data, and a compatibility score is applied to each strategy-tool combination. The scoring criteria include: tool availability rate, tool call difficulty, strategy coverage completeness, and execution safety level. Through weighted calculations, the overall execution feasibility of each combination is evaluated, and the optimal combination path is output after ranking, generating optimal strategy matching data. Based on the optimal strategy matching data, the system automatically constructs replacement plans for faulty components. The replacement plan includes: detailed information and location number of the faulty component; selection information and spare part call method for the replacement component; specific operation steps, precautions, and expected testing points; and a list of required maintenance tools and their configuration methods, including tool access locations and recommended spares. Finally, the output is a structured, executable replacement task sheet, which can be displayed on a human-machine interface and simultaneously sent to the maintenance terminal to guide maintenance personnel in efficient fault handling.

[0046] As an example of the present invention, reference is made to Figure 3 As shown, step S4 in this example includes: Step S41: The replacement plan for the faulty parts is encoded and converted, and then packaged into command data according to the display format of the HMI in the cabinet; the command data is transmitted to the maintenance terminal through the HMI in the cabinet, and the maintenance terminal receives and confirms the data. Step S42: Receive confirmation data through the maintenance terminal and re-collect power outage status data and induction hardware operating parameters of the current low-voltage interconnection cabinet according to the preset time interval, and generate periodic diagnostic trigger data; Step S43: Repeat step S2 using periodic diagnostic trigger data to generate a new round of inductive hardware operating parameters; repeat step S3 based on the new round of inductive hardware operating parameters to generate the neutral wire loop verification results and fault status judgment data for this round. Step S44: Perform consistency judgment on the neutral wire loop verification results and fault status judgment data of multiple consecutive rounds. If the continuous detection results are normal, generate a successful fault resolution verification result.

[0047] In this embodiment of the invention, the faulty component replacement scheme generated in step S3 is used as structured task information input, and encoding conversion processing is performed, including: mapping command codes to the replacement component name, execution steps, tool list, etc.; encapsulating the format according to the communication protocol and visual layout required by the cabinet's human-machine interface, including instruction frame structure, field order, command trigger identifier, etc.; and finally forming instruction data conforming to the protocol format. Subsequently, the instruction data is transmitted in real time to the maintenance terminal (such as a handheld maintenance tablet, wireless maintenance station, etc.) through the human-machine interface of the low-voltage communication cabinet (such as a touch screen controller or maintenance panel). After receiving the instruction, the maintenance terminal automatically generates maintenance terminal reception confirmation data, including reception timestamp, reception status identifier, command number, etc., and feeds it back to the cabinet control system to establish a task response link. After the maintenance terminal confirms the receipt of the task instruction, the system enters the periodic status monitoring phase. The system repeatedly collects the status data of the current low-voltage interconnection cabinet at preset time intervals (e.g., 10 seconds, 30 seconds, or 1 minute). This includes: repeatedly detecting the power outage status of the bus section; and re-collecting the operating parameters of the inductor hardware (e.g., terminal resistance, voltage status, transformer output, etc.). The collected results are automatically packaged into periodic diagnostic trigger data and enter the next round of diagnostic process. Based on the periodic diagnostic trigger data obtained in step S42, the system repeatedly executes steps S2 and S3: Step S2: Analyze the power outage status and the operating parameters of the inductor hardware, and execute the neutral wire loop verification process; Step S3: Match the verification results with the inductor data to a preset fault mode, perform fault diagnosis, and generate updated neutral wire loop verification results and fault status judgment data. This process can run automatically without manual intervention. The system performs consistency checks on the results of multiple consecutive rounds (e.g., 3 or 5 rounds) of neutral wire loop verification and fault status determination data. This includes: verifying whether the result of each round is in a "normal" state; determining whether consecutive detection rounds meet the set "stability" criteria (e.g., no abnormal fluctuations, parasitic channel index stable in the low-risk range); if the results of multiple consecutive rounds of detection are all normal, the system automatically determines that the fault has been completely eliminated and generates a successful fault resolution verification result. This verification result can be displayed to maintenance personnel through the human-machine interface and recorded in the system operation and maintenance log as a closed-loop identifier for the maintenance task.

[0048] Preferably, step S44 includes the following steps: Step S441: Perform consistency judgment on the neutral wire loop verification results and fault status judgment data of multiple consecutive rounds, and classify the status of each round of verification results. The normal state is defined as the loop resistance value is between 0.1Ω and 1.0Ω, and the fault judgment flag is "no fault". Step S442: Perform multiple rounds of result consistency judgment. If the result is judged to be normal for N consecutive rounds, the verification is considered to have passed; otherwise, it is judged to be abnormal and the subsequent fault handling process is triggered. N is 3 to 5 rounds, and the verification time interval is set to 5 to 30 seconds. Step S443: After the verification pass conditions are met, generate the fault resolution success verification result data, including the verification round, verification timestamp, average loop resistance and standard deviation, and upload the result to the fault management system.

[0049] In this embodiment of the invention, the results of multiple consecutive rounds of neutral wire loop verification and fault status determination data are analyzed round by round. Specifically, this includes: extracting the loop resistance value and fault determination flag bit for each round; classifying each round's verification result into "normal" or "abnormal" states, where: the loop resistance value is between 0.1Ω and 1.0Ω; the fault determination flag bit is "no fault." Those meeting both conditions are marked as "normal state," otherwise as "abnormal state." Multi-round consistency analysis is performed on the classified and marked verification results: the parameter N (configurable, recommended value 3-5) is set as the number of consecutive verification rounds; the time interval between each verification round is set to 5 seconds to 30 seconds; if the verification results for N consecutive rounds are all "normal state," the neutral wire loop state is considered stable, and the system marks it as "verification passed"; if any round shows an "abnormal state," the judgment process is terminated, and the preceding fault handling process is re-triggered to perform re-diagnosis and re-verification. Each round's verification result is accompanied by a timestamp and bus segment number to ensure data traceability. The judgment process features an automatic retry mechanism and supports setting the error round tolerance (e.g., allowing one round of fluctuation but requiring subsequent rounds for stabilization). Upon successful verification, the system automatically generates structured verification result data, including: the number of verification rounds used in the current verification process; the timestamp for each round; the average and standard deviation of all loop resistance values ​​during the verification process; the covered bus segment numbers and isolation point identifiers. This data is uniformly packaged as "Fault Resolution Successful Verification Result Data" and uploaded to the fault management system via the communication module as the final confirmation basis for closed-loop maintenance tasks. The system simultaneously marks this result in the maintenance log for subsequent operation and maintenance recording and auditing.

[0050] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0051] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for generating a fault solution for a low-voltage interconnection cabinet, characterized in that, Includes the following steps: Step S1: Obtain the division of the main busbar segments in the low-voltage interconnection cabinet and the segment positions of the circuit breakers and disconnect switches inside the cabinet. Perform power-off segmentation processing on each busbar segment in sequence to obtain the power isolation position data of the busbar segment. Based on the power isolation position data of the busbar segment, collect the position information and power-off status data of each breakpoint. Step S2: Analyze the hardware structure operation status of each busbar segment's incoming and outgoing terminals based on the location information of each breakpoint to obtain the inductor hardware operation parameters; use the power-off state data to perform neutral loop verification on the inductor hardware operation parameters to obtain the neutral loop verification results. Step S3: Construct a fault diagnosis model; input the neutral wire loop verification results into the fault diagnosis model for fault matching calculation to generate preliminary fault diagnosis results; The fault diagnosis results are intelligently linked with the preset fault handling strategy library and maintenance tool list to generate replacement plans for faulty parts. Step S4: Send the replacement plan for the faulty parts to the maintenance terminal through the HMI in the cabinet, and repeat steps S2 and S3 at preset time intervals to verify the fault resolution of the low-voltage communication cabinet until a successful fault resolution verification result is generated.

2. The method for generating a low-voltage interconnection cabinet fault solution according to claim 1, characterized in that, Step S1 includes the following steps: Step S11: Obtain the structural drawings of the low-voltage tie cabinet, and identify and analyze the structural drawings of the low-voltage tie cabinet to extract the main busbar segment division information and the installation positions of circuit breakers and disconnect switches in each segment, so as to obtain the main busbar structure division data. Step S12: Generate a power outage control operation sequence based on the positions of the circuit breaker and disconnector, and perform segmented processing in conjunction with the main bus structure data to obtain the power outage processing instruction set data; Step S13: Control each bus section to perform power outage segmentation operation according to the power outage processing instruction set data, record the power outage execution point of each bus section, and generate bus section power isolation position data; Step S14: Number the breakpoints in the power isolation location data of the bus section, collect the physical location information corresponding to each isolation point, and generate breakpoint location information data; Step S15: Perform on-site power outage status detection on the breakpoint location information data, record the conduction status and voltage status of each breakpoint, and generate power outage status data.

3. The method for generating a low-voltage interconnection cabinet fault solution according to claim 2, characterized in that, Step S13 includes the following steps: Step S131: Parse the power outage processing instruction set data and extract the target power outage instruction for each bus segment. Each instruction includes the power outage node number, power outage sequence number, and maximum allowed switching time, where the maximum switching time ranges from 50ms to 500ms. Step S132: Drive the circuit breaker and disconnector actuators on the bus section according to the instruction control signal to perform the power-off segmentation operation; the circuit breaker contact complete disconnection time is required to be less than 100ms, the disconnector mechanical action time is not more than 300ms, and the control system sampling frequency for the execution status is not less than 1kHz. Step S133: After the power-off action is completed, record the physical location data corresponding to the power-off operation in real time, including the bus segment number, execution device ID, phase line position, spatial coordinate position, and record the execution time; perform integrity checks and position uniqueness verification on the recorded physical location data. If there are more than one unclosed point on the same bus segment, or if any power-off point fails to respond within the specified time limit, it is marked as an abnormal isolation point and entered into the alarm record. Step S134: Integrate the information of the non-abnormal isolation points of each bus section with their corresponding physical location data to generate bus section power isolation location data.

4. The method for generating a low-voltage interconnection cabinet fault solution according to claim 1, characterized in that, Step S2 involves analyzing the hardware structure and operational status of each busbar segment's incoming and outgoing ends based on the location information of each breakpoint, including: Based on the location information of each breakpoint, the incoming and outgoing ends are identified, and the incoming and outgoing ends corresponding to each busbar segment are selected to generate the busbar segment incoming and outgoing end positioning data. The busbar terminal contact resistance is detected by measuring the positioning data of the busbar section's incoming and outgoing ends using a micro-ohmmeter, and terminal contact resistance data is generated. The busbar section's incoming and outgoing line end positioning data is used to collect busbar contact temperature data. The temperature of each contact is read through infrared or contact sensors to generate terminal temperature data. The signal of the energized indicator device in the positioning data of the bus section's incoming and outgoing ends is read, the indication status of each phase is analyzed, and energized status indication data is generated. Secondary signal sampling is performed on the current transformers in the positioning data of the busbar section's incoming and outgoing ends to record the current, voltage, and phase sequence outputs and generate current transformer output data; The positioning data of the busbar section's incoming and outgoing ends are used to identify the status of the disconnecting switches, collect the status of the mechanical interlocking detection contacts, and generate the disconnecting switch interlocking position data. By jointly analyzing terminal contact resistance data, terminal temperature data, energized status indication data, transformer output data, and isolation switch interlocking position data, the operating parameter data of the inductor hardware is generated.

5. The method for generating a low-voltage interconnection cabinet fault solution according to claim 1, characterized in that, Step S2, which uses power-off state data to perform neutral loop verification on the operating parameters of the inductor hardware, includes: Perform potential synchronization verification of electrical nodes in busbar segments on power outage status data, identify whether there is abnormal potential drift at non-breakpoint segments, and generate abnormal potential drift data. The grounding connectivity of the inductive hardware operating parameter data is compared to determine whether there is an illegal interconnection between the neutral point of the busbar incoming and outgoing terminals and the PE line, and neutral point grounding anomaly data is generated. Dynamic modeling of parasitic paths in the neutral wire loop is performed on the operating parameters of the inductive hardware under power-off conditions to obtain parasitic path modeling data; The neutral loop response voltage curve caused by the release of residual capacitance during the instantaneous interruption of the parasitic path modeling data is analyzed to quantify potential undesigned neutral paths in the loop and generate neutral filament parasitic channel index data. By using the parasitic channel index data of the neutral wire to fuse and compare the abnormal data of potential drift and the abnormal data of neutral point grounding, the integrity, abnormal path and safety level of the neutral wire circuit are comprehensively judged, and the neutral wire loop verification result data is generated.

6. The method for generating a low-voltage interconnection cabinet fault solution according to claim 5, characterized in that, Analyzing the neutral loop response voltage curve caused by the release of residual capacitance during the instantaneous electrical state interruption in parasitic path modeling data, we quantify the potential undesigned neutral paths in the loop, including: The time window of the parasitic path modeling data is clipped to extract the voltage response segment at the moment of power failure and generate transient voltage waveform data. Calculate the rate of change of transient voltage waveform data and extract the locations of rapid voltage changes to generate voltage mutation feature data; Residual capacitance release curves are constructed based on voltage mutation characteristic data, and residual capacitance response data are generated. Using residual capacitance response data, the structure of the neutral loop path is determined, abnormal closed branches are identified, and non-designed path data is generated. The parasitic path influence score is calculated based on non-designed pathway data, and neutral filament parasitic channel index data is generated.

7. The method for generating a low-voltage interconnection cabinet fault solution according to claim 1, characterized in that, Step S3 involves intelligently associating the fault diagnosis results with the preset fault handling strategy library and maintenance tool list, including: The fault diagnosis results are classified and identified, the component name and fault type corresponding to the fault are extracted, and the fault component feature data are generated. Based on the characteristic data of the faulty components, the system retrieves matching processing entries from the fault handling strategy library to generate candidate fault handling strategy data. Extract the required maintenance tool tags from the candidate fault handling strategy data, perform tool adaptation filtering in the maintenance tool list, and generate tool availability data; By combining candidate fault handling strategy data with tool availability data, a suitability score is calculated to select the best handling solution path and generate optimal strategy matching data. Based on the optimal strategy matching data, an executable replacement plan for faulty components is generated, including the replacement parts, execution steps, and required tool configurations.

8. The method for generating a low-voltage interconnection cabinet fault solution according to claim 1, characterized in that, Step S4 includes the following steps: Step S41: The replacement plan for the faulty parts is encoded and converted, and then packaged into command data according to the display format of the HMI in the cabinet; the command data is transmitted to the maintenance terminal through the HMI in the cabinet, and the maintenance terminal receives and confirms the data. Step S42: Receive confirmation data through the maintenance terminal and re-collect power outage status data and induction hardware operating parameters of the current low-voltage interconnection cabinet according to the preset time interval, and generate periodic diagnostic trigger data; Step S43: Repeat step S2 using periodic diagnostic trigger data to generate a new round of inductive hardware operating parameters; repeat step S3 based on the new round of inductive hardware operating parameters to generate the neutral wire loop verification results and fault status judgment data for this round. Step S44: Perform consistency judgment on the neutral wire loop verification results and fault status judgment data of multiple consecutive rounds. If the continuous detection results are normal, generate a successful fault resolution verification result.

9. The method for generating a low-voltage interconnection cabinet fault solution according to claim 8, characterized in that, Step S44 includes the following steps: Step S441: Perform consistency judgment on the neutral wire loop verification results and fault status judgment data of multiple consecutive rounds, and classify the status of each round of verification results. The normal state is defined as the loop resistance value is between 0.1Ω and 1.0Ω, and the fault judgment flag is "no fault". Step S442: Perform multiple rounds of result consistency judgment. If the result is judged to be normal for N consecutive rounds, the verification is considered to have passed; otherwise, it is judged to be abnormal and the subsequent fault handling process is triggered. N is 3 to 5 rounds, and the verification time interval is set to 5 to 30 seconds. Step S443: After the verification pass conditions are met, generate the fault resolution success verification result data, including the verification round, verification timestamp, average loop resistance and standard deviation, and upload the result to the fault management system.

10. A low-voltage interconnection cabinet fault solution generation system, characterized in that, For executing the low-voltage interconnection cabinet fault solution generation method as described in claim 1, the low-voltage interconnection cabinet fault solution generation system comprises: The breakpoint analysis module is used to obtain the division of the main busbar segments in the low-voltage tie cabinet and the segment positions of the circuit breakers and disconnect switches in the cabinet. It sequentially performs power-off segmentation processing on each busbar segment to obtain the power isolation position data of the busbar segment. Based on the power isolation position data of the busbar segment, it collects the position information and power-off status data of each breakpoint. The loop verification module is used to analyze the hardware structure operation status of each busbar segment's incoming and outgoing terminals based on the location information of each breakpoint, and obtain the operating parameters of the inductor hardware; it uses the power-off state data to perform neutral wire loop verification on the operating parameters of the inductor hardware, and obtains the neutral wire loop verification result. The fault diagnosis module is used to build a fault diagnosis model; input the neutral wire loop verification results into the fault diagnosis model to perform fault matching calculations and generate preliminary fault diagnosis results; intelligently associate the fault diagnosis results with the preset fault handling strategy library and maintenance tool list to generate replacement plans for faulty parts. The diagnostic verification module is used to send the replacement plan for the faulty parts to the maintenance terminal through the human-machine interface inside the cabinet, and repeat steps S2 and S3 at preset time intervals to verify the fault resolution of the low-voltage communication cabinet until a successful fault resolution verification result is generated.

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