Method and apparatus for training a command address bus

Abstract

The application relates to the technical field of integrated circuits and provides a command address bus training method and a training device. Through optimization design of a test signal and overall optimization design of a training method, the influence of factors such as device characteristics, path delay, wire layout and signal quality is fully considered, and comprehensive analysis of signal integrity and power integrity is considered, so that the accuracy of training and signal stability are improved, the demand of high-performance memory in state alignment and synchronization is met, a higher data transmission rate and a higher working frequency are supported, and the demand of data centers, high-performance servers, artificial intelligence infrastructure and the like on data transmission and high-speed interconnection is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a command address bus training method and training device. BACKGROUND

[0002] In applications such as data centers, high-performance servers, artificial intelligence infrastructure, etc., a large number of high-performance memories are used, such as fourth-generation double data rate synchronous dynamic random access memory (DDR4 SDRAM) and fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM). In these application scenarios of high-performance memories, the standard double data rate memory physical layer interface (DDR PHY Interface, DFI) protocol version 5.1, also known as DFI 5.1, is supported, and in order to meet the demand for high-speed interconnection between the controller and the storage grain, a parallel interface connection solution is adopted. The semiconductor memory defines a command address (CA) bus, a clock (CK) signal, and a data (DQ) bus. The command address bus is used to transmit operation commands such as read, write, activation, etc., and to transmit row and column addresses. Due to factors such as device characteristics, path delay, layout of wires, signal quality, etc., the semiconductor memory needs to be trained to meet the requirements of state alignment and synchronization. In addition, with the increasing demand for data transmission, the data transmission rate and the operating frequency are greatly increased, for example, the operating frequency is required to be no less than 5200 megahertz, which means that the signal quality of the command address bus becomes the bottleneck of the overall system performance, and therefore the accuracy of the training of the command address bus needs to be improved. The training schemes in the prior art do not fully consider the inter-symbol interference (ISI) problem caused by poor signal quality, and lack comprehensive analysis and consideration of signal integrity and power integrity (SIPI), so it is difficult to meet the requirements of digital signal transmission quality and power supply stability in high-speed interfaces and high-speed circuits, especially when the operating frequency is high, it is difficult to improve the system performance. For example, the Chinese patent with the authorization announcement number CN118567575B discloses a training method for command address signals, the storage grain samples the command address signals, and the storage grain feeds back the multi-bit target sampling value of the command address signals to the controller, and then the controller adjusts the delay of the command address signals based on the multi-bit target sampling value. For another example, the Chinese patent with the authorization announcement number CN108320765B discloses a memory-related training method, the memory samples n command / address signals according to first and second signal edges of a clock signal to obtain first and second sampling contents; the memory selectively outputs one of the first and second sampling contents to a memory controller through m data signals in response to a control signal.For another example, a Chinese patent application with the application publication number CN116569263A discloses a memory device, which includes a first interface, a data interface, and a mode register, and the first interface is in a mode for receiving a CA signal in a CA bus loopback mode, the data interface is in a mode for outputting the received CA signal in the loopback mode, and the mode register is used to store a value representing a timing offset between a clock signal and a sampling point of the first interface. For another example, a Chinese patent with the grant announcement number CN113496719B discloses a training method of a semiconductor memory, acquires a stored historical training result of the semiconductor memory, and the historical training result includes a historical expected time delay value and a historical expected voltage; sets a time delay threshold value and a current training voltage range.

[0003] To this end, the present application provides a command address bus training method and training device, which not only fully considers the influence of device characteristics, path delay, wire layout, signal quality and other factors, but also considers the comprehensive analysis of signal integrity and power integrity, improves the accuracy of training and signal stability, is conducive to meeting the needs of high-performance memory in state alignment and synchronization, supports higher data transmission rate and higher working frequency, and helps to meet the needs of data centers, high-performance servers, artificial intelligence infrastructure and other applications for data transmission and high-speed interconnection. SUMMARY

[0004] In a first aspect, the present application provides a training method of a command address bus. The command address bus includes a plurality of command address signal lines. The training method includes performing a training procedure for each of the plurality of command address signal lines one by one. A first command address signal line is a command address signal line corresponding to the training procedure among the plurality of command address signal lines. A second command address signal line set is a set of command address signal lines other than the first command address signal line among the plurality of command address signal lines. A clock signal is a clock signal transmitted by a clock signal line corresponding to the command address bus. The training procedure includes receiving a first command address signal transmitted through the first command address signal line, and receiving a plurality of second command address signals transmitted through the command address signal lines included in the second command address signal line set. A first test signal is sent to the first command address signal line. The first test signal has a peak region and a valley region that are periodically and alternately distributed. An inverted signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set. Based on the plurality of second command address signals, a first edge determination result of a left edge of the valley region of the first command address signal and a second edge determination result of a left edge of the peak region of the first command address signal are determined using a rising edge of the clock signal as a sampling signal. Based on the plurality of second command address signals, a third edge determination result of a left edge of the valley region of the first command address signal and a fourth edge determination result of a left edge of the peak region of the first command address signal are determined using a falling edge of the clock signal as a sampling signal. A first delay value is determined using an intersection between the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result. The first delay value is used for calibration of the first command address signal line.

[0005] By the first aspect of the present application, by requiring the peak region and the valley region of the first test signal to be periodically and alternately distributed, and by requiring the inverted signal of the first test signal to be sent to an even number of command address signal lines in the second command address signal line set, unlike just a simple pull-up mode or a simple pull-down mode, the influence of the code interference factor can be better highlighted by the regular change of the first test signal, and the anti-interference capability under the condition of poor test signal quality can also be better simulated, which helps to test the performance of a complex system under extreme conditions, and also takes into account the influence of signal integrity and power integrity, which helps to improve the signal transmission quality and power supply stability; by obtaining four edge determination results, i.e., by obtaining the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, the sampling scenarios of the rising edge and the falling edge of the clock signal are covered, and the margin of the rising edge and the falling edge of the clock signal and the duty cycle of the clock signal itself are also taken into account, which helps to improve the signal quality of the command address signal, so as to better adapt to the performance difference of the hardware on the receiving side; in this way, the training of the command address bus is realized, and it is ensured that the command address signal is correctly received, not only taking into account the influence of factors such as device characteristics, path delay, layout of lines, signal quality, but also considering the comprehensive analysis of signal integrity and power integrity, improving the accuracy of training and signal stability, which is beneficial to meet the needs of high-performance memories in state alignment and synchronization, support higher data transmission rate and higher working frequency, and help to meet the needs of data transmission and high-speed interconnection in applications such as data centers, high-performance servers, and artificial intelligence infrastructure.

[0006] In a possible implementation manner of the first aspect of the present application, the first edge determination result is a sampling result of the left edge of the valley region of the first command address signal obtained by using the rising edge of the clock signal as a sampling signal to sample the first command address signal, the second edge determination result is a sampling result of the left edge of the peak region of the first command address signal obtained by using the rising edge of the clock signal as a sampling signal to sample the first command address signal, the third edge determination result is a sampling result of the left edge of the valley region of the first command address signal obtained by using the falling edge of the clock signal as a sampling signal to sample the first command address signal, and the fourth edge determination result is a sampling result of the left edge of the peak region of the first command address signal obtained by using the falling edge of the clock signal as a sampling signal to sample the first command address signal.

[0007] In a possible implementation of the first aspect of the present application, the first XOR calculation result is obtained by performing XOR calculation on a first sample result set, and the second XOR calculation result is obtained by performing XOR calculation on a second sample result set.

[0008] In a possible implementation of the first aspect of the present application, the first edge determination result is a sampling result of a left edge of a trough region of the first command address signal, which is obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, including: keeping delays of the plurality of second command address signals unchanged, subtracting a delay of the first command address signal by a half period of the clock signal, thereby obtaining a first logic result of the first XOR calculation result; then, gradually increasing the delay of the first command address signal, and updating the first XOR calculation result after each increase of the delay of the first command address signal, until a second logic result of the first XOR calculation result is obtained, which is opposite to the first logic result of the first XOR calculation result; then, gradually increasing the delay of the first command address signal, and updating the first XOR calculation result after each increase of the delay of the first command address signal, until a third logic result of the first XOR calculation result is obtained, which is opposite to the second logic result of the first XOR calculation result; using the delay of the first command address signal corresponding to the third logic result of the first XOR calculation result as the first edge determination result.

[0009] In a possible implementation of the first aspect of the present application, the second edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, and the sampling includes: keeping delays of the plurality of second command address signals unchanged, increasing a delay of the first command address signal by one period of the clock signal to obtain a fourth logic result of the first XOR calculation result; then, increasing the delay of the first command address signal step by step, and updating the first XOR calculation result after each increase of the delay of the first command address signal until a fifth logic result of the first XOR calculation result is obtained, the fifth logic result of the first XOR calculation result being opposite to the fourth logic result of the first XOR calculation result; then, increasing the delay of the first command address signal step by step, and updating the first XOR calculation result after each increase of the delay of the first command address signal until a sixth logic result of the first XOR calculation result is obtained, the sixth logic result of the first XOR calculation result being opposite to the fifth logic result of the first XOR calculation result; and using the delay of the first command address signal corresponding to the sixth logic result of the first XOR calculation result as the second edge determination result.

[0010] In a possible implementation of the first aspect of the present application, the third edge determination result is a sampling result of a left edge of a valley region of the first command address signal obtained by sampling the first command address signal using a falling edge of the clock signal as a sampling signal, and the sampling includes: keeping delays of the plurality of second command address signals unchanged, subtracting a delay of the first command address signal by half a period of the clock signal to obtain a first logic result of the second XOR calculation result; then, increasing the delay of the first command address signal step by step, and updating the second XOR calculation result after each increase of the delay of the first command address signal until a second logic result of the second XOR calculation result is obtained, the second logic result of the second XOR calculation result being opposite to the first logic result of the second XOR calculation result; then, increasing the delay of the first command address signal step by step, and updating the second XOR calculation result after each increase of the delay of the first command address signal until a third logic result of the second XOR calculation result is obtained, the third logic result of the second XOR calculation result being opposite to the second logic result of the second XOR calculation result; and using the delay of the first command address signal corresponding to the third logic result of the second XOR calculation result as the third edge determination result.

[0011] In a possible implementation of the first aspect of the application, the fourth edge determination result is a sampling result of a left edge of a peak region of the first command address signal, which is obtained by sampling the first command address signal using a falling edge of the clock signal as a sampling signal, and the sampling comprises: keeping the delays of the plurality of second command address signals unchanged, increasing the delay of the first command address signal by one cycle of the clock signal to obtain a fourth logic result of the second XOR calculation result; then, gradually increasing the delay of the first command address signal, and updating the second XOR calculation result after each increase of the delay of the first command address signal until a fifth logic result of the second XOR calculation result is obtained, which is opposite to the fourth logic result of the second XOR calculation result; then, gradually increasing the delay of the first command address signal, and updating the second XOR calculation result after each increase of the delay of the first command address signal until a sixth logic result of the second XOR calculation result is obtained, which is opposite to the fifth logic result of the second XOR calculation result; and using the delay of the first command address signal corresponding to the sixth logic result of the second XOR calculation result as the fourth edge determination result.

[0012] In a possible implementation of the first aspect of the application, the first edge determination result and the second edge determination result are respectively determined by detecting two continuous logic jump points of the first XOR calculation result in a process of gradually increasing the delay of the first command address signal from a corresponding initial delay, wherein the initial delay corresponding to the first edge determination result is a half cycle of the clock signal in a negative direction, and the initial delay corresponding to the second edge determination result is a single cycle of the clock signal in a positive direction.

[0013] In a possible implementation of the first aspect of the application, in the process of gradually increasing the delay of the first command address signal from the initial delay corresponding to the first edge determination result, the two continuous logic jump points of the first XOR calculation result correspond to a right edge of a valley region of the first command address signal and a left edge of the valley region of the first command address signal, and in the process of gradually increasing the delay of the first command address signal from the initial delay corresponding to the second edge determination result, the two continuous logic jump points of the first XOR calculation result correspond to a right edge of a peak region of the first command address signal and a left edge of the peak region of the first command address signal.

[0014] In a possible implementation manner of the first aspect of the present application, the third edge determination result and the fourth edge determination result are respectively determined by detecting two continuous logic jump points of the second XOR calculation result in a process of gradually increasing the delay of the first command address signal from a corresponding initial delay, wherein the initial delay corresponding to the third edge determination result is a half cycle of the clock signal in negative number, and the initial delay corresponding to the fourth edge determination result is a single cycle of the clock signal in positive number.

[0015] In a possible implementation manner of the first aspect of the present application, in the process of gradually increasing the delay of the first command address signal from the initial delay corresponding to the third edge determination result, the two continuous logic jump points of the second XOR calculation result correspond to the right edge of the valley region of the first command address signal and the left edge of the valley region of the first command address signal, and in the process of gradually increasing the delay of the first command address signal from the initial delay corresponding to the fourth edge determination result, the two continuous logic jump points of the second XOR calculation result correspond to the right edge of the peak region of the first command address signal and the left edge of the peak region of the first command address signal.

[0016] In a possible implementation manner of the first aspect of the present application, the first XOR calculation result and the second XOR calculation result are both implemented by an XOR calculation function of a register clock driver on the receiving side of the command address bus, and during the execution of the training method by the register clock driver, a check signal transmitted by a check signal line corresponding to the command address bus is pulled low.

[0017] In a possible implementation manner of the first aspect of the present application, the first XOR calculation result and the second XOR calculation result are both implemented by an XOR calculation circuit on the receiving side of the command address bus, and the XOR calculation circuit takes the first sampling result set or the second sampling result set as input.

[0018] In a possible implementation of the first aspect of the present application, any three of the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result are obtained by sampling the first command address signal using a rising edge of the clock signal or a falling edge of the clock signal as a sampling signal, and the last one of the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result other than the any three is obtained by calculating using a half-wave width of a peak region of the first command address signal or a half-wave width of a valley region of the first command address signal.

[0019] In a possible implementation of the first aspect of the present application, the peak region and the valley region of the first test signal are periodically and alternately distributed, including that the first test signal is a periodic signal with a duty cycle of 50%, or the first test signal is a periodic signal with a duty cycle other than 50%.

[0020] In a possible implementation of the first aspect of the present application, the peak region and the valley region of the first test signal are periodically and alternately distributed, including that a mode of the first test signal is periodically flipped according to a preset rule.

[0021] In a possible implementation of the first aspect of the present application, the mode of the first test signal is periodically flipped according to a preset rule, including that the mode of the first test signal is flipped in a manner of "010101".

[0022] In a possible implementation of the first aspect of the present application, the other command address signal lines in the second command address signal line set other than the even number of command address signal lines are pulled high or pulled low.

[0023] In a possible implementation of the first aspect of the present application, the inverted signal of the first test signal is sent to all the command address signal lines in the second command address signal line set.

[0024] In a possible implementation of the first aspect of the present application, the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result are used to determine a duty cycle quality of the clock signal.

[0025] In a possible implementation of the first aspect of the present application, the communication protocol associated with the command address bus comprises: a multiplexed dual inline memory module, a reduced load dual inline memory module, a fourth generation double data rate, a fifth generation double data rate, and a double data rate memory physical layer interface protocol version 5.1.

[0026] In a possible implementation of the first aspect of the present application, the training method further comprises: performing the training procedure for each of the plurality of command address signal lines, thereby determining a plurality of delay values corresponding to the plurality of command address signal lines respectively; training a register clock driver at a receiving side of the command address bus, thereby determining a working voltage of a plurality of configuration registers of the register clock driver, wherein the plurality of command address signal lines are input to the plurality of configuration registers respectively, and the working voltage of the plurality of configuration registers is used to make a plurality of half-wave widths corresponding to the plurality of command address signal lines respectively meet a preset waveform requirement under a plurality of delay values corresponding to the plurality of command address signal lines respectively; and updating the plurality of delay values corresponding to the plurality of command address signal lines respectively based on left and right edge data under the working voltage of the plurality of configuration registers respectively.

[0027] In a possible implementation of the first aspect of the present application, the training procedure further comprises: after calibrating the first command address signal line using the first delay value, determining an optimal working voltage of a first configuration register by traversing working voltages of the first configuration register, wherein the first command address signal line is input to the first configuration register of a register clock driver at a receiving side of the command address bus; determining left and right edge data of the first command address signal under the optimal working voltage of the first configuration register, and then determining a second delay value based on a center point algorithm, wherein the second delay value and the optimal working voltage of the first configuration register are used for adaptation between the first command address signal line and the first configuration register.

[0028] In a possible implementation of the first aspect of the application, after the first command address signal line is calibrated using the first delay value, the optimal working voltage of the first configuration register is determined by traversing the working voltage of the first configuration register, including: determining the change trend of the delay margin of the first command address signal relative to the change of the working voltage of the first configuration register by traversing the working voltage of the first configuration register; determining the optimal working voltage of the first configuration register based on the change trend of the delay margin of the first command address signal, the optimal working voltage of the first configuration register corresponding to a single maximum delay margin of the first command address signal, or a center point position of multiple maximum delay margins of the first command address signal.

[0029] In a possible implementation of the first aspect of the application, after the first command address signal line is calibrated using the first delay value, the optimal working voltage of the first configuration register is determined by traversing the working voltage of the first configuration register, including: determining the half-wave width and duty cycle of the first command address signal at the optimal working voltage of the first configuration register by traversing the working voltage of the first configuration register, the half-wave width and duty cycle meeting a preset training target.

[0030] In a possible implementation of the first aspect of the application, the working frequency of the command address bus is not less than 5200 MHz, and the working mode of the command address bus is a double data rate mode.

[0031] In a possible implementation of the first aspect of the application, the command address bus is used for a fourth generation double data rate synchronous dynamic random access memory or a fifth generation double data rate synchronous dynamic random access memory, and the training method is executed by a training firmware of a physical layer of the double data rate synchronous dynamic random access memory.

[0032] In a second aspect, the present application provides a training device for a command address bus. The training device comprises a training firmware deployed on a chip physical layer, the training firmware being configured to calibrate a plurality of command address signal lines included in the command address bus. The training firmware is configured to perform a training procedure for each of the plurality of command address signal lines one by one. A first command address signal line is a command address signal line of the plurality of command address signal lines corresponding to the training procedure. A second command address signal line set is a set of command address signal lines of the plurality of command address signal lines other than the first command address signal line. A clock signal is a clock signal transmitted by a clock signal line corresponding to the command address bus. The training procedure comprises: receiving a first command address signal transmitted through the first command address signal line, and receiving a plurality of second command address signals transmitted through the command address signal lines included in the second command address signal line set. A first test signal is sent to the first command address signal line. The first test signal has a peak region and a valley region periodically alternatingly distributed. An inverted signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set. Based on the plurality of second command address signals, a rising edge of the clock signal is used as a sampling signal to determine a first edge determination result of a left edge of the valley region of the first command address signal and a second edge determination result of a left edge of the peak region of the first command address signal. Based on the plurality of second command address signals, a falling edge of the clock signal is used as a sampling signal to determine a third edge determination result of a left edge of the valley region of the first command address signal and a fourth edge determination result of a left edge of the peak region of the first command address signal. An intersection between the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result is used to determine a first delay value. The first delay value is used for calibration of the first command address signal line.

[0033] Through the second aspect of the present application, by requiring the peak region and the valley region of the first test signal to be periodically alternately distributed, and by requiring the inverted signal of the first test signal to be sent to an even number of command address signal lines in the second command address signal line set, unlike just a simple pull-up mode or a simple pull-down mode, through the regular change of the first test signal, the influence of the code interference factor can be better highlighted, and the anti-interference ability under the condition of poor test signal quality can be better simulated, which helps to test the performance of a complex system under extreme conditions, and also considers the influence of signal integrity and power integrity, which helps to improve the signal transmission quality and power supply stability; by obtaining four edge determination results, that is, by obtaining the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, the sampling scenarios of the rising edge and the falling edge of the clock signal are covered, and the margin of the rising edge and the falling edge of the clock signal and the duty cycle of the clock signal itself are considered, which helps to improve the signal quality of the command address signal, so as to better adapt to the performance difference of the hardware on the receiving side; in this way, the training of the command address bus is realized, which ensures that the command address signal is correctly received, not only fully considers the influence of factors such as device characteristics, path delay, layout of lines, signal quality, but also considers the comprehensive analysis of signal integrity and power integrity, improves the accuracy of training and signal stability, and is beneficial to meet the needs of high-performance memories in state alignment and synchronization, supports higher data transmission rate and higher working frequency, and helps to meet the needs of data transmission and high-speed interconnection in applications such as data centers, high-performance servers, and artificial intelligence infrastructure. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0035] Figure 1 A schematic diagram of a memory provided by an embodiment of the present application;

[0036] Figure 2 A flowchart of a command address bus training method provided by an embodiment of the present application;

[0037] Figure 3 A first signal waveform diagram of a command address bus training method provided by an embodiment of the present application according to Figure 2

[0038] Figure 4 ​According to the embodiments provided in this application Figure 2 The diagram shows the second signal waveform of the training method for the command address bus.

[0039] Figure 5 According to the embodiments provided in this application Figure 2 The diagram shows the third signal waveform of the training method for the command address bus.

[0040] Figure 6 According to the embodiments provided in this application Figure 2 The diagram shows the fourth signal waveform of the training method for the command address bus.

[0041] Figure 7 This is a schematic diagram of a command address bus training device provided in an embodiment of this application. Detailed Implementation

[0042] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0043] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0044] Figure 1 This is a schematic diagram of a memory provided in an embodiment of this application. Figure 1 As shown, the memory 100 includes a controller 102 and a memory chip 104. For example, assume the memory 100 is a fourth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR4 SDRAM) or a fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR5 SDRAM). The controller 102 can be a DDR controller, and the memory chip 104 can be a DDR device. To achieve high-speed interconnection between the DDR controller and the DDR device, a parallel interface connection scheme can be adopted. Specifically, the controller 102 and the memory chip 104 can interact via multiple signal lines. Figure 1 The diagram shows the Command Address (CA) bus 110, also called the DCA bus or CA bus. It may include, for example, 7 signal lines such as CA (6:0), which are responsible for transmitting operation commands such as read, write, activate, etc., as well as transmitting row addresses or column addresses. Figure 1The memory 100 further includes a check signal line 120 for transmitting a check signal, such as a parity signal, for verifying whether the transmission of the command address bus 110 is correct. In addition, Figure 1 The memory 100 further includes a chip select (CS) line 130 for transmitting a chip select signal. The memory 100 can include any number of memory cells 104, and the controller 102 can perform corresponding memory operations, such as performing a read operation, a write operation, and the like, by sending various signals to the memory cells 104. Depending on the specific topology of the memory 100 and the specific locations of the memory cells 104, the length of the traces between the controller 102 and the memory cells 104 can vary. In addition, there can be variations in transmission delay and timing characteristics due to device characteristics, such as rise time, fall time, setup time, and hold time. In addition, there can be issues with the quality of the clock signal transmitted through the clock (CK) signal line, such as an undesirable duty cycle, which means that the margins of the rising and falling edges of the clock signal can cause inter-symbol interference (ISI) issues. In high-speed interface and high-speed circuit applications, as the operating frequency increases, such as requiring an operating frequency of no less than 5200 megahertz, the quality of the signal transmission and the stability of the power supply can be affected, and therefore, a comprehensive analysis of signal integrity and power integrity (SIPI) needs to be considered. As such, due to device characteristics, path delay, trace layout, signal quality, and the like, the command address signals transmitted to different memory cells 104 can have different delays, and the multiple signal lines in the same command address bus 110 can also have different delays, and therefore, the command address bus 110 needs to be trained to ensure that the command address signals can be correctly received, thereby satisfying the requirements for state alignment and synchronization. In addition, Figure 1The controller 102 can include various suitable circuits, devices to implement corresponding functions, such as a command generator, an address generator, an interface, and the like, which are not shown. The storage grain 104 can also include various circuits and storage unit arrays to implement corresponding functions. The following will be described in detail in combination with specific embodiments of the present application and the accompanying drawings. The training method and training device of the command address bus provided by the present application realize the training of the command address bus, ensure that the command address signals are correctly received, fully consider the influence of factors such as device characteristics, path delay, layout of lines, signal quality, and also consider the comprehensive analysis of signal integrity and power integrity, improve the accuracy of training and signal stability, which is conducive to meeting the needs of high-performance storage in state alignment and synchronization, supporting higher data transmission rate and higher working frequency, and helping to meet the needs of data transmission and high-speed interconnection of applications such as data centers, high-performance servers, and artificial intelligence infrastructure.

[0045] Figure 2 The flowchart of the training method of the command address bus provided by the embodiments of the present application is shown. The command address bus includes a plurality of command address signal lines. As shown in Figure 2 The training method includes the following steps.

[0046] Step S201: The training process is executed for each of the plurality of command address signal lines. The first command address signal line is the command address signal line corresponding to the training process in the plurality of command address signal lines. The second command address signal line set is a set of command address signal lines other than the first command address signal line in the plurality of command address signal lines. The clock signal is the clock signal transmitted by the clock signal line corresponding to the command address bus. The training process executed for each command address signal line is illustrated below taking the first command address signal line as an example.

[0047] Step S203: Receive the first command address signal transmitted through the first command address signal line, and receive a plurality of second command address signals transmitted through the command address signal lines included in the second command address signal line set. The first test signal is sent to the first command address signal line, the peak region and the valley region of the first test signal are periodically and alternately distributed, and the inverse signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set.

[0048] Step S205: based on the plurality of second command address signals, using rising edges of the clock signal as sampling signals to determine a first edge determination result of a left edge of a trough region of the first command address signal and a second edge determination result of a left edge of a peak region of the first command address signal, and based on the plurality of second command address signals, using falling edges of the clock signal as sampling signals to determine a third edge determination result of a left edge of the trough region of the first command address signal and a fourth edge determination result of a left edge of the peak region of the first command address signal.

[0049] Step S207: determining a first delay value by using an intersection between the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result, wherein the first delay value is used for calibration of the first command address signal line.

[0050] Referring to Figure 2 , Figure 2The training method of the command address bus shown can be applied to application scenarios of high-performance memories such as DDR5 SDRAM or DDR4 SDRAM, and supports the standard DFI5.1 protocol. In the application scenario of DDR5 SDRAM, the receiving side also includes a registering clock driver (RCD) for signal enhancement driving of the address and control signals of the memory. Taking DDR5 as an example, the interface defines that the command address bus is 7 signal lines CA(6:0). The input of the RCD includes 7 bits of CA signals, 1 bit of parity signal (PAR), and 2 bits of chip select signal (CS). The working mode of the command address bus can be divided into a double data rate (DDR) mode and a single data rate (SDR) mode. In the application scenario of high-speed interfaces and high-speed circuits, the DDR mode is generally used to pursue higher system performance. In the DDR mode, the width of the command address signal is only half of the width of the clock signal, and when the rate is low, the influence of voltage and time delay deviation is limited, but when the rate increases to a certain extent such as 5200 megabits per second and above, the influence of voltage and time delay deviation becomes very obvious, thereby possibly becoming a performance bottleneck of the entire system. Therefore, taking the application scenario of DDR5 SDRAM as an example, higher requirements are put forward for the working frequency, and if the voltage configuration of the RCD used to receive the signal is inaccurate, or the time delay configuration is inaccurate, the execution of the command may be affected, for example, causing the system to feed back a parity error when reading and writing the memory. In addition to being sensitive to voltage and time delay deviation, at a higher working frequency, the performance difference between different RCD products also needs to be considered, so the CA signal quality needs to be improved to adapt to the RCD products. Device characteristics such as the rise time, fall time, setup time, and hold time of the circuit device may also cause differences in transmission delay and timing characteristics. Therefore, the influence of the register rise and fall time caused by the voltage configuration of the RCD needs to be considered. In addition, as the transmission rate and working frequency increase, the influence of inter-symbol interference caused by environmental factors and the like on system performance is more obvious, so the challenges brought by complex and variable application environments need to be simulated in the training process. In addition, at a higher working frequency such as 5200 megahertz and above, the duty cycle problem of the clock signal may be more prominent, and the influence of the margin of the rising edge and falling edge of the clock signal is more obvious, which may cause inter-symbol interference problems and may also affect signal transmission quality and power supply stability, which further puts higher requirements on configuration accuracy.

[0051] With reference to Figure 2In step S201, the training procedure is performed for each of the plurality of command address signal lines, the first command address signal line is the command address signal line corresponding to the training procedure among the plurality of command address signal lines, the second command address signal line set is a set of command address signal lines other than the first command address signal line among the plurality of command address signal lines, and the clock signal is a clock signal transmitted by the clock signal line corresponding to the command address bus. Thus, taking the DDR5 SRAM as an example, the command address signal bus includes 7 signal lines, such as CA(6:0), that is, the command address bus includes 7 command address signal lines, numbered CA0, CA1, CA2, CA3, CA4, CA5, and CA6. The training method of the command address bus includes performing the training procedure for each of the command address signal lines, that is, 7 training procedures are required for the 7 command address signal lines of the DDR5 SRAM, and each training procedure is performed for a specific command address signal line among the 7 command address signal lines. For example, the training procedure can be performed for the command address signal line CA0, and then the training procedure is performed for the other command address signal lines CA1, CA2, CA3, CA4, CA5, and CA6 in sequence. It should be understood that the number of command address signal lines included in the command address bus can be set according to the specific interface standard, and can also be adapted to new standards and new communication protocols that can be published after the filing date of the present application. For example, the number of command address signal lines included in the command address bus can be 11, 13, 15, or any number. Therefore, for the plurality of command address signal lines included in the command address bus, as long as the training procedure is performed for each of the command address signal lines in sequence, and the training procedures corresponding to the plurality of command address signal lines are executed in a serial relationship as a whole, the training requirement of the command address bus with any number of command address signal lines, or the command address bus with any bit number, can be met. In addition, the execution order of the training procedures corresponding to the plurality of command address signal lines can be arbitrary, that is, the training procedure can be performed for each of the plurality of command address signal lines in any order. Taking the command address bus defined by the DDR5 SRAM as an example, the training procedure can be performed for the command address signal line CA0 first and then for the command address signal line CA1, or the training procedure can be performed for the command address signal line CA1 first and then for the command address signal line CA0.The first command address signal line can refer to any one of the plurality of command address signal lines, and the description of the training procedure is that the first command address signal line is taken as the execution object of the current training procedure, that is, in order to facilitate the description of the training procedure executed for each command address signal line, the first command address signal line is taken as the command address signal line corresponding to the training procedure. Moreover, the second command address signal line set refers to the set of other command address signal lines except the first command address signal line in the plurality of command address signal lines. Taking the command address bus defined by the DDR5 SRAM as an example, the first command address signal line can be command address signal line CA0, the training procedure is the training procedure executed for command address signal line CA0, and the second command address signal line set refers to other command address signal lines CA1, CA2, CA3, CA4, CA5, and CA6. In addition, the clock signal is the clock signal transmitted by the clock signal line corresponding to the command address bus. Therefore, for the plurality of command address signal lines included in the command address bus, the clock signal line and the clock signal are shared.

[0052] With reference to the foregoing Figure 2In step S203, the first command address signal transmitted through the first command address signal line is received, and a plurality of second command address signals transmitted through the command address signal lines included in the second command address signal line set are received. The first test signal is sent to the first command address signal line, the peak region and the valley region of the first test signal are periodically and alternately distributed, and the inverse signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set. In this way, in the training process for each command address signal line, taking the training process corresponding to the first command address signal line as an example, the first test signal is sent to the first command address signal line, and the inverse signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set. For example, taking the command address bus defined by DDR5 SRAM as an example, the first command address signal line can be command address signal line CA0, the first test signal is sent to command address signal line CA0, and the inverse signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set (CA1, CA2, CA3, CA4, CA5, CA6), such as 2, 4, and 6. Moreover, optimization design is proposed for the first test signal, that is, the peak region and the valley region of the first test signal are periodically and alternately distributed. Here, the peak region can correspond to the signal pull-up part, such as the high level state, and the valley region can correspond to the signal pull-down part, such as the low level state. By requiring the peak region and the valley region of the first test signal to be periodically and alternately distributed, the first test signal is limited to have regular variation characteristics and meet the variation law of the periodically and alternately distributed peak region and valley region. In contrast, the inverse signal of the first test signal also has regular variation characteristics. Therefore, the first test signal and the inverse signal of the first test signal that meet the requirements can be constructed by any suitable signal generation circuit and sent to the corresponding command address signal line. For example, a signal code type that meets the requirements can be constructed by designing a state machine or an encoder. The waveform of the first test signal can be designed as a square wave, a sine wave, or other waveforms, as long as it meets the specific distribution requirements of the peak region and the valley region. For example, the first test signal can be a periodic signal that regularly jumps between two levels every half clock cycle.It should be understood that by requiring the peak region and the valley region of the first test signal to be periodically and alternately distributed, this is different from simply a pattern of pulling high or a pattern of pulling low, and by regular changes of the first test signal, the influence of the code interference factor can be better highlighted, and the anti-interference capability under the condition of poor test signal quality can be better simulated, which is helpful for testing the performance of a complex system under extreme conditions, and also takes into account the influence of signal integrity and power integrity (SIPI), which is helpful for improving signal transmission quality and power supply stability. In addition, by requiring the inverted signal of the first test signal to be sent to an even number of command address signal lines in the second command address signal line set, this is helpful for subsequent logical calculation to better highlight the influence of various interference factors such as noise, and thus the performance of the system under extreme conditions can be better tested. In this way, by optimizing the design of the test signal, the training of the delay configuration, i.e., the training of the delay value, can better meet the accuracy requirements under high-speed data transmission rate and under high working frequency. To some extent, the flip pattern of the first test signal basically determines the performance or error rate of the calibrated system under high-speed data transmission rate. In some embodiments, the first test signal can adopt a flip pattern of “010101” or a flip pattern of “0100101001” or other flip patterns that periodically and regularly flip, in order to meet the design requirement that the peak region and the valley region of the first test signal are periodically and alternately distributed. By sending the first test signal to the first command address signal line and sending the inverted signal of the first test signal to an even number of command address signal lines in the second command address signal line set, the sampling results of the first command address signal line and the sampling results of other command address signal lines in the second command address signal line set can be logically calculated, such as exclusive or logical calculation, so that the influence of noise can be reflected by comparison, achieving the purpose of calibration. In some embodiments, the flip pattern of the first test signal is “010101”, and the width of the peak region and the valley region is the same and alternately continuous, for example, an ideal clock signal with a duty cycle of 50% can be used as the first test signal, which is helpful for maximizing the influence of noise. In other embodiments, the test signal can also be a reference clock signal with a duty cycle of non-50%, for example, the flip pattern of the first test signal is “001001001”.In some embodiments, the first test signal is sent to the first command address signal line and the inverse of the first test signal is sent to an even number of command address signal lines in the second command address signal line set, and for the remaining command address signal lines in the second command address signal line set, a forced high or a forced low can be taken, which means that the contribution made by the first command address signal line in the subsequent logic calculation, such as an XOR logic calculation, should exactly cancel out the contribution made by the even number of command address signal lines, so that the influence of various interference factors can be highlighted through the logic calculation result, thereby improving the calibration effect. Taking the command address bus defined by the DDR5 SRAM as an example, the first command address signal line can be command address signal line CA0, and the first test signal is sent to command address signal line CA0, and the inverse of the first test signal is sent to an even number of command address signal lines in the second command address signal line set (CA1, CA2, CA3, CA4, CA5, CA6), such as 2, 4, and 6. In this way, it can be seen that 2, 4, or 6 command address signal lines receive the inverse of the first test signal, and command address signal line CA0 receives the first test signal, so that by performing an XOR logic calculation on the sampling results of all command address signal lines, the contribution of command address signal line CA0 should exactly cancel out the contribution of the 2, 4, or 6 command address signal lines. In addition, in combination with the delay configuration, by detecting the jump point of the logic calculation result, that is, the jump point of the logic state from 0 to 1 or from 1 to 0, it is helpful to find a suitable delay value.

[0053] With continued reference to Figure 2At step S205, based on the plurality of second command address signals, the rising edge of the clock signal is used as a sampling signal to determine a first edge determination result of the left edge of the trough region of the first command address signal and a second edge determination result of the left edge of the peak region of the first command address signal, and based on the plurality of second command address signals, the falling edge of the clock signal is used as a sampling signal to determine a third edge determination result of the left edge of the trough region of the first command address signal and a fourth edge determination result of the left edge of the peak region of the first command address signal. As described above, in the training process of each command address signal line, taking the training process corresponding to the first command address signal line as an example, the first test signal is sent to the first command address signal line and the inverted signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set, and through the optimization design of the first test signal, the first test signal is limited to have the characteristics of regular change and meet the change rule that the peak region and the trough region are periodically and alternately distributed. Here, taking the training process corresponding to the first command address signal line as an example, based on the plurality of second command address signals, the rising edge of the clock signal is used as a sampling signal to obtain the first edge determination result and the second edge determination result, and the falling edge of the clock signal is used as a sampling signal to obtain the third edge determination result and the fourth edge determination result. In this way, the first edge determination result corresponds to the left edge of the trough region of the first command address signal, so it covers the scene of sampling and edge determination of the left edge of the trough region (or the pull-down region) using the rising edge of the clock signal. The second edge determination result corresponds to the left edge of the peak region of the first command address signal, so it covers the scene of sampling and edge determination of the left edge of the peak region (or the pull-up region) using the rising edge of the clock signal. In addition, the third edge determination result corresponds to the left edge of the trough region of the first command address signal, so it covers the scene of sampling and edge determination of the left edge of the trough region (or the pull-down region) using the falling edge of the clock signal. The fourth edge determination result corresponds to the left edge of the peak region of the first command address signal, so it covers the scene of sampling and edge determination of the left edge of the peak region (or the pull-up region) using the falling edge of the clock signal. In this way, by obtaining the four edge determination results, i.e., by obtaining the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, the sampling scenarios of the rising edge and the falling edge of the clock signal are covered at the same time, and considering the margin of the rising edge and the falling edge of the clock signal and the duty cycle of the clock signal itself, the code interference problem caused by poor clock signal quality (for example, the duty cycle of the clock signal is not 50%) can be effectively overcome.It should be understood that, taking the training process corresponding to the first command address signal line as an example, based on the plurality of second command address signals, the sampling clock edge (rising edge or falling edge) of the corresponding clock signal is used to obtain the corresponding edge determination result, and a total of four edge determination results are obtained. In the process of obtaining each edge determination result, the adjustment operation of the time delay configuration can be combined, for example, according to a certain delay value, the selected command address signal line, that is, the first command address signal line corresponding to the current training process, is moved in the timing operation, while the other command address signal lines remain unchanged. In this way, by moving the direction and the size of the movement, the jump point of the logic calculation result, that is, the jump point of the logic state from 0 to 1 or from 1 to 0, can help to find the appropriate delay value, and thus the corresponding edge determination result can be determined. And taking the training process corresponding to the first command address signal line as an example, the corresponding operations of the four edge determination results correspond to each other, and can be executed in any order, as long as all four edge determination results are finally obtained.

[0054] With continued reference to Figure 2At step S207, a first delay value is determined by using an intersection between the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, where the first delay value is used for calibration of the first command address signal line. In this way, by using four edge determination results, i.e., the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, the first delay value finally used for calibration of the first command address signal line can be determined by calculating the intersection between the four edge determination results. In some embodiments, taking the application scenario of DDR5 SDRAM as an example, the receiving side further includes a registering clock driver (RCD), and the influence of the device characteristics such as the rise and fall times of the register caused by the voltage configuration of the RCD needs to be considered, so the voltage configuration of the RCD is required to be accurate and the time delay configuration is required to be accurate, i.e., the voltage and time delay deviation are more sensitive and the working frequency and the configuration accuracy are generally required to be higher. In this way, by obtaining four edge determination results, i.e., by obtaining the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, while covering the sampling scenarios of the rising edge and the falling edge of the clock signal, and considering the margin of the rising edge and the falling edge of the clock signal and the duty cycle problem of the clock signal itself, the signal quality of the command address signal can be improved, so as to better adapt to the performance difference of the RCD. Moreover, by optimizing the design of the test signal, the influence of various interference factors such as noise can be better highlighted, so as to better test the performance of the system under extreme conditions, simulate the challenges brought by complex and changeable application environments in the training process, and in this way, the training of the time delay configuration, i.e., the delay value, can better meet the accuracy requirements under high-speed data transmission rate and under high working frequency. In some embodiments, the training of the time delay configuration and the training of the RCD voltage configuration can be combined in the training method of the command address bus, for example, the combination of the reference voltage (Vref) of the RCD voltage and the pull-up and pull-down states of the command address signal line can be used to determine the reference voltage with the maximum duty cycle, or a suitable center point algorithm can be used to determine the center point position, so that the trained command address signal line can not only adapt to the hardware of the RCD, but also effectively overcome the inter-symbol interference caused by complex signal patterns and the signal quality problems of the clock signal itself such as duty cycle reduction.

[0055] In summary, Figure 2The training method of the command address bus shown, by requiring the peak area and the valley area of the first test signal to be periodically alternately distributed, and by requiring the inverted signal of the first test signal to be sent to an even number of command address signal lines in the second command address signal line set, thus different from just a simple pull-up mode or a simple pull-down mode, through the regular change of the first test signal, the influence of the code interference factor can be better highlighted, and the anti-interference ability under the condition of poor test signal quality can also be better simulated, which is helpful for testing the performance of complex systems under extreme conditions, and also takes into account the influence of signal integrity and power integrity, which is helpful for improving signal transmission quality and power supply stability; by obtaining four edge determination results, that is, by obtaining the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, while covering the sampling scenarios of the rising edge and the falling edge of the clock signal, and taking into account the margin of the rising edge and the falling edge of the clock signal and the duty cycle problem of the clock signal itself, it is helpful to improve the signal quality of the command address signal, so as to better adapt to the performance difference of the hardware on the receiving side; in this way, the training of the command address bus is realized, ensuring that the command address signal is correctly received, not only fully considering the influence of factors such as device characteristics, path delay, layout of traces, signal quality, but also considering the comprehensive analysis of signal integrity and power integrity, improving the accuracy of training and signal stability, which is helpful to meet the needs of high-performance memories in state alignment and synchronization, support higher data transmission rate and higher working frequency, and help to meet the needs of data centers, high-performance servers, artificial intelligence infrastructure and other applications for data transmission and high-speed interconnection.

[0056] Referring to Figure 2In a possible implementation, the first edge determination result is a sampling result of a left edge of a trough region of the first command address signal obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, the second edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using the rising edge of the clock signal as the sampling signal, the third edge determination result is a sampling result of a left edge of the trough region of the first command address signal obtained by sampling the first command address signal using a falling edge of the clock signal as the sampling signal, and the fourth edge determination result is a sampling result of a left edge of the peak region of the first command address signal obtained by sampling the first command address signal using the falling edge of the clock signal as the sampling signal. In this way, the first edge determination result corresponds to the left edge of the trough region of the first command address signal, and thus covers a scenario of sampling and edge determination of the left edge of the trough region (or the pull-down region) using the rising edge of the clock signal; the second edge determination result corresponds to the left edge of the peak region of the first command address signal, and thus covers a scenario of sampling and edge determination of the left edge of the peak region (or the pull-up region) using the rising edge of the clock signal. In addition, the third edge determination result corresponds to the left edge of the trough region of the first command address signal, and thus covers a scenario of sampling and edge determination of the left edge of the trough region (or the pull-down region) using the falling edge of the clock signal; the fourth edge determination result corresponds to the left edge of the peak region of the first command address signal, and thus covers a scenario of sampling and edge determination of the left edge of the peak region (or the pull-up region) using the falling edge of the clock signal. By obtaining the four edge determination results, that is, by obtaining the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, the sampling scenarios of the rising edge and the falling edge of the clock signal are covered at the same time, and the margin of the rising edge and the falling edge of the clock signal and the duty cycle of the clock signal itself are considered, which helps to improve the signal quality of the command address signal and is conducive to overcoming the problem of poor signal quality of the clock signal, such as an undesirable duty cycle.

[0057] In some embodiments, the first XOR calculation result is obtained by XOR calculation on a first sample result set, and the second XOR calculation result is obtained by XOR calculation on a second sample result set. The first sample result set is all sample results obtained by sampling the first command address signal and the plurality of second command address signals using rising edges of the clock signal, and the second sample result set is all sample results obtained by sampling the first command address signal and the plurality of second command address signals using falling edges of the clock signal. In this way, taking the training process corresponding to the first command address signal line as an example, based on the plurality of second command address signals, the sampling clock edge (rising edge or falling edge) of the corresponding clock signal is used to obtain the corresponding edge determination result, and four edge determination results are obtained in total. In the process of obtaining each edge determination result, the adjustment operation of the time delay configuration can be combined, for example, the selected command address signal line, i.e., the first command address signal line corresponding to the current training process, is moved in the timing operation according to a specific delay value, while the other command address signal lines remain unchanged. In this way, by moving the direction and size, combining the corresponding XOR calculation result, and detecting the jump point of the logic calculation result, i.e., the jump point of the logic state from 0 to 1 or from 1 to 0, the appropriate delay value can be found, and the corresponding edge determination result can be determined. Here, in obtaining the first edge determination result and the second edge determination result, the rising edge of the clock signal is used as the sampling clock edge, and all sample results obtained are the first sample result set, which is applicable to the first XOR calculation result. In contrast, in obtaining the third edge determination result and the fourth edge determination result, the falling edge of the clock signal is used as the sampling clock edge, and all sample results obtained are the second sample result set, which is applicable to the second XOR calculation result. In combination with the above optimization design of the first test signal, the first test signal is sent to the first command address signal line, and the inverted signal of the first test signal is sent to the even number of command address signal lines in the second command address signal line set. This means that in the XOR logic calculation, the contribution made by the first command address signal line should be exactly offset by the contribution made by the even number of command address signal lines, so that the influence of various interference factors can be highlighted through the logic calculation result, thereby improving the calibration effect.

[0058] The following describes how to obtain the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result.

[0059] 1) the first edge determination result is a sampling result of a left edge of a trough region of the first command address signal, which is obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, comprising: keeping the delays of the plurality of second command address signals unchanged, subtracting the delay of the first command address signal by half a period of the clock signal, thereby obtaining a first logic result of the first exclusive-OR calculation result; then, gradually increasing the delay of the first command address signal, and after each increase of the delay of the first command address signal, updating the first exclusive-OR calculation result until a second logic result of the first exclusive-OR calculation result is obtained, which is opposite to the first logic result of the first exclusive-OR calculation result; then, gradually increasing the delay of the first command address signal, and after each increase of the delay of the first command address signal, updating the first exclusive-OR calculation result until a third logic result of the first exclusive-OR calculation result is obtained, which is opposite to the second logic result of the first exclusive-OR calculation result; using the delay of the first command address signal corresponding to the third logic result of the first exclusive-OR calculation result as the first edge determination result. In this way, in combination with the adjustment operation of the delay configuration, for example, moving the selected command address signal line, i.e. the first command address signal line corresponding to the current training process, in terms of timing operation according to a certain delay value while keeping the other command address signal lines unchanged, the direction and size of the movement can help to find the appropriate delay value by detecting the jump point of the logic calculation result, i.e. the jump point of the logic state from 0 to 1 or from 1 to 0, and then the corresponding edge determination result can be determined. First, the delay of the first command address signal is adjusted according to a certain initial delay value (here, it refers to subtracting half a period of the clock signal), while keeping the delays of the plurality of second command address signals unchanged, thereby obtaining a first logic result. Then, taking the initial position of the first command address signal after adjustment as the starting point, gradually increasing the delay of the first command address signal, and sampling (here, it refers to the first sampling result set, i.e. all sampling results obtained by sampling the first command address signal and the plurality of second command address signals using the rising edge of the clock signal) and updating the corresponding exclusive-OR calculation result (here, it refers to updating the first exclusive-OR calculation result) using the specified sampling clock edge of the clock signal. It should be understood that the delay of the first command address signal can be gradually increased according to any suitable step, for example, by any suitable delay adjustment circuit or encoder, etc. With the gradual movement of the first command address signal in terms of timing operation while keeping the delays of the plurality of second command address signals unchanged, the jump of the corresponding exclusive-OR calculation result may be triggered, i.e. the jump point of the logic state from 0 to 1 or from 1 to 0.Here, by setting three kinds of logic results, the first logic result, the second logic result opposite to the first logic result, and the third logic result opposite to the second logic result. Therefore, taking the initial position of the adjusted first command address signal as the starting point, gradually increasing the delay of the first command address signal, the first jump point is detected first, that is, the second logic result, and then the second jump point is detected, that is, the third logic result, so as to realize the edge detection of the left and right edges. The first jump point corresponds to the right edge of the trough region of the first command address signal, and the second jump point corresponds to the left edge of the trough region of the first command address signal. In this way, the optimized design of the above-mentioned sampling aspect, exclusive-OR logic calculation aspect and jump point detection aspect helps to determine the appropriate delay value and the half-wave width of the peak region and the half-wave width of the trough region under the delay value, improve the signal quality and overcome the influence of the duty cycle, and adapt to the hardware performance of the receiving side, such as the influence of adapting the reference voltage of the RCD.

[0060] 2) the second edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, comprising: keeping the delays of the plurality of second command address signals unchanged, increasing the delay of the first command address signal by one cycle of the clock signal to obtain a fourth logic result of the first exclusive-OR calculation result; then, gradually increasing the delay of the first command address signal, and updating the first exclusive-OR calculation result after each increase of the delay of the first command address signal until a fifth logic result of the first exclusive-OR calculation result opposite to the fourth logic result of the first exclusive-OR calculation result is obtained; then, gradually increasing the delay of the first command address signal, and updating the first exclusive-OR calculation result after each increase of the delay of the first command address signal until a sixth logic result of the first exclusive-OR calculation result opposite to the fifth logic result of the first exclusive-OR calculation result is obtained; using the delay of the first command address signal corresponding to the sixth logic result of the first exclusive-OR calculation result as the second edge determination result. In this way, in combination with the adjustment operation of the delay configuration, for example, moving the selected command address signal line, i.e., the first command address signal line corresponding to the current training process, in the timing operation by a certain delay value while keeping other command address signal lines unchanged, the moving direction and the moving size can help find a suitable delay value through the detection of the jumping point of the logic calculation result, i.e., the jumping point of the logic state from 0 to 1 or from 1 to 0, and thus the corresponding edge determination result can be determined. First, the delay of the first command address signal is adjusted (here, it refers to increasing the delay of the clock signal by one cycle) according to a certain initial delay value while keeping the delays of the plurality of second command address signals unchanged to obtain the fourth logic result. Then, taking the initial position of the first command address signal after the adjustment as the starting point, the delay of the first command address signal is gradually increased, and the sampling clock edge of the specified clock signal is used for sampling (here, it refers to the first sampling result set, i.e., all sampling results obtained by sampling the first command address signal and the plurality of second command address signals using the rising edge of the clock signal) and the corresponding exclusive-OR calculation result is updated (here, it refers to updating the first exclusive-OR calculation result). It should be understood that the delay of the first command address signal can be gradually increased by any suitable step, for example, by any suitable delay adjustment circuit or encoder, etc. With the gradual moving of the first command address signal in the timing operation while keeping the delays of the plurality of second command address signals unchanged, the jumping of the corresponding exclusive-OR calculation result, i.e., the jumping point of the logic state from 0 to 1 or from 1 to 0, can be triggered.Here, by setting three kinds of logic results, the fourth logic result, the fifth logic result opposite to the fourth logic result, and the sixth logic result opposite to the fifth logic result. Therefore, taking the initial position of the adjusted first command address signal as the starting point, gradually increasing the delay of the first command address signal, the first jump point is detected first, that is, the fifth logic result, and then the second jump point is detected, that is, the sixth logic result, so as to realize the edge detection of the left and right edges. The first jump point corresponds to the right edge of the peak region of the first command address signal, and the second jump point corresponds to the left edge of the peak region of the first command address signal. In this way, the optimized design of the above-mentioned sampling aspect, exclusive or logic calculation aspect and jump point detection aspect helps to determine the appropriate delay value and the half-wave width of the peak region and the half-wave width of the valley region under the delay value, helps to improve the signal quality and overcome the influence of the duty cycle, and is conducive to adapting to the hardware performance of the receiving side, such as adapting to the influence of the reference voltage of the RCD.

[0061] 3) the third edge determination result is a sampling result of a left edge of a trough region of the first command address signal, which is obtained by sampling the first command address signal using a falling edge of the clock signal as a sampling signal, comprising: keeping the delays of the plurality of second command address signals unchanged, subtracting a delay of the first command address signal by half a period of the clock signal, thereby obtaining a first logic result of the second XOR calculation result; then, gradually increasing the delay of the first command address signal, and after each increase of the delay of the first command address signal, updating the second XOR calculation result until a second logic result of the second XOR calculation result is obtained, which is opposite to the first logic result of the second XOR calculation result; then, gradually increasing the delay of the first command address signal, and after each increase of the delay of the first command address signal, updating the second XOR calculation result until a third logic result of the second XOR calculation result is obtained, which is opposite to the second logic result of the second XOR calculation result; using the delay of the first command address signal corresponding to the third logic result of the second XOR calculation result as the third edge determination result. In this way, in combination with the adjustment operation of the delay configuration, for example, moving the selected command address signal line, i.e. the first command address signal line corresponding to the current training process, in terms of timing operation according to a certain delay value while keeping the other command address signal lines unchanged, the direction and size of the movement can help to find the appropriate delay value by detecting the jumping point of the logic calculation result, i.e. the jumping point of the logic state from 0 to 1 or from 1 to 0, and then the corresponding edge determination result can be determined. First, adjust the delay of the first command address signal according to a certain initial delay value (here, it refers to subtracting half a period of the clock signal), while keeping the delays of the plurality of second command address signals unchanged, thereby obtaining the first logic result. Then, taking the initial position of the first command address signal after adjustment as the starting point, gradually increasing the delay of the first command address signal, and sampling (here, it refers to the second sampling result set, i.e. all sampling results obtained by sampling the first command address signal and the plurality of second command address signals using the falling edge of the clock signal) using the specified sampling clock edge of the clock signal, and updating the corresponding XOR calculation result (here, it refers to updating the second XOR calculation result). It should be understood that the delay of the first command address signal can be gradually increased by any suitable step, for example, by any suitable delay adjustment circuit or encoder, etc. With the gradual movement of the first command address signal in terms of timing operation while keeping the delays of the plurality of second command address signals unchanged, the jumping of the corresponding XOR calculation result may be triggered, i.e. the jumping point of the logic state from 0 to 1 or from 1 to 0.Here, by setting three kinds of logic results, the first logic result, the second logic result opposite to the first logic result, and the third logic result opposite to the second logic result. Therefore, taking the initial position of the adjusted first command address signal as the starting point, gradually increasing the delay of the first command address signal, the first jump point is detected first, that is, the second logic result, and then the second jump point is detected, that is, the third logic result, so as to realize the edge detection of the left and right edges. The first jump point corresponds to the right edge of the trough region of the first command address signal, and the second jump point corresponds to the left edge of the trough region of the first command address signal. In this way, the optimized design of the above-mentioned sampling aspect, exclusive-OR logic calculation aspect and jump point detection aspect helps to determine the appropriate delay value and the half-wave width of the peak region and the half-wave width of the trough region under the delay value, improve the signal quality and overcome the influence of the duty cycle, and adapt to the hardware performance of the receiving side, such as the influence of adapting the reference voltage of the RCD.

[0062] 4) the fourth edge determination result is a sampling result of a left edge of a peak region of the first command address signal, which is obtained by sampling the first command address signal using a falling edge of the clock signal as a sampling signal, comprising: keeping the delays of the plurality of second command address signals unchanged, increasing the delay of the first command address signal by one cycle of the clock signal to obtain a fourth logic result of the second XOR calculation result; then, gradually increasing the delay of the first command address signal, and updating the second XOR calculation result after each increase of the delay of the first command address signal until a fifth logic result of the second XOR calculation result is obtained, which is opposite to the fourth logic result of the second XOR calculation result; then, gradually increasing the delay of the first command address signal, and updating the second XOR calculation result after each increase of the delay of the first command address signal until a sixth logic result of the second XOR calculation result is obtained, which is opposite to the fifth logic result of the second XOR calculation result; using the delay of the first command address signal corresponding to the sixth logic result of the second XOR calculation result as the fourth edge determination result. In this way, in combination with the adjustment operation of the delay configuration, for example, moving the selected command address signal line, i.e. the first command address signal line corresponding to the current training process, in terms of timing operation according to a certain delay value while keeping the other command address signal lines unchanged, the moving direction and the moving size can help to find a suitable delay value by detecting the jump point of the logic calculation result, i.e. the jump point of the logic state from 0 to 1 or from 1 to 0, and then the corresponding edge determination result can be determined. First, the delay of the first command address signal is adjusted according to a certain initial delay value (here, it refers to increasing the delay of the first command address signal by one cycle of the clock signal) while keeping the delays of the plurality of second command address signals unchanged to obtain the fourth logic result. Then, taking the initial position of the first command address signal after adjustment as the starting point, the delay of the first command address signal is gradually increased, and the sampling clock edge of the specified clock signal is used for sampling (here, it refers to the second sampling result set, i.e. all sampling results obtained by sampling the first command address signal and the plurality of second command address signals using the falling edge of the clock signal) and updating the corresponding XOR calculation result (here, it refers to updating the second XOR calculation result). It should be understood that the delay of the first command address signal can be gradually increased according to any suitable step, for example, by any suitable delay adjustment circuit or encoder, etc. With the gradual movement of the first command address signal in terms of timing operation while keeping the delays of the plurality of second command address signals unchanged, the jump of the corresponding XOR calculation result may be triggered, i.e. the jump point of the logic state from 0 to 1 or from 1 to 0.Here, by setting three logic results, a fourth logic result, a fifth logic result opposite to the fourth logic result, and a sixth logic result opposite to the fifth logic result. Therefore, taking the initial position of the adjusted first command address signal as the starting point, gradually increasing the delay of the first command address signal, the first jump point is detected first, that is, the fifth logic result, and then the second jump point is detected, that is, the sixth logic result, so as to realize the edge detection of the left and right edges. The first jump point corresponds to the right edge of the peak region of the first command address signal, and the second jump point corresponds to the left edge of the peak region of the first command address signal. In this way, the optimized design of the above-mentioned sampling aspect, the exclusive-OR logic calculation aspect and the jump point detection aspect helps to determine the appropriate delay value and the half-wave width of the peak region and the half-wave width of the valley region under the delay value, helps to improve the signal quality and overcome the influence of the duty cycle, and is conducive to adapting to the hardware performance of the receiving side, such as adapting to the influence of the reference voltage of the RCD.

[0063] Referring to Figure 2, the first edge determination result is a sampling result of a left edge of a trough region of the first command address signal obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, the second edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using the rising edge of the clock signal as the sampling signal, the third edge determination result is a sampling result of a left edge of a trough region of the first command address signal obtained by sampling the first command address signal using a falling edge of the clock signal as the sampling signal, and the fourth edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using the falling edge of the clock signal as the sampling signal. After obtaining the four edge determination results, the four edge determination results can be intersected to determine a suitable delay configuration, or a suitable voltage configuration of RCD in the application scenario of DDR5 SDRAM. It should be understood that the execution processes corresponding to the four edge determination results described above can be executed in any order, for example, the execution processes can be executed in the order of 1), 2), 3), and 4), or the execution processes can be executed in the order of 4), 3), 2), and 1), as long as all four edge determination results are finally obtained. In addition, it can be seen that the execution processes corresponding to the four edge determination results described above use a specified sampling clock edge of the clock signal for sampling, and adjust the delay of the first command address signal according to a specific initial delay value, and then gradually increase the delay of the first command address signal from the initial position of the adjusted first command address signal as the starting point, so as to detect two transition points corresponding to the exclusive or calculation result, and further achieve the edge detection of the left and right edges. In this way, through the execution processes corresponding to the four edge determination results, the sampling scenarios of the rising and falling edges of the clock signal are covered at the same time, and the margin of the rising and falling edges of the clock signal and the duty cycle of the clock signal itself are considered, which is helpful to determine a suitable delay value and the half-wave width of the peak region and the half-wave width of the trough region under the delay value.

[0064] In some embodiments, the first edge determination result and the second edge determination result are determined by detecting, in a process of gradually increasing the delay of the first command address signal from a corresponding initial delay, two consecutive logic transition points of the first XOR calculation result, wherein the initial delay corresponding to the first edge determination result is a half cycle of the clock signal in negative, and the initial delay corresponding to the second edge determination result is a single cycle of the clock signal in positive. In this way, with the optimized design of sampling, XOR logic calculation and transition point detection, it is helpful to determine the appropriate delay value and the half wave width of the peak region and the half wave width of the valley region under the delay value, to improve the signal quality and overcome the influence of the non-ideal duty cycle, and to adapt to the hardware performance of the receiving side, such as the influence of adapting the reference voltage of the RCD. In addition, by setting the corresponding initial delay, the logic transition point detection mechanism can be reused, which is helpful to improve the circuit reuse rate and save hardware cost.

[0065] In some examples, in a process of gradually increasing the delay of the first command address signal from an initial delay corresponding to the first edge determination result, the two consecutive logic transition points of the first XOR calculation result correspond to the right edge of the valley region of the first command address signal and the left edge of the valley region of the first command address signal, and in a process of gradually increasing the delay of the first command address signal from an initial delay corresponding to the second edge determination result, the two consecutive logic transition points of the first XOR calculation result correspond to the right edge of the peak region of the first command address signal and the left edge of the peak region of the first command address signal. In this way, the left and right edge detection is realized, which is helpful to determine the appropriate delay value and the half wave width of the peak region and the half wave width of the valley region under the delay value, to improve the signal quality and overcome the influence of the non-ideal duty cycle. In addition, by XOR calculation on the corresponding sample result set, it means that the command address signal of the receiving side can be sampled and XOR logic calculation can be performed by the firmware of the physical layer of the memory, which simplifies the circuit design and reduces the control complexity.

[0066] In some embodiments, the third edge determination result and the fourth edge determination result are determined by detecting, in a process of gradually increasing the delay of the first command address signal from a corresponding initial delay, two consecutive logic jump points of the second XOR calculation result, wherein the initial delay corresponding to the third edge determination result is a half cycle of the clock signal in negative number, and the initial delay corresponding to the fourth edge determination result is a single cycle of the clock signal in positive number. In this way, with the optimized design of sampling aspect, XOR logic calculation aspect and jump point detection aspect, it is helpful to determine the appropriate delay value and the half wave width of the peak region and the half wave width of the valley region under the delay value, to improve the signal quality and overcome the impact of the non-ideal duty cycle, and to adapt to the hardware performance of the receiving side, such as the impact of adapting the reference voltage of the RCD. In addition, by setting the corresponding initial delay, the logic jump point detection mechanism can be reused, which is helpful to improve the circuit reuse rate and save hardware cost.

[0067] In some examples, in a process of gradually increasing the delay of the first command address signal from an initial delay corresponding to the third edge determination result, two consecutive logic jump points of the second XOR calculation result correspond to the right edge of the valley region of the first command address signal and the left edge of the valley region of the first command address signal, and in a process of gradually increasing the delay of the first command address signal from an initial delay corresponding to the fourth edge determination result, two consecutive logic jump points of the second XOR calculation result correspond to the right edge of the peak region of the first command address signal and the left edge of the peak region of the first command address signal. In this way, the left and right edge detection is realized, which is helpful to determine the appropriate delay value and the half wave width of the peak region and the half wave width of the valley region under the delay value, to improve the signal quality and overcome the impact of the non-ideal duty cycle. In addition, by XOR calculation on the corresponding sample result set, it means that the command address signal of the receiving side can be sampled and XOR logic calculation can be performed by the firmware of the physical layer of the memory, which simplifies the circuit design and reduces the control complexity.

[0068] In some embodiments, the first XOR calculation result and the second XOR calculation result are both implemented by an XOR calculation function of a register clock driver at a receiving side of the command address bus, and a check signal transmitted by a check signal line corresponding to the command address bus is pulled low during execution of the training method by the register clock driver. In the application scenario of DDR5 SDRAM, the receiving side further includes a registering clock driver (RCD). In this way, the training method of the command address bus is implemented by using the XOR calculation function of the RCD itself. In addition, because the XOR calculation of the RCD itself takes all command address signal lines (CA lines) and check signal lines (DPAR lines) as inputs, in order to avoid the influence of the check signal line on the XOR calculation, the check signal transmitted by the check signal line corresponding to the command address bus is forced to be pulled low, for example, to 0.

[0069] In some embodiments, the first XOR calculation result and the second XOR calculation result are both implemented by an XOR calculation circuit at a receiving side of the command address bus, which takes the first sampling result set or the second sampling result set as input. In this way, the training method of the command address bus is implemented by using the XOR calculation circuit at the receiving side. This is helpful for adapting to other DDR standards or other interface standards.

[0070] In a possible implementation, any three of the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result are obtained by sampling the first command address signal using a rising edge of the clock signal or a falling edge of the clock signal as a sampling signal, and the last one of the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result is obtained by calculating using a half-wave width of a peak region of the first command address signal or a half-wave width of a valley region of the first command address signal. As mentioned above, the four edge determination results, i.e., the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result, are obtained to cover the sampling scenarios of the rising edge and the falling edge of the clock signal, and the duty cycle of the clock signal and the margin of the rising edge and the falling edge of the clock signal are considered. The first edge determination result is the sampling result of the left edge of the valley region of the first command address signal obtained by sampling the first command address signal using the rising edge of the clock signal as a sampling signal, the second edge determination result is the sampling result of the left edge of the peak region of the first command address signal obtained by sampling the first command address signal using the rising edge of the clock signal as a sampling signal, the third edge determination result is the sampling result of the left edge of the valley region of the first command address signal obtained by sampling the first command address signal using the falling edge of the clock signal as a sampling signal, and the fourth edge determination result is the sampling result of the left edge of the peak region of the first command address signal obtained by sampling the first command address signal using the falling edge of the clock signal as a sampling signal. Therefore, the four edge determination results can be obtained by the sampling edge of the corresponding clock signal, or three of the four edge determination results can be obtained by sampling and the fourth edge determination result can be obtained by calculation using a half-wave width of a peak region of the first command address signal or a half-wave width of a valley region of the first command address signal. By combining the sampling method and the calculation method, the burden of the sampling circuit can be reduced. If all the four edge determination results are obtained by sampling, i.e., the specified sampling clock edge of the clock signal is used for sampling, and the delay of the first command address signal is adjusted according to a specific initial delay value, then the initial position of the adjusted first command address signal is taken as a starting point, and the delay of the first command address signal is gradually increased, so that the two transition points of the corresponding exclusive or calculation result are detected, and the edge detection of the left and right edges is realized.In this way, the four edge determination results are respectively executed by sampling, which helps to meet the pressure test requirements in mass production, and is also conducive to dealing with the influence of peak or valley changes caused by the voltage configuration changes of the RCD.

[0071] In a possible implementation, the peak region and the valley region of the first test signal are periodically and alternately distributed, including that the first test signal is a periodic signal with a duty cycle of 50%, or the first test signal is a periodic signal with a duty cycle of non-50%. In some embodiments, the flip mode of the first test signal is a mode of "010101", and the width of the peak region and the valley region is the same and alternately continuous, for example, an ideal clock signal with a duty cycle of 50% can be used as the first test signal, which helps to maximize the noise influence. In other embodiments, the test signal can also be a reference clock signal with a duty cycle of non-50%, for example, the flip mode of the first test signal is a mode of "001001001". In this way, the code type of the flexible test signal is supported, and by designing the first test signal to be a periodic signal with a duty cycle of 50%, the noise influence is maximized, which helps to better highlight the influence of various interference factors such as noise through subsequent logic calculation, and thus the performance of the system under extreme conditions can be better tested.

[0072] In a possible implementation, the peak region and the valley region of the first test signal are periodically and alternately distributed, including that the mode of the first test signal is periodically flipped according to a preset rule. In this way, the test signal can adopt a flip mode of "010101", or the test signal can adopt a flip mode of "0100101001", or the test signal can adopt other flip modes that are periodic and regularly flipped, in order to meet the design requirement that the peak region and the valley region of the first test signal are periodically and alternately distributed. By sending the first test signal to the first command address signal line and sending the inverse signal of the first test signal to an even number of command address signal lines in the second command address signal line set, in this way, the sampling results of the first command address signal line and the sampling results of other command address signal lines in the second command address signal line set can be logically calculated, for example, exclusive or logical calculation, so that the influence of noise can be reflected by comparison, achieving the purpose of calibration.

[0073] In some embodiments, the pattern of the first test signal is periodically flipped according to a preset rule, including: the pattern of the first test signal is flipped in a manner of "010101". The flipping pattern of the first test signal is "010101", and the width of the peak region and the valley region is the same and alternates continuously, for example, an ideal clock signal with a duty cycle of 50% can be used as the first test signal, so as to maximize the influence of noise. It is helpful to better highlight the influence of various interference factors such as noise through subsequent logic calculation, and thus the performance of the system under extreme conditions can be better tested.

[0074] In a possible implementation, the other command address signal lines in the second command address signal line set except the even number of command address signal lines are pulled high or low. The first test signal is sent to the first command address signal line and the inverse signal of the first test signal is sent to the even number of command address signal lines in the second command address signal line set, and for the remaining command address signal lines in the second command address signal line set, a forced high or low can be taken, which means that in the subsequent logic calculation, for example, the contribution of the first command address signal line should be exactly offset by the contribution of the even number of command address signal lines, so that the influence of various interference factors can be highlighted through the logic calculation result, and thus the calibration effect is improved.

[0075] In a possible implementation, the inverted signal of the first test signal is sent to all command address signal lines in the second command address signal line set. Taking the command address bus defined in DDR5 SRAM as an example, the first command address signal line can be command address signal line CA0, the first test signal is sent to command address signal line CA0, and the inverted signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set (CA1, CA2, CA3, CA4, CA5, CA6), such as 2, 4, and 6. As can be seen, 2, 4, or 6 command address signal lines receive the inverted signal of the first test signal, and command address signal line CA0 receives the first test signal. Therefore, by performing exclusive-OR logical calculation on the sampling results of all command address signal lines, the contribution of command address signal line CA0 should exactly offset the contribution of 2, 4, or 6 command address signal lines. In addition, in combination with the delay configuration, by detecting the jump point of the logical calculation result, that is, the jump point of the logical state from 0 to 1 or from 1 to 0, a suitable delay value can be found. In this way, by requiring the inverted signal of the first test signal to be sent to all command address signal lines in the second command address signal line set, the noise influence is maximized, the influence of the code interference factor can be better highlighted, the anti-interference ability under the condition of poor test signal quality can be better simulated, the performance of the complex system under extreme conditions can be tested, and the influence of signal integrity and power integrity is also considered, which helps to improve the signal transmission quality and power supply stability.

[0076] In a possible implementation, the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result are used to determine the duty cycle quality of the clock signal. The execution process corresponding to each of the above four edge determination results uses a specified sampling clock edge of the clock signal for sampling, and adjusts the delay of the first command address signal according to a specific initial delay value, and then takes the initial position of the adjusted first command address signal as the starting point, gradually increases the delay of the first command address signal, thereby detects two jump points of the corresponding exclusive-OR calculation result, and further realizes the edge detection of the left and right edges. In this way, through the execution process corresponding to each of the four edge determination results, the sampling scenarios of the rising edge and the falling edge of the clock signal are covered, and the margin of the rising edge and the falling edge of the clock signal and the duty cycle of the clock signal itself are considered. Further, the four edge determination results are used to determine the duty cycle quality of the clock signal, which helps to calibrate the result.

[0077] In one possible implementation, the communication protocol associated with the command address bus includes: a Multiplexed Rank Dual In-line Memory Module (MRDIMM), a Load Reduced Dual In-line Memory Module (LRDIMM), a Double Data Rate 4 (DDR4), a Double Data Rate 5 (DDR5), and a Double Data Rate Memory Physical Layer Interface (DDR PHY Interface, DFI) protocol version 5.1. In this way, the DDR5 protocol and related derivative protocols are supported, as well as various high performance memory application scenarios.

[0078] In a possible implementation, the training method further comprises: performing the training procedure for each of the plurality of command address signal lines one by one, so as to determine a plurality of delay values corresponding to the plurality of command address signal lines respectively; training a register clock driver at a receiving side of the command address bus, so as to determine a working voltage of each of a plurality of configuration registers of the register clock driver, wherein the plurality of command address signal lines are input to the plurality of configuration registers respectively, and the working voltage of each of the plurality of configuration registers is used to make a plurality of half-wave widths of the plurality of command address signal lines respectively corresponding to the plurality of delay values meet a preset waveform requirement; and updating the plurality of delay values corresponding to the plurality of command address signal lines respectively based on left and right edge data at the working voltage of each of the plurality of configuration registers. In the application scenario of DDR5 SDRAM, the receiving side further comprises a register clock driver (RCD), and the influence of the voltage configuration of the RCD on the device characteristics such as the rise and fall times of the register needs to be considered, and therefore the voltage configuration of the RCD and the delay configuration need to be accurate, that is, the RCD is more sensitive to voltage and delay deviation and generally requires a higher working frequency and higher configuration accuracy. In this way, the training of the delay configuration and the training of the RCD voltage configuration can be combined in the training method of the command address bus, and on the basis of the training of the delay configuration, the working voltage of the configuration register applied to the register clock driver is adjusted, so that after the half-wave width of a specified command address signal line is determined, the working voltage of the corresponding configuration register can be trained, so that the working voltage can be traversed to observe the influence on the half-wave width, and then a suitable working voltage can be determined. For example, the reference voltage (Vref) of the RCD voltage and the combination of the pull-up and pull-down states of the command address signal line can be used to traverse the reference voltage to determine the reference voltage with the maximum duty cycle, or a suitable center point algorithm can be used to determine the center point position, so that the trained command address signal line can not only adapt to the hardware of the RCD, but also effectively overcome the code interference caused by complex signal patterns and the signal quality problems of the clock signal itself such as the decrease of the duty cycle.

[0079] In a possible implementation, the training procedure further comprises: after calibrating the first command address signal line using the first delay value, determining an optimal working voltage of the first configuration register by traversing the working voltage of the first configuration register, wherein the first command address signal line is input to the first configuration register of the register clock driver on the receiving side of the command address bus; determining the left and right edge data of the first command address signal at the optimal working voltage of the first configuration register, and then determining a second delay value based on a center point algorithm, wherein the second delay value and the optimal working voltage of the first configuration register are used for the adaptation between the first command address signal line and the first configuration register. In this way, the training of the time delay configuration and the training of the RCD voltage configuration are combined in the training method of the command address bus, so that the training target can be divided into two levels. The first level of training target is the delay value training between the clock signal line and the plurality of command address signal lines, and the respective delay value and the half-wave width under the delay value are determined by serially training the delay value of each command address signal line. The second level of training target is to realize the hardware adaptation of the RCD on the receiving side to which the plurality of command address signal lines are input, and the influence of the working voltage of the configuration register on the device performance such as the rise and fall time of the register is specifically considered. By serially training the working voltage of the corresponding configuration register of each command address signal line, the working voltage value of the configuration register of the RCD is traversed to determine that the rising edge and the falling edge of the corresponding command address signal line meet the training target, for example, the duty cycle is optimal, under the appropriate working voltage. Here, the influence of the waveform distortion and the difference between the rise time and the fall time of the device itself is considered, and the influence of the fact that the clock signal and the command address signal in the actual application may not meet the ideal duty cycle of 50% is also considered. Therefore, finally determined are the delay value of the command address signal line, that is, the time delay configuration, and the optimal working voltage of the corresponding configuration register for the voltage configuration of the RCD, so that not only the hardware of the RCD can be adapted, but also the code interference caused by the complex signal mode and the signal quality problem of the clock signal itself such as the decrease of the duty cycle can be effectively overcome.

[0080] In some embodiments, after the first command address signal line is calibrated using the first delay value, the optimal working voltage of the first configuration register is determined by traversing the working voltage of the first configuration register, including: determining the change trend of the delay margin of the first command address signal relative to the change of the working voltage of the first configuration register by traversing the working voltage of the first configuration register; determining the optimal working voltage of the first configuration register based on the change trend of the delay margin of the first command address signal, the optimal working voltage of the first configuration register corresponding to a single maximum delay margin of the first command address signal, or a center point position of multiple maximum delay margins of the first command address signal. In this way, the four edge determination results described above can be intersected by the physical layer (PHY) of the memory, so as to obtain the combined effect of a certain command address signal line in the low and high states under a certain working voltage, and the RCD adaptation can be realized by traversing the working voltage in the outer layer. After obtaining the change trend of the delay margin after traversing the entire working voltage, the working voltage with the maximum margin or the center point position of multiple maximum margins is taken as the working voltage configuration of the corresponding command address signal line, so that the command address signal line can work at the appropriate working voltage. Using the left and right edge data under this working voltage and using the center point algorithm, the command address signal can work at the appropriate delay. In this way, the time delay configuration training and working voltage configuration training corresponding to the first command address signal line are realized, the accuracy and signal stability of the training are improved, the demand for state alignment and synchronization of high-performance memory is met, a higher data transmission rate and a higher working frequency are supported, and the demand for data transmission and high-speed interconnection of data center, high-performance server, artificial intelligence infrastructure and other applications is met.

[0081] In some embodiments, after the first command address signal line is calibrated using the first delay value, the optimal working voltage of the first configuration register is determined by traversing the working voltage of the first configuration register, including: determining the half-wave width and duty cycle of the first command address signal under the optimal working voltage of the first configuration register by traversing the working voltage of the first configuration register, so as to meet the preset training target. In this way, the time delay configuration training and working voltage configuration training corresponding to the first command address signal line are realized, and the accuracy and signal stability of the training are improved.

[0082] In a possible implementation, the working frequency of the command address bus is not less than 5200MHz, and the working mode of the command address bus is a double data rate mode. In this way, higher data transmission rate and higher working frequency are supported, which helps to meet the demand for data transmission and high-speed interconnection in applications such as data centers, high-performance servers, artificial intelligence infrastructure, and the like.

[0083] In a possible implementation, the command address bus is used for a fourth generation double data rate synchronous dynamic random access memory or a fifth generation double data rate synchronous dynamic random access memory, and the training method is performed by a training firmware of a physical layer of the double data rate synchronous dynamic random access memory. In this way, the training of the command address bus is implemented, ensuring that the command address signals are correctly received, not only considering the influence of factors such as device characteristics, path delay, wire layout, and signal quality, but also considering the comprehensive analysis of signal integrity and power integrity, thereby improving the accuracy of the training and the stability of the signals.

[0084] Figure 3 The method provided in the embodiments of the present application is performed according to the training method provided in the embodiments of the present application. Figure 2The first signal waveform diagram of the training method of the command address bus is shown. Taking DDR5 SRAM as an example, the command address signal bus includes 7 signal lines, such as CA (6:0), that is, the command address bus includes 7 command address signal lines, which are numbered as CA0, CA1, CA2, CA3, CA4, CA5, and CA6. Here, the first command address signal line can refer to any one of the plurality of command address signal lines, and the description of the training process is to take the first command address signal line as the execution object of the current training process, that is, in order to facilitate the description of the training process executed for each command address signal line, the first command address signal line is taken as the command address signal line corresponding to the training process. Moreover, the second command address signal line set refers to the set of other command address signal lines except the first command address signal line. Here, taking the command address bus defined by DDR5 SRAM as an example, the first command address signal line can be command address signal line CA0, the training process is the training process executed for command address signal line CA0, and the second command address signal line set refers to other command address signal lines CA1, CA2, CA3, CA4, CA5, and CA6. In addition, the clock signal is the clock signal transmitted by the clock signal line corresponding to the command address bus, and the clock signal line is represented by TCK. Therefore, for the plurality of command address signal lines (CA0, CA1, CA2, CA3, CA4, CA5, and CA6) included in the command address bus, the clock signal line (TCK) and the clock signal are shared. In addition, DCS refers to the chip select (Chip Select, CS) line. In this way, by corresponding to the plurality of command address signal lines CA0, CA1, CA2, CA3, CA4, CA5, and CA6, and corresponding to the clock signal line TCK, and corresponding to the chip select signal line DCS, the signal waveform diagram is used to demonstrate the use scenario of using the corresponding clock signal sampling edge for sampling and edge determination.

[0085] Referring to Figure 3 , Figure 3The use of the corresponding clock signal sampling edge to sample and determine the use of the scene refers to 1) the first edge determination result is the sampling result of the left edge of the trough area of the first command address signal obtained by sampling the first command address signal using the rising edge of the clock signal as the sampling signal. The specific process includes: keeping the delays of the plurality of second command address signals unchanged, subtracting the delay of the first command address signal by half a period of the clock signal, thereby obtaining the first logic result of the first exclusive or calculation result; then, gradually increase the delay of the first command address signal, and after each increase of the delay of the first command address signal, update the first exclusive or calculation result until the second logic result of the first exclusive or calculation result is obtained, which is opposite to the first logic result of the first exclusive or calculation result; then, gradually increase the delay of the first command address signal, and after each increase of the delay of the first command address signal, update the first exclusive or calculation result until the third logic result of the first exclusive or calculation result is obtained, which is opposite to the second logic result of the first exclusive or calculation result; using the delay of the first command address signal corresponding to the third logic result of the first exclusive or calculation result as the first edge determination result. In this way, the optimized design of the above-mentioned sampling aspect, exclusive or logic calculation aspect and jump point detection aspect helps to determine the appropriate delay value and the half wave width of the peak area and the half wave width of the trough area under the delay value, helps to improve the signal quality and overcome the influence of the duty cycle, and is beneficial to adapt to the hardware performance of the receiving side, such as the influence of adapting the reference voltage of RCD.

[0086] Figure 4 The method provided by the embodiment of the present application is used for Figure 2The second signal waveform schematic diagram of the training method of the command address bus is shown. Taking the DDR5 SRAM as an example, the command address signal bus includes 7 signal lines, such as CA (6:0), that is, the command address bus includes 7 command address signal lines, which are numbered as CA0, CA1, CA2, CA3, CA4, CA5, and CA6. Here, the first command address signal line can refer to any one of the plurality of command address signal lines, and the description of the training process is to take the first command address signal line as the execution object of the current training process, that is, in order to facilitate the description of the training process executed for each command address signal line, the first command address signal line is taken as the command address signal line corresponding to the training process. Moreover, the second command address signal line set refers to the set of other command address signal lines except the first command address signal line in the plurality of command address signal lines. Here, taking the command address bus defined by the DDR5 SRAM as an example, the first command address signal line can be the command address signal line CA0, the training process is the training process executed for the command address signal line CA0, and the second command address signal line set refers to the other command address signal lines CA1, CA2, CA3, CA4, CA5, and CA6. In addition, the clock signal is the clock signal transmitted by the clock signal line corresponding to the command address bus, and the clock signal line is represented by TCK. Therefore, for the plurality of command address signal lines (CA0, CA1, CA2, CA3, CA4, CA5, and CA6) included in the command address bus, the clock signal line (TCK) and the clock signal are shared. In addition, the chip select signal (Chip Select, CS) line is represented by DCS. In this way, by corresponding to the plurality of command address signal lines CA0, CA1, CA2, CA3, CA4, CA5, and CA6, and corresponding to the clock signal line TCK and the chip select signal line DCS, the signal waveform schematic diagram is used to demonstrate the use scenario of using the corresponding clock signal sampling edge for sampling and edge determination.

[0087] Referring to Figure 4 , Figure 4The illustrated use of the corresponding clock signal sampling edge and edge determination refers to 2) the second edge determination result is a sampling result of the left edge of the peak region of the first command address signal obtained by sampling the first command address signal using the rising edge of the clock signal as the sampling signal. The specific process includes: keeping the delays of the plurality of second command address signals unchanged, increasing the delay of the first command address signal according to a single period of the clock signal, thereby obtaining a fourth logic result of the first exclusive or calculation result; then, gradually increasing the delay of the first command address signal, and updating the first exclusive or calculation result after each increase of the delay of the first command address signal until a fifth logic result of the first exclusive or calculation result is obtained, which is opposite to the fourth logic result of the first exclusive or calculation result; then, gradually increasing the delay of the first command address signal, and updating the first exclusive or calculation result after each increase of the delay of the first command address signal until a sixth logic result of the first exclusive or calculation result is obtained, which is opposite to the fifth logic result of the first exclusive or calculation result; using the delay of the first command address signal corresponding to the sixth logic result of the first exclusive or calculation result as the second edge determination result. In this way, the optimized design of the above-mentioned sampling aspect, exclusive or logic calculation aspect and jump point detection aspect helps to determine a suitable delay value and the half-wave width of the peak region and the half-wave width of the valley region under the delay value, helps to improve signal quality and overcome the influence of non-ideal duty cycle, and is conducive to adapting to the hardware performance of the receiving side, such as adapting to the influence of the reference voltage of the RCD.

[0088] Figure 5 The method provided by the embodiment of the present application is used for Figure 2The third signal waveform schematic diagram of the training method of the command address bus is shown. Taking the DDR5 SRAM as an example, the command address signal bus includes 7 signal lines, such as CA (6:0), that is, the command address bus includes 7 command address signal lines, which are numbered as CA0, CA1, CA2, CA3, CA4, CA5, and CA6. Here, the first command address signal line can refer to any one of the plurality of command address signal lines, and the description of the training process is to take the first command address signal line as the execution object of the current training process, that is, in order to facilitate the description of the training process executed for each command address signal line, the first command address signal line is taken as the command address signal line corresponding to the training process. Moreover, the second command address signal line set refers to the set of other command address signal lines except the first command address signal line in the plurality of command address signal lines. Here, taking the command address bus defined by the DDR5 SRAM as an example, the first command address signal line can be the command address signal line CA0, the training process is the training process executed for the command address signal line CA0, and the second command address signal line set refers to the other command address signal lines CA1, CA2, CA3, CA4, CA5, and CA6. In addition, the clock signal is the clock signal transmitted by the clock signal line corresponding to the command address bus, and the clock signal line is represented by TCK. Therefore, for the plurality of command address signal lines (CA0, CA1, CA2, CA3, CA4, CA5, and CA6) included in the command address bus, the clock signal line (TCK) and the clock signal are shared. In addition, the chip select signal (Chip Select, CS) line is represented by DCS. In this way, by corresponding to the plurality of command address signal lines CA0, CA1, CA2, CA3, CA4, CA5, and CA6, and corresponding to the clock signal line TCK and the chip select signal line DCS, the signal waveform schematic diagram is used to demonstrate the use scenario of using the corresponding clock signal sampling edge for sampling and edge determination.

[0089] Referring to Figure 5 , Figure 5The use of the corresponding clock signal sampling edge to sample and determine the use of the scene refers to 3) the third edge determination result is the sampling result of the left edge of the trough area of the first command address signal obtained by sampling the first command address signal using the falling edge of the clock signal as the sampling signal. The specific process includes: keeping the delay of each of the plurality of second command address signals unchanged, subtracting the delay of the first command address signal by half a period of the clock signal, thereby obtaining the first logic result of the second XOR calculation result; then, gradually increase the delay of the first command address signal, and after each increase of the delay of the first command address signal, update the second XOR calculation result until the second logic result of the second XOR calculation result is obtained, which is opposite to the first logic result of the second XOR calculation result; then, gradually increase the delay of the first command address signal, and after each increase of the delay of the first command address signal, update the second XOR calculation result until the third logic result of the second XOR calculation result is obtained, which is opposite to the second logic result of the second XOR calculation result; using the delay of the first command address signal corresponding to the third logic result of the second XOR calculation result as the third edge determination result. In this way, the optimized design of the above-mentioned sampling aspect, XOR logic calculation aspect and jump point detection aspect helps to determine the appropriate delay value and the half-wave width of the peak area and the half-wave width of the trough area under the delay value, helps to improve the signal quality and overcome the influence of the duty cycle, and is beneficial to adapt to the hardware performance of the receiving side, such as the influence of adapting the reference voltage of the RCD.

[0090] Figure 6 The method provided by the embodiment of the present application is used for Figure 2The fourth signal waveform diagram of the training method of the command address bus is shown. Taking the DDR5 SRAM as an example, the command address signal bus includes 7 signal lines, such as CA (6:0), that is, the command address bus includes 7 command address signal lines, which are numbered as CA0, CA1, CA2, CA3, CA4, CA5, and CA6. Here, the first command address signal line can refer to any one of the plurality of command address signal lines, and the description of the training process is to take the first command address signal line as the execution object of the current training process, that is, in order to facilitate the description of the training process executed for each command address signal line, the first command address signal line is taken as the command address signal line corresponding to the training process. Moreover, the second command address signal line set refers to the set of other command address signal lines except the first command address signal line. Here, taking the command address bus defined by the DDR5 SRAM as an example, the first command address signal line can be the command address signal line CA0, the training process is the training process executed for the command address signal line CA0, and the second command address signal line set refers to the other command address signal lines CA1, CA2, CA3, CA4, CA5, and CA6. In addition, the clock signal is the clock signal transmitted by the clock signal line corresponding to the command address bus, and the clock signal line is represented by TCK. Therefore, for the plurality of command address signal lines (CA0, CA1, CA2, CA3, CA4, CA5, and CA6) included in the command address bus, the clock signal line (TCK) and the clock signal are shared. In addition, DCS refers to the chip select (Chip Select, CS) line. In this way, by corresponding to the plurality of command address signal lines CA0, CA1, CA2, CA3, CA4, CA5, and CA6, and corresponding to the clock signal line TCK, and corresponding to the chip select signal line DCS, the signal waveform diagram is used to demonstrate the use scenario of using the corresponding clock signal sampling edge for sampling and edge determination.

[0091] Referring to Figure 6 , Figure 6The use of the corresponding clock signal sampling edge to sample and determine the use scene shown refers to 4) the fourth edge determination result is the sampling result of the left edge of the peak region of the first command address signal obtained by sampling the first command address signal using the falling edge of the clock signal as the sampling signal. The specific process includes: keeping the delays of the plurality of second command address signals unchanged, increasing the delay of the first command address signal according to a single period of the clock signal, thereby obtaining a fourth logic result of the second XOR calculation result; then, gradually increasing the delay of the first command address signal, and updating the second XOR calculation result after each increase of the delay of the first command address signal, until a fifth logic result of the second XOR calculation result is obtained, which is opposite to the fourth logic result of the second XOR calculation result; then, gradually increasing the delay of the first command address signal, and updating the second XOR calculation result after each increase of the delay of the first command address signal, until a sixth logic result of the second XOR calculation result is obtained, which is opposite to the fifth logic result of the second XOR calculation result; using the delay of the first command address signal corresponding to the sixth logic result of the second XOR calculation result as the fourth edge determination result. In this way, the optimized design of the above-mentioned sampling aspect, XOR logic calculation aspect and jump point detection aspect helps to determine a suitable delay value and the half-wave width of the peak region and the half-wave width of the valley region under the delay value, helps to improve signal quality and overcome the influence of an undesirable duty cycle, and is conducive to adapting to the hardware performance of the receiving side, such as adapting to the influence of the reference voltage of the RCD.

[0092] Referring to Figure 3 , Figure 4 , Figure 5 and Figure 6 , through the respective execution processes of the four edge determination results, the sampling scenes of the rising edge and the falling edge of the clock signal are covered, and the margin of the rising edge and the falling edge of the clock signal and the duty cycle of the clock signal itself are considered, which helps to determine a suitable delay value and the half-wave width of the peak region and the half-wave width of the valley region under the delay value.

[0093] Figure 7 A schematic diagram of a command address bus training device provided by an embodiment of the present application. As Figure 7As shown, the training apparatus includes a training firmware 700 deployed on a chip physical layer. The training firmware 700 is configured to calibrate a plurality of command address signal lines included in a command address bus. The training firmware 700 is configured to perform a training procedure for each of the plurality of command address signal lines one by one, a first command address signal line being a command address signal line of the plurality of command address signal lines corresponding to the training procedure, a second command address signal line set being a set of command address signal lines of the plurality of command address signal lines other than the first command address signal line, and a clock signal being a clock signal transmitted by a clock signal line corresponding to the command address bus. In some embodiments, the training firmware 700 includes a sampling circuit 710, a calculation circuit 720, and a delay circuit 730. The training procedure includes: receiving a first command address signal transmitted through the first command address signal line, and receiving a plurality of second command address signals transmitted through command address signal lines included in the second command address signal line set, wherein a first test signal is sent to the first command address signal line, a peak region and a valley region of the first test signal are periodically alternately distributed, and an inverted signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set; based on the plurality of second command address signals, using a rising edge of the clock signal as a sampling signal to determine a first edge determination result of a left edge of the valley region of the first command address signal and a second edge determination result of a left edge of the peak region of the first command address signal, and based on the plurality of second command address signals, using a falling edge of the clock signal as a sampling signal to determine a third edge determination result of a left edge of the valley region of the first command address signal and a fourth edge determination result of a left edge of the peak region of the first command address signal; determining a first delay value using an intersection between the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, wherein the first delay value is used for calibration of the first command address signal line.

[0094] Referring to Figure 7 The sampling circuit 710, the calculation circuit 720, and the delay circuit 730 included in the training firmware 700 are configured to perform corresponding sampling operations, logical calculation operations, and delay adjustment operations. With the optimized design of the sampling aspect, the exclusive-OR logical calculation aspect, and the jump point detection aspect, it is helpful to determine a suitable delay value and the half-wave width of the peak region and the half-wave width of the valley region under the delay value, to improve signal quality and overcome the impact of an undesirable duty cycle, and to adapt to the hardware performance of the receiving side, such as the impact of adapting the reference voltage of the RCD. It should be understood that Figure 7The training firmware 700 shown is only exemplary. The training device of the command address bus can include any firmware, circuit, subsystem, device, etc., and can also incorporate software support on the software side, as long as it can implement the training process for each of the plurality of command address signal lines one by one.

[0095] In summary, Figure 7 The training device of the command address bus shown, by requiring the peak region and the valley region of the first test signal to be periodically and alternately distributed, and by requiring the inverted signal of the first test signal to be sent to an even number of command address signal lines in the second set of command address signal lines, the regular change of the first test signal can better highlight the influence of the code interference factor, and better simulate the anti-interference ability under the condition of poor test signal quality, help to test the performance of the complex system under extreme conditions, and also consider the influence of signal integrity and power integrity, help to improve the signal transmission quality and power supply stability; by obtaining four edge determination results, that is, by obtaining the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result, the sampling scenarios of the rising edge and the falling edge of the clock signal are covered, and the margin of the rising edge and the falling edge of the clock signal and the duty cycle of the clock signal itself are considered, which helps to improve the signal quality of the command address signal, so as to better adapt to the performance difference of the hardware on the receiving side; in this way, the training of the command address bus is realized, and the command address signal is correctly received, not only considering the influence of factors such as device characteristics, path delay, layout of lines, signal quality, but also considering the comprehensive analysis of signal integrity and power integrity, improving the accuracy of training and signal stability, which is beneficial to meet the needs of high-performance memory in state alignment and synchronization, support higher data transmission rate and higher working frequency, and help to meet the needs of data transmission and high-speed interconnection of data center, high-performance server, artificial intelligence infrastructure and other applications.

[0096] The method and device provided by the embodiments of the present application are based on the same inventive concept. Since the principles of the method and device for solving problems are similar, the embodiments, implementation manners, examples or implementation manners of the method and device can be referred to each other, and the repeated parts will not be described herein. The embodiments of the present application also provide a system, which includes a plurality of computing devices. The structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be described herein.

[0097] The embodiment of the present application further provides a computer readable storage medium, wherein computer instructions are stored in the computer readable storage medium, and when the computer instructions are run on a computer device (such as one or more processors), the computer instructions can implement the method steps in the method embodiment described above. The specific implementation of the processor of the computer readable storage medium in executing the method steps described above can refer to the specific operations described in the method embodiment described above and / or the specific functions described in the device embodiment described above, and will not be described here again.

[0098] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. The present application can be in the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. The embodiments of the present application can be realized wholly or partially by software, hardware, firmware or any combination thereof. When realized by software, the above-mentioned embodiments can be realized in the form of a computer program product in whole or in part. The present application can be in the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the above-mentioned embodiments are wholly or partially generated according to the processes or functions described in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, WiFi, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center and the like containing one or more available medium sets. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium or a semiconductor medium. The semiconductor medium can be a solid state disk or a random access memory, a flash memory, a read-only memory, an electrically erasable programmable read-only memory, a register or any other suitable storage medium.

[0099] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in conjunction with the flowcharts described above. Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks or in conjunction with the flowcharts described above. Figure 1 one or more flowcharts and / or blocks Figure 1 Figure 1 one or more flowcharts and / or blocks

[0100] In the above embodiments, the description of each embodiment is focused on respectively, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiments of the present application can be adjusted in sequence, combined or deleted according to actual needs; the modules in the system of the embodiments of the present application can be divided, combined or deleted according to actual needs. If these modifications and variations of the embodiments of the present application belong to the scope of the claims of the present application and the equivalent technologies thereof, the present application also intends to include these modifications and variations.

Claims

1. A method of training a command address bus, the method comprising: The command address bus comprises a plurality of command address signal lines, and the training method comprises performing a training process on each of the plurality of command address signal lines one by one, a first command address signal line is a command address signal line corresponding to the training process among the plurality of command address signal lines, a second command address signal line set is a set of command address signal lines other than the first command address signal line among the plurality of command address signal lines, a clock signal is a clock signal transmitted by a clock signal line corresponding to the command address bus, and the training process comprises: receiving a first command address signal transmitted through the first command address signal line, and receiving a plurality of second command address signals transmitted through the command address signal lines included in the second command address signal line set, wherein a first test signal is sent to the first command address signal line, a peak region and a valley region of the first test signal are periodically alternately distributed, and an inverted signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set; based on the plurality of second command address signals, using a rising edge of the clock signal as a sampling signal to determine a first edge determination result of a left edge of a valley region of the first command address signal and a second edge determination result of a left edge of a peak region of the first command address signal, and based on the plurality of second command address signals, using a falling edge of the clock signal as a sampling signal to determine a third edge determination result of a left edge of a valley region of the first command address signal and a fourth edge determination result of a left edge of a peak region of the first command address signal; determining a first delay value by using an intersection between the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result, wherein the first delay value is used for calibration of the first command address signal line.

2. The training method of claim 1, wherein, The first edge determination result is a sampling result of a left edge of a valley region of the first command address signal obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, the second edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, and the third edge determination result is a sampling result of a left edge of a valley region of the first command address signal obtained by sampling the first command address signal using a falling edge of the clock signal as a sampling signal, and the fourth edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using a falling edge of the clock signal as a sampling signal.

3. The training method of claim 2, wherein, The first exclusive-OR calculation result is obtained by performing exclusive-OR calculation on a first sampling result set, and the second exclusive-OR calculation result is obtained by performing exclusive-OR calculation on a second sampling result set.

4. The training method of claim 3, wherein, The first edge determination result is a sampling result of a left edge of a trough region of the first command address signal obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, and includes: The delay of the first command address signal is reduced by half a period of the clock signal while keeping the delays of the plurality of second command address signals unchanged, thereby obtaining a first logic result of the first exclusive-OR calculation result; Then, the delay of the first command address signal is gradually increased, and the first exclusive-OR calculation result is updated after each increase of the delay of the first command address signal until a second logic result of the first exclusive-OR calculation result is obtained, which is opposite to the first logic result of the first exclusive-OR calculation result; Then, the delay of the first command address signal is gradually increased, and the first exclusive-OR calculation result is updated after each increase of the delay of the first command address signal until a third logic result of the first exclusive-OR calculation result is obtained, which is opposite to the second logic result of the first exclusive-OR calculation result; The delay of the first command address signal corresponding to the third logic result of the first exclusive-OR calculation result is used as the first edge determination result.

5. The training method of claim 3, wherein, The second edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using a rising edge of the clock signal as a sampling signal, and includes: The delay of the first command address signal is increased by one period of the clock signal while keeping the delays of the plurality of second command address signals unchanged, thereby obtaining a fourth logic result of the first exclusive-OR calculation result; Then, the delay of the first command address signal is gradually increased, and the first exclusive-OR calculation result is updated after each increase of the delay of the first command address signal until a fifth logic result of the first exclusive-OR calculation result is obtained, which is opposite to the fourth logic result of the first exclusive-OR calculation result; Then, the delay of the first command address signal is increased step by step, and after each increase of the delay of the first command address signal, the first XOR calculation result is updated until a sixth logic result of the first XOR calculation result is obtained, which is opposite to a fifth logic result of the first XOR calculation result; The delay of the first command address signal corresponding to the sixth logic result of the first XOR calculation result is used as the third edge determination result.

6. The training method of claim 3, wherein, The third edge determination result is a sampling result of a left edge of a trough region of the first command address signal obtained by sampling the first command address signal using a falling edge of the clock signal as a sampling signal, and includes: The delay of the first command address signal is increased by one period of the clock signal while keeping the delays of the plurality of second command address signals unchanged, so as to obtain a fourth logic result of the second XOR calculation result; Then, the delay of the first command address signal is increased step by step, and after each increase of the delay of the first command address signal, the second XOR calculation result is updated until a second logic result of the second XOR calculation result is obtained, which is opposite to the first logic result of the second XOR calculation result; Then, the delay of the first command address signal is increased step by step, and after each increase of the delay of the first command address signal, the second XOR calculation result is updated until a third logic result of the second XOR calculation result is obtained, which is opposite to the second logic result of the second XOR calculation result; The delay of the first command address signal corresponding to the third logic result of the second XOR calculation result is used as the third edge determination result.

7. The training method of claim 3, wherein, The fourth edge determination result is a sampling result of a left edge of a peak region of the first command address signal obtained by sampling the first command address signal using a falling edge of the clock signal as a sampling signal, and includes: The delay of the first command address signal is increased by one period of the clock signal while keeping the delays of the plurality of second command address signals unchanged, so as to obtain a fourth logic result of the second XOR calculation result; Then, the delay of the first command address signal is increased step by step, and after each increase of the delay of the first command address signal, the second XOR calculation result is updated until a fifth logic result of the second XOR calculation result is obtained, which is opposite to the fourth logic result of the second XOR calculation result; Then, the delay of the first command address signal is increased step by step, and after each increase of the delay of the first command address signal, the second XOR calculation result is updated until a sixth logic result of the second XOR calculation result is obtained, which is opposite to the fifth logic result of the second XOR calculation result; The delay of the first command address signal corresponding to the sixth logic result of the second exclusive or calculation result is used as the fourth edge determination result.

8. The training method of claim 3, wherein, The first edge determination result and the second edge determination result are respectively determined by detecting two continuous logic jump points of the first exclusive or calculation result in a process of gradually increasing the delay of the first command address signal from a corresponding initial delay, wherein the initial delay corresponding to the first edge determination result is a half cycle of the clock signal in negative number, and the initial delay corresponding to the second edge determination result is a single cycle of the clock signal in positive number.

9. The training method of claim 8, wherein, In the process of gradually increasing the delay of the first command address signal from the initial delay corresponding to the first edge determination result, the two continuous logic jump points of the first exclusive or calculation result correspond to the right edge of the valley region of the first command address signal and the left edge of the valley region of the first command address signal, and in the process of gradually increasing the delay of the first command address signal from the initial delay corresponding to the second edge determination result, the two continuous logic jump points of the first exclusive or calculation result correspond to the right edge of the peak region of the first command address signal and the left edge of the peak region of the first command address signal.

10. The training method of claim 3, wherein, The third edge determination result and the fourth edge determination result are respectively determined by detecting two continuous logic jump points of the second exclusive or calculation result in a process of gradually increasing the delay of the first command address signal from a corresponding initial delay, wherein the initial delay corresponding to the third edge determination result is a half cycle of the clock signal in negative number, and the initial delay corresponding to the fourth edge determination result is a single cycle of the clock signal in positive number.

11. The training method of claim 10, wherein, In the process of gradually increasing the delay of the first command address signal from the initial delay corresponding to the third edge determination result, the two continuous logic jump points of the second exclusive or calculation result correspond to the right edge of the valley region of the first command address signal and the left edge of the valley region of the first command address signal, and in the process of gradually increasing the delay of the first command address signal from the initial delay corresponding to the fourth edge determination result, the two continuous logic jump points of the second exclusive or calculation result correspond to the right edge of the peak region of the first command address signal and the left edge of the peak region of the first command address signal.

12. The training method of claim 3, wherein, The first exclusive or calculation result and the second exclusive or calculation result are both realized by an exclusive or calculation function of a register clock driver on the receiving side of the command address bus, and a check signal transmitted by a check signal line corresponding to the command address bus is pulled low during the execution of the training method by the register clock driver.

13. The training method of claim 3, wherein, The first exclusive or calculation result and the second exclusive or calculation result are both realized by an exclusive or calculation circuit on the receiving side of the command address bus, and the exclusive or calculation circuit takes the first sampling result set or the second sampling result set as input.

14. The training method of claim 1, wherein, Any three of the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result are obtained by sampling the first command address signal using a rising edge of the clock signal or a falling edge of the clock signal as a sampling signal, and the last one of the first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result is obtained by calculating a half-wave width of a peak region of the first command address signal or a half-wave width of a valley region of the first command address signal.

15. The training method of claim 1, wherein, The peak region and the valley region of the first test signal are periodically and alternately distributed, including that the first test signal is a periodic signal with a duty cycle of 50%, or the first test signal is a periodic signal with a duty cycle of non-50%.

16. The training method of claim 1, wherein, The peak region and the valley region of the first test signal are periodically and alternately distributed, including that the mode of the first test signal is periodically flipped according to a preset rule.

17. The training method of claim 16, wherein, The mode of the first test signal is periodically flipped according to a preset rule, including that the mode of the first test signal is flipped in a manner of "010101".

18. The training method of claim 1, wherein, The other command address signal lines in the set of second command address signal lines except the even number of command address signal lines are pulled high or pulled low.

19. The training method of claim 1, wherein, The inverted signal of the first test signal is sent to all the command address signal lines in the set of second command address signal lines.

20. The training method of claim 1, wherein, The first edge determination result, the second edge determination result, the third edge determination result and the fourth edge determination result are used to determine the duty cycle quality of the clock signal.

21. The training method of claim 1, wherein, The communication protocol associated with the command address bus includes: a multiplexing level dual in-line memory module, a reduced load dual in-line memory module, a fourth generation double data rate, a fifth generation double data rate, and a double data rate memory physical layer interface protocol version 5.

1.

22. The training method of claim 1, wherein, The training method further includes: The training process is performed for each of the plurality of command address signal lines one by one, so as to determine a plurality of delay values corresponding to the plurality of command address signal lines respectively; The register clock driver on the receiving side of the command address bus is trained, so as to determine a working voltage of each of a plurality of configuration registers of the register clock driver, wherein the plurality of command address signal lines are respectively input to the plurality of configuration registers, and the working voltage of each of the plurality of configuration registers is used to make a plurality of half-wave widths corresponding to the plurality of command address signal lines respectively meet a preset waveform requirement under a plurality of delay values corresponding to the plurality of command address signal lines respectively; Based on left and right edge data under the working voltage of each of the plurality of configuration registers, the plurality of delay values corresponding to the plurality of command address signal lines respectively are updated.

23. The training method of claim 1, wherein, The training process further includes: determining an optimal working voltage of the first configuration register by traversing working voltages of the first configuration register after calibrating the first command address signal line using the first delay value, wherein the first command address signal line is input to the first configuration register of the register clock driver at a receiving side of the command address bus; determining left and right edge data of the first command address signal at the optimal working voltage of the first configuration register, and then determining a second delay value based on a center point algorithm, wherein the second delay value and the optimal working voltage of the first configuration register are used for adaptation between the first command address signal line and the first configuration register.

24. The training method of claim 23, wherein, determining an optimal working voltage of the first configuration register by traversing working voltages of the first configuration register after calibrating the first command address signal line using the first delay value, wherein the first command address signal line is input to the first configuration register of the register clock driver at a receiving side of the command address bus; determining a change trend of a delay margin of the first command address signal relative to a change of the working voltage of the first configuration register by traversing the working voltages of the first configuration register; determining an optimal working voltage of the first configuration register based on the change trend of the delay margin of the first command address signal, wherein the optimal working voltage of the first configuration register corresponds to a single maximum delay margin of the first command address signal, or a center point position of multiple maximum delay margins of the first command address signal.

25. The training method of claim 23, wherein, determining an optimal working voltage of the first configuration register by traversing working voltages of the first configuration register after calibrating the first command address signal line using the first delay value, wherein the first command address signal line is input to the first configuration register of the register clock driver at a receiving side of the command address bus; determining a half-wave width and a duty cycle of the first command address signal by traversing the working voltages of the first configuration register, wherein the half-wave width and the duty cycle of the first command address signal at the optimal working voltage of the first configuration register meet a preset training target.

26. The training method of claim 1, wherein, The working frequency of the command address bus is not less than 5200 MHz, and the working mode of the command address bus is a double data rate mode.

27. The training method of claim 1, wherein, The command address bus is used for a fourth generation double data rate synchronous dynamic random access memory or a fifth generation double data rate synchronous dynamic random access memory, and the training method is executed by a training firmware of a physical layer of the double data rate synchronous dynamic random access memory.

28. A training device for a command address bus, characterized by The training device includes a training firmware deployed on a chip physical layer, and the training firmware is used to calibrate a plurality of command address signal lines included in a command address bus. The training firmware is used to execute a training process for each of the plurality of command address signal lines one by one. A first command address signal line is a command address signal line corresponding to the training process in the plurality of command address signal lines. A second command address signal line set is a set of other command address signal lines except the first command address signal line in the plurality of command address signal lines. A clock signal is a clock signal transmitted by a clock signal line corresponding to the command address bus. The training process includes: The first command address signal transmitted through the first command address signal line is received, and a plurality of second command address signals transmitted through the command address signal lines included in the second command address signal line set are received, wherein a first test signal is sent to the first command address signal line, a peak region and a valley region of the first test signal are periodically and alternately distributed, and an inverse signal of the first test signal is sent to an even number of command address signal lines in the second command address signal line set; Based on the plurality of second command address signals, a rising edge of the clock signal is used as a sampling signal to determine a first edge determination result of a left edge of a valley region of the first command address signal and a second edge determination result of a left edge of a peak region of the first command address signal, and based on the plurality of second command address signals, a falling edge of the clock signal is used as a sampling signal to determine a third edge determination result of a left edge of a valley region of the first command address signal and a fourth edge determination result of a left edge of a peak region of the first command address signal; An intersection between the first edge determination result, the second edge determination result, the third edge determination result, and the fourth edge determination result is used to determine a first delay value, wherein the first delay value is used for calibration of the first command address signal line.

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