Convergence preposed time sequence optimization method, device, equipment, medium and product

Abstract

The invention provides a time sequence optimization method and device for convergence preposition, equipment, a medium and a product, and relates to the technical field of computers, in particular to the field of artificial intelligence and chips. According to the specific implementation scheme, all modules are combined into subsystems in a lightweight manner for time sequence analysis, and a cross-module time sequence violation path is obtained; performing path grouping on each cross-module time sequence violation path to obtain at least one path group; according to the time violation value of each cross-module time sequence violation path, allocating a repair weight to each path packet; determining a delay constraint compensation value of each path group according to an actual routing value of each cross-module time sequence violation path in the path end point module; according to each time delay constraint compensation value, each repair weight and the boundary constraint information and clock tree intervention information of the high-repair-level module, a subsystem-level optimization script is generated, and module-level layout and wiring optimization is carried out, so that the time sequence performance and reliability of chip design are improved, later large-scale modification is avoided, and the design efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, in particular to the field of artificial intelligence and chip, and specifically to a convergence-preceding timing optimization method and device, electronic equipment, non-transitory computer-readable storage medium and computer program product. BACKGROUND

[0002] In modern chip design, the hierarchical structure usually includes subsystem level, module level and register transfer level, and the number of layers is more than three. Due to the objective difference of timing under different hierarchical perspectives, when the timing repair under the module level perspective ends and each module is merged into a subsystem, new timing problems will occur under the subsystem.

[0003] In related technologies, after the layout and routing work of the module level is completed, each module is integrated into a subsystem according to a complex merging manner. Timing analysis is performed at the subsystem level, and timing violation information is collected and provided to each module again. The module performs local optimization based on the information to solve the newly occurring timing problems. This method will cause over-repair or under-repair on some timing paths, and thus more optimization times are needed to solve the problems, the process is lengthy, and the chip design efficiency is reduced. SUMMARY

[0004] The present disclosure provides a method, device, equipment and storage medium for convergence-preceding timing optimization.

[0005] According to an aspect of the present disclosure, a convergence-preceding timing optimization method is provided, comprising:

[0006] Lightweight merging of each module currently in the layout and routing stage into a subsystem, and performing timing analysis on the subsystem to obtain a plurality of cross-module timing violation paths;

[0007] Path grouping of each of the cross-module timing violation paths to obtain at least one path group corresponding to each target module;

[0008] According to the actual routing value of each of the cross-module timing violation paths in the path end module, determining a delay constraint compensation value corresponding to each path group of each target module;

[0009] Generating a subsystem-level optimization script according to each of the delay constraint compensation values, and performing optimization of the module-level layout and routing through the subsystem-level optimization script.

[0010] According to another aspect of the present disclosure, a convergence-preceding timing optimization device is also provided, comprising:

[0011] The light-weight merging module is configured to merge light-weight modules currently in a layout and routing stage into a subsystem, and perform timing analysis on the subsystem to obtain a plurality of cross-module timing violation paths;

[0012] The path grouping module is configured to group the cross-module timing violation paths to obtain at least one path group corresponding to each target module;

[0013] The compensation determining module is configured to determine a delay constraint compensation value corresponding to each path group of each target module according to an actual routing value of each cross-module timing violation path in a path end module;

[0014] The module optimization module is configured to generate a subsystem-level optimization script according to the delay constraint compensation values, and perform optimization of module-level layout and routing through the subsystem-level optimization script.

[0015] According to another aspect of the embodiments of the present disclosure, an electronic device is also provided, which includes:

[0016] at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the pre-convergent timing optimization method according to any one of the embodiments of the present disclosure.

[0017] According to another aspect of the embodiments of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is also provided, wherein the computer instructions are used to enable a computer to perform the pre-convergent timing optimization method according to any one of the embodiments of the present disclosure.

[0018] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings are used to better understand the present scheme, and do not limit the present disclosure. Among them:

[0020] Figure 1 is a schematic diagram of a pre-convergent timing optimization method according to an embodiment of the present disclosure;

[0021] Figure 2 is a schematic diagram of another pre-convergent timing optimization method according to an embodiment of the present disclosure;

[0022] Figure 3 is a schematic diagram of still another pre-convergent timing optimization method according to an embodiment of the present disclosure;

[0023] Figure 4 is a specific application scenario applicable to the embodiments of the present disclosure;

[0024] Figure 5 is a structural diagram of a pre-convergence timing optimization device according to an embodiment of the present disclosure;

[0025] Figure 6 is a block diagram of an electronic device for implementing the method of pre-convergence timing optimization according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to assist in understanding, and should be considered as merely exemplary. Thus, those skilled in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of known functions and constructions are omitted in the following description for clarity and conciseness.

[0027] Figure 1 is a schematic diagram of a pre-convergence timing optimization method according to an embodiment of the present disclosure. The embodiments of the present disclosure can be applicable to a case where, in the design phase of an integrated circuit chip, a module-level layout and routing optimization is performed for the timing problems of the discovered inter-module interfaces by adding a subsystem-level delay constraint compensation value. The method can be executed by a pre-convergence timing optimization device. The device can be implemented in hardware and can generally be configured in an electronic device with data processing functions, such as various terminals or servers. In the electronic device, a chip layout tool (software) is generally configured.

[0028] Correspondingly, as shown in Figure 1 , the method can specifically include:

[0029] S110, merging each module currently in the layout and routing stage into a subsystem in a lightweight manner, and performing timing analysis on the subsystem to obtain a plurality of cross-module timing violation paths.

[0030] In the embodiments of the present disclosure, the lightweight merging can be specifically understood as: in the chip design process, the operation of simplifying each module and temporarily combining it into a subsystem in the layout and routing stage. This operation only retains the key information of the inter-module connection and interaction, and does not involve the detailed implementation of the module.

[0031] The subsystem level can be understood as a high level in chip design. A chip can include multiple subsystems, each of which implements a specific function. The subsystem level focuses on the cooperation and communication between different modules to ensure that the modules work together to achieve complex functions. The module level can be understood as a middle level within a subsystem. A subsystem includes multiple modules, each of which completes a specific task. The module level focuses on the implementation of specific functions. The register transfer level can be understood as a specific implementation level of module function design, which describes the flow and processing of data between registers.

[0032] The cross-module timing violation path can be understood as a path in which a signal is transmitted from one module to another module, and due to layout and routing, the signal arrival time does not meet the timing requirements.

[0033] It can be understood that the layout and routing stage of the embodiments of the present disclosure is a multi-round iterative optimization process. Taking the transmission from module A to module B as an example, in the first round of iteration, the module level repair can be performed using fixed values or fixed proportions. For example, if the clock period of the designed chip is 2.5 nanoseconds, module A and module B can be allocated a time delay of 1.25 nanoseconds according to a preset proportion (such as 50%) for timing repair.

[0034] It should be noted that the module level repair in the related art is usually only for repairing each module itself without considering the influence between modules. The module level repair of the embodiments of the present disclosure additionally considers the wire length of the timing violation path within the adjacent module. Specifically, the wire length within the module mentioned in the embodiments can include the wire length within module A and the wire length within module B that have direct connections.

[0035] That is, in the application scenario in which module O, module A, and module B are directly connected in sequence, when performing timing repair on the multiple timing violation paths from module A to module B for module A, the actual wire length of each timing violation path within module B (the path end module) needs to be considered. Alternatively, when performing timing repair on the multiple timing violation paths from module O to module A for module O, the actual wire length of each timing violation path within module A (the path end module) needs to be considered.

[0036] The method of the embodiment is introduced from the second iteration after the first iteration of module-level placement and routing is completed, in which a fixed value or a fixed ratio of the design chip clock cycle is used as the time delay. The modules are combined into a subsystem, and timing analysis is performed at the subsystem level to check whether there are timing violation problems, which are converted into delay constraints for optimization of module-level placement and routing. The optimization of module-level placement and routing is performed in an environment closer to actual system integration, and the length of the wiring inside the path end module of the cross-module timing violation path is considered, which helps to reduce the number of iteration calculation rounds and improve the efficiency and accuracy of timing convergence.

[0037] Specifically, the modules currently in the placement and routing stage are combined into a subsystem, and it is checked whether there is a timing violation when a signal is transmitted between the modules of the subsystem, i.e., whether the signal delay exceeds the allowed range in the design specification, and a plurality of cross-module timing violation paths are identified.

[0038] S120, the path grouping of each of the cross-module timing violation paths is performed to obtain at least one path grouping corresponding to each target module.

[0039] Specifically, in order to more effectively manage and optimize the cross-module timing violation paths, the cross-module timing violation paths can be grouped according to their common characteristics, for example, the cross-module timing violation paths can be divided into at least one path grouping according to the start and end modules of the paths or the direction of the data flow, and the target module to which each path grouping belongs is determined according to the path start module of each path grouping.

[0040] For example, the path start modules of each cross-module timing violation path in a path grouping X are all module A, and the path grouping X is determined as the path grouping corresponding to module A.

[0041] It can be understood that each target module (such as module A and module B, etc.) can involve multiple cross-module timing violation paths. Through path grouping, at least one path grouping can be generated for each target module. These path groupings contain all cross-module timing violation paths related to the module (typically, the module as the path start module).

[0042] S130, according to the actual wiring value of each of the cross-module timing violation paths in the path end module, a delay constraint compensation value corresponding to each path grouping of each target module is determined.

[0043] In the embodiments of the present disclosure, the path end module can be specifically understood as a module in which the end of the signal transmission path is located. The actual routing value can be specifically understood as a time measurement value determined by the actual physical routing of the signal in the path end module. For example, for a cross-module timing violation path Y from module A to module B, the path end module is module B. In the cross-module timing violation path Y, it is defined that after the signal enters module B from the set port, it finally reaches register 2 in module B after passing through register 1 in module B. At this time, the routing delay t1 of the signal from the port to register 1, the cell delay t2 of the signal on register 1, and the routing delay t3 of the signal from register 1 to register 2 can be obtained in sequence by combining the timing report generated during the subsystem timing analysis, and the sum value of t1+t2+t3 is calculated as the actual routing value of the cross-module timing violation path Y in the path end module B.

[0044] The delay constraint compensation value can be specifically understood as a value for compensating the delay of the path, which is calculated based on the actual routing value. The delay constraint compensation value is used to adjust the timing constraint of the path to ensure that the signal reaches the end module within a specified time.

[0045] Specifically, the actual routing value of each cross-module timing violation path in the same path group in the path end module can be obtained by an electronic design automation tool, and the delay constraint compensation value corresponding to the path group can be finally calculated according to each actual routing value corresponding to the path group.

[0046] It can be understood that comparing the actual routing value of each path group with the timing constraint in the design specification can determine the severity of the timing violation. The greater the violation amount between the actual routing value of the path group and the allowed delay, the more serious the violation that can occur in the path group. At this time, a larger delay constraint compensation value needs to be set for the path group.

[0047] Optionally, the delay constraint compensation value corresponding to each path group of each target module can be determined according to the size and concentration of each actual routing value in a path group.

[0048] S140, generating a subsystem-level optimization script according to each delay constraint compensation value, and optimizing the module-level layout and routing through the subsystem-level optimization script.

[0049] Specifically, after the subsystem level analysis, the delay constraint compensation values of each path group are obtained, and a subsystem level optimization script is written according to the delay constraint compensation values, the compensation values are specified for each target module and path group to adjust the timing constraint. The optimization script is applied to the module level layout and routing tool, and the tool adjusts the layout and routing of each path according to the script to optimize the timing. After optimization, timing analysis is performed again to check whether the timing constraint is met. If there are still violations, the above steps are repeated until all path timing converges.

[0050] The technical scheme of the embodiments of the present disclosure combines the modules currently in the layout and routing stage into subsystems in a lightweight manner, performs timing analysis on the subsystems, and obtains a plurality of cross-module timing violation paths. The cross-module timing violation paths are grouped to obtain at least one path group corresponding to each target module. The delay constraint compensation value corresponding to each path group of each target module is determined according to the actual trace value of each cross-module timing violation path in the path endpoint module. The timing problem of a specific module can be more accurately identified and processed, the actual timing requirement can be more accurately reflected, the accuracy of timing optimization can be improved, and targeted optimization can be realized. A subsystem level optimization script is generated according to the delay constraint compensation values, and the optimization of the module level layout and routing is performed through the subsystem level optimization script. By adding the delay constraint compensation value at the subsystem level, timing repair can be performed earlier for the timing problem of the module interface found, the timing performance and reliability of the entire chip design are improved, large-scale modification in the later stage is avoided, and the design efficiency is improved.

[0051] Figure 2 is a schematic diagram of another convergent pre-timing optimization method provided by the embodiments of the present disclosure. The present embodiment is a refinement of the convergent pre-timing optimization method in the above-mentioned embodiments. In the present embodiment, after grouping the cross-module timing violation paths to obtain at least one path group corresponding to each target module, it can further include: assigning a repair weight to each path group of each target module according to the time violation value of each cross-module timing violation path;

[0052] Correspondingly, generating a subsystem level optimization script according to the delay constraint compensation values can further include: generating the subsystem level optimization script according to the delay constraint compensation values and the repair weights.

[0053] Correspondingly, as shown in Figure 2 the method can specifically include:

[0054] S210, combining the modules currently in the layout and routing stage into subsystems in a lightweight manner, and performing timing analysis on the subsystems to obtain a plurality of cross-module timing violation paths.

[0055] S220, performing path grouping on each of the cross-module timing violation paths to obtain at least one path group corresponding to each target module.

[0056] Optionally, on the basis of each of the above embodiments, performing path grouping on each of the cross-module timing violation paths to obtain at least one path group corresponding to each target module can include:

[0057] dividing each of the cross-module timing violation paths corresponding to the same path starting module and the same path ending module into the same original group;

[0058] dividing each of the original groups into a matching target module with the path starting module as the target module;

[0059] re-grouping the original groups belonging to each of the target modules according to at least one of the port timing data flow type, the physical position, the clock domain type, and the data interaction mode corresponding to each of the cross-module timing paths to obtain at least one path group corresponding to each target module.

[0060] In the embodiments of the present disclosure, the port timing data flow type can be specifically understood as the data flow characteristics of signals when transmitted between modules, such as input / output direction, data width, whether it is a control signal, and data interaction mode, etc. Among them, each of the cross-module timing violation paths in the same original group has the same path starting module and the same path ending module, but generally, each of the cross-module timing violation paths in the same original group often corresponds to different ports, for example, in the cross-module timing violation path 1, the signal is transmitted from the path starting module A to the path ending module B via the port 1, while in the cross-module timing violation path 2, the signal is transmitted from the path starting module A to the path ending module B via the port 2, and so on. Correspondingly, the physical position can be specifically understood as the physical position of the signal transmission port in each of the cross-module timing violation paths in the same original group. Further, each of the cross-module timing violation paths with close port physical positions in the same original group can be divided into the same path group. The clock domain type can be specifically understood as the type of clock signal on which the module operates. The data interaction mode can be understood as the transmission mechanism of signals between different modules.

[0061] Specifically, the cross-module timing violation paths of the same path start module and the same path end module are divided into the same original group, that is, all paths with the same start and end points are placed in the same group. Each original group is associated with a target module, that is, the original group is assigned to the start module of the path. On the basis of the original group, further subdivision is performed according to at least one of other key characteristics such as port timing data flow type, physical location, clock domain type, and data interaction mode of the path, to obtain at least one path group corresponding to each target module, and the paths in each group have at least one similar other key characteristic such as similar start, end, and port timing data flow type, physical location, clock domain type, and data interaction mode.

[0062] By classifying the cross-module timing violation paths with the same start and end points and regrouping the paths based on at least one other key characteristic such as port timing data flow type, physical location, clock domain type, and data exchange mode for the start module, the subsequent optimization strategy is more targeted, similar timing problems can be solved by concentrating resources, the timing performance and reliability of the entire chip design are improved, large-scale modification in the later stage is avoided, and design efficiency is improved.

[0063] S230, according to the time violation value of each cross-module timing violation path, a repair weight is respectively assigned to each path group of each target module.

[0064] In the embodiments of the present disclosure, the time violation value can be specifically understood as the difference value between the actual transmission time of the signal on the cross-module timing violation path and the allowed transmission time specified in the design specification. The repair weight can be specifically understood as a numerical value used to represent the severity of the timing problem of each cross-module timing violation path in a path group, which reflects the degree to which each cross-module timing violation path in the path group needs to be processed first in the timing optimization process.

[0065] Specifically, after performing timing analysis on the subsystem and obtaining a timing analysis report, the time violation value of each cross-module timing violation path can be obtained. Since each path group usually contains multiple cross-module timing violation paths, the time violation values of all paths in the group can be collected. Based on the distribution of the time violation values in the group, the multiple time violation values in the same path group are processed according to a preset algorithm, and finally the repair weight corresponding to the path group can be obtained.

[0066] For example, a time measurement value can be calculated by calculating the average of the time violation values of all paths in a path group, or taking the maximum value of the time violation values of all paths in a path group, and then converting the time measurement value into the repair weight of the path group by a certain algorithm. For example, the larger the time measurement value of a path group, the larger the repair weight of the path group.

[0067] Optionally, on the basis of the above embodiments, according to the time violation values of the cross-module timing violation paths, a repair weight is respectively assigned to each path group of each target module, including:

[0068] A second path group corresponding to a second target module is obtained, and each second cross-module timing path in the second path group is obtained.

[0069] According to the target time violation values respectively corresponding to each of the second cross-module timing paths, a standardized time violation value corresponding to the second path group is calculated.

[0070] A time violation extreme value is obtained from the target time violation values, and a normalized violation delay degree value corresponding to the second path group is calculated according to the time violation extreme value and the standardized time violation value.

[0071] According to the normalized violation delay degree value, a repair weight assigned to the second path group is calculated.

[0072] In the embodiments of the present disclosure, the second target module can be understood as a target module selected from the target modules and currently processed in the process of calculating the repair weight. The second path group is a path group corresponding to the second target module. The second cross-module timing path is all timing paths in the second path group. The normalized violation delay degree value can be understood as a standardization time violation information for quantifying the severity of path timing violation, reflecting the relative position of path delay within the overall allowed range.

[0073] Specifically, the second path group corresponding to the second target module is determined, and each second cross-module timing path in the second path group is identified and obtained. The target time violation value corresponding to each path in the second path group is obtained, and a standardized time violation value is calculated. For example, the percentile of each target time violation value in all values can be calculated, and the percentile is converted into a standardized time violation value (for example, the maximum value of the normalized percentile in a preset range is selected).

[0074] Among all the target time violation values, a time violation extreme value (e.g. maximum value or minimum value) is obtained. According to the time violation extreme value and the normalized time violation value, a normalized violation delay degree value corresponding to the second path group is calculated, for example, the normalized violation delay degree value can be calculated by the following formula: normalized violation delay degree value = (normalized time violation value-time violation minimum value) / (time violation maximum value-time violation minimum value). The normalized violation delay degree value is linearly mapped to a weight range, or the normalized value is exponentially operated to obtain a weight, or the normalized value is segmented according to its size, each segment corresponds to a different weight, and the repair weight allocated to the second path group is calculated.

[0075] By obtaining the time violation values of each second cross-module timing path in the second path group, the normalized time violation value is calculated, which can eliminate the differences in dimension and order of magnitude between different paths, realize unified comparison, and further calculate the normalized violation delay degree value in combination with the time violation extreme value, so as to more accurately identify the timing violation severity of each path. According to the value, the repair weight is calculated, which can optimize the timing repair order, preferentially repair the serious path, realize targeted optimization, improve the timing performance and reliability of the entire chip design, avoid large-scale modification in the later stage, and improve the design efficiency.

[0076] Optionally, based on each of the above embodiments, according to the target time violation values respectively corresponding to each of the second cross-module timing paths, the normalized time violation value corresponding to the second path group can be calculated, which can include:

[0077] According to the target time violation values respectively corresponding to each of the second cross-module timing paths, a second statistical index value corresponding to the second path group is calculated.

[0078] According to the second statistical index value, each of the target time violation values is normalized and scored to obtain a time violation score value respectively corresponding to each of the target time violation values.

[0079] Among the time violation score values, a standardized time violation value meeting a standardized condition is selected.

[0080] Specifically, according to the target time violation values of each second cross-module timing path in the second path group, a second statistical index value (such as average value and standard deviation) corresponding to the second path group is calculated. Based on the second statistical index value, each path is processed through unified dimension conversion to obtain the deviation position of each second cross-module timing path in the overall distribution under the second path group, that is, the time violation score value is obtained.

[0081] By calculating the second statistical index value, the overall timing violation condition of the second path group can be quantitatively analyzed, and based on this, the target time violation value is normalized and scored to obtain a time violation score value, which eliminates the differences in dimensions and orders of magnitude between different paths, makes the time violation score value more consistent with the overall distribution, and after screening out the time violation score value meeting the standardization condition as the standardized time violation value, the path group with serious and concentrated timing violation can be effectively determined, a higher repair weight is set, the identification accuracy of the key path group is improved, and the timing repair efficiency is improved.

[0082] Optionally, on the basis of each of the above embodiments, the second statistical index value can include: a mean value of the violation values of the target time violation values corresponding to each of the second cross-module timing paths, and a standard deviation of the violation values of the target time violation values corresponding to each of the second cross-module timing paths.

[0083] Correspondingly, on the basis of each of the above embodiments, according to the second statistical index value, the target time violation value is normalized and scored to obtain a time violation score value corresponding to each of the target time violation values, which can include:

[0084] According to the formula: z_delay_score j =(y j -μ_delay) / σ_delay, the time violation score value z_delay_score j corresponding to the target time violation value y j of the jth second cross-module timing path is calculated.

[0085] Wherein, μ_delay is the mean value of the violation values, and σ_delay is the standard deviation of the violation values.

[0086] In the embodiments of the present disclosure, the mean value of the violation values can be specifically understood as the mean value of all target time violation values in the second path group, which reflects the central tendency of the timing violation of the second path group. The standard deviation of the violation values can be specifically understood as the standard deviation of all target time violation values in the second path group, which reflects the deviation degree of each time violation value from the mean value of the violation values.

[0087] Specifically, the second statistical index value includes: the mean value (μ_delay) of the violation values and the standard deviation (σ_delay) of the violation values. According to the Z-score formula z_delay_score j =(y j -μ_delay) / σ_delay, the time violation score value z_delay_score jcorresponding time violation score z_delay_score j .

[0088] By calculating the average and standard deviation of the time violation values of the second path group as statistical indicators, the timing violation situation of the path group can be comprehensively understood. By using the Z-score formula, the time violation values of each path are converted into time violation scores, which eliminates the dimensional and order of magnitude differences, making the scores of different paths directly comparable, improving the identification accuracy of the key timing repair path, providing a basis for the calculation of subsequent repair weights, and improving the efficiency and effectiveness of timing repair.

[0089] Optionally, on the basis of each of the above embodiments, the standardized time violation value meeting the standardization condition can be selected from the time violation scores, which can include:

[0090] Selecting each candidate time violation score less than or equal to the standardized constraint threshold value from the time violation scores.

[0091] Determining the maximum value of each candidate time violation score as the standardized time violation value.

[0092] Specifically, the candidate time violation score less than or equal to the standardized constraint threshold value is obtained from all time violation scores. The time violation score is calculated according to the Z-score method, and the score is taken as a unit of measurement in units of sigma (sigma). Optionally, according to business requirements, the standardized constraint threshold value can be set to 3sigma, so that the selected candidate time violation score can cover about 99% of the timing violation situation, i.e., the candidate time violation score less than or equal to 3sigma is found. Since the maximum value in the normalized scale can reflect the most serious timing violation situation under the premise of meeting the standardization condition, the maximum value is selected from the candidate values as the standardized time violation value. Without taking the maximum value of all time violation scores as the standardized time violation value, the calculation can be simplified, and the timing violation situation in most cases can be represented.

[0093] By selecting the candidate value less than or equal to the standardized constraint threshold value from the time violation scores, and determining the maximum value thereof as the standardized time violation value, the most representative timing violation problem can be identified, which focuses on the most serious timing violation and reduces the calculation complexity and improves the optimization efficiency.

[0094] Optionally, on the basis of each of the above embodiments, the time violation extreme value is obtained from the target time violation values, and the normalized violation delay degree value corresponding to the second path group is calculated according to the time violation extreme value and the standardized time violation value, which can include:

[0095] According to the formula:

[0096] severity_g=(z_group_slack-slack_min) / (slack_max-slack_min), calculate the normalized violation delay degree value severity_g corresponding to the second path group;

[0097] Wherein, z_group_slack is the normalized time violation value, slack_min is the minimum time violation value in each target time violation value, slack_max is the maximum time violation value in each target time violation value.

[0098] Specifically, in all target time violation values of the second path group, the minimum value (slack_min) and the maximum value (slack_max) are obtained.

[0099] According to the formula: severity_g=(z_group_slack-slack_min) / (slack_max-slack_min), the normalized violation delay degree value severity_g corresponding to the second path group is calculated, wherein z_group_slack is the normalized time violation value, which represents the current path group standardized timing violation condition.

[0100] By obtaining the time violation extreme value and the normalized time violation value, and calculating the normalized violation delay degree value according to the formula, the timing violation conditions of different paths can be standardized to the same scale, the evaluation accuracy of the timing problem severity of each path is improved, the optimization work is concentrated on the most critical path, and the efficiency and effect of timing optimization are improved.

[0101] Optionally, on the basis of each of the above embodiments, according to the normalized violation delay degree value, the repair weight allocated for the second path group can be calculated, which can include:

[0102] According to the formula: weight_g=min(P, exp(λ*(1-severity_g))), the repair weight weight_g allocated for the second path group is calculated;

[0103] Wherein, P is a preset upper limit of repair weight, and λ is a preset weight correction coefficient.

[0104] Specifically, by bringing the normalized violation delay degree value severity_g into the above formula, the smaller one between the exponential calculation value exp(λ*(1-severity_g) and the preset upper limit P is taken as the repair weight weight_g, which prevents the repair weight from being too large, avoids individual extreme paths from occupying too many optimization resources, and makes the repair weight curve smoother. Optionally, the preset repair weight upper limit P can be set to 20.

[0105] By calculating the repair weight according to the normalized violation delay degree value using the formula, the exponential function ensures that the repair weight changes correspondingly and nonlinearly with the change of the normalized violation delay degree value, and at the same time, the weight upper limit prevents the weight of individual paths from being too high, ensures reasonable allocation of resources, realizes dynamic allocation of repair weight, and improves the efficiency and effect of timing optimization.

[0106] Further, on the basis of the above embodiments, before calculating the repair weight allocated to the second path group according to the normalized violation delay degree value, the method can further include:

[0107] According to the formula: λ base = asinh(1 / σ_delay), the standardization sensitivity coefficient λ corresponding to the second path group is calculated. base Where asinh(.) is the inverse hyperbolic sine function, and σ_delay is the standard deviation of the time violation value in the second path group.

[0108] According to the current layout and routing optimization stage in which each module is located, the scaling coefficient k stage is determined.

[0109] According to the formula: λ = k stage · λ base , the weight correction coefficient λ is calculated.

[0110] In the embodiments of the present disclosure, the standardization sensitivity coefficient can be specifically understood as an index for measuring the distribution characteristics of the time violation value and determining the sensitivity degree of the repair weight. The scaling coefficient can be specifically understood as a parameter for adjusting the weight correction coefficient according to the current layout and routing optimization stage. It can be understood that different optimization stages require different weight adjustment strategies. Optionally, the optimization process can be divided into a layout stage and a CTS (Clock Tree Synthesis) stage. In the layout stage, a smaller scaling coefficient (such as 0.7-0.9) can be used for conservative exploration, and in the CTS stage, a larger scaling coefficient (such as 1.0-1.2) can be used for more accurate optimization.

[0111] The embodiment comprehensively considers the current optimization stage and the dispersion degree of the time violation value, dynamically adjusts the calculation of the repair weight, improves the flexibility of the timing repair process, enhances the rationality and adaptability of the timing repair, improves the timing optimization efficiency and effect, and ensures the reliability of the timing optimization in different optimization stages.

[0112] Further, on the basis of each of the above embodiments, after the repair weight is respectively allocated to each path group of each target module, the method can further include:

[0113] According to the repair weight respectively allocated to each path group of each target module, a high-repair-level module is identified in each target module, and boundary constraint information and clock tree intervention information corresponding to the high-repair-level module are generated;

[0114] Correspondingly, on the basis of each of the above embodiments, the sub-system-level optimization script is generated according to the delay constraint compensation value and the repair weight, and the method further includes:

[0115] The sub-system-level optimization script is generated according to the delay constraint compensation value, the repair weight, and the boundary constraint information and the clock tree intervention information corresponding to the high-repair-level module.

[0116] In the embodiment of the disclosure, the high-repair-level module can be specifically understood as a module with a high repair priority because of a greater impact on the overall timing performance.

[0117] Specifically, by analyzing the repair weight of each path group of each module, a module whose path repair weight meets a preset high-repair-level condition is identified as a high-repair-level module. Specific boundary constraint information, such as input delay or output delay, is set for the high-repair-level module to ensure that the timing requirements of these modules are met, and specific clock tree intervention information, such as adjusting the position of the clock buffer or optimizing the structure of the clock tree, is made for the high-repair-level module to reduce clock skew and delay.

[0118] In a specific example, if the repair weight of more than a preset proportion of path groups in each path group of a module is greater than a preset weight threshold, the module is determined as a high-repair-level module that meets the repair level condition; or if the repair weight of more than a preset number of path groups in each path group of a module is greater than a preset weight threshold, the module is determined as a high-repair-level module that meets the repair level condition, and the like. The embodiment does not limit this.

[0119] Correspondingly, when generating the subsystem-level optimization script, not only the delay constraint compensation value and the repair weight, but also the boundary constraint information and the clock tree intervention information of the high-repair-level module are integrated to generate the subsystem-level optimization script. The subsystem-level optimization script will guide the module-level layout and routing tool to make targeted adjustment, so as to preferentially solve the timing problem of the high-repair-level module and ensure the timing performance of the overall design.

[0120] After assigning the repair weight to each path group of the target module, the high-repair-level module can be further identified, and the corresponding boundary constraint information and clock tree intervention information can be generated. By integrating the repair weight, the delay constraint compensation value and the specific information of the high-repair-level module into the subsystem-level optimization script, the accuracy of the module-level layout and routing optimization is improved, the optimization resources are concentrated on the module that needs most attention, the efficiency and effect of the timing optimization are improved, the iteration number is reduced, and the chip design cycle is shortened.

[0121] S240, according to the actual routing value of each cross-module timing violation path in the path endpoint module, determining the delay constraint compensation value corresponding to each path group of the target module respectively.

[0122] S250, generating the subsystem-level optimization script according to each delay constraint compensation value and each repair weight, and optimizing the module-level layout and routing through the subsystem-level optimization script.

[0123] Specifically, the delay constraint compensation value and the repair weight of each path group are integrated into the subsystem-level optimization script, the script is applied in the module-level layout and routing stage, the tool is guided to preferentially optimize the critical path and allocate resources. Analyzing the timing report after optimization, the effect is evaluated. If there are still violations, the above steps are repeated for iterative optimization.

[0124] The technical scheme of the embodiments of the present disclosure is that each module currently in the layout and routing stage is merged into a subsystem in a lightweight manner, timing analysis is performed on the subsystem, and a plurality of cross-module timing violation paths are obtained; each cross-module timing violation path is grouped to obtain at least one path group corresponding to each target module, a repair weight is respectively assigned to each path group of each target module according to the time violation value of each cross-module timing violation path, so as to identify a path with a serious timing problem, a delay constraint compensation value corresponding to each path group of each target module is determined according to the actual routing value of each cross-module timing violation path in the path end module, the timing problem of a specific module can be more accurately identified and processed, the actual timing requirement can be more accurately reflected, the accuracy of timing optimization is improved, and targeted optimization is realized; a subsystem-level optimization script is generated according to each delay constraint compensation value and each repair weight, and optimization of module-level layout and routing is performed through the subsystem-level optimization script, the timing problem of the discovered module interface can be repaired in order according to the severity of the timing problem earlier by comprehensively considering the delay constraint compensation value and the repair weight of the subsystem level, unnecessary repair and iteration are reduced, the timing performance and reliability of the entire chip design are improved, large-scale modification in the later stage is avoided, the timing optimization efficiency is improved, the chip design cycle is shortened, and the design efficiency is improved.

[0125] Figure 3 is a schematic diagram of another convergent pre-timing optimization method provided by the embodiments of the present disclosure. The present embodiment is a refinement of the above-mentioned "determining a delay constraint compensation value corresponding to each path group of each target module according to the actual routing value of each cross-module timing violation path in the path end module" in each of the above-mentioned embodiments, which can specifically include: obtaining a first path group corresponding to a first target module, and obtaining each first cross-module timing path in the first path group; calculating a first statistical index value corresponding to the first path group according to the target actual routing length of each first cross-module timing path in the path end module; normalizing and scoring each target actual routing length according to the first statistical index value to obtain a length score value corresponding to each target actual routing length; and filtering a standardized length score value meeting a standardization condition from each length score value as the delay constraint compensation value corresponding to the first path group of the first target module.

[0126] Correspondingly, as shown in Figure 3 , the method can specifically include:

[0127] S310, each module currently in the layout and routing stage is merged into a subsystem in a lightweight manner, and timing analysis is performed on the subsystem to obtain a plurality of cross-module timing violation paths.

[0128] S320, performing path grouping on each of the cross-module timing violation paths to obtain at least one path group corresponding to each target module.

[0129] S330, obtaining a first path group corresponding to a first target module, and obtaining each first cross-module timing path in the first path group.

[0130] In the embodiments of the present disclosure, the first target module can be specifically understood as: selecting one target module that needs to be processed currently among the target modules in the process of calculating the delay constraint compensation value. The first path group is a path group corresponding to the first target module. The first cross-module timing path is all timing paths in the first path group.

[0131] S340, calculating a first statistical index value corresponding to the first path group according to the target actual trace length of each of the first cross-module timing paths in the path end module.

[0132] Specifically, the first path group corresponding to the first target module can be obtained through the report provided by the layout and routing tool, each first cross-module timing path in the first path group can be obtained, the actual trace length of each path in the path end module in the first path group can be obtained, and the first statistical index value of the actual trace length data, such as the average value, the median, the standard deviation, the maximum value or the minimum value, etc. can be calculated.

[0133] S350, according to the first statistical index value, normalizing and scoring each of the target actual trace lengths to obtain a length score value corresponding to each of the target actual trace lengths.

[0134] In the embodiments of the present disclosure, the length score value can be specifically understood as: the normalized score value of each target actual trace length, which is used to reflect the relative position of the target actual trace length in the overall distribution.

[0135] Optionally, on the basis of each of the above embodiments, the first statistical index value can include: a length average value of each target actual trace length in the first path group, and a length standard deviation of each target actual trace length in the first path group.

[0136] Correspondingly, on the basis of each of the above embodiments, according to the first statistical index value, normalizing and scoring each of the target actual trace lengths to obtain a length score value corresponding to each of the target actual trace lengths can include:

[0137] According to the formula: z_path_score i =(x i- μ_path) / σ_path, the length score value corresponding to the i-th target actual trace length x icorresponding length score z_path_score i ;

[0138] wherein μ_path is the length average value, and σ_path is the length standard deviation.

[0139] Specifically, the first statistical indicator value can include: a length average value μ_path of all target actual routing lengths in the first path group, and a length standard deviation σ_path of all target actual routing lengths in the first path group.

[0140] By calculating the length average value and the length standard deviation of each target actual routing length in the first path group as the first statistical indicator value, the concentration trend and the dispersion degree of the routing lengths in the path group can be comprehensively understood. The formula is used to normalize the score of each target actual routing length, which can convert the routing length data of different dimensions and orders of magnitude to the same scale, so that the routing lengths of each path are comparable. The length score obtained reflects the relative position of the routing lengths of each path in the whole, which helps to reasonably allocate resources in the subsequent optimization process, to preferentially focus on the paths with significantly deviated lengths, to improve the accuracy of timing repair, and to enhance the pertinence and reliability of the optimization strategy.

[0141] S360, in each of the length scores, a standardized length score meeting a standardization condition is selected as a time delay constraint compensation value corresponding to the first path group of the first target module.

[0142] Specifically, from all the length scores, a value meeting the standardization condition (for example, selecting the maximum value in a preset range) is selected as the time delay constraint compensation value corresponding to the first path group of the first target module.

[0143] Optionally, on the basis of each of the above embodiments, in each of the length scores, a standardized length score meeting a standardization condition can include:

[0144] In each of the length scores, each candidate length score less than or equal to a standardized constraint threshold value is selected.

[0145] The maximum value in each of the candidate length scores is determined as the standardized length score.

[0146] Specifically, among all the length score values, the candidate length score values less than or equal to the normalized constraint threshold value are obtained. Similarly, the length score value is calculated in the manner of Z-score, which is a measurement unit in sigma (sigma) units. Optionally, the normalized constraint threshold value can be set to 3 sigma, so that the selected candidate length score values can cover about 99% of the latency conditions, that is, the candidate length score values less than or equal to 3 sigma are found. Since the maximum value on the normalized scale can reflect the most serious impact of the actual routing length of the path on the latency under the premise of meeting the normalization condition. Therefore, the maximum value is selected from these candidate values as the normalized length score value. Instead of taking the maximum value of all length score values as the normalized length score value, it can simplify the calculation and represent the latency condition in most cases.

[0147] By screening the candidate values less than or equal to the normalized constraint threshold value from the length score values, and determining the maximum value among them as the normalized length score value, the path with the most serious latency condition can be accurately identified, ensuring that the optimization resources are focused on the most critical part, reducing iterations, shortening the design cycle, focusing on the most serious latency condition, reducing the calculation complexity, and improving the optimization efficiency.

[0148] S370, generating a subsystem-level optimization script according to each latency constraint compensation value, and performing module-level layout and wiring optimization through the subsystem-level optimization script.

[0149] Figure 4 is a specific application scenario applicable to the embodiments of the present disclosure, as shown in Figure 4 As shown, first, the timing violation paths with timing problems in the subsystem are identified, and these paths are grouped within the module according to the direction of the data flow or other characteristics. The timing constraints between different levels are coordinated to ensure that the timing requirements of the subsystem match the interface timing of the module level. Through simulation analysis, it is determined which groups of paths need to be optimized the most, and optimization weight coefficients are assigned to these groups, which reflect the priority of optimization. Based on the latency constraint compensation value and the weight coefficient, a subsystem-level optimization script is generated, which includes the optimization strategy and weight coefficient determined according to the above steps. Physical realization (PR) is performed at the module level, that is, layout and wiring optimization is performed.

[0150] After optimization, it is checked whether the current timing condition meets the design requirements. If yes, the flow enters the approval stage, indicating that the design has passed the verification; if no, the database (Database, db) needs to be retrieved, and the design data and timing analysis results generated in the module-level physical realization stage are fed back for secondary analysis to correct the deviation.

[0151] The technical scheme of the embodiment of the present disclosure is characterized in that: each module currently in a layout and routing stage is merged into a subsystem in a lightweight manner, timing analysis is performed on the subsystem, and a plurality of cross-module timing violation paths are obtained; each cross-module timing violation path is grouped into a path group, at least one path group corresponding to each target module is obtained, a first path group corresponding to a first target module is obtained, and each first cross-module timing path in the first path group is obtained; a first statistical index value corresponding to the first path group is calculated according to the target actual routing length of each first cross-module timing path in the path end module; each target actual routing length is normalized and scored according to the first statistical index value, and a length score value corresponding to each target actual routing length is obtained; a standardized length score value meeting a standardization condition is selected from each length score value as a delay constraint compensation value corresponding to the first path group of the first target module, the dimension and order of magnitude difference are eliminated through the normalized scoring, different path lengths can be uniformly compared and evaluated, the standardized length score value ensures the accuracy and consistency of the delay constraint compensation value, the influence of each path on timing is accurately quantified, the precision of timing optimization is improved, and targeted optimization is realized; a subsystem-level optimization script is generated according to each delay constraint compensation value, and optimization of module-level layout and routing is performed through the subsystem-level optimization script, the timing repair of the timing problem of the inter-module interface discovered can be performed earlier by adding the delay constraint compensation value at the subsystem level, the timing performance and reliability of the entire chip design are improved, large-scale modification in the later stage is avoided, and the design efficiency is improved.

[0152] As an implementation of the timing optimization method before convergence, the present disclosure further provides an optional embodiment of an execution device for implementing the timing optimization method before convergence.

[0153] Specifically, Figure 5 is a structural diagram of a timing optimization device before convergence provided by the embodiment of the present disclosure. As shown in Figure 5 , the device comprises a lightweight merging module 510, a path grouping module 520, a determination compensation module 530, and a module optimization module 540, wherein:

[0154] The lightweight merging module 510 is configured to merge each module currently in a layout and routing stage into a subsystem in a lightweight manner, and perform timing analysis on the subsystem to obtain a plurality of cross-module timing violation paths.

[0155] The path grouping module 520 is configured to group each cross-module timing violation path into a path group, and obtain at least one path group corresponding to each target module.

[0156] The compensation module 530 is configured to determine a delay constraint compensation value corresponding to each path group of each target module according to an actual routing value of each cross-module timing violation path in a path end module.

[0157] The module optimization module 540 is configured to generate a subsystem-level optimization script according to the delay constraint compensation values, and perform module-level layout and wiring optimization through the subsystem-level optimization script.

[0158] The technical scheme of the embodiments of the present disclosure can more accurately identify and process the timing problem of a specific module, more accurately reflect the actual timing requirement, improve the timing optimization accuracy, and realize targeted optimization by merging each module currently in the layout and wiring stage into a subsystem, performing timing analysis on the subsystem, obtaining a plurality of cross-module timing violation paths, performing path grouping on each cross-module timing violation path, obtaining at least one path group corresponding to each target module, determining a delay constraint compensation value corresponding to each path group of each target module according to an actual routing value of each cross-module timing violation path in a path end module, generating a subsystem-level optimization script according to each delay constraint compensation value, and performing module-level layout and wiring optimization through the subsystem-level optimization script. By adding the delay constraint compensation value at the subsystem level, timing repair can be performed earlier for the timing problem of the module interface found, the timing performance and reliability of the entire chip design are improved, large-scale modification in the later stage is avoided, and the design efficiency is improved.

[0159] Further, on the basis of each of the above embodiments, the timing optimization device before convergence can further include a weight distribution module, wherein:

[0160] The weight distribution module is configured to, after the path grouping of each cross-module timing violation path to obtain at least one path group corresponding to each target module, respectively distribute a repair weight for each path group of each target module according to a time violation value of each cross-module timing violation path.

[0161] Correspondingly, on the basis of each of the above embodiments, the module optimization module 540 is specifically configured to:

[0162] Generate the subsystem-level optimization script according to the delay constraint compensation values and the repair weights.

[0163] On the basis of each of the above embodiments, the path grouping module 520 is specifically configured to:

[0164] Divide each cross-module timing violation path corresponding to the same path start module and the same path end module into the same original group.

[0165] The path start module is taken as a target module, and the original groups are divided into matched target modules;

[0166] According to at least one of the port timing data stream type, the physical position, the clock domain type and the data interaction mode corresponding to each cross-module timing path, the original groups belonging to each target module are regrouped to obtain at least one path group corresponding to each target module.

[0167] On the basis of each of the above embodiments, the compensation module 530 is determined, and is specifically used for:

[0168] The first path group corresponding to the first target module is obtained, and each first cross-module timing path in the first path group is obtained.

[0169] According to the target actual trace length of each first cross-module timing path in the path end module, a first statistical index value corresponding to the first path group is calculated.

[0170] According to the first statistical index value, the target actual trace length is normalized and scored to obtain a length score value corresponding to each target actual trace length.

[0171] In each of the length score values, a standardized length score value meeting a standardization condition is selected as a time delay constraint compensation value corresponding to the first path group of the first target module.

[0172] On the basis of each of the above embodiments, the first statistical index value can include a length average value of each target actual trace length in the first path group and a length standard deviation of each target actual trace length in the first path group.

[0173] Correspondingly, on the basis of each of the above embodiments, the compensation module 530 is determined, and is further used for:

[0174] According to the formula: z_path_score i =(x i -μ_path) / σ_path, the length score value z_path_score i corresponding to the i-th target actual trace length xi is calculated.

[0175] Wherein, μ_path is the length average value, and σ_path is the length standard deviation.

[0176] On the basis of each of the above embodiments, the compensation module 530 is further used for:

[0177] In each of the length score values, each candidate length score value less than or equal to a standardized constraint threshold value is selected.

[0178] The maximum value among the alternative length score values is determined as the normalized length score value.

[0179] On the basis of the above embodiments, the weight distribution module is specifically configured to:

[0180] Obtain a second path group corresponding to the second target module, and obtain each second cross-module timing path in the second path group;

[0181] According to the target time violation values respectively corresponding to each second cross-module timing path, calculate a normalized time violation value corresponding to the second path group;

[0182] Obtain a time violation extreme value among the target time violation values, and calculate a normalized violation delay degree value corresponding to the second path group according to the time violation extreme value and the normalized time violation value;

[0183] According to the normalized violation delay degree value, calculate a repair weight allocated to the second path group.

[0184] On the basis of the above embodiments, the weight distribution module is further configured to:

[0185] According to the target time violation values respectively corresponding to each second cross-module timing path, calculate a second statistical index value corresponding to the second path group;

[0186] According to the second statistical index value, normalize the scores of each target time violation value to obtain a time violation score value respectively corresponding to each target time violation value;

[0187] Among the time violation score values, a normalized time violation value meeting a normalization condition is screened out.

[0188] On the basis of the above embodiments, the second statistical index value can include a violation value average of each target time violation value respectively corresponding to each second cross-module timing path, and a violation value standard deviation of each target time violation value respectively corresponding to each second cross-module timing path.

[0189] Correspondingly, on the basis of the above embodiments, the weight distribution module is further configured to:

[0190] According to the formula: z_delay_score j =(y j- μ_delay) / σ_delay, the target time violation value y jcorresponding time violation score z_delay_score j ;

[0191] wherein μ_delay is the average of the violation values, and σ_delay is the standard deviation of the violation values.

[0192] On the basis of each of the above embodiments, the weight distribution module is further configured to:

[0193] In each of the time violation scores, filter out each candidate time violation score less than or equal to a normalized constraint threshold value;

[0194] Determine the maximum value among each of the candidate time violation scores as the normalized time violation value.

[0195] On the basis of each of the above embodiments, the weight distribution module is further configured to:

[0196] According to the formula:

[0197] severity_g = (z_group_slack - slack_min) / (slack_max - slack_min), calculate the normalized violation delay degree value severity_g corresponding to the second path group;

[0198] wherein z_group_slack is the normalized time violation value, slack_min is the minimum time violation value among each of the target time violation values, and slack_max is the maximum time violation value among each of the target time violation values.

[0199] On the basis of each of the above embodiments, the weight distribution module is further configured to:

[0200] According to the formula: weight_g = min(P, exp(λ*(1-severity_g))), calculate the repair weight weight_g assigned to the second path group;

[0201] wherein P is a pre-set upper limit of the repair weight, and λ is a pre-set weight correction coefficient.

[0202] Optionally, on the basis of each of the above embodiments, the weight distribution module can include a sensitivity coefficient unit, a scaling coefficient unit, and a correction coefficient unit, wherein:

[0203] The sensitivity coefficient unit is configured to, before calculating the repair weight assigned to the second path group according to the normalized violation delay degree value, according to the formula:

[0204] λ base= asinh (1 / σ_delay), calculating a normalized sensitivity coefficient λ corresponding to the second path group base wherein asinh(.) is an inverse hyperbolic sine function;

[0205] a scaling coefficient unit configured to determine a scaling coefficient k according to a current layout and routing optimization stage in which each module is located stage ;

[0206] a correction coefficient unit configured to calculate the weight correction coefficient λ according to a formula: λ = k stage · λ base .

[0207] Optionally, on the basis of each of the above embodiments, the weight distribution module can comprise a high repair unit, wherein:

[0208] the high repair unit is configured to, after the repair weight is respectively distributed to each path group of each target module, identify a high repair level module in each target module according to the repair weight respectively distributed to each path group of each target module, and generate boundary constraint information and clock tree intervention information corresponding to the high repair level module.

[0209] Correspondingly, on the basis of each of the above embodiments, the module optimization module 540 is further configured to:

[0210] generate the subsystem-level optimization script according to the delay constraint compensation value, the repair weight, and the boundary constraint information and clock tree intervention information corresponding to the high repair level module.

[0211] The product can execute the method provided by any embodiment of the present disclosure, and has the corresponding function modules and beneficial effects of executing the method.

[0212] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information comply with relevant laws and regulations and do not violate public order and good customs.

[0213] According to the embodiments of the present disclosure, the present disclosure further provides an electronic device, a readable storage medium and a computer program product.

[0214] Figure 6A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit the implementations of the present disclosure described and / or claimed in this document.

[0215] As shown in Figure 6 The device 600 includes a computing unit 601 that can perform various appropriate actions and processes in accordance with a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. Various programs and data required for the operation of the device 600 can also be stored in the RAM 603. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0216] Various components in the device 600 are connected to the I / O interface 605, including an input unit 606, such as a keyboard, a mouse, etc., an output unit 607, such as various types of displays, speakers, etc., a storage unit 608, such as a magnetic disk, an optical disk, etc., and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0217] The computing unit 601 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 601 performs various methods and processes described above, such as the pre-convergence timing optimization method, i.e.:

[0218] Lightweight merging of modules currently in the place and route stage into subsystems, and timing analysis on the subsystems, resulting in a plurality of cross-module timing violation paths;

[0219] Path grouping of the plurality of cross-module timing violation paths, resulting in at least one path group corresponding to each target module, respectively;

[0220] determining a delay constraint compensation value corresponding to each path group of each target module according to actual routing values of each of the cross-module timing violation paths within the path end module;

[0221] generating a subsystem-level optimization script according to each of the delay constraint compensation values, and performing optimization of module-level placement and routing through the subsystem-level optimization script.

[0222] For example, in some embodiments, the pre-convergence timing optimization method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 608. In some embodiments, portions or all of the computer program can be loaded onto and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded onto RAM 603 and executed by the computing unit 601, one or more steps of the pre-convergence timing optimization method described above can be performed. Alternatively, in other embodiments, the computing unit 601 can be configured to perform the pre-convergence timing optimization method by any other suitable means, such as by means of firmware.

[0223] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a complex programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0224] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be embodied in whole or in part within a machine, executed partially on the machine, partially on one or more remote machines, and / or entirely on one or more remote machines or servers.

[0225] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0226] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0227] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0228] The computer system can include clients and servers. This relationship can be. The servers are generally remote from the users and can be accessed via the Internet using a communication network. The relationship can be a client-server relationship over a communications network, and as such, the servers can be accessed by the clients using a protocol designed to provide communication over the Internet. The relationship can be a client-server relationship over a communications network, and as such, the servers can be accessed by the clients using a protocol designed to provide communication over the Internet. The servers can also be cloud servers, also known as cloud computing servers or cloud hosts, which are a host product in the cloud computing service system to solve the defects of large management difficulty and weak business scalability in traditional physical hosts and VPS services. The servers can also be servers of a distributed system, or servers combined with a blockchain.

[0229] Artificial intelligence is a discipline that studies enabling computers to simulate some human thinking processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.), both hardware and software technologies. Artificial intelligence hardware technology generally includes technologies such as sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing, etc.; artificial intelligence software technology mainly includes computer vision technology, speech recognition technology, natural language processing technology, machine learning / deep learning technology, big data processing technology, knowledge graph technology, etc.

[0230] Cloud computing refers to accessing elastic and scalable shared physical or virtual resource pools through a network, which can include servers, operating systems, networks, software, applications, and storage devices, and can deploy and manage resources in a self-service manner as needed. Through cloud computing technology, powerful data processing capabilities can be provided for artificial intelligence, blockchain, and other technology applications and model training.

[0231] It should be understood that various forms of the flow shown above can be used to reorder, add or delete steps. For example, each step described in the present disclosure can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions provided by the present disclosure can be achieved, which is not limited herein.

[0232] The above detailed description does not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A convergence-preceding time-series optimization method, comprising: The modules currently in the placement and routing phase are lightly merged into a subsystem, and timing analysis is performed on the subsystem to obtain multiple cross-module timing violation paths; Each cross-module timing violation path is grouped to obtain at least one path group corresponding to each target module. Based on the actual routing value of each cross-module timing violation path within the path endpoint module, determine the delay constraint compensation value corresponding to each path group of each target module. A subsystem-level optimization script is generated based on the aforementioned delay constraint compensation values, and module-level layout and routing are optimized using the subsystem-level optimization script.

2. The method according to claim 1, characterized in that, After grouping the cross-module timing violation paths to obtain at least one path group corresponding to each target module, the method further includes: Based on the time violation value of each cross-module timing violation path, a repair weight is assigned to each path group of each target module; The step of generating a subsystem-level optimization script based on each of the aforementioned delay constraint compensation values ​​includes: The subsystem-level optimization script is generated based on the respective delay constraint compensation values ​​and the respective repair weights.

3. The method according to claim 1, wherein, The step of grouping the cross-module timing violation paths to obtain at least one path group corresponding to each target module includes: Each cross-module timing violation path corresponding to the same path start module and the same path end module is assigned to the same original group; Using the path starting module as the target module, each of the original groups is assigned to a matching target module; Based on at least one of the port timing data stream type, physical location, clock domain type, and data interaction method corresponding to each of the cross-module timing paths, the original groups belonging to each of the target modules are regrouped to obtain at least one path group corresponding to each target module.

4. The method according to claim 1, wherein, The step of determining the delay constraint compensation value corresponding to each path group of each target module based on the actual routing value of each cross-module timing violation path within the path endpoint module includes: Obtain the first path group corresponding to the first target module, and obtain each first cross-module timing path in the first path group; Based on the target actual routing length of each of the first cross-module time-series paths in the path endpoint module, calculate the first statistical index value corresponding to the first path grouping. Based on the first statistical index value, the actual wiring length of each target is normalized and scored to obtain the length score value corresponding to the actual wiring length of each target. Among the various length scores, the standardized length scores that meet the standardization conditions are selected as the time delay constraint compensation values ​​corresponding to the first path group of the first target module.

5. The method according to claim 4, wherein, The first statistical indicator value includes: the average length of the actual routing length of each target in the first path group, and the standard deviation of the actual routing length of each target in the first path group; The step of normalizing and scoring the actual routing length of each target based on the first statistical index value to obtain a length score value corresponding to the actual routing length of each target includes: According to the formula: z_path_score i =(x i -μ_path) / σ_path, calculates the actual trace length x of the i-th target. i The corresponding length score z_path_score i ; Where μ_path is the average length and σ_path is the standard deviation of the length.

6. The method according to claim 4, wherein, The step of selecting standardized length scores that meet the standardization criteria from among the various length scores includes: Among the length scores, select candidate length scores that are less than or equal to the standardized constraint threshold. The maximum value among the candidate length scores is determined as the standardized length score.

7. The method according to claim 2, wherein, The step of assigning repair weights to each path group of each target module based on the time violation values ​​of each cross-module timing violation path includes: Obtain the second path group corresponding to the second target module, and obtain the second cross-module timing path in the second path group; Based on the target time violation value corresponding to each of the second cross-module timing paths, calculate the standardized time violation value corresponding to the second path group; Obtain the extreme value of time violation from each of the target time violation values, and calculate the normalized violation delay value corresponding to the second path group based on the extreme value of time violation and the normalized time violation value. Based on the normalized violation delay value, the repair weights assigned to the second path group are calculated.

8. The method according to claim 7, wherein, The step of calculating the standardized time violation value corresponding to the second path group based on the target time violation value corresponding to each of the second cross-module timing paths includes: Based on the target time violation value corresponding to each of the second cross-module timing paths, calculate the second statistical index value corresponding to the second path grouping; Based on the second statistical index value, each of the target time violation values ​​is normalized and scored to obtain the time violation score value corresponding to each of the target time violation values. Among the various time violation scores, standardized time violation values ​​that meet the standardization criteria are selected.

9. The method according to claim 8, wherein, The second statistical indicator value includes: the average value of the violation of each target time violation value corresponding to each second cross-module timing path, and the standard deviation of the violation value of each target time violation value corresponding to each second cross-module timing path; The step of normalizing and scoring each of the target time violation values ​​based on the second statistical index value to obtain a time violation score value corresponding to each of the target time violation values ​​includes: According to the formula: z_delay_score j =(y j -μ_delay) / σ_delay, calculates the target time violation value y of the j-th second cross-module timing path. j The corresponding time violation score is z_delay_score j ; Where μ_delay is the average value of the violation values, and σ_delay is the standard deviation of the violation values.

10. The method according to claim 8, wherein, From the various time violation scores, standardized time violation values ​​that meet the standardization criteria are selected, including: Among the time violation scores, select candidate time violation scores that are less than or equal to the standardized constraint threshold. The maximum value among the candidate time violation scores is determined as the standardized time violation value.

11. The method according to claim 7, wherein, The step of obtaining the extreme value of time violation from each of the target time violation values, and calculating the normalized violation delay value corresponding to the second path group based on the extreme value of time violation and the normalized time violation value, includes: According to the formula: severity_g = (z_group_slack - slack_min) / (slack_max - slack_min), calculate the normalized violation delay severity value severity_g corresponding to the second path group; Wherein, z_group_slack is the standardized time violation value, slack_min is the minimum time violation value among the target time violation values, and slack_max is the maximum time violation value among the target time violation values.

12. The method according to claim 9, wherein, The step of calculating the repair weights assigned to the second path group based on the normalized violation delay value includes: The repair weight weight assigned to the second path group is calculated according to the formula: weight_g=min(P,exp(λ*(1-severity_g))). Where P is the preset upper limit of the repair weight, and λ is the preset weight correction coefficient.

13. The method of claim 12, further comprising, before calculating the repair weight assigned to the second path group based on the normalized violation delay level value: According to the formula: λ base =asinh(1 / σ_delay), calculate the standardized sensitivity coefficient λ corresponding to the second path group. base Where asinh(.) is the inverse hyperbolic sine function; Determine the scaling factor k based on the current layout and routing optimization stage of each module. stage ; According to the formula: λ=k stage ·λ base Calculate the weight correction coefficient λ.

14. The method of claim 2, further comprising, after assigning repair weights to each path group of each target module: Based on the repair weights assigned to each path group of each target module, high-repair-level modules are identified in each target module, and boundary constraint information and clock tree intervention information corresponding to the high-repair-level modules are generated. The step of generating the subsystem-level optimization script based on each of the aforementioned delay constraint compensation values ​​and each of the aforementioned repair weights further includes: The subsystem-level optimization script is generated based on the delay constraint compensation values, the repair weights, and the boundary constraint information and clock tree intervention information corresponding to the high repair level modules.

15. A timing optimization apparatus with convergence pre-processing, comprising: The lightweight merging module is used to lightweight merge the modules currently in the placement and routing stage into a subsystem, and perform timing analysis on the subsystem to obtain multiple cross-module timing violation paths; The path grouping module is used to group the cross-module timing violation paths to obtain at least one path group corresponding to each target module. The compensation determination module is used to determine the delay constraint compensation value corresponding to each path group of each target module based on the actual routing value of each cross-module timing violation path in the path endpoint module; The module optimization module is used to generate subsystem-level optimization scripts based on the delay constraint compensation values, and to optimize module-level layout and routing through the subsystem-level optimization scripts.

16. An electronic device comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-14.

17. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-14.

18. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1-14.

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