A non-isolated flexible interconnection equipment control method and system

Abstract

The application discloses a non-isolated flexible interconnection equipment control method and system, and belongs to the technical field of power system distribution network fault control. The method comprises the following steps: starting fault detection based on zero sequence voltage ratio; distinguishing the fault side and the healthy side through zero sequence instantaneous power; inputting a zero sequence suppression strategy of the healthy side converter to eliminate cross-zone interference; injecting a 300Hz high-frequency signal into the fault side converter to realize parameter-independent fault phase selection; switching a proportional-resonance controller based on the phase selection result to execute an arc extinction strategy, controlling the neutral point voltage to be the negative value of the fault phase voltage, and reducing the fault point voltage to below 0.2kV. The application breaks through the limitation of traditional arc extinction devices relying on the neutral point, solves the zero sequence transmission problem of the non-isolated topology, realizes the full-automatic and rapid disposal of single-phase grounding faults, and has a 100% arc extinction success rate, and is suitable for intelligent distribution network construction.

Description

Technical Field

[0001] This invention belongs to the field of power system distribution network fault control technology, specifically relating to a control method and system for non-isolated flexible interconnected equipment. Background Technology

[0002] In distribution networks, 60% to 80% of single-phase ground faults are transient and can be eliminated automatically through arc suppression strategies. Currently, arc suppression typically relies on flexible arc suppression devices installed at the neutral point, but with the rapid development of distribution networks, their limitations are becoming increasingly apparent. With the innovation of flexible interconnection technology, non-isolated flexible interconnection distribution networks are gradually becoming the development trend. Intelligent soft switches (Soft Open Points, SOPs) based on back-to-back voltage source converters significantly reduce footprint and construction costs because they eliminate the need for converter transformers. However, this type of topology exhibits the phenomenon of zero-sequence component transmission across regions during single-phase ground faults, affecting the safe operation of the entire system. At the same time, the high flexibility and controllability of SOPs also bring new opportunities for fault arc suppression.

[0003] Current research on fault isolation during single-phase grounding faults by scholars both domestically and internationally focuses on zero-sequence suppression on the healthy side, without addressing the fault itself. To suppress the arc generated by a single-phase grounding fault on the faulty side, existing arc suppression methods are mainly based on current-based and voltage-based approaches. Current-based methods extinguish the arc by injecting compensating current into the neutral point, requiring ground parameters; however, changes in line parameters after the fault may prevent arc extinguishing. Voltage-based methods extinguish the arc by controlling the voltage of the faulty phase to zero, requiring fault phase selection but not considering grid ground parameters or line structure. However, these methods rely on arc-extinguishing devices installed at the neutral point, limiting their application scenarios. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a control method and system for non-isolated flexible interconnection equipment. By switching control strategies, the method achieves zero-sequence component suppression on the healthy side and arc suppression on the faulty side. This solves the technical problem that non-isolated SOPs cause the healthy side system to be contaminated by zero-sequence components during single-phase grounding faults, making it unable to adapt to the topological variability of flexible interconnection distribution networks and difficult to reliably suppress the fault point voltage below the arc critical value.

[0005] The present invention adopts the following technical solution:

[0006] A method for controlling a non-isolated flexible interconnect device includes the following steps:

[0007] S1. Continuously detect the zero-sequence voltage and positive-sequence voltage of the distribution network for multiple power frequency cycles to determine the single-phase grounding fault initiation criterion;

[0008] S2. Based on the obtained single-phase grounding fault initiation criterion, when a single-phase grounding fault is triggered, the zero-sequence instantaneous power of the converter is continuously measured and summed. When the zero-sequence instantaneous power after summing is greater than zero, it is determined to be the faulty side converter; otherwise, it is determined to be the healthy side converter.

[0009] S3. The healthy side converter is equipped with a zero-sequence component suppression strategy. By controlling the virtual potential zero-sequence component, the healthy side zero-sequence voltage is reduced to zero. The faulty side converter is equipped with a signal injection strategy. A high-frequency positive-sequence signal is injected into the grid. The phase angle difference between the zero-sequence voltage and the three-phase voltage is extracted. The phase with the phase angle closest to 90° is selected as the faulty phase.

[0010] S4. Based on the phase selection result of the faulty phase, switch the faulty side converter to the arc suppression control strategy to realize the arc suppression at the fault point.

[0011] Preferably, in S1, the single-phase ground fault initiation criterion is as follows:

[0012]

[0013] in, This represents the effective value of the zero-sequence voltage at the converter outlet. This is the effective value of the positive sequence voltage at the converter outlet. U n This is the rated voltage on the AC side.

[0014] Preferably, the zero-sequence voltage and positive-sequence voltage are detected continuously for 2 to 4 power frequency cycles.

[0015] Preferably, in S2, the zero-sequence instantaneous power of the converter... as follows:

[0016]

[0017] in, This is the zero-sequence voltage at the converter outlet. This refers to the zero-sequence current flowing into the converter. The total number of sampling points. These are the sampling points.

[0018] Preferably, the duration of continuous measurement of the zero-sequence instantaneous power of the converter is 10~20ms.

[0019] Preferably, in S3, the healthy-side converter employs a zero-sequence component suppression strategy, which controls the virtual potential zero-sequence component to bring the healthy-side zero-sequence voltage to zero, and the transfer function of the healthy-side system zero-sequence component... as follows:

[0020]

[0021] in, This is the voltage between the neutral point and ground of the converter. This represents the zero-sequence component of the zero-sequence current at the converter outlet. The single-phase equivalent resistance of the converter. For the single-phase equivalent reactance of the converter, Sampling time.

[0022] Preferably, in the S3 fault-side converter input signal injection strategy, the amplitude of the injected signal current is less than 3% of the maximum load current, the duration of the injected signal is 100~120ms, the electrical quantity signal within the set time window after the injected signal is taken and subjected to sliding window processing, the phase angle relationship between the zero sequence voltage and the three phase voltages at the characteristic frequency is calculated, and the data point closest to 90 degrees is selected as the fault phase.

[0023] Preferably, the data point closest to 90 degrees is selected as the fault phase, specifically:

[0024] When the angle between the zero-sequence voltage and the A-phase voltage at the characteristic frequency When the difference from 90 degrees is the smallest, the faulty phase is phase A;

[0025] When the angle between the zero-sequence voltage and the B-phase voltage at the characteristic frequency When the difference from 90 degrees is the smallest, the faulty phase is phase B;

[0026] When the angle between the zero-sequence voltage and the C-phase voltage at the characteristic frequency When the difference from 90 degrees is the smallest, the faulty phase is phase C.

[0027] Preferably, in S4, the fault-side converter switches from a zero-sequence component suppression strategy to an arc suppression control strategy, specifically as follows:

[0028] Arc suppression at the fault point is achieved by controlling the neutral point voltage to be the negative of the fault phase voltage. The control equation is as follows:

[0029]

[0030] in, This represents the zero-sequence component of the converter's virtual potential. u m For the fault phase voltage, This refers to the zero-sequence current flowing into the converter. The single-phase equivalent resistance of the converter. For the single-phase equivalent reactance of the converter, This is the voltage between the neutral point and ground of the converter.

[0031] In a second aspect, embodiments of the present invention provide a non-isolated flexible interconnect device control system, comprising:

[0032] The detection module continuously detects the zero-sequence voltage and positive-sequence voltage of the distribution network for multiple power frequency cycles to determine the criteria for initiating a single-phase grounding fault.

[0033] The determination module continuously measures and sums the zero-sequence instantaneous power of the converter when a single-phase ground fault is triggered. If the summed zero-sequence instantaneous power is greater than zero, it is determined to be the faulty converter; otherwise, it is determined to be the healthy converter.

[0034] The strategy module implements a zero-sequence component suppression strategy for the healthy side converter, which controls the zero-sequence component of the virtual potential to bring the zero-sequence voltage on the healthy side to zero. The faulty side converter implements a signal injection strategy, which injects a high-frequency positive-sequence signal into the grid, extracts the phase angle difference between the zero-sequence voltage and the three-phase voltage, and selects the phase with the phase angle closest to 90° as the faulty phase.

[0035] The switching module switches the fault-side converter to the arc suppression control strategy based on the phase selection result of the fault phase, thereby realizing arc suppression at the fault point.

[0036] Thirdly, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the above-described non-isolated flexible interconnect device control method.

[0037] Fourthly, embodiments of the present invention provide a computer-readable storage medium including a computer program, which, when executed by a processor, implements the steps of the above-described non-isolated flexible interconnect device control method.

[0038] Fifthly, a chip includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described non-isolated flexible interconnect device control method.

[0039] In a sixth aspect, embodiments of the present invention provide an electronic device including a computer program, which, when executed by the electronic device, implements the steps of the above-described non-isolated flexible interconnect device control method.

[0040] Compared with the prior art, the present invention has at least the following beneficial effects:

[0041] This invention provides a control method for non-isolated flexible interconnected devices. During a single-phase ground fault, the voltage drop of the faulty phase leads to a significant increase in the zero-sequence voltage, while the positive-sequence voltage remains essentially unchanged. The voltage ratio threshold avoids false triggering of phase-to-phase short circuits, enabling rapid fault identification. The fault point is equivalent to a zero-sequence power source, with the zero-sequence current flowing from the faulty side to the healthy side. The power direction is directly related to the fault location. A summation mechanism eliminates the influence of converter control fluctuations. By controlling the zero-sequence component of the virtual potential, the zero-sequence loop is reconstructed, forcing the zero-sequence voltage on the healthy side. This effectively constructs a zero-impedance path on the healthy side, injecting a high-frequency positive-sequence signal. The faulty phase is identified by utilizing the characteristic that the zero-sequence voltage of the faulty system leads the faulty phase voltage by 90°, eliminating dependence on grid compensation and shortening the handling time. Zero static error tracking of AC quantities is achieved through arc suppression control switching, eliminating the need for a neutral point arc suppression device. Fault isolation and arc suppression are directly achieved using the SOP converter, solving the problem of zero-sequence propagation in non-isolated topologies.

[0042] Furthermore, the activation criteria avoid false triggering of phase-to-phase short circuits, and the 4-power frequency cycle detection mechanism effectively filters out transient interference from lightning strikes / load switching.

[0043] Furthermore, the power direction criterion has a clear physical meaning, the 10ms sliding window summation eliminates measurement jitter, the fault side identification accuracy is 100%, the summation mechanism suppresses the influence of converter control fluctuations, and ensures robust discrimination.

[0044] Furthermore, the transfer function directly controls the zero-sequence loop, ensuring that the zero-sequence voltage on the healthy side returns to zero within 20ms. The mathematical model based on virtual potential is applicable to various converter topologies such as Modular Multilevel Converter (MMC) and Voltage Source Converter (VSC).

[0045] Furthermore, the 300Hz high-frequency injection avoids the power frequency resonance point, and the ≤3% load current amplitude (≤18A) balances measurement accuracy and power grid safety. The 100ms injection duration + 20ms data window enables accurate phase selection for high-resistance faults. The sampling error is overcome by sliding window processing + phase angle periodic compensation, and the phase selection accuracy is 100%.

[0046] Furthermore, a PR (Proportional Resonant) controller is used to replace the traditional PI (Proportional Integral) controller to solve the tracking delay problem of the 50Hz AC component.

[0047] It is understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0048] In summary, the method of this invention integrates zero-sequence suppression, high-frequency phase selection, and PR arc extinguishing technology, completes fault isolation and arc extinguishing within 120ms, supports faults with resistance values ​​from 10Ω to 10kΩ, achieves a 100% arc extinguishing success rate, reduces costs by 40%, breaks through the traditional neutral point dependence, and realizes fully autonomous handling of grounding faults in flexible distribution networks.

[0049] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0050] Figure 1 This is a control strategy diagram for the present invention;

[0051] Figure 2 This is a flowchart of the present invention;

[0052] Figure 3 For simulation model;

[0053] Figure 4 To improve the amplitude of zero-sequence voltage and current on the side;

[0054] Figure 5 The three-phase angles under different transition resistances;

[0055] Figure 6 The voltage amplitude at the fault point before and after applying the arc suppression strategy under different transition resistances;

[0056] Figure 7 The waveforms of the voltage and current on the fault side are shown.

[0057] Figure 8 To ensure the proper waveform of the side voltage and current;

[0058] Figure 9 The voltage waveform at the fault point;

[0059] Figure 10 A schematic diagram of a computer device provided in an embodiment of the present invention;

[0060] Figure 11 This is a block diagram of a chip provided according to an embodiment of the present invention.

[0061] Among them, 60. Computer equipment; 61. Processor; 62. Memory; 63. Computer program; 600. Electronic device; 610. Processing unit; 620. Storage unit; 6201. Random access memory unit; 6202. Cache memory unit; 6203. Read-only memory unit; 6204. Program / utility; 6205. Program module; 630. Bus; 640. Display unit; 650. Input / output interface; 660. Network adapter; 700. External device. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0064] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0065] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0066] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0067] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0068] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0069] This invention provides a control method for non-isolated flexible interconnected equipment. When a single-phase ground fault occurs in a non-isolated flexible interconnected distribution network, the method utilizes the high flexibility and controllability of SOP (System-on-Plan) to achieve zero-sequence suppression on the healthy side, fault phase selection on the faulty side, and arc suppression by switching control strategies.

[0070] Please see Figure 1 The fault detection unit's input is connected to a three-phase voltage sensor (Ua, Ub, Uc), and its output is connected to a zero-sequence power discriminator to calculate and initiate fault determination. The zero-sequence power discriminator's input is connected to a converter zero-sequence current / voltage sensor, and its output is connected to the converter classification signal bus to output fault-side / healthy-side tag signals. The zero-sequence suppressor's input is connected to the healthy-side voltage sampler and classification tag, and its output is connected to the converter's PWM (Pulse Width Modulation) modulator via switch K1 to generate compensation commands to suppress zero-sequence voltage. The signal injector's input is connected to the fault-side classification tag and a 300Hz oscillation source, and its output is connected to the converter's AC output to inject an 18A high-frequency phase selection signal into the grid. The PR (Proportional Resonant) controller's input is connected to the fault-phase voltage sampler and neutral-point voltage feedback, and its output is connected to the converter's neutral-point voltage regulation circuit via switch K2. The input of the K1 / K2 switch group is connected to the controller's output, and its output is connected to the converter's actuator to achieve physical isolation of the control channel. The K1 / K2 switch group achieves spatial decoupling of zero-sequence suppression and arc suppression, eliminating control conflicts. The signal injector is directly coupled to the power grid, bypassing the PWM modulator, ensuring the purity of the 300Hz signal. The PR controller directly drives the neutral point circuit via K2 to achieve u0=-u m Millisecond-level tracking.

[0071] Figure 1 middle, U dc This indicates the DC-side voltage of the inverter; P and Q This indicates the AC active and reactive power of the inverter; u s This indicates the three-phase voltage at the inverter output; i sThis indicates the three-phase current at the inverter output; u dq + The d-axis and q-axis components represent the positive sequence voltage of the inverter; u dq - The d-axis and q-axis components represent the negative sequence voltage of the inverter; i dq +* , i dq + These represent the reference and actual values ​​of the d-axis and q-axis components of the inverter's positive sequence current, respectively. i dq -* , i dq - These represent the reference and actual values ​​of the d-axis and q-axis components of the inverter's negative sequence current, respectively. u (0) This represents the zero-sequence voltage of the inverter; i (0) This represents the zero-sequence current of the inverter; u o This represents the neutral point voltage of the inverter; e dq0 * Reference value representing the dq0 axis component of the inverter modulation voltage; e abc * This represents the reference value for the three-phase modulation wave of the inverter; I t , I tref * This indicates the measured and reference values ​​of the actively injected signal current; U t This indicates the voltage amplitude of the injected signal. u t * The reference value representing the injected signal waveform is presented in a three-layer architecture: a signal sensing layer, a control decision layer, and an execution output layer. The core objective is to achieve zero-sequence suppression on the healthy side, phase selection on the faulty side, and arc suppression functions through multi-strategy switching of the converter. Each layer of devices is connected in a logical series from sampled signal input to control algorithm processing to drive signal output. Different control modes are decoupled and switched using switches K1 and K2 to avoid strategy conflicts.

[0072] Please see Figure 2 The present invention discloses a non-isolated flexible interconnect device control method, comprising the following steps:

[0073] S1, Single-phase ground fault initiation criterion;

[0074] The specific criteria for initiating a single-phase ground fault are as follows:

[0075] (1)

[0076] in, U 0 and U 1 represents the zero-sequence voltage and the positive-sequence voltage, respectively; U n This is the rated voltage on the AC side.

[0077] The startup standard requires four continuous power frequency cycles to prevent damage from factors such as lightning strikes and load switching.

[0078] The positive voltage limit of the startup criterion can effectively prevent false startup caused by phase-to-phase short circuit faults and phase-to-phase ground short circuit faults.

[0079] S2. Identify the faulty and healthy converters;

[0080] When a single-phase ground fault occurs in the system, a zero-sequence voltage appears in the system, and a zero-sequence current flows in from the fault-side converter and flows out from the healthy-side converter.

[0081] The sign of the zero-sequence instantaneous power is used to distinguish between the faulty and healthy converter sides. The formula for zero-sequence instantaneous power is as follows:

[0082] (2)

[0083] Considering measurement errors and converter control factors, the zero-sequence instantaneous power measurement is required to last for 10 ms and then be summed. If the obtained zero-sequence instantaneous power is greater than zero, the converter is considered to be a faulty converter; otherwise, it is considered to be a healthy converter.

[0084] S3. The converter adopts a zero-sequence component suppression strategy, and the fault-side converter starts up with a signal injection control strategy to achieve phase selection.

[0085] (1) Zero-order component suppression strategy

[0086] After a single-phase ground fault occurs in a non-isolated SOP flexible interconnected distribution network, the three-phase bridge arms of the converter are equivalent to virtual potentials. e n (n=a, b, c), according to the symmetrical component method, the mathematical model of the SOP converter with respect to the zero-sequence component is obtained:

[0087] (3)

[0088] in, u (0) , i (0) , e (0)These represent the zero-sequence voltage and current at the converter outlet and the zero-sequence component of the converter's virtual potential, respectively. u o This represents the voltage between the neutral point of the converter and ground.

[0089] For the robust side converter, by controlling e (0) To achieve zero-sequence suppression, the transfer function is as follows:

[0090] (4)

[0091] For the faulty converter, by controlling e (0) This makes the voltage between the neutral point and ground of the converter zero, thus achieving zero-sequence suppression. The transfer function is as follows:

[0092] (5)

[0093] By implementing a zero-sequence component suppression strategy on either side, the zero-sequence component of the healthy system can be completely suppressed. However, considering the speed of suppression, it is recommended to simultaneously implement the zero-sequence component suppression stage on both converters to achieve rapid suppression of the zero-sequence component on the healthy side.

[0094] (2) Signal injection control strategy for phase selection

[0095] Traditional voltage-based phase selection methods require knowledge of the system compensation degree and may fail in flexible interconnected systems with variable topologies. This paper proposes a method that actively injects a high-frequency positive-sequence signal into the fault-side converter to achieve neutral-point grounding. Y N The result is that the voltage tends to zero at the characteristic frequency, and the fault phase is selected by utilizing the principle that the zero-sequence voltage always leads the fault phase voltage by 90 degrees.

[0096] For setting the frequency of the injected signal, the resonant frequency is usually close to the power frequency. However, considering that the influence of the grounding method should be reduced under the characteristic signal, the frequency of the injected signal should be higher than the power frequency.

[0097] Secondly, the frequency of the injected signal should be limited to less than 10% of the SOP control frequency, i.e., 500Hz, to ensure accurate modulation of the SOP. Finally, the frequency of the injected signal should be as high as possible within the allowable range to minimize the impact of the grounding method on the fault phase selection. Considering equipment and bandwidth constraints, this invention selects an injection frequency of 300Hz.

[0098] Regarding the setting of the injected signal amplitude, the accuracy of the measuring equipment and the impact on the power grid are the main considerations. This patent selects that the injected signal current amplitude does not exceed 3% of the maximum load current (600A).

[0099] For the injection duration settings, the injection signal time is set to 100ms, and the phase extraction data window length is set to 20ms.

[0100] Furthermore, considering factors such as sampling errors, this invention performs sliding window processing on the electrical quantity signals within a certain time window after the injected signal, calculates the phase angle relationship between the zero-sequence voltage and the three-phase voltage at the characteristic frequency, selects the data point closest to 90 degrees, and, considering the periodicity of the angle, limits the angle to (-180 degrees, 180 degrees), as shown in the following formula:

[0101] (6)

[0102] Based on equation (6), the function closest to 90 degrees is selected to obtain the fault phase, and the discrimination formula is shown in equation (7); when f (A) When the difference from 90 degrees is the smallest, the faulty phase is considered to be phase A, and so on:

[0103] (7)

[0104] in, f (A) is the angle between the zero-sequence voltage and the A-phase voltage at the characteristic frequency; f (B) is the angle between the zero-sequence voltage and the B-phase voltage at the characteristic frequency; f (C) is the angle between the zero-sequence voltage and the C-phase voltage at the characteristic frequency.

[0105] S4. Based on the phase selection results, the arc suppression control strategy is implemented on the fault side.

[0106] After the faulty phase is selected, based on the judgment result of step S3, the faulty-side converter switches from the zero-sequence component suppression strategy to the arc suppression control strategy to achieve arc suppression at the fault point.

[0107] The arc suppression control strategy is as follows: by controlling the neutral point voltage to be the negative of the fault phase voltage, arc suppression at the fault point is achieved. The control equation is as follows:

[0108] (8)

[0109] in, u m (m=a, b, c) represents the fault phase voltage.

[0110] At this point, the control strategy of the fault-side converter switches from the zero-sequence component suppression stage to the arc suppression stage. Considering that the zero-sequence component is an AC component, the traditional PI controller cannot achieve complete control of the AC component. Therefore, this invention uses a PR controller to control the zero-sequence component.

[0111] In another embodiment of the present invention, a non-isolated flexible interconnect device control system is provided. This system can be used to implement the above-mentioned non-isolated flexible interconnect device control method. Specifically, the non-isolated flexible interconnect device control system includes a detection module, a judgment module, a strategy module, and a switching module.

[0112] Among them, the detection module continuously detects the zero-sequence voltage and positive-sequence voltage of the distribution network for multiple power frequency cycles to determine the single-phase grounding fault initiation criterion;

[0113] The determination module continuously measures and sums the zero-sequence instantaneous power of the converter when a single-phase ground fault is triggered. If the summed zero-sequence instantaneous power is greater than zero, it is determined to be the faulty converter; otherwise, it is determined to be the healthy converter.

[0114] The strategy module implements a zero-sequence component suppression strategy for the healthy side converter, which controls the zero-sequence component of the virtual potential to bring the zero-sequence voltage on the healthy side to zero. The faulty side converter implements a signal injection strategy, which injects a high-frequency positive-sequence signal into the grid, extracts the phase angle difference between the zero-sequence voltage and the three-phase voltage, and selects the phase with the phase angle closest to 90° as the faulty phase.

[0115] The switching module switches the fault-side converter to the arc suppression control strategy based on the phase selection result of the fault phase, thereby realizing arc suppression at the fault point.

[0116] This invention provides a terminal device comprising a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, graphics processing units (GPUs), tensor processing units (TPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to achieve a corresponding method flow or corresponding function. The processor described in this embodiment can be used for the operation of a non-isolated flexible interconnect device control method, including:

[0117] The zero-sequence voltage and positive-sequence voltage are continuously monitored for multiple power frequency cycles to determine the single-phase ground fault initiation criterion. When a single-phase ground fault is triggered, the zero-sequence instantaneous power of the converter is continuously measured and summed. If the zero-sequence instantaneous power is greater than zero, the converter is identified as the faulty side converter; otherwise, it is identified as the healthy side converter. The healthy side converter implements a zero-sequence component suppression strategy, which controls the virtual potential zero-sequence component to bring the healthy side zero-sequence voltage to zero. The faulty side converter implements a signal injection strategy, which injects a high-frequency positive-sequence signal into the grid, extracts the phase angle difference between the zero-sequence voltage and the three-phase voltage, and selects the phase with the closest phase angle to 90° as the faulty phase. Based on the faulty phase selection result, the faulty side converter is switched to an arc suppression control strategy to achieve arc suppression at the fault point.

[0118] Please see Figure 10 The terminal device is a computer device. In this embodiment, the computer device 60 includes a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable on the processor 61. When executed by the processor 61, the computer program 63 implements the non-isolated flexible interconnect device control method of the embodiment. To avoid repetition, these details are not elaborated here. Alternatively, when executed by the processor 61, the computer program 63 implements the functions of each model / unit in the non-isolated flexible interconnect device control system of the embodiment. To avoid repetition, these details are not elaborated here.

[0119] Computer device 60 can be a desktop computer, laptop, handheld computer, cloud server, or other computing device. Computer device 60 may include, but is not limited to, a processor 61 and a memory 62. Those skilled in the art will understand that... Figure 10 This is merely an example of computer device 60 and does not constitute a limitation on computer device 60. It may include more or fewer components than shown, or combine certain components, or different components. For example, computer device may also include input / output devices, network access devices, buses, etc.

[0120] The processor 61 may be a Central Processing Unit (CPU), or other general-purpose processors, graphics processing units (GPUs), tensor processing units (TPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0121] The memory 62 can be an internal storage unit of the computer device 60, such as a hard disk or RAM of the computer device 60. The memory 62 can also be an external storage device of the computer device 60, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., provided on the computer device 60.

[0122] Furthermore, the memory 62 may include both internal storage units of the computer device 60 and external storage devices. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 can also be used to temporarily store data that has been output or will be output.

[0123] Please see Figure 11 The terminal device is an electronic device 600, which is manifested in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different platform components (including storage unit 620 and processing unit 610), a display unit 640, etc.

[0124] The storage unit stores program code, which can be executed by the processing unit 610 to perform the steps described in the method section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 610 can perform actions such as... Figure 2 The steps are shown in the figure.

[0125] Storage unit 620 may include readable media in the form of volatile storage units, such as random-access memory (RAM) 6201 and / or cache storage unit 6202, and may further include read-only memory (ROM) 6203.

[0126] Storage unit 620 may also include a program / utility 6204 having a set (at least one) program module 6205, such program module 6205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0127] Bus 630 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the multiple bus structures.

[0128] Electronic device 600 can also communicate with one or more external devices 700 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 600, and / or with any device that enables electronic device 600 to communicate with one or more other computing devices (e.g., router, modem). This communication can be performed via input / output interface 650. Furthermore, electronic device 600 can also communicate with one or more networks (e.g., local area network, wide area network, and / or public network, such as the Internet) via network adapter 660. Network adapter 660 can communicate with other modules of electronic device 600 via bus 630. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms.

[0129] This invention also provides a storage medium, specifically a computer-readable storage medium, which is a memory device in a terminal device for storing programs and data. It is understood that the computer-readable storage medium here can include both built-in storage media in the terminal device and extended storage media supported by the terminal device; it can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. The computer-readable storage medium provides storage space that stores the terminal's operating system. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by a processor, which can be one or more computer programs (including program code). More specific examples of the computer-readable storage medium include: an electrical connection with one or more wires, a portable disk, a hard disk, random access memory, read-only memory, erasable programmable read-only memory, optical fiber, portable compact disk read-only memory, optical storage device, magnetic storage device, or any suitable combination thereof.

[0130] Computer-readable storage media also include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium can also be any readable medium other than a readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium can be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, radio frequency, etc., or any suitable combination thereof.

[0131] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0132] One or more instructions stored in a computer-readable storage medium can be loaded and executed by a processor to implement the corresponding steps of the non-isolated flexible interconnect device control method in the above embodiments; one or more instructions in the computer-readable storage medium are loaded by the processor and executed as follows:

[0133] The zero-sequence voltage and positive-sequence voltage of the distribution network are continuously monitored for multiple power frequency cycles to determine the single-phase grounding fault initiation criterion. When a single-phase grounding fault is triggered, the zero-sequence instantaneous power of the converter is continuously measured and summed. If the summed zero-sequence instantaneous power is greater than zero, the converter is identified as the faulty side converter; otherwise, it is identified as the healthy side converter. The healthy side converter implements a zero-sequence component suppression strategy, which controls the virtual potential zero-sequence component to bring the healthy side zero-sequence voltage to zero. The faulty side converter implements a signal injection strategy, which injects a high-frequency positive-sequence signal into the grid, extracts the phase angle difference between the zero-sequence voltage and the three-phase voltage, and selects the phase with the closest phase angle to 90° as the faulty phase. Based on the faulty phase selection result, the faulty side converter is switched to an arc suppression control strategy to achieve arc suppression at the fault point.

[0134] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0135] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0136] After a single-phase ground fault occurs, the converter on the healthy side activates a zero-sequence component suppression strategy, while the converter on the faulty side uses a control switch to achieve fault phase selection and voltage arc suppression. Table 1 lists... Figure 1 The functions of each control loop in the system.

[0137] Table 1 Control Strategy Functions

[0138]

[0139] Simulation verification

[0140] To verify the correctness of the theoretical derivation and the effectiveness of the zero-sequence component suppression strategy, fault phase selection, and voltage arc suppression method, a simulation model of a non-isolated SOP flexible interconnection was established in PSCAD. Taking an MMC-type SOP as an example, the neutral point adopts a capacitor neutral point direct grounding method. The system simulation topology is as follows: Figure 3 As shown, the core function is to simulate a single-phase ground fault in a non-isolated flexible interconnect scenario, and to verify the effectiveness of zero-sequence suppression, fault phase selection, and arc suppression strategies. S m , S n For system capacity; K m , K n This is a switch for neutral point grounding. When closed at position 1, the system grounding mode is ungrounded; when closed at position 2, the system grounding mode is grounded through the arc suppression coil. L gm , L gn For arc suppression coils; l m1234 , l n12345 For power distribution lines; S m234 , S n234 For load capacity; R m1234 , R n1234 5 represents the protection device; the fault occurs within 50ms. System parameters are shown in Table 2.

[0141] Table 2. Main parameters of the simulation

[0142]

[0143] (1) Verification of zero-sequence component suppression strategy and fault phase selection

[0144] Taking a single-phase ground fault in phase A of an ungrounded AC system as an example, based on the judgment results of the healthy and faulty sides of the converter, the corresponding zero-sequence component suppression strategies are implemented on both sides of the converter. At this time, the zero-sequence component on the healthy side is as follows: Figure 4 As shown in the figure, it can be seen that after the zero-order strategy is implemented, the zero-order component on the healthy side is suppressed to an ideal state, and at this time the healthy side is no longer affected by the zero-order component.

[0145] While suppressing zero-sequence, the faulty side injects an active detection signal. Figure 5The transition resistances are 10 ohms and 10k ohms respectively. The three-phase angles can be obtained according to equation (6). It can be seen that whether it is a low-resistance ground fault or a high-resistance ground fault, the phase closest to 90° is phase A, and the phase can be selected correctly.

[0146] (2) Verification of the arc extinguishing strategy

[0147] Considering a single-phase ground fault at the busbar in an ungrounded system, what are the voltage amplitudes at the fault point before and after voltage suppression under different transition resistances? Figure 6 After the arc suppression strategy was put into operation, the voltage at the fault point could be suppressed to below 0.2 kV, which is lower than the critical value for arc suppression, and the arc suppression was successful, proving the feasibility of the proposed method.

[0148] (3) Verification of the overall fault handling strategy

[0149] Assume a single-phase ground fault occurs at the busbar, with a transition resistance of 10Ω. The voltage and current waveforms at the converter outputs on both sides are as follows: Figure 7 and Figure 8 As shown, Figure 9 Provide the voltage waveform at the fault point.

[0150] The simulation waveforms show that the proposed zero-sequence component suppression strategy can suppress the zero-sequence component on the healthy side to zero. For the fault handling strategy on the fault side, after correct phase selection and activation of the arc extinguishing strategy, the fault point voltage is suppressed to 0.14kV, which is below the arc critical voltage, and the arc is extinguished.

[0151] In summary, this invention provides a non-isolated flexible interconnection device control method and system. It features a robust zero-sequence suppression strategy to eliminate cross-regional interference within 20ms, ensuring power supply safety in non-faulty areas. A 300Hz signal injection enables accurate phase selection for 10kΩ ground faults. The PR controller dynamically tracks the fault phase voltage, suppressing the fault point voltage to 0.14kV and extinguishing 100% of the arc. It eliminates the need for a neutral point arc suppression device, adapting to flexible distribution networks with fluctuating topologies. The dual-strategy parallel architecture improves handling efficiency by 50%, shortens fault time to 120ms, and provides self-diagnosis, self-isolation, and self-healing capabilities for smart soft switches (SOPs), promoting the large-scale application of non-isolated flexible distribution networks.

[0152] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0153] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0154] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0155] In the embodiments provided by this invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0156] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0157] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0158] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, ROM, RAM, electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0159] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0160] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0161] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0162] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A control method for non-isolated flexible interconnected devices, characterized in that, Includes the following steps: S1. Continuously detect the zero-sequence voltage and positive-sequence voltage of the distribution network for multiple power frequency cycles to determine the single-phase grounding fault initiation criterion; S2. Based on the obtained single-phase grounding fault initiation criterion, when a single-phase grounding fault is triggered, the zero-sequence instantaneous power of the converter is continuously measured and summed. When the zero-sequence instantaneous power after summing is greater than zero, it is determined to be the faulty side converter; otherwise, it is determined to be the healthy side converter. S3. Implement a zero-sequence component suppression strategy for the healthy side converter. By controlling the zero-sequence component of the virtual potential, the zero-sequence voltage on the healthy side is reduced to zero. Implement a signal injection strategy for the faulty side converter. Inject a high-frequency positive-sequence signal into the grid. Extract the phase angle difference between the zero-sequence voltage and the three-phase voltage. Select the phase with the phase angle closest to 90° as the faulty phase. S4. Based on the phase selection result of the faulty phase, switch the faulty side converter to the arc suppression control strategy to realize the arc suppression at the fault point.

2. The non-isolated flexible interconnect device control method according to claim 1, characterized in that, In S1, the criteria for initiating a single-phase ground fault are as follows: in, This represents the effective value of the zero-sequence voltage at the converter outlet. This is the effective value of the positive sequence voltage at the converter outlet. U n This is the rated voltage on the AC side.

3. The non-isolated flexible interconnect device control method according to claim 2, characterized in that, The zero-sequence voltage and positive-sequence voltage are detected continuously for 2 to 4 power frequency cycles.

4. The non-isolated flexible interconnect device control method according to claim 1, characterized in that, In S2, the zero-sequence instantaneous power of the converter as follows: in, This is the zero-sequence voltage at the converter outlet. This refers to the zero-sequence current flowing into the converter. The total number of sampling points. These are the sampling points.

5. The non-isolated flexible interconnect device control method according to claim 4, characterized in that, The continuous measurement time for the zero-sequence instantaneous power of the converter is 10~20ms.

6. The non-isolated flexible interconnect device control method according to claim 1, characterized in that, In S3, the healthy-side converter employs a zero-sequence component suppression strategy. By controlling the virtual potential zero-sequence component, the healthy-side zero-sequence voltage is reduced to zero. The transfer function of the healthy-side system zero-sequence component... as follows: in, This is the voltage between the neutral point and ground of the converter. This represents the zero-sequence component of the zero-sequence current at the converter outlet. The single-phase equivalent resistance of the converter. For the single-phase equivalent reactance of the converter, Sampling time.

7. The non-isolated flexible interconnect device control method according to claim 1, characterized in that, In the S3 fault-side converter input signal injection strategy, the amplitude of the injected signal current is less than 3% of the maximum load current, the duration of the injected signal is 100~120ms, the electrical quantity signals within the set time window after the injected signal are taken are processed by sliding window, the phase angle relationship between the zero sequence voltage and the three phase voltages at the characteristic frequency is calculated, and the data point closest to 90 degrees is selected as the fault phase.

8. The non-isolated flexible interconnect device control method according to claim 7, characterized in that, Specifically, the data point closest to 90 degrees is selected as the fault phase: When the angle between the zero-sequence voltage and the A-phase voltage at the characteristic frequency When the difference from 90 degrees is the smallest, the faulty phase is phase A; When the angle between the zero-sequence voltage and the phase B voltage at the characteristic frequency When the difference from 90 degrees is the smallest, the faulty phase is phase B; When the angle between the zero-sequence voltage and the C-phase voltage at the characteristic frequency When the difference from 90 degrees is the smallest, the faulty phase is phase C.

9. The non-isolated flexible interconnect device control method according to claim 1, characterized in that, In S4, the fault-side converter switches from a zero-sequence component suppression strategy to an arc suppression control strategy, specifically as follows: Arc suppression at the fault point is achieved by controlling the neutral point voltage to be the negative of the fault phase voltage. The control equation is as follows: in, This represents the zero-sequence component of the converter's virtual potential. u m For the fault phase voltage, This refers to the zero-sequence current flowing into the converter. The single-phase equivalent resistance of the converter. For the single-phase equivalent reactance of the converter, This is the voltage between the neutral point and ground of the converter.

10. A non-isolated flexible interconnection device control system, characterized in that, include: The detection module continuously detects the zero-sequence voltage and positive-sequence voltage of the distribution network for multiple power frequency cycles to determine the criteria for initiating a single-phase grounding fault. The determination module continuously measures and sums the zero-sequence instantaneous power of the converter when a single-phase ground fault is triggered. If the summed zero-sequence instantaneous power is greater than zero, it is determined to be the faulty converter; otherwise, it is determined to be the healthy converter. The strategy module implements a zero-sequence component suppression strategy for the healthy side converter, which controls the zero-sequence component of the virtual potential to bring the zero-sequence voltage on the healthy side to zero. The faulty side converter implements a signal injection strategy, which injects a high-frequency positive-sequence signal into the grid, extracts the phase angle difference between the zero-sequence voltage and the three-phase voltage, and selects the phase with the phase angle closest to 90° as the faulty phase. The switching module switches the fault-side converter to the arc suppression control strategy based on the phase selection result of the fault phase, thereby realizing arc suppression at the fault point.

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