High-frequency synchronization method for wired parallel connection of inverters

Abstract

The application discloses an inverter wired parallel machine high-frequency synchronization method, which is used for realizing power frequency synchronization and high-frequency carrier wave synchronization through a group of power frequency synchronization signals and comprises the following steps: circuit configuration; after a plurality of inverters are connected in parallel in a master-slave working mode, output ends are connected to load equipment; a master device sends a power frequency synchronization signal to a slave device; the slave device detects the power frequency synchronization signal; a phase difference of a high-frequency carrier wave signal between the slave device and the master device is calculated; and the slave device adjusts a high-frequency carrier wave frequency of itself according to the phase difference. Compared with a traditional scheme, the number of IO ports is reduced, the circuit structure is simplified, and the requirement of circuit components is reduced. Meanwhile, the synchronization signal is accurately captured through the capture function of a master control unit, synchronization information is acquired, the carrier wave frequency of the slave device is adjusted through a software algorithm, parallel connection is realized, the influence of signal delay of a hardware circuit on parallel connection is greatly weakened, the universality is higher, the reliability is higher, and the parallel connection effect is better.

Description

Technical Field

[0001] This invention relates to the field of inverter parallel application technology, specifically to a high-frequency synchronization method for wired parallel operation of inverters. Background Technology

[0002] As photovoltaic power plants and energy storage systems expand in scale, the capacity of a single inverter is insufficient to meet demand, necessitating the parallel operation of multiple inverters. Traditional wireless parallel connection is susceptible to interference, leading to circulating current and power oscillations. Wired parallel technology achieves high-speed and precise synchronization control between inverters through dedicated communication cables (such as I / O buses), ensuring strict consistency in phase, frequency, and voltage, effectively suppressing circulating current, and improving system stability and efficiency. This technology is a core solution supporting the high-reliability expansion of large-scale new energy power plants.

[0003] Traditional multi-unit parallel operation requires additional configuration of synchronous communication circuits, high-precision sampling modules, and current sharing control units. The main power topology and signal interaction links are deeply coupled, significantly increasing hardware design complexity and system cost. Existing wired parallel inverter methods use two sets of synchronization signals plus dedicated communication lines to establish a real-time information exchange channel between the parallel inverters, such as... Figure 1 As shown, one set is the power frequency synchronization signal, used to synchronize the power frequency of the master and slave machines; another set is the high frequency synchronization signal, used to synchronize the high frequency carrier signal; and the communication line is used to synchronize the inverter status information.

[0004] In existing wired parallel inverter solutions, the power frequency synchronization signal and the high frequency synchronization signal need to be transmitted separately, which makes the equipment structure complex and the processing cumbersome. Summary of the Invention

[0005] Therefore, it is necessary to provide a high-frequency synchronization method for wired parallel operation of inverters that can simultaneously achieve power frequency synchronization and high-frequency synchronization through a power frequency synchronization signal.

[0006] A method for wired parallel high-frequency synchronization of inverters, used to achieve power frequency synchronization and high-frequency carrier synchronization through a set of power frequency synchronization signals, the method comprising the following steps:

[0007] Step 1, Circuit Configuration: After multiple inverters are connected in parallel in master-slave mode, their output terminals are connected to the load device.

[0008] Step 2: The host device sends a power frequency synchronization signal to each slave device, and each slave device detects the received power frequency synchronization signal.

[0009] Step 3: Calculate the phase difference of the high-frequency carrier signal between the slave device and the master device;

[0010] Step four: Each of the slave devices adjusts its own high-frequency carrier frequency according to the phase difference.

[0011] Preferably, step one, the specific steps of circuit configuration, includes:

[0012] Step 1.1: Connect the output terminals of multiple inverters in parallel to the load device;

[0013] Step 1.2: Identify the master device and slave devices; one of them is the master device, and the rest are slave devices. Set up communication cables between the master device and the slave devices.

[0014] Step 1.3: The master control unit of the host device and the master control unit of the slave device establish a communication connection through CAN communication to realize the synchronization of the status information of the inverter parallel system;

[0015] Step 1.4: The high-frequency carrier signal counters in the host device and slave device begin counting.

[0016] Preferably, the specific method for determining the master device and slave device in step 1.2 is either system-specified or dynamically elected.

[0017] Preferably, the host device and the slave device each include a master control unit. The master control unit adopts a master control chip configured with IO port capture function. The GPIO port of the master control chip of the slave device is configured in input mode and connected to the output port of the master control chip of the host device.

[0018] Preferably, the master control unit of the host device and the slave device each include a modulation wave counter and a high-frequency carrier signal counter. The modulation wave counter is used to count the modulation wave signal, and the high-frequency carrier signal counter is used to count the high-frequency carrier signal. On the rising edge of the power frequency synchronization signal, the modulation wave counter and the high-frequency carrier signal counter are reset and start counting again from 0.

[0019] Preferably, the high-frequency carrier signal counter in the host device is a first high-frequency carrier signal counter, which is used to count the high-frequency carrier signals of the host device; the high-frequency carrier signal counter in the slave device is a second high-frequency carrier signal counter, which is used to count the high-frequency carrier signals of the slave device.

[0020] When the rising edge of the power frequency synchronization signal arrives, the slave device reads the count value in the second high-frequency carrier signal counter, compares the count value of the second high-frequency carrier signal counter with the count value of the first high-frequency carrier signal counter, and adjusts the frequency of the high-frequency carrier signal of the slave device according to the comparison result.

[0021] Preferably, in step two, the host device sends a power frequency synchronization signal to each slave device, and the specific steps for each slave device to detect the received power frequency synchronization signal include:

[0022] Step 2.1: The high-frequency carrier signal counters in the host device and the slave device count the high-frequency carrier signals;

[0023] Step 2.2: The main control unit of the host device flips and generates the power frequency synchronization signal of the host device based on the time point when the inverter AC signal crosses zero and the carrier signal count value is zero.

[0024] Step 2.3: The host device sends the generated power frequency synchronization signal to the master control unit of the slave device;

[0025] Step 2.4: The main control unit of the host device receives and detects the power frequency synchronization signal;

[0026] Step 2.5: The slave device captures the rising edge of the power frequency synchronization signal and generates an interrupt signal;

[0027] Step 2.6: The interrupt signal locks onto and follows the power frequency synchronization signal. The slave device adjusts the voltage amplitude, frequency, and phase of its output voltage signal according to the period of the interrupt signal, so that it is completely consistent with the voltage amplitude, frequency, and phase of the master device.

[0028] Preferably, step three, calculating the phase difference of the high-frequency carrier signal between the slave device and the master device, includes the following specific steps:

[0029] Step 3.1: The slave device acquires the count value of the second high-frequency carrier signal counter before it is reset;

[0030] Step 3.2: Compare the count value of the second high-frequency carrier signal counter of the slave device with the count value of the first high-frequency carrier signal counter of the master device;

[0031] Step 3.3: Determine the phase difference between the high-frequency carrier signal of the slave device and the high-frequency carrier signal of the master device based on the difference between the count value of the second high-frequency carrier signal counter of the slave device and the count value of the first high-frequency carrier signal counter of the master device.

[0032] Preferably, step four, in which each slave device adjusts its own high-frequency carrier frequency according to the phase difference, includes the following specific steps:

[0033] Step 4.1: If the count value of the second high-frequency carrier signal counter of the slave device before reset is greater than the count value of the first high-frequency carrier signal counter of the master device before reset, and the high-frequency carrier signal of the slave device leads the high-frequency carrier signal of the master device, then the slave device reduces the frequency of the high-frequency carrier signal.

[0034] Step 4.2: If the count value of the second high-frequency carrier signal counter of the slave device before reset is less than the count value of the first high-frequency carrier signal counter of the master device before reset, and the high-frequency carrier signal of the slave device lags behind the high-frequency carrier signal of the master device, then the slave device increases the frequency of the high-frequency carrier signal.

[0035] Step 4.3: If the count value of the second high-frequency carrier signal counter of the slave device before reset is equal to the count value of the first high-frequency carrier signal counter of the master device before reset, then the slave device maintains the frequency of the high-frequency carrier signal unchanged.

[0036] In the above-mentioned wired parallel high-frequency synchronization method for inverters, the master device transmits the power frequency synchronization signal through the ordinary I / O port of the master control unit. The master control unit of the slave device acquires the power frequency synchronization signal information sent by the master device through the I / O port with capture function, and obtains the power frequency frequency of the master device. When the power frequency synchronization signal of the master device is transmitted to the slave device, an interrupt is triggered and the carrier count value of the slave device at this moment is acquired. The phase difference between the high-frequency carrier of the slave device and the high-frequency carrier of the master device is calculated. The slave device achieves synchronization of the master and slave carrier signals by adjusting the carrier frequency, reducing parallel circulating current. The technical solution of this invention achieves parallel synchronization through the ordinary I / O port of a master control unit. Compared with the traditional solution, it reduces the number of I / O ports used, simplifies the circuit structure, and lowers the requirements of circuit components. At the same time, the master control unit accurately captures the synchronization signal through its capture function, obtains synchronization information, and adjusts the slave carrier frequency through software algorithms to achieve parallel operation, greatly reducing the impact of hardware circuit signal delay on parallel operation. It has stronger versatility, higher reliability, and better parallel operation effect. The method of this invention is simple, easy to implement, low in cost, and easy to promote. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the traditional parallel operation method of inverters in existing technology.

[0038] Figure 2 This is a flowchart of the high-frequency synchronization method for wired parallel operation of inverters according to an embodiment of the present invention.

[0039] Figure 3 This is a schematic diagram of the inverter parallel operation mode in the inverter wired parallel high-frequency synchronization method of the present invention.

[0040] Figure 4 This is a schematic diagram illustrating the implementation principle of the wired parallel high-frequency synchronization method for inverters according to an embodiment of the present invention.

[0041] Figure 5 This is a partially enlarged view of the implementation principle diagram of the wired parallel high-frequency synchronization method for inverters according to an embodiment of the present invention. Detailed Implementation

[0042] This embodiment takes a multi-dimensional vocabulary expansion query method, system, and computer-readable storage medium for trademark registration risk assessment as an example. The invention will be described in detail below with reference to specific embodiments and accompanying drawings.

[0043] Please see Figure 2 This illustration shows a wired parallel high-frequency synchronization method for inverters provided by an embodiment of the present invention. The method is used to achieve power frequency synchronization and high-frequency carrier synchronization through a set of power frequency synchronization signals. The method includes the following steps:

[0044] Step 1, circuit configuration, such as Figure 3 As shown, after multiple inverters are connected in parallel in a master-slave mode, their output terminals are connected to the load device.

[0045] The specific steps include:

[0046] Step 1.1: Connect the output terminals of multiple inverters in parallel to the load device.

[0047] Step 1.2: Identify the master device and slave devices; one of them is the master device and the rest are slave devices. Set up communication cables between the master device and the slave devices.

[0048] The specific methods for determining the master and slave devices in the above steps can be system-specified, dynamically elected, or a combination of both.

[0049] Specifically, when using system-assigned configuration, the master and slave devices are pre-assigned based on factors such as hardware performance and device location during the system design phase. System-assigned configuration allows for the sorting of devices within the system, ensuring that if the master device fails, the next slave device in the sequence automatically takes over, thus guaranteeing stable system operation.

[0050] When dynamic election is used, the election criteria are first determined, and then the master device is dynamically determined through an election algorithm. When the master device fails, a new master device is elected from among the slave devices to ensure stable system operation.

[0051] Specifically, when determining the master and slave devices, system designation and dynamic election can be combined. First, the master device is designated by the system. When the master device fails or leaves the service, a new master device is elected from the remaining slave devices through dynamic election to ensure stable system operation.

[0052] Preferably, the host device and the slave device each include a master control unit. The master control unit adopts a master control chip configured with IO port capture function. The GPIO port of the master control chip of the slave device is configured in input mode and connected to the output port of the master control chip of the host device.

[0053] Specifically, I / O port capture is an important input processing mechanism for microcontrollers, primarily used for accurately measuring the timing parameters of external signals. The microcontroller's GPIO is configured as an input and bound to the timer's capture / compare channel. When a specified edge (rising / falling edge) is detected, the hardware automatically latches the current timer count value into a dedicated register (such as the CCR register), and may trigger an interrupt or DMA request.

[0054] The IO port capture function is used to achieve high-precision time measurement, event-driven response, etc., and is widely used in signal parameter measurement, industrial control and intelligent detection scenarios.

[0055] Specifically, the master control units of the host device and the slave device preferably use chips from the same series to ensure consistent operating performance of the master control units of the host device and the slave device, resulting in more stable performance under the same design and reducing performance differences caused by quality differences of different types of chips.

[0056] Specifically, the main control unit includes, but is not limited to, ST series and TI series chips. In this embodiment, the main control unit is preferably an STM32G4 series chip or a TIP65 series chip.

[0057] The STM32G4 series chips are high-performance mixed-signal microcontrollers with high-performance processing capabilities, capable of efficiently executing complex algorithms. They provide rich external interfaces, integrating multiple 12-bit ADCs (up to 4Msps sampling rate), DACs (15Msps), high-speed comparators (17ns response time), and programmable gain operational amplifiers. They support AES hardware encryption, secure storage areas, dual-storage flash memory (with ECC error correction code), and field firmware upgrade functionality. They provide multiple interfaces such as I2C, SPI, USART, FDCAN, and USB Type-C (with power delivery support).

[0058] The TIP65 series chips are high-performance products in real-time microcontrollers, designed for power electronics and industrial control applications. They employ an innovative multi-core architecture and include the following key components: dual C28x DSP CPUs, a CLA coprocessor, and an accelerator unit, providing superior processing capabilities suitable for real-time control applications.

[0059] Preferably, the master control unit of the host device and the slave device each include a modulation wave counter and a high-frequency carrier signal counter. The modulation wave counter is used to count the modulation wave signal, and the high-frequency carrier signal counter is used to count the high-frequency carrier signal. On the rising edge of the power frequency synchronization signal, the modulation wave counter and the high-frequency carrier signal counter are reset and start counting again from 0.

[0060] Step 1.3: The master control unit of the host device and the master control unit of the slave device establish a communication connection through CAN communication to realize the synchronization of the status information of the inverter parallel system.

[0061] Specifically, the master-slave mode is a distributed system architecture. In this mode, the master device is responsible for actively searching for and connecting to slave devices. It is the initiator and controller of communication with slave devices, manages access to the communication line, and initiates data transmission. Slave devices respond to the master device, waiting for connection requests and sending / receiving data, as well as receiving and executing commands from the master device.

[0062] In this embodiment, two inverters are connected in parallel, with one inverter acting as the master device and the other as the slave device. The master-slave operation mode enables both power frequency and high-frequency synchronization between the two inverters. The master device is responsible for the start-stop logic and power distribution strategy of the entire parallel system, and monitors the overall operating status of the parallel system.

[0063] In another embodiment, multiple inverters are connected in parallel, with one inverter acting as the master device and the rest acting as slave devices, to achieve power frequency synchronization and high frequency synchronization of the multiple inverters in a master-slave working mode.

[0064] Specifically, the CAN communication between master control units includes control information, status information, and basic information (voltage, current, power) sent by the master device. The slave device also transmits its own status information and basic information to the master device through CAN communication. The master device performs power distribution based on the information returned by the slave device and manages the entire parallel system.

[0065] Step 1.4: The high-frequency carrier signal counters in the host device and slave device begin counting.

[0066] Specifically, the high-frequency carrier signal counter in the host device is a first high-frequency carrier signal counter, which is used to count the high-frequency carrier signals of the host device; the high-frequency carrier signal counter in the slave device is a second high-frequency carrier signal counter, which is used to count the high-frequency carrier signals of the slave device.

[0067] When the rising edge of the power frequency synchronization signal arrives, the slave device reads the count value in the second high-frequency carrier signal counter, compares the count value of the second high-frequency carrier signal counter with the count value of the first high-frequency carrier signal counter, and adjusts the frequency of the high-frequency carrier signal of the slave device according to the comparison result.

[0068] Step 2: The host device sends a power frequency synchronization signal to each slave device, and each slave device detects the received power frequency synchronization signal.

[0069] The specific steps include:

[0070] Step 2.1: The high-frequency carrier signal counters in the host device and the slave device count the high-frequency carrier signals.

[0071] Step 2.2: The main control unit of the host device flips and generates the power frequency synchronization signal of the host device based on the zero-crossing point of the inverter AC signal and the time point when the carrier signal count value is zero.

[0072] Specifically, the power frequency synchronization signal includes information such as the frequency, phase, and voltage value of the output voltage signal of the host device. Since the power frequency synchronization signal flips at the zero-crossing point of the inverter AC signal and the time point when the carrier signal count is zero, the period of the power frequency synchronization signal is the same as the period of the output voltage signal of the host device, and it also contains the frequency information of the high-frequency carrier signal.

[0073] Specifically, in this embodiment, the frequency of the modulating wave is 50Hz, and the carrier frequency is 19.2kHz. A carrier signal with a fixed frequency is present within the modulation wave period. One period of the modulation wave is divided into 400 equally spaced counting points, with each counting point spaced 20ms apart. Figure 4 The host adjusts the wave count value to 0~399.

[0074] The carrier wave within a modulation wave cycle is divided into a predetermined number of carrier counting points, such as 3000 counting points in this embodiment. In the main control device, the host carrier count value is 0~2999.

[0075] Step 2.3: The host device sends the generated power frequency synchronization signal to the master control unit of the slave device.

[0076] Step 2.4: The main control unit of the host device receives and detects the power frequency synchronization signal.

[0077] Step 2.5: The slave device captures the rising edge of the power frequency synchronization signal and generates an interrupt signal.

[0078] Step 2.6: The interrupt signal locks onto and follows the power frequency synchronization signal. The slave device adjusts the voltage amplitude, frequency, and phase of its output voltage signal according to the period of the interrupt signal, so that it is completely consistent with the voltage amplitude, frequency, and phase of the master device.

[0079] Step 3, as Figure 4 and Figure 5 As shown, the phase difference of the high-frequency carrier signal between the slave device and the master device is calculated.

[0080] The specific steps include:

[0081] Step 3.1: The slave device obtains the count value of the second high-frequency carrier signal counter before it is reset.

[0082] Step 3.2: Compare the count value of the second high-frequency carrier signal counter of the slave device with the count value of the first high-frequency carrier signal counter of the master device.

[0083] Step 3.3: Determine the phase difference between the high-frequency carrier signal of the slave device and the high-frequency carrier signal of the master device based on the difference between the count value of the second high-frequency carrier signal counter of the slave device and the count value of the first high-frequency carrier signal counter of the master device.

[0084] Specifically, since the modulation wave frequency and carrier frequency of the host device are both fixed, the count value of the first high-frequency carrier signal counter is also fixed within one cycle of the modulation wave. The slave device synchronizes its modulation wave with that of the host device through a power frequency synchronization signal. The second high-frequency carrier signal counter of the slave device counts within one cycle of the modulation wave. By comparing the count value in the second high-frequency carrier signal counter with the count value in the first high-frequency carrier signal counter, the difference between the frequency of the carrier signal of the slave device and the frequency of the carrier signal of the host device can be determined. Furthermore, by adjusting the frequency of the carrier signal of the slave device, the count value of the second high-frequency carrier signal counter is made equal to the count value of the first high-frequency carrier signal counter, thereby achieving synchronous adjustment of the carrier signal of the slave device with that of the host device.

[0085] Step four: Each of the slave devices adjusts its own high-frequency carrier frequency according to the phase difference.

[0086] The specific steps include:

[0087] Step 4.1: If the count value of the second high-frequency carrier signal counter of the slave device before reset is greater than the count value of the first high-frequency carrier signal counter of the master device before reset, and the high-frequency carrier signal of the slave device leads the high-frequency carrier signal of the master device, then the slave device reduces the frequency of the high-frequency carrier signal.

[0088] Step 4.2: If the count value of the second high-frequency carrier signal counter of the slave device before reset is less than the count value of the first high-frequency carrier signal counter of the master device before reset, and the high-frequency carrier signal of the slave device lags behind the high-frequency carrier signal of the master device, then the slave device increases the frequency of the high-frequency carrier signal.

[0089] Step 4.3: If the count value of the second high-frequency carrier signal counter of the slave device before reset is equal to the count value of the first high-frequency carrier signal counter of the master device before reset, then the slave device maintains the frequency of the high-frequency carrier signal unchanged.

[0090] Specifically, in this technical solution, a common IO port of the main control unit chip is used to realize the synchronization of the power frequency signal and the high-frequency carrier signal between the inverter master and slave; the master control unit of the slave device is configured with IO port capture function to detect the power frequency synchronization signal of the master device and obtain the power frequency information of the master device.

[0091] When the master device transmits its power frequency synchronization signal to the slave device, an interrupt is triggered to obtain the carrier count value of the slave device at this moment. The phase difference between the slave carrier and the master carrier is calculated, and the slave device achieves synchronization of the master and slave carrier signals by adjusting the carrier frequency.

[0092] One of the general-purpose I / O ports in the master control unit of the host device is used as a synchronization signal. The host device transmits synchronization information to the slave device through this I / O port.

[0093] The slave device detects the master synchronization signal. The slave device receives the master synchronization signal. The master control unit of the slave device needs to be configured with the capture function of the IO port to capture the periodic changes of the synchronization signal and obtain the master power frequency period. Each time the synchronization signal crosses zero, it needs to enter an interrupt to obtain the slave carrier signal count value and calculate the phase difference between the slave carrier signal and the master carrier signal at this moment. This phase difference is used as an important basis for adjusting the slave carrier period and realizing parallel synchronization.

[0094] When inverters are connected in parallel, the number of inverters can be two or more.

[0095] The parallel system achieves both power frequency synchronization and high-frequency carrier synchronization through a set of power frequency synchronization signals. The slave device obtains the periodic information of the power frequency synchronization signal and the comparison value of the high-frequency carrier signal through the capture function of the master control unit, obtains the phase difference between the high-frequency carrier signals of the master and slave devices, and adjusts the slave carrier frequency according to the phase difference to reduce the phase difference between the high-frequency carrier signals of the master and slave devices, thus achieving high-frequency synchronization between the master and slave devices. Compared with the traditional wired parallel system of inverters, this solution saves a set of high-frequency synchronization signal circuits. The master control unit can obtain the phase difference between the master and slave carriers by capturing the power frequency synchronization signal, and adjust the slave carrier frequency according to the phase difference to achieve parallel synchronization between the master and slave devices.

[0096] In a master-slave parallel operation, the master device sends a power frequency synchronization signal based on its own zero-crossing and the carrier signal count value being zero. The master's power frequency period is fixed, and the hardware circuit delay of the synchronization signal is consistent. This invention detects the power frequency synchronization signal through the slave device. When the slave device receives the master's synchronization signal, it triggers an interrupt to obtain the count value of the slave's carrier signal. By calculation, the phase difference between the slave's carrier signal and the master's carrier signal can be obtained. The slave adjusts the carrier frequency according to the phase difference to achieve synchronization of the master and slave carrier signals and reduce parallel circulating current.

[0097] When inverters are configured in parallel, the main unit flips its power frequency synchronization signal (e.g., when the inverter AC signal crosses zero and the carrier signal count reaches zero) at each zero-crossing point. Figure 4 The master unit's power frequency synchronization signal; the slave unit's synchronization signal input I / O port needs to be configured to enable capture function and to trigger an interrupt when a rising edge is detected (e.g., ...). Figure 4 Interrupt trigger signal); the host's power frequency cycle value can be obtained by calculating the time difference of entering the interrupt.

[0098] When the slave device triggers an interrupt, it simultaneously retrieves the carrier control register count value (e.g., ...). Figure 5 (Slave carrier count value). This count allows us to determine the phase difference between the master and slave carrier signals, such as... Figure 5 As shown, the master carrier count is zero, while the slave carrier count is 3000. This indicates that the slave carrier signal is ahead of the master. In this case, the slave should increase the carrier frequency and decrease the carrier period. After several power frequency cycles of adjustment, the phase difference between the master and slave can be reduced until the carrier count value approaches 0 when the slave device enters an interrupt. At this point, the master and slave phases are synchronized. If the slave carrier signal lags behind the master, the slave should decrease the carrier frequency and increase the carrier period. After adjustment, the master and slave can achieve parallel synchronization.

[0099] In the above-mentioned wired parallel high-frequency synchronization method for inverters, the master device transmits the power frequency synchronization signal through the ordinary I / O port of the master control unit. The master control unit of the slave device acquires the power frequency synchronization signal information sent by the master device through the I / O port with capture function, and obtains the power frequency frequency of the master device. When the power frequency synchronization signal of the master device is transmitted to the slave device, an interrupt is triggered and the carrier count value of the slave device at this moment is acquired. The phase difference between the high-frequency carrier of the slave device and the high-frequency carrier of the master device is calculated. The slave device achieves synchronization of the master and slave carrier signals by adjusting the carrier frequency, reducing parallel circulating current. The technical solution of this invention achieves parallel synchronization through the ordinary I / O port of a master control unit. Compared with the traditional solution, it reduces the number of I / O ports used, simplifies the circuit structure, and lowers the requirements of circuit components. At the same time, the master control unit accurately captures the synchronization signal through its capture function, obtains synchronization information, and adjusts the slave carrier frequency through software algorithms to achieve parallel operation, greatly reducing the impact of hardware circuit signal delay on parallel operation. It has stronger versatility, higher reliability, and better parallel operation effect. The method of this invention is simple, easy to implement, low in cost, and easy to promote.

[0100] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for high frequency synchronization of inverters by wired connection, for realizing power frequency synchronization and high frequency carrier wave synchronization by a group of power frequency synchronization signals, characterized in that, The method includes the following steps: Step 1, Circuit Configuration: After multiple inverters are connected in parallel in master-slave mode, their output terminals are connected to the load device. Step 2: The host device sends a power frequency synchronization signal to each slave device, and each slave device detects the received power frequency synchronization signal. Step 3: Calculate the phase difference of the high-frequency carrier signal between the slave device and the master device; Step four: Each of the slave devices adjusts its own high-frequency carrier frequency according to the phase difference; The specific steps of circuit configuration in step one include: Step 1.1: Connect the output terminals of multiple inverters in parallel to the load device; Step 1.2: Identify the master device and slave devices; one of them is the master device, and the rest are slave devices. Set up communication cables between the master device and the slave devices. Step 1.3: The master control unit of the host device and the master control unit of the slave device establish a communication connection through CAN communication to realize the synchronization of the status information of the inverter parallel system; Step 1.4: The high-frequency carrier signal counters in the master and slave devices begin counting; The master control unit of the host device and the slave device each include a modulation wave counter and a high-frequency carrier signal counter. The modulation wave counter is used to count the modulation wave signal, and the high-frequency carrier signal counter is used to count the high-frequency carrier signal. At the rising edge of the power frequency synchronization signal, the modulation wave counter and the high-frequency carrier signal counter are reset and start counting again from 0. The high-frequency carrier signal counter in the host device is a first high-frequency carrier signal counter, which is used to count the high-frequency carrier signals of the host device; the high-frequency carrier signal counter in the slave device is a second high-frequency carrier signal counter, which is used to count the high-frequency carrier signals of the slave device. When the rising edge of the power frequency synchronization signal arrives, the slave device reads the count value in the second high-frequency carrier signal counter, compares the count value of the second high-frequency carrier signal counter with the count value of the first high-frequency carrier signal counter, and adjusts the frequency of the high-frequency carrier signal of the slave device according to the comparison result; Step three, calculating the phase difference of the high-frequency carrier signal between the slave device and the master device, includes the following specific steps: Step 3.1: The slave device acquires the count value of the second high-frequency carrier signal counter before it is reset; Step 3.2: Compare the count value of the second high-frequency carrier signal counter of the slave device with the count value of the first high-frequency carrier signal counter of the master device; Step 3.3: Determine the phase difference between the high-frequency carrier signal of the slave device and the high-frequency carrier signal of the master device based on the difference between the count value of the second high-frequency carrier signal counter of the slave device and the count value of the first high-frequency carrier signal counter of the master device.

2. The inverter wired machine high frequency synchronization method according to claim 1, wherein, The specific method for determining the master device and slave device in step 1.2 is either system-specified or dynamically elected.

3. The inverter wired machine high frequency synchronization method of claim 1, wherein, The host device and the slave device each include a master control unit. The master control unit adopts a master control chip configured with IO port capture function. The GPIO port of the master control chip of the slave device is configured as input mode and connected to the output port of the master control chip of the host device.

4. The inverter wired machine high frequency synchronization method of claim 1, wherein, In step two, the host device sends a power frequency synchronization signal to each slave device, and the specific steps for each slave device to detect the received power frequency synchronization signal include: Step 2.1: The high-frequency carrier signal counters in the host device and the slave device count the high-frequency carrier signals; Step 2.2: The main control unit of the host device flips and generates the power frequency synchronization signal of the host device based on the time point when the inverter AC signal crosses zero and the carrier signal count value is zero. Step 2.3: The host device sends the generated power frequency synchronization signal to the master control unit of the slave device; Step 2.4: The main control unit of the host device receives and detects the power frequency synchronization signal; Step 2.5: The slave device captures the rising edge of the power frequency synchronization signal and generates an interrupt signal; Step 2.6: The interrupt signal locks onto and follows the power frequency synchronization signal. The slave device adjusts the voltage amplitude, frequency, and phase of its output voltage signal according to the period of the interrupt signal, so that it is completely consistent with the voltage amplitude, frequency, and phase of the master device.

5. The method of claim 1, wherein the inverter wirelessly synchronizes with the high frequency power source by transmitting a synchronization signal to the high frequency power source. Step four, in which each slave device adjusts its own high-frequency carrier frequency according to the phase difference, includes the following specific steps: Step 4.1: If the count value of the second high-frequency carrier signal counter of the slave device before reset is greater than the count value of the first high-frequency carrier signal counter of the master device before reset, and the high-frequency carrier signal of the slave device is ahead of the high-frequency carrier signal of the master device, then the slave device reduces the frequency of the high-frequency carrier signal. Step 4.2: If the count value of the second high-frequency carrier signal counter of the slave device before reset is less than the count value of the first high-frequency carrier signal counter of the master device before reset, and the high-frequency carrier signal of the slave device lags behind the high-frequency carrier signal of the master device, then the slave device increases the frequency of the high-frequency carrier signal. Step 4.3: If the count value of the second high-frequency carrier signal counter of the slave device before reset is equal to the count value of the first high-frequency carrier signal counter of the master device before reset, then the slave device maintains the frequency of the high-frequency carrier signal unchanged.

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