Low power consumption super-high speed 8-bit analog-digital conversion system and device

Abstract

The application provides a low-power-consumption super-high-speed 8-bit analog-digital conversion system and device, which comprises a timing control module, an input driving module, a flash analog-digital conversion module and a digital data processing module. The flash analog-digital conversion module has a plurality of flash analog-digital conversion channels. The digital data processing module discretizes and converts analog signals obtained through sampling of the plurality of flash analog-digital conversion channels into digital signals, and reduces gain error and offset error by using circuit elements, and reduces clock phase error by optimizing a clock distribution network. The timing control module selects the plurality of flash conversion channels, obtains conversion results, and combines the obtained conversion results to form high-speed channel output. The input driving module suppresses common-mode noise interference in the plurality of flash analog-digital conversion channels through a differential input mode.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of communication, and particularly relates to a low-power-consumption super-high-speed 8-bit analog-to-digital conversion system and equipment. BACKGROUND

[0002] There are great challenges in realizing a low-power-consumption super-high-speed 8-bit analog-to-digital conversion system by using existing analog-to-digital conversion technologies. Currently, the following ADCs (Analog-to-Digital Converter) are commonly used: SAR ADC (also known as successive approximation ADC), Flash ADC, Pipeline ADC, and time-interleaved SAR ADC.

[0003] Compared with Flash ADC and Pipeline ADC, the conversion speed of SAR ADC is slower, and in low resolution, noise may have a greater impact on the conversion result. Large power consumption: the parallel operation of a large number of comparators significantly increases power consumption.

[0004] However, Flash ADC has large power consumption and high cost, and as the resolution increases, the number of comparators required increases exponentially, which increases the manufacturing cost.

[0005] Pipeline ADC is relatively complex in design and implementation, and due to multi-stage sampling and quantization error noise transmission, the final output digital signal may be subject to strong noise interference, so further processing of the interference is required to achieve a higher signal-to-noise ratio.

[0006] By using the low-power-consumption feature of SAR ADC, SAR ADC is used as a sub-ADC, which has the following problems:

[0007] 1) In the case of a 96Gsps super-high sampling rate, the time interleaving of SAR ADC is difficult, and at least 128 SAR ADCs need to be time interleaved, which brings high design difficulty and also brings large area and high power consumption;

[0008] 2) Due to the low conversion rate of SAR ADC, more ADC channel numbers are required, at least 128 SAR ADCs are required, which will bring greater area and power consumption;

[0009] 3) The working frequency of the DAC inside the SAR ADC is at least 8 times the sampling rate, which will increase the design difficulty of the input signal driving circuit and the reference voltage;

[0010] 4) SAR ADC internal DAC requires matching so that its total capacitance is actually greater than KT / C (the process of integrating the resistance noise in the RC network to power), further increasing the requirements for the input signal driving circuit and the reference voltage, increasing the design difficulty.

[0011] Based on the above analysis, there are some design difficulty problems in using SAR ADC as time-interleaved ADC, which also brings large area, and cannot meet the requirements of ultra-high conversion rate and low power consumption. SUMMARY

[0012] Therefore, the application provides a low-power ultra-high-speed 8-bit analog-digital conversion system, which comprises a timing control module, an input driving module, a flash analog-digital conversion module and a digital data processing module, characterized in that the flash analog-digital conversion module has a plurality of flash analog-digital conversion channels; the digital data processing module discretizes and converts analog signals obtained by sampling through the plurality of flash analog-digital conversion channels into digital signals, and reduces the gain error and offset error of each of the plurality of flash analog-digital conversion channels by using circuit elements, and reduces the clock phase error of each of the plurality of flash analog-digital conversion channels by optimizing the clock distribution network; the timing control module selects the plurality of flash conversion channels in the flash analog-digital conversion module in turn according to a first timing rule and a preset time interval, obtains the conversion results of the selected flash conversion channels, and combines the obtained conversion results according to a second timing rule to form a high-speed channel output; and the input driving module suppresses common-mode noise interference in the plurality of flash analog-digital conversion channels by a differential input mode.

[0013] In addition, preferably, in the low-power ultra-high-speed 8-bit analog-digital conversion system of the application, the low-power ultra-high-speed 8-bit analog-digital conversion system further comprises a reference voltage output module, one reference voltage is shared by every n flash analog-digital conversion channels, and one input driving module is shared by the n flash analog-digital conversion channels, wherein n is a positive integer greater than or equal to 4.

[0014] In addition, preferably, in the low-power ultra-high-speed 8-bit analog-digital conversion system of the application, the timing control module further comprises a clock duty cycle detection circuit and a clock duty cycle correction circuit, and the clock duty cycle correction circuit adjusts the delay of the falling edge by controlling the discharge current to realize duty cycle correction.

[0015] In addition, preferably, in the low-power ultra-high-speed 8-bit analog-digital conversion system of the application, the plurality of input driving modules adopt a balanced signal processing mode to improve the dynamic range of analog signals.

[0016] Further, preferably, in the low-power super-high-speed 8-bit analog-digital conversion system of the present application, the flash analog-digital conversion module is composed of 32 time interlaced modules, each flash analog-digital conversion channel has a sampling rate of 3Gsps, and a sampling differential clock input of 12GHz clkp / clkn differential clock; the timing control module generates IQ clock, obtains 32 phase 12GHz clock, and then obtains 3GHz clock through frequency division and sends to each flash analog-digital conversion channel.

[0017] Further, preferably, in the low-power super-high-speed 8-bit analog-digital conversion system of the present application, the low-power super-high-speed 8-bit analog-digital conversion system further comprises a flash analog-digital converter for error calibration, which is used for calibration of gain error, offset error and clock phase error.

[0018] Further, preferably, in the low-power super-high-speed 8-bit analog-digital conversion system of the present application, the flash analog-digital converter for error calibration uses digital calibration algorithm to adjust sampling points of each flash conversion channel through interpolation and reconstruction technology, and realizes calibration of gain error, offset error and clock phase error.

[0019] Further, preferably, in the low-power super-high-speed 8-bit analog-digital conversion system of the present application, the flash analog-digital converter for error calibration uses digital calibration algorithm to adjust sampling points of each flash conversion channel through interpolation and reconstruction technology, and realizes calibration of gain error, offset error and clock phase error.

[0020] Further, the present application also provides a low-power super-high-speed 8-bit analog-digital conversion device, which is installed with any of the low-power super-high-speed 8-bit analog-digital conversion systems mentioned above.

[0021] The present application realizes low-power super-high-speed 8-bit analog-digital conversion, and improves conversion speed while ensuring conversion quality. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a schematic block diagram showing the architecture of a SAR ADC according to an embodiment of the present application.

[0023] Figure 2 is a schematic block diagram showing the architecture of a Flash ADC according to an embodiment of the present application.

[0024] Figure 3 is a schematic block diagram showing the architecture of a Pipeline ADC according to an embodiment of the present application.

[0025] Figure 4 is a schematic block diagram showing the architecture of a low-power super-high-speed 8-bit analog-digital conversion system according to an embodiment of the present application.

[0026] Figure 5 This is a schematic block diagram illustrating the architecture of an ADC system-on-a-chip for a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0028] The following sections will explain the commonly used types of ADCs and their advantages and disadvantages.

[0029] The first type is the successive approximation (SAR) ADC:

[0030] Figure 1 This is a schematic block diagram illustrating the architecture of a SAR ADC according to one embodiment of the present invention.

[0031] Working principle: SAR ADCs use a successive approximation algorithm to achieve analog-to-digital conversion. It first sets an intermediate reference voltage (usually half of the full-scale voltage), then compares the input signal with this reference voltage using a comparator. Based on the comparison result, the range of the reference voltage is adjusted, and the above process is repeated until the desired resolution is achieved. The final binary sequence is the digital representation of the input signal.

[0032] Advantages:

[0033] Low power consumption: The successive approximation algorithm reduces unnecessary comparison operations, thereby reducing power consumption.

[0034] Low cost: Due to its relatively simple structure, the manufacturing cost of SAR ADC is low.

[0035] Disadvantages:

[0036] Slower conversion speed: Compared to Flash ADCs and pipelined ADCs, SAR ADCs have a slower conversion speed.

[0037] Susceptible to noise interference: At low resolutions, noise may have a significant impact on the conversion results.

[0038] The second type is Flash ADC.

[0039] Working principle: A Flash ADC, also known as a fast analog-to-digital converter, is the speed king in the field of analog-to-digital conversion. It uses a series of high-precision comparators working in parallel to compare the input analog signal with a series of preset reference voltages. Each comparator outputs a binary bit representing the comparison result. These binary bits are then integrated by an encoder into the final digital output.

[0040] The N-bit Flash ADC consists of two powered 2 N -1 comparator, two power supplies 2 N The comparator consists of a matching resistor and a priority encoder. It compares the input analog signal with a reference voltage and outputs the comparison result, i.e., a binary code. The encoder encodes the comparator's output, outputting a digital signal; an 8-bit Flash ADC outputs an 8-bit digital signal.

[0041] Advantages:

[0042] High conversion speed: Thanks to the parallel processing mechanism, Flash ADC can achieve extremely high conversion rates, making it suitable for applications that require high-speed conversion.

[0043] High resolution: By increasing the number of comparators, Flash ADCs can achieve higher resolution and meet high precision requirements.

[0044] Disadvantages:

[0045] High power consumption: The parallel operation of a large number of comparators leads to a significant increase in power consumption.

[0046] High cost: As resolution increases, the number of comparators required grows exponentially, driving up manufacturing costs.

[0047] The third type is Pipeline ADC.

[0048] A pipelined ADC is a high-speed ADC that employs a multi-stage pipeline structure, dividing the entire ADC conversion process into multiple unit stages. Each unit stage is responsible for processing and sampling the output of the previous stage and outputting it to the next stage. Because each unit stage only needs to process a portion of the bits, the conversion speed can be significantly improved.

[0049] Advantages: High-precision, high-speed analog signal conversion.

[0050] Disadvantages: Pipeline ADCs are more complex to design and implement, and due to the propagation of multi-level sampling and quantization error noise, the final output digital signal may be subject to strong noise interference. Therefore, further processing of these interferences is required to achieve a higher signal-to-noise ratio.

[0051] The fourth type is time-interleaved SAR ADC.

[0052] Traditional time interleaving is implemented using SAR ADCs. Time-Interleaved ADC (TI-ADC) is a technique that increases the sampling rate by connecting multiple ADC channels in parallel. In this architecture, each ADC channel operates at the same rate, but their sampling times are staggered in the time domain, thus achieving a higher overall sampling rate. The overall sampling rate of a time-interleaved ADC system is a multiple of the sampling rate of a single ADC (the multiple equals the number of channels).

[0053] Taking advantage of the low power consumption of SAR ADCs and using them as sub-ADCs presents the following problems:

[0054] 1) Due to the high sampling rate of 96Gsps, the interleaving of SAR ADCs is very difficult, requiring time interleaving between at least 128 SAR ADCs, which leads to high design difficulty, large area and high power consumption.

[0055] 2) Due to the low conversion rate of SAR ADC, more ADC channels will be required, at least 128 SAR ADCs, which will result in a larger area and higher power consumption.

[0056] 3) The operating frequency of the DAC inside the SAR ADC is at least 8 times the sampling rate, which will increase the design difficulty of the input signal driving circuit and the reference voltage.

[0057] 4) The matching requirements of the internal DAC of the SAR ADC make its total capacitance actually greater than the requirement of KT / C (the process of integrating the resistive noise in the RC network to obtain the power), which further increases the requirements of the input signal driving circuit and the reference voltage, and increases the design difficulty.

[0058] Based on the above analysis, using SAR ADC as a time-interleaved ADC presents some design challenges, results in a large area, and fails to meet the requirements of ultra-high conversion rate and low power consumption.

[0059] Ultra-high-speed ADCs refer to sampling rates reaching tens of Gsps, capable of capturing and converting high-frequency analog signals in real time. Compared to conventional ADCs, their core difference lies in their breakthrough conversion speed and bandwidth support capabilities. These ADCs typically employ advanced architectures (such as pipeline ADCs or Flash ADC designs) and integrate high-speed clock management and low-noise circuitry to meet the demands of instantaneous signal processing in scenarios such as radar, communication base stations, and medical imaging.

[0060] Ultra-high-speed ADCs are driving technological innovation across various fields with their exceptional performance. When selecting an ADC that meets specific needs, it is essential to comprehensively evaluate key performance indicators such as sampling rate, resolution, and dynamic range, and optimize the system design in conjunction with the actual application scenario.

[0061] Bottleneck barriers:

[0062] 1) ADC bit depth + effective bits

[0063] The resolution is expressed in bits (e.g., 8 bits, 10 bits), reflecting the precision of the converted digital signal. High resolution reduces quantization errors and is suitable for applications requiring subtle signal differences.

[0064] 2) ADC with a high sampling rate of 10–96 Gsps

[0065] The number of analog signal samples an ADC can process per second is the core criterion distinguishing between "high-speed" and "ultra-high-speed" ADCs. Ultra-high-speed ADCs typically have sampling rates exceeding 1 GSPS, with some cutting-edge products even surpassing 10 GSPS. This invention supports a maximum of 96 GSPS.

[0066] 3) ADC analog bandwidth greater than 12GHz

[0067] This indicator reflects the upper limit of the signal frequency that the ADC can process. Ultra-high-speed ADC chips typically have analog bandwidths covering several GHz and require anti-aliasing filters to ensure lossless conversion of high-frequency signals. The ADC of this invention supports 12 GHz.

[0068] 4) Ultra-low ADC power consumption

[0069] High performance of ultra-high-speed ADCs is often accompanied by high power consumption. In the design, it is necessary to balance speed, accuracy and energy efficiency to meet the heat dissipation and battery life requirements of practical applications. This invention requires ultra-low power consumption.

[0070] 5) Small ADC area

[0071] A smaller footprint saves on overall system design costs, but the increased design complexity also leads to increased footprint overhead. Performance is sacrificed for footprint, in order to reduce footprint overhead while ensuring performance.

[0072] 6) ADCs are greatly affected by manufacturing processes.

[0073] Ultra-high-speed ADCs have extremely stringent requirements for manufacturing processes. In nanoscale manufacturing processes, even minute deviations in transistor size can directly affect signal conversion accuracy, while ultra-high-speed characteristics require circuits with extremely low parasitic effects, and high sampling rates require circuits with extremely low latency.

[0074] The design and manufacturing of ultra-high-speed ADCs involve too many factors. The technological barriers not only stem from breakthroughs in a single link, but also depend on the precise coordination of the entire chain.

[0075] Based on the above design challenges and the analysis of several ADCs, existing technologies are insufficient to meet the requirements of ultra-high-speed ADCs. This invention supports a sampling rate of up to 96 Gsps (SPS (samples per second)), 8-bit resolution, input bandwidth ≥12 GHz, ultra-low power consumption, and is based on the principle of Flash ADC, employing a time-interleaved ADC for implementation.

[0076] This invention utilizes the high conversion speed of Flash ADC to compensate for the shortcomings of SAR ADC.

[0077] In an ultra-low power, ultra-high speed 8-bit analog-to-digital converter system according to one embodiment of the present invention, since the Flash ADC requires many comparators, supporting 8-bit resolution requires 2 8 -1 comparator, while a large number of comparators would increase the overall area and power consumption; this invention uses time interpolation technology to reduce the required number of comparators from 2 8 -1 reduced to 2 6 -1, thus greatly reducing area and power consumption while ensuring its conversion performance.

[0078] In a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention, the number of interleavings is 32, which is 1 / 4 of the number of SAR ADCs; the Flash ADC using time interleaving can meet the characteristics of low power consumption and high conversion rate.

[0079] Time-interleaved ADC (TI-ADC) is a technique that increases the sampling rate by connecting multiple ADC channels in parallel. In a low-power, ultra-high-speed 8-bit ADC conversion system according to an embodiment of the present invention, each ADC channel operates at the same rate, but their sampling times are staggered in the time domain, thereby achieving a higher overall sampling rate. The overall sampling rate of a time-interleaved ADC system is a multiple of the sampling rate of a single ADC (the multiple equals the number of channels).

[0080] The basic principle of time-interleaved ADCs is explained below:

[0081] In a time-interleaved ADC, assuming there are N ADC channels, each channel samples at a sampling period T, but the sampling time difference between adjacent channels is T / N. Thus, the first channel samples at times t, t+NT, t+2NT..., the second channel samples at times t+T / N, t+NT+T / N, t+2NT+T / N..., and so on.

[0082] Figure 4 This is a block diagram of an 8-bit ultra-high-speed ADC architecture. In a low-power ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention, a time-interleaved Flash ADC is used to realize the ultra-high-speed ADC, achieving higher conversion speed while ensuring conversion quality; it mainly consists of the following modules: Timing Control, Input Driver, Flash ADC, VREF, REF ADC, Digital data processor, etc., which are described in detail below.

[0083] Timing control

[0084] The conversion results from multiple Flash ADC channels are interleaved using timing control, thereby merging multiple Flash ADC channels into a single high-speed channel. This method improves the overall conversion speed without increasing the conversion speed of individual ADCs.

[0085] Timing control is the core of a time-interleaved ADC. The timing control module is responsible for interleaving the sampling results from multiple Flash ADC channels to achieve high-speed conversion. During interleaving, the timing control module selects and acquires the conversion results of each Flash ADC channel sequentially at specific time intervals according to preset timing rules. Through proper timing control, a time-interleaved ADC can combine the sampling results from multiple ADC channels in a specific order to form a high-speed output channel.

[0086] Since the ADC consists of 32 time-interleaved channels, each Flash ADC has a sampling rate of 3Gsps. Considering the clock transmission problem, the sampling differential clock input is a 12GHz (clkp, clkn) clock. The timing control generates an IQ clock, resulting in a 12GHz clock with 32 phases. This 12GHz clock is then divided to obtain a 3GHz clock, which is sent to each Flash ADC.

[0087] A clock duty cycle collector circuit (DCC) typically includes a duty cycle detection circuit and a duty cycle correction circuit. The duty cycle detection circuit is usually implemented using an integrator and a comparator. An ideal clock signal duty cycle is 50%, and its DC component can be considered the average of the high and low levels. When the duty cycle is less than 50%, the DC component is less than the average value; conversely, the DC component is greater than the average value. Therefore, a comparator and an integrator can be used to implement the duty cycle detection function. The duty cycle correction circuit is the execution unit that modulates the duty cycle by fixing one edge and adjusting the delay of another edge. Duty cycle correction is achieved by controlling the discharge current to adjust the delay of the falling edge.

[0088] Input driver

[0089] The purpose of the input driver is to address the large parasitic load at node Ain caused by the numerous comparators connected to the analog input signal Ain within the Flash ADC. Such a large capacitive load typically limits the speed of the Flash ADC, thus requiring a powerful, high-power buffer to drive Ain.

[0090] In a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention, every four Flash ADCs share a common input driver.

[0091] Differential inputs are used to suppress common-mode noise and interference. Due to the use of balanced signal processing, this method improves the dynamic range by a factor of two, thereby enhancing overall performance.

[0092] Flash ADC

[0093] During the sampling process, the analog signal is discretized and converted into a digital signal. To ensure the accuracy of the sampling results, time-interleaved ADCs typically use multiple Flash ADC channels for parallel sampling. Each ADC channel then only needs to handle a lower conversion rate, thereby improving the accuracy and stability of the sampling.

[0094] To save area and reduce power consumption, this Flash ADC eliminates the need for comparators. In a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention, based on a time-domain 4x interpolation technique, the number of comparators in the 8-bit Flash ADC can be reduced from the traditional 2... 8 -1 reduced to 2 6-1 reduces the number of comparators by a total of 191. Unlike traditional interpolation techniques, this technique effectively achieves a 4x interpolation factor using a simple SR latch, without additional clock and calibration hardware overhead. Only 2 calibration steps are required during the interpolation stage. 6 -1 comparator offset voltage, thus saving area.

[0095] Explanation of 4x interpolation technique:

[0096] Using a 2x interpolation technique in the time domain can reduce the number of comparators in a Flash ADC by half. However, the hardware complexity, input capacitance, and clock distributed load capacitance remain high. Therefore, a 4x interpolation technique is used to reduce the number of comparators in the Flash ADC from 2... 8 -1 reduced to 2 6 -1 can reduce the number of comparators by more than 70% while still achieving a high sampling rate.

[0097] In a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to one embodiment of the present invention, every four Flash ADCs share a set of VREF (reference voltage).

[0098] REF-ADC

[0099] In a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to one embodiment of the present invention, a reference ADC is added for various calibrations of time interleaving errors.

[0100] Digital Data Processor

[0101] In a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention, by observing the output results of REF-ADC and Flash ADC, the offset, gain error, and clock offset of each Flash ADC can be obtained through an algorithm, and the timing control and Flash ADC errors can be corrected.

[0102] Digital data processing is the final step in a time-interleaved ADC. After sampling and interleaving are completed by the timing control module, the resulting high-speed output signal requires further digital processing. In a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention, this step includes filtering, correction, and encoding of the data to ensure a high-quality final output digital signal.

[0103] Meanwhile, in the low-power ultra-high-speed 8-bit analog-to-digital converter system according to one embodiment of the present invention, the data processing module can also perform noise reduction, compression and other processing on the adopted results according to the specific application requirements, so as to improve the performance and efficiency of the entire system.

[0104] In a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention, the 128-bit digital output ensures transmission bandwidth, reduces operating frequency, and reduces system power consumption.

[0105] Errors and calibration in digital data processing

[0106] Time-interleaved ADCs are the structure for achieving ultra-high-speed ADCs. Time-interleaved ADCs improve the speed and accuracy of ADCs by superimposing the number of channels. However, in reality, mismatch errors between channels can cause the performance of time-interleaved ADCs to drop sharply.

[0107] Based on the detailed design specifications above, there are some errors and their calibration mechanisms, which are explained in detail below:

[0108] 1) Gain error

[0109] Gain errors in each ADC channel can lead to inconsistent output amplitudes across different channels. This error primarily stems from a gain mismatch between the gain amplifiers of each channel and the ADC's gain.

[0110] Calibration method:

[0111] Gain error can be reduced by matching circuit components during the design process.

[0112] A digital calibration algorithm is used to calculate and adjust the gain of each channel based on a known input signal (such as a sine wave).

[0113] The calculation formula is: Gain error = (Set gain - Actual gain) / Set gain.

[0114] The input sinusoidal signal Ax(t) = Asin(@0t) is input to the ADC, where A is the amplitude of the input signal, @0 is the angular frequency, @0 = (P / L) × 2πfs, and @0 < π × fs / M), and L is the number of FFT points, L = 2. n， n and P are positive integers and are coprime with L;

[0115] Using channel 0 as the reference channel, that is, using the spectral amplitude value H0 of channel 0 as the benchmark, the gain error ΔG of each channel is calculated. m =G m / G0=H m / H0.

[0116] 2) Offset error

[0117] The offset error of each ADC channel causes a shift in the DC level of the output signal. This error mainly stems from the mismatch between the bias voltage of each channel and the offset of the ADC.

[0118] Calibration method:

[0119] Misalignment errors are reduced during the design phase by using matching circuit components.

[0120] A digital calibration algorithm is used to calculate and adjust the offset of each channel based on the known input signal.

[0121] For an 8-bit ADC, the ideal output should be 128 when the input voltage is zero. The offset error is the difference between the ADC's actual output and this ideal value.

[0122] Offset error is typically expressed in LSB (smallest unit of resolution) or as a percentage of full scale. The formulas are: ΔOffset Error (LSB) = Actual output value - Ideal output value, and ΔOffset Error (%FSR) = OffsetError (LSB) / LSB * 100.

[0123] 3) Clock phase error

[0124] Clock phase errors in each ADC channel can lead to inconsistencies in sampling times, resulting in deviations in time-domain sampling points. These errors primarily originate from asymmetry in the clock distribution network and clock signal jitter.

[0125] Calibration method:

[0126] Phase error is reduced by optimizing the clock distribution network during the design phase.

[0127] A digital calibration algorithm is used to adjust the sampling points of each channel through interpolation and reconstruction techniques.

[0128] After the gain error of all ADC channels has been corrected, re-acquire the ADC data. i The quantized output is then subjected to an L-point FFT transform to determine the phase value of each channel at point @. P ADC i The time error ΔT of each channel was calculated based on the baseline. i =( P ADC i - P ADC0-i@0Ts) / @0.

[0129] Figure 5This is a schematic block diagram illustrating the architecture of an ADC system-on-a-chip for a low-power, ultra-high-speed 8-bit analog-to-digital converter system according to an embodiment of the present invention.

[0130] As shown in the figure, in order to better design the ADC, a complete on-chip ADC system needs to be built, which requires the addition of some auxiliary design modules to complete the task. The main auxiliary design modules are as follows:

[0131] 1) PLL generates a high-frequency clock, with a maximum output of 12GHz, for use by the ADC and the entire system;

[0132] 2) PVT monitors the current process angle, temperature, and voltage;

[0133] 3) SerDes provides high-bandwidth, high-speed signal output for the ADC, with 16 high-speed serial port output interfaces, each with a maximum IO rate of 20Gbps.

[0134] 4) Slave SPI: It interfaces with external devices via the SPI interface, and the application layer configures the registers to support multiple modes and read the ADC system's operating status.

[0135] 5) Design for Testability (DFT)

[0136] This invention achieves low-power, ultra-high-speed 8-bit analog-to-digital conversion, improving conversion speed while ensuring conversion quality, and can be widely applied to the following technical fields.

[0137] High-speed data acquisition

[0138] High-speed data acquisition systems have extremely high sampling rates, making them particularly suitable for applications where instantaneous changes in measurement quantities occur. Examples include power transmission, explosions, shock waves, and rocket launches.

[0139] High-bandwidth communication systems

[0140] Communication Systems: In communication systems, high-speed ADCs are used to process rapidly changing signals, such as 5G radio frequency signals. They convert analog signals into digital signals for transmission and processing in digital communication networks.

[0141] Instrumentation: High-speed ADCs are used in oscilloscopes to capture rapidly changing electrical signals and convert them into digital signals for display and analysis. This helps engineers diagnose and troubleshoot circuit and system faults.

[0142] Precision Instruments and Testing Equipment: In precision instruments and testing equipment, high-speed ADCs are used for high-precision signal acquisition and processing. For example, in CT / MRI scanners, vital sign monitoring equipment, precision sensors, and automotive electronics, high-speed ADCs ensure high-precision data acquisition and processing.

[0143] Autonomous driving: In autonomous driving technology, high-speed ADCs are used to process data from LiDAR, cameras, and various sensors. This data needs to be processed and analyzed in real time to ensure vehicle safety and navigation accuracy.

[0144] Furthermore, according to one embodiment of the present invention, the AAD08S020G is a high-speed analog-to-digital converter chip manufactured using CMOS technology. It has a maximum sampling rate of 20GS / s and a resolution of 8 bits. The chip employs a multi-channel time-interleaved ADC (TI-ADC) architecture, integrating a total of 128 sub-ADCs, each using a low-power successive approximation (SAR) architecture. For output interfaces, the chip integrates 16 high-speed serial output interfaces, each with a maximum rate of 10Gbps. The chip scrambles the converted 8-bit digital signal by XORing it with PRBS11 code, and then outputs it through the high-speed serial interface. The chip supports both QFN76 and BGA225 packages. The chip power consumption is approximately 1.9W.

[0145] Furthermore, according to one embodiment of the present invention, the AAD08S040G is a high-speed analog-to-digital converter chip manufactured using CMOS technology. It has a maximum sampling rate of 40GS / s and a resolution of 8 bits. The chip employs a multi-channel time-interleaved ADC (TI-ADC) architecture, integrating a total of 128 sub-ADCs, each using a low-power successive approximation (SAR) architecture. For output interfaces, the chip integrates 16 high-speed serial output interfaces, each with a maximum rate of 20Gbps. The chip XORs the converted 8-bit digital signal with PRBS11 code, then outputs it through the high-speed serial interface. The chip power consumption is approximately 2.7W.

[0146] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0147] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0148] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0149] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A low-power, ultra-high-speed 8-bit analog-to-digital converter system, comprising: The timing control module, input drive module, flash analog-to-digital converter module, and digital data processing module are characterized in that: The flash analog-to-digital converter module has multiple flash analog-to-digital conversion channels; The digital data processing module discretizes and converts the analog signals sampled by the multiple flash analog-to-digital conversion channels into digital signals, and uses circuit elements to reduce the gain error and offset error of the multiple flash analog-to-digital conversion channels, and optimizes the clock distribution network to reduce the clock phase error of the multiple flash analog-to-digital conversion channels. The timing control module sequentially selects multiple flash conversion channels in the flash analog-to-digital converter according to the first timing rule and the preset time interval, obtains the conversion results of the selected flash conversion channels, and merges the obtained conversion results into a high-speed channel output according to the second timing rule. The input driver module suppresses common-mode noise interference in the multiple flash analog-to-digital conversion channels through differential input. The gain error and offset error of the multiple flash analog-to-digital converter channels are reduced by utilizing circuit elements, and the clock phase error of the multiple flash analog-to-digital converter channels is reduced by optimizing the clock distribution network, including: Using a digital calibration algorithm, the gain error of each channel is calculated and adjusted based on the input sine wave signal Ax(t) = Asin(@0t). The calculation formula is: Gain Error = (Set Gain - Actual Gain) / Set Gain, where A is the amplitude of the input signal, @0 is the angular frequency, @0 = (P / L) × 2πfs, and @0 < π × fs / M, and L is the number of FFT points, L = 2. n， n and P are positive integers and coprime to L. With channel 0 as the reference channel, that is, with the spectral amplitude value H0 of channel 0 as the benchmark, the gain error of each channel is calculated. Using a digital calibration algorithm, the offset error of each channel is calculated and adjusted based on the input signal. The offset error is usually expressed in the smallest resolution unit LSB or as a percentage relative to full scale. The calculation formula is: ΔOffset Error (LSB) = Actual output value - Ideal output value, and ΔOffset Error (%FSR) = Offset Error (LSB) / LSB * 100. A digital calibration algorithm is used to adjust the sampling points of each channel through interpolation and reconstruction techniques. After the gain error of all channels has been corrected, the quantization output ADC of each channel is reacquired. i Then, perform an L-point FFT transform on the output to obtain the phase value of each channel at @. P ADC i Calculate the time error ΔT for each channel. i =( P ADC i - P ADC0 -i@0Ts) / @0, where i is a positive integer. The low-power, ultra-high-speed 8-bit analog-to-digital converter system also includes a reference voltage output module. Each n flash analog-to-digital converter channel shares a reference voltage and a shared input driver module, where n is a positive integer greater than or equal to 4.

2. The low-power, ultra-high-speed 8-bit analog-to-digital converter system according to claim 1, characterized in that, The timing control module also includes a clock duty cycle detection circuit and a clock duty cycle correction circuit. The clock duty cycle correction circuit achieves duty cycle correction by controlling the discharge current to adjust the delay of the falling edge.

3. The low-power, ultra-high-speed 8-bit analog-to-digital converter system according to claim 1, characterized in that, The multiple input drive modules employ a balanced signal processing method to improve the dynamic range of analog signals.

4. The low-power, ultra-high-speed 8-bit analog-to-digital converter system according to claim 1, characterized in that, The flash analog-to-digital converter module consists of 32 time-interleaved channels, with each flash analog-to-digital converter channel having a sampling rate of 3Gsps and a sampling differential clock input of a 12GHz clkp / clkn clock. The timing control module generates an IQ clock, resulting in a 12GHz clock with 32 phases, which is then divided to obtain a 3GHz clock and sent to each flash analog-to-digital converter channel.

5. A low-power, ultra-high-speed 8-bit analog-to-digital converter, comprising the low-power, ultra-high-speed 8-bit analog-to-digital converter system as described in any one of claims 1 to 4.

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