Error injection and verification methods, apparatuses, and storage media

Abstract

The present application relates to the technical field of chip testing, and provides an error injection and verification method, device and storage medium, the method comprising: obtaining error injection configuration information of a data stream; determining protocol error injection configuration and control signal error injection configuration of data packets in the data stream based on the error injection configuration information; generating error injection data packets based on the protocol error injection configuration and generating error injection signals based on the control signal error injection configuration; and driving error injection on a wrong packet filtering circuit based on the error injection data packets and the error injection signals.The method, device and medium provided by the present application schedule data packets with error injection configuration information, ensure the coupling between errors of each data packet, generate error injection data packets and error injection signals based on protocol error injection configuration and control signal error injection configuration respectively, realize the separate control of the protocol layer and the signal layer, ensure the variety and flexibility of error injection, split error injection control and driving, reduce the difficulty of error injection, and improve the efficiency of error injection.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, and in particular to an error injection and verification method, device and storage medium. BACKGROUND

[0002] An error packet filtering circuit is a hardware circuit used to detect and discard error packets transmitted in a network. Error injection for the error packet filtering circuit is an important means to verify the error packet processing capability and robustness of the error packet filtering circuit.

[0003] Currently, to implement error injection, force / release statements are usually used to inject errors into a device under test at a certain time, or error packets are extended from normal packets in a driver based on a UVM (Universal Verification Methodology) platform. However, the above error injection methods usually have the problems of single, fixed, poor flexibility and low efficiency of error types, and cannot complete a large number of complex error injections. SUMMARY

[0004] The present application provides an error injection and verification method, device and storage medium to solve the defects of poor flexibility and low efficiency of error injection in related technologies.

[0005] The present application provides an error injection method, comprising:

[0006] obtaining error injection configuration information of a data stream;

[0007] determining protocol error injection configuration and control signal error injection configuration of a data packet in the data stream based on the error injection configuration information;

[0008] generating an error injection data packet based on the protocol error injection configuration, and generating an error injection signal based on the control signal error injection configuration;

[0009] driving error injection on an error packet filtering circuit based on the error injection data packet and the error injection signal.

[0010] According to the error injection method provided by the present application, the error injection configuration information comprises directional configuration information of a data stream and a data stream template.

[0011] The directional configuration information comprises at least one of a protocol type, a data packet length and an error type.

[0012] According to the error injection method provided by the present application, the determination of the protocol error injection configuration and the control signal error injection configuration for the data packet based on the error injection configuration information comprises:

[0013] Based on the data stream template, the protocol error injection configuration and the control signal error injection configuration of each data packet in the data stream are sequentially determined under the constraint of the directional configuration information.

[0014] According to the error injection method provided by the application, the error injection data packet is generated based on the protocol error injection configuration, and the error injection method comprises the following steps of:

[0015] Based on the protocol error injection configuration, a protocol error injection indication of a protocol error type is determined, and the protocol error injection indication indicates whether each protocol error type is injected or not.

[0016] Based on the protocol error injection indication, the error injection data packet is generated.

[0017] According to the error injection method provided by the application, the error injection signal is generated based on the control signal error injection configuration, and the error injection method comprises the following steps of:

[0018] Based on the control signal error injection configuration, a signal error injection indication of a signal error type is determined, and the signal error injection indication indicates whether each signal error type is injected or not.

[0019] Based on the signal error injection indication, the error injection signal is generated.

[0020] According to the error injection method provided by the application, the error injection method further comprises the following steps of:

[0021] After the driving error injection, if the error injection data packet is not the last data packet of the data stream, then based on the error injection configuration information, the protocol error injection configuration and the control signal error injection configuration of the next data packet in the data stream are determined.

[0022] The application further provides a verification method of a wrong packet filtering circuit, which comprises the following steps of:

[0023] Error injection configuration information of a data stream is acquired.

[0024] Based on the error injection configuration information, the protocol error injection configuration and the control signal error injection configuration of a data packet in the data stream are determined.

[0025] Error injection data packets are generated based on the protocol error injection configuration, and error injection signals are generated based on the control signal error injection configuration.

[0026] Based on the error injection data packets and the error injection signals, a wrong packet filtering circuit is driven for error injection.

[0027] Output data of the wrong packet filtering circuit is acquired, and the performance of the wrong packet filtering circuit is verified based on the output data.

[0028] The application further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the error injection method or the check method of the error packet filtering circuit according to any one of the above when executing the program.

[0029] The application further provides a non-transitory computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the error injection method or the check method of the error packet filtering circuit according to any one of the above.

[0030] The application further provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the error injection method or the check method of the error packet filtering circuit according to any one of the above.

[0031] The application provides the error injection method, the device and the storage medium, which schedule data packets according to error injection configuration information of a data stream, ensure the coupling between errors of data packets in the data stream, generate error injection data packets and error injection signals based on protocol error injection configuration and control signal error injection configuration, respectively, implement the error injection control at the protocol layer and the signal layer, make the error injection of complex combined errors more simple and convenient, and ensure the diversity and flexibility of error injection. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0033] Figure 1 is an integrated block diagram of the error packet filtering circuit in the related art.

[0034] Figure 2 is one of the flowcharts of the error injection method provided by the application.

[0035] Figure 3 is another of the flowcharts of the error injection method provided by the application.

[0036] Figure 4 is the flowchart of the check method of the error packet filtering circuit provided by the application.

[0037] Figure 5is a structural schematic diagram of an error injection device provided by the present application.

[0038] Figure 6 is a structural schematic diagram of a check device of an error packet filtering circuit provided by the present application.

[0039] Figure 7 is a structural schematic diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0041] An error packet filtering circuit is a hardware circuit for detecting and discarding error data packets transmitted in a network. Figure 1 is an integrated block diagram of an error packet filtering circuit in the related art, as shown in Figure 1 A media access control (MAC) layer can transmit a data stream to an error packet filtering circuit or a reliable connection link (rc_link) through a stream2mux1. The error packet filtering circuit can receive the data stream forwarded by the stream2mux1 through a peer-to-peer network layer protocol (p2p_ntl_pro), and perform error packet filtering on the data stream. The error packet filtering circuit can send the filtered data packets to a data retention and counting (keep2cnt) module to count the number of correct data packets, and send the correct data packets to the reliable connection link or a peer-to-peer protocol (p2p_pro) module.

[0042] Generally, the error packet filtering circuit can support three protocol modes, and error packet filtering of a total of 11 packet types in the three protocol modes. The partial interface definitions of the error packet filtering circuit are as follows:

[0043]

[0044] In the above interface definition, the signals start_i, last_i and err_i can all be used to mark errors.

[0045] In order to verify the error packet processing capability and robustness of the error packet filtering circuit, error injection can be performed on the error packet filtering circuit. Through error injection, pre-set error packets can be actively introduced during the operation of the error packet filtering circuit to observe the reaction and processing capability of the error packet filtering circuit to these error packets.

[0046] Commonly injectable error types can include the following:

[0047] Error packet: This type of error usually refers to an error in the data packet itself. For example, it can be ilength err, i.e. an error in the ilength field of the data packet; or it can be Input err, which specifically refers to an error packet indicated by the previous stage through a control signal, such as the error packet indicated by the signal err_i.

[0048] Illegal packet: This type of error usually refers to a data packet that does not conform to the pre-set configuration in terms of format or length. For example, it can be type err, which specifically refers to a packet length range that does not belong to the reasonable range of the type.

[0049] Short packet: This type of error refers to a packet length that is less than the configured value.

[0050] Long packet: This type of error refers to a packet length that is greater than the maximum length, such as a packet length greater than 1304B.

[0051] Header and tail mismatch: This type of error is related to the boundary definition of the data packet, such as the case where the header is more than the tail, and the case where the tail is more than the header. These two cases can be determined by the number of received signals start_i and last_i.

[0052] Based on the above error types, there are many types of injectable errors, some of which involve protocol layer specifications, such as ilength err, type err, short packet, long packet, etc., and some of which involve signal layer, such as Input err, header and tail mismatch. In actual applications, different types of errors may be coupled, for example, an Input err in the signal layer may be accompanied by a short packet in the protocol layer. Such combinations of different types of errors should be considered within the scope of error injection.

[0053] Currently, there are mainly two methods for error injection of error packet filtering circuits:

[0054] One is based on the Verilog language, and force / release statements are used to inject errors into data streams at a certain time. Specifically, the signal values of the data stream are directly modified through the force / release statements. This error injection method is performed at the signal level, and if data packet level errors are to be injected, the signal values of multiple signals need to be accurately modified at a specific time, which makes the error injection operation very difficult, the error types are difficult to expand, and the flexibility is poor. Moreover, for each error signal to be injected, a corresponding force / release statement needs to be written, and for a large number of complex error injection requirements, the workload is huge, resulting in low error injection efficiency.

[0055] Another is based on the UVM platform, and error packets are extended from normal packets in the driver. This means that for each error type, corresponding code needs to be written for the driver. If complex error combinations need to be injected, code for error combinations also needs to be written for the driver, resulting in a huge workload for code writing, low error injection efficiency, and limiting the possibility of flexible combination of various error types. In addition, this error injection method is limited to the data packet level and lacks error types at the signal level.

[0056] As can be seen from the above, the current error injection method for the error packet filtering circuit has the problems of single, fixed, poor flexibility, and low efficiency of error types, and cannot complete a large number of complex error injections. To solve the above problems, the embodiments of the present application provide an error injection method.

[0057] Figure 2 is one of the flowcharts of the error injection method provided by the present application. As shown in Figure 2 the method comprises:

[0058] Step 210, obtaining error injection configuration information of a data stream.

[0059] Here, the data stream is a data stream to be input into the error packet filtering circuit. The error injection configuration information is configuration information for error injection of the data stream. The error injection configuration information can plan error injection from the data stream level. The error injection configuration information can include configuration information of the data stream itself, such as the protocol type applied by the data stream, the packet length of each data packet in the data stream, and also includes error information for error injection of the data stream, such as the error type to be injected, the position of the injected error, and the number of injected errors, etc., which are not limited by the embodiments of the present application.

[0060] The error injection configuration information of the data stream can be specifically loading the error injection configuration information set by the user, or selecting from the various error injection configuration information set in advance by the user, or can be randomly generated based on a preset rule, which is not limited by the embodiments of the present application.

[0061] In step 220, based on the error injection configuration information, the protocol error injection configuration and the control signal error injection configuration of the data packet in the data stream are determined.

[0062] Specifically, after obtaining the error injection configuration information of the data stream, the data stream scheduling can be performed based on the error injection configuration information. Specifically, based on the error injection configuration information, the data packets in the data stream are scheduled one by one, and thus the protocol error injection configuration and the information of each data packet are sequentially determined according to the order of the data packet in the data stream.

[0063] That is, when scheduling the data packet in the data stream that needs to be scheduled at present, the configuration information of error injection for the data packet can be determined according to the configuration of the number, position, type, etc. of the injected error in the error injection configuration information. It can be understood that, according to the global error injection configuration information of the data stream, the data packets in the data stream are scheduled one by one, and thus the configuration information of error injection for each data packet can take into account the influence of the error states of different data packets in the data stream on each other, that is, the influence of the error state of one data packet in the data stream on the error state of the subsequent data packet can be fully considered, thereby ensuring the error coupling between the data packets in the data stream.

[0064] Further, the configuration information of error injection for one data packet can be divided into two categories, namely, the protocol error injection configuration and the control signal error injection configuration. Among them, the protocol error injection configuration is used to configure the error injection information of the data packet at the protocol layer, and the control signal error injection configuration is used to configure the error injection information of the data packet at the signal layer.

[0065] In step 230, the error injection data packet is generated based on the protocol error injection configuration, and the error injection signal is generated based on the control signal error injection configuration.

[0066] Specifically, for each data packet, the error injection data packet of the data packet can be generated based on the protocol error injection configuration of the data packet, and in addition, the error injection signal of the data packet can be generated based on the control signal error injection configuration of the data packet. It can be understood that, for each data packet, the generation of the error injection data packet and the error injection signal is parallel, and the generation of the error injection data packet and the error injection signal is independent of each other.

[0067] Further, based on the protocol error injection configuration, the generation of the data packet and the error injection of the protocol layer can be realized, for example, the protocol error injection configuration can be used to control the fields including the protocol type, the packet type, the packet length, the packet header, the packet tail, the payload, the channel type, the ilength, and the like, thereby generating the data packet with the error of the protocol layer indicated by the protocol error injection configuration, that is, obtaining the error injection data packet; in addition, based on the control signal error injection configuration, the generation of the control signal and the error injection can be realized, for example, the control signal error injection configuration can be used to control the generation and the error injection of the signals including the error signal err_i, the packet header indication signal start_i, the packet tail indication signal last_i, and the like, that is, obtaining the error injection signal.

[0068] In step 240, the error injection data packet and the error injection signal are used to drive the error packet filtering circuit.

[0069] Specifically, after obtaining the error injection data packet and the error injection signal of a data packet, the two can be driven to the input port of the error packet filtering circuit, thereby realizing the error injection of the error packet filtering circuit. Moreover, after completing the driving error injection of a data packet, it can be judged whether the transmission of the data stream is completed, if not, the next data packet in the data stream can be scheduled in step 220 until the transmission of the data stream is completed.

[0070] In the method provided in the embodiments of the present application, the error injection configuration information of the data stream is used to schedule the data packet, the coupling between the errors of the data packets in the data stream is ensured, the error injection data packet and the error injection signal are respectively generated based on the protocol error injection configuration and the control signal error injection configuration, the error injection is respectively controlled in the protocol layer and the signal layer, the injection of the complex combined error is more simple and convenient, the variety and flexibility of the error injection are ensured. In addition, for the error injection data packet and the error injection signal which have completed the error injection control, the error injection can be completed by driving into the error packet filtering circuit, the error injection control and the driving are split, the difficulty of the error injection is further reduced, and the error injection efficiency is improved.

[0071] Based on any of the above embodiments, the error injection configuration information includes the directional configuration information of the data stream and the data stream template.

[0072] The directional configuration information includes at least one of the protocol type, the data packet length, and the error type.

[0073] Specifically, the error injection configuration information of the data stream can include two parts, specifically, the directional configuration information of the data stream and the data stream template.

[0074] The directional configuration information of the data stream includes configuration information of the data stream itself, such as a protocol type applied by the data stream, a packet length of a data packet in the data stream, and configuration information for error injection of the data stream, such as an error type to be injected.

[0075] The data stream template is a configurable test sequence, and the data stream template is used to define a flow step of error injection in the data stream. Different data stream templates can exist for different test scenarios or error injection requirements. For example, a data stream template for continuously and without interval sending multiple error packets can exist, and a data stream template for sending error packets according to a specified period can exist. The embodiments of the present application do not make specific limitations in this regard. The directional configuration information can be used as a data source when the data stream template is executed. During the execution process of the data stream template, the corresponding error injection operation can be implemented by reading the configuration in the directional configuration information.

[0076] In the embodiments of the present application, by splitting the directional configuration information and the data stream template, the user only needs to fill in the directional configuration information and select the data stream template when performing error injection, so as to complete automatic complex error injection. Therefore, the human cost consumed by error injection is greatly reduced.

[0077] Based on any of the above embodiments, in step 220, the protocol error injection configuration and the control signal error injection configuration for the data packet are determined based on the error injection configuration information, including:

[0078] The protocol error injection configuration and the control signal error injection configuration of each data packet in the data stream are sequentially determined based on the data stream template and the constraint of the directional configuration information.

[0079] Specifically, after the data stream template and the directional configuration information of the data stream are determined, the data packets in the data stream can be scheduled one by one through the data stream template.

[0080] Suppose that a data packet currently being scheduled is recorded as a current scheduling data packet. When the current scheduling data packet is scheduled, the data stream template can refer to information of each data packet that has been scheduled before the current scheduling data packet according to a position of the current scheduling data packet in the data stream, and refer to configuration of the data packet and configuration of the error type in the directional configuration information, to decide the protocol error injection configuration and the control signal error injection configuration of the current scheduling data packet. Therefore, the data stream template can control the number of error injections, the position of error injection, the error type, and the like in the process of sequentially scheduling each data packet in the data stream, and ensure error coupling between data packets.

[0081] Based on any of the above embodiments, in step 230, the error injection data packet is generated based on the protocol error injection configuration, including:

[0082] Based on the protocol error injection configuration, a protocol error injection indication of protocol error types is determined, the protocol error injection indication indicating whether each protocol error type is injected or not;

[0083] Based on the protocol error injection indication, an error injection data packet is generated.

[0084] Specifically, the protocol error injection configuration can configure the data packet and error injection of the data packet from the protocol layer. In the protocol error injection configuration, information of fields of the data packet such as protocol type, packet type, packet length, packet header, packet tail, payload, channel type, ilength, etc. can be contained, and whether error injection is performed on these information can be contained.

[0085] After obtaining the protocol error injection configuration, the protocol error injection indication can be determined based on the protocol error injection configuration. Here, the protocol error injection indication covers all error types associated with the protocol layer, and the indication of whether each error type is injected is obtained from the protocol error injection configuration. That is, the protocol error injection indication can uniformly control and manage all error types that need to be injected.

[0086] Further, the protocol error injection indication can be implemented in Transaction, and error injection control parameters can be set in Transaction, each error injection control parameter being used to indicate whether an error type is injected.

[0087] Based on the obtained protocol error injection indication, a corresponding data packet, referred to as an error injection data packet, can be generated. It should be noted that the error injection data packet refers to a data packet generated based on the protocol error injection indication, and the protocol error types indicated to be injected in the protocol error injection indication can be injected in the error injection data packet. When the protocol error injection indication indicates that no protocol error type is injected, the error injection data packet can be a correct data packet.

[0088] Further, constraint is also set in Transaction, and constraint can define rules between the error injection control parameters for each protocol error type, so that combinations of various protocol error types are possible, and after obtaining the protocol error injection indication, error injection data packet generation can be combined with constraint. For example, when the error injection control parameter for ilength err in the protocol error injection indication is injection, constraint can be applied to randomly generate an error value not equal to the correct value as the field of the ilength field, and when the error injection control parameter for ilength err in the protocol error injection indication is not injection, constraint can be applied to directly generate a value equal to the correct value as the field of the ilength field.

[0089] In addition, the generation of the error injection data packet can be based on the protocol error injection configuration, so that the generated error injection data packet conforms to the configurations in the protocol error injection configuration, and for the part not configured in the protocol error injection configuration, random generation can be performed in the generation process.

[0090] Based on any of the above embodiments, in step 230, the error injection signal is generated based on the control signal error injection configuration, including:

[0091] Based on the control signal error injection configuration, a signal error type signal error injection indication is determined, and the signal error injection indication indicates whether each signal error type is injected or not;

[0092] Based on the signal error injection indication, an error injection signal is generated.

[0093] Specifically, the control signal error injection configuration can configure the control signal of the data packet from the signal layer and the error injection of the control signal. In the control signal error injection configuration, information can be included for whether to inject error signals err_i, packet header indication signals start_i, and packet tail indication signals last_i.

[0094] After obtaining the control signal error injection configuration, the signal error injection indication can be determined based on the control signal error injection configuration. Here, the signal error injection indication covers all error types associated with the signal layer, and the indication of whether each error type is injected is obtained from the control signal error injection configuration. That is, the signal error injection indication can uniformly control and manage all error types that need to be injected.

[0095] Further, the signal error injection indication can be implemented in Transaction, and error injection control parameters can be set in Transaction, each of which is used to indicate whether an error type is injected. In some embodiments, the protocol error injection indication and the signal error injection indication can be represented together, and specifically, error injection control parameters corresponding to all error types associated with the protocol layer and all error types associated with the signal layer can be set in Transaction.

[0096] Based on the obtained signal error injection indication, the corresponding control signal, denoted as an error injection signal, can be generated. It should be noted that the error injection signal refers to the control signal of the data packet generated based on the signal error injection indication, and the signal error types indicated to be injected in the signal error injection indication can be injected in the error injection signal, and when the signal error injection indication indicates that no signal error type is injected, the error injection signal can be a correct control signal.

[0097] Further, the constraint in the Transaction can also define rules between the error injection control parameters of various signal error types, so that combinations between various signal error types are possible, and after obtaining the signal error indication, the error injection signal can be generated in combination with the constraint. For example, when the error injection control parameter for Inputerr in the signal error indication is injection, the constraint can be applied to randomly generate the error value of signal err_i, which can be any one of 1, 2, and 3, where 1, 2, and 3 correspond to binary representations of 01, 10, and 11, respectively, all of which can represent that the error signal from the previous stage indicates a wrong packet; when the error injection control parameter for Inputerr in the signal error indication is no injection, the constraint can be applied to directly generate the value of signal err_i as 0, which indicates that the error signal from the previous stage indicates no wrong packet.

[0098] In addition, the generation of the error injection signal can be based on the control signal error injection configuration, so that the generated error injection signal conforms to each configuration in the control signal error injection configuration, and for the part not configured in the control signal error injection configuration, random generation can be performed in the generation process.

[0099] Based on any of the above embodiments, the method further comprises:

[0100] After the driving of the error injection data packet, if the error injection data packet is not the last data packet of the data stream, the protocol error injection configuration and the control signal error injection configuration of the next data packet in the data stream are determined based on the error injection configuration information.

[0101] Specifically, after the driving injection of the error injection data packet and the error injection signal for one data packet is completed, it can be determined whether the error injection is completed, which is specifically whether the error injection data packet completed driving injection is the last data packet in the data stream, that is, whether the data packet completed driving injection is the last data packet in the data stream.

[0102] For the case that the error injection data packet is the last data packet of the data stream, it can be determined that the data stream has been completely driven to the error packet filtering circuit, and the error injection for the error packet filtering circuit is completed this time.

[0103] For the case that the error injection data packet is not the last data packet of the data stream, it can be determined that the data stream has not been completely driven to the error packet filtering circuit, and the error injection process continues, returning to step 220, the next data packet is scheduled based on the error injection configuration information, the protocol error injection configuration and the control signal error injection configuration of the next data packet are obtained, so as to generate the error injection data packet and the error injection signal of the next data packet, thereby driving the next data packet to the error packet filtering circuit, and so on, until the data stream is completely driven to the error packet filtering circuit.

[0104] Therefore, in the error injection process, the data packets can be scheduled one by one based on the error injection configuration information, the next data packet is scheduled after the current data packet is driven to the error packet filtering circuit, and the error injection of the entire data stream is realized.

[0105] Based on any of the above embodiments, Figure 3 is a flowchart of the error injection method provided by the present application. As shown in the figure, the method comprises the following steps. Figure 3

[0106] First, the first-stage error injection control is performed.

[0107] Here, the first-stage error injection control is an error injection control at the data stream level.

[0108] Specifically, the error injection configuration information of the data stream can be acquired first. Here, the error injection configuration information can plan the configuration information of the error injection at the data stream level, and can include the directional configuration information of the data stream and the data stream template. Then, the scheduling can be performed based on the error injection configuration information. Here, the scheduling based on the error injection configuration information specifically realizes the scheduling of the data packets in the data stream one by one, and further determines the protocol error injection configuration and the control signal error injection configuration for each data packet.

[0109] Second, the second-stage error injection control is performed.

[0110] Here, the second-stage error injection control is an error injection control at the data packet level. Specifically, for the currently scheduled data packet, the protocol layer and the signal layer can be further divided for error injection.

[0111] For the error injection of the protocol layer, whether to inject an error at the protocol layer, i.e., whether to generate an error packet, can be determined based on the protocol error injection configuration of the data packet. If it is determined that there is a protocol error type to be injected in the protocol error injection configuration, a data packet containing the protocol error type is generated, i.e., an error packet is generated; if it is determined that there is no protocol error type to be injected in the protocol error injection configuration, a correct data packet is generated, i.e., a normal packet is generated. For ease of description, the generated data packet containing the protocol error type and the correct data packet are collectively referred to as error injection data packets.

[0112] In addition, for the error injection of the signal layer, whether to inject an error at the signal layer can be determined based on the control signal error injection configuration of the data packet. If it is determined that there is a signal error type to be injected in the control signal error injection configuration, a control signal containing the signal error type is generated, i.e., an error signal is generated; if it is determined that there is no signal error type to be injected in the control signal error injection configuration, a correct control signal is generated, i.e., a normal signal is generated. For ease of description, the generated control signal containing the signal error type and the correct control signal are collectively referred to as error injection signals. ​

[0113] Subsequently, the driving control is performed:

[0114] Here, the driving control is used to drive the error injection data packets and the error injection signals generated by the first and second level error injection control into the error packet filtering circuit in units of data packets. It can be understood that the driving control here is completely decoupled from the error injection.

[0115] Specifically, the error injection data packets can be driven into the error packet filtering circuit in the form of data signals, and the error injection signals can be driven into the error packet filtering circuit in the form of control signals.

[0116] After the driving control for a single data packet is completed, it is determined whether the error injection is ended, i.e., whether the data packet just subjected to the driving control is the last data packet in the data stream. If yes, the error injection process is ended; otherwise, the next data packet is scheduled to perform the error injection by returning to the first level error injection control.

[0117] In the method provided in the embodiment of the present application, the two-level error injection control of the data stream and the data packet is set, thereby ensuring the coupling between the errors of the data packets in the data stream, and the protocol layer error injection and the signal layer error injection are separated in the second level error injection control, so that the injection of complex combined errors is more simple and convenient, and the variety and flexibility of the error injection are ensured. Moreover, the error injection control and the driving control are separated, which further reduces the difficulty of the error injection and improves the error injection efficiency. Based on the method provided in the embodiment of the present application, a large number of multi-level, multi-type and complex errors, especially the error injection with coupling relationship, can be injected, thereby efficiently meeting the verification requirements of the error packet filtering circuit.

[0118] Figure 4 is a flowchart of a verification method of an error packet filtering circuit provided by the present application, as shown in 4, the method comprises:

[0119] In step 410, error injection configuration information of a data stream is acquired.

[0120] In step 420, based on the error injection configuration information, protocol error injection configuration and control signal error injection configuration of data packets in the data stream are determined.

[0121] In step 430, error injection data packets are generated based on the protocol error injection configuration, and error injection signals are generated based on the control signal error injection configuration.

[0122] In step 440, the error packet filtering circuit is driven and injected with errors based on the error injection data packets and the error injection signals.

[0123] In step 450, output data of the error packet filtering circuit is acquired, and the performance of the error packet filtering circuit is verified based on the output data.

[0124] Specifically, in the embodiments of the present application, steps 410-440 are the process of error injection for the error packet filtering circuit in the scenario of checking the error packet filtering circuit. The specific implementation of steps 410-440 is the same as the method of error injection in the above-mentioned embodiments, for example, steps 410-440 in the checking method of the error packet filtering circuit can be implemented based on the specific implementation of steps 210-240. Therefore, the specific implementation of steps 410-440 in the embodiments of the present application is not described in detail.

[0125] While error injection is performed on the error packet filtering circuit, the output data of the error packet filtering circuit can be monitored. It can be understood that the function of the error packet filtering circuit is to detect and discard error packets, so that the output data of the error packet filtering circuit should ideally only contain correct packets and no error packets.

[0126] Therefore, in the process of error injection for the error packet filtering circuit, it can be determined based on the error injection configuration information of the data stream whether the packet driven to the error packet filtering circuit at each time is a correct packet or an error packet, and the output of the corresponding time in the output data of the error packet filtering circuit is monitored accordingly. If a correct packet is driven to the error packet filtering circuit, but the error packet filtering circuit does not output a packet or the content of the output packet changes, or an error packet is driven to the error packet filtering circuit, but the error packet filtering circuit outputs a packet, it means that the checking of the error packet filtering circuit fails; if a correct packet is driven to the error packet filtering circuit and the output packet is unchanged during the entire driving process of the data stream, and an error packet is driven to the error packet filtering circuit and no packet is output, it is determined that the checking of the error packet filtering circuit is successful.

[0127] It can be understood that the performance checking of the error packet filtering circuit can be used to verify whether the error packet filtering circuit can normally operate under various complex and combined error scenarios, thereby obtaining the premise of applying the error packet filtering circuit in specific products.

[0128] In the method provided in the embodiments of the present application, the error coupling between the packets in the data stream is ensured by scheduling the packets based on the error injection configuration information of the data stream, the error injection packets and error injection signals are respectively generated based on the protocol error injection configuration and the control signal error injection configuration, the control of error injection at the protocol layer and the signal layer is realized, the injection of complex and combined errors is more simple and convenient, the variety and flexibility of error injection are ensured, and the integrity and reliability of the checking of the error packet filtering circuit are ensured.

[0129] The error injection device provided by the present application is described below, and the error injection device described below can be referred to in correspondence with the error injection method described above.

[0130] Figure 5 is a structural schematic diagram of the error injection device provided by the present application, as Figure 5 indicated, the device comprises:

[0131] A first configuration unit 510 is configured to obtain error injection configuration information of a data stream.

[0132] A first scheduling unit 520 is configured to determine protocol error injection configuration and control signal error injection configuration of data packets in the data stream based on the error injection configuration information.

[0133] A first error injection unit 530 is configured to generate error injection data packets based on the protocol error injection configuration, and generate error injection signals based on the control signal error injection configuration.

[0134] A first driving unit 540 is configured to drive error injection on a wrong packet filtering circuit based on the error injection data packets and the error injection signals.

[0135] In the device provided by the embodiment of the present application, the error injection configuration information of the data stream is used to schedule the data packets, so as to ensure the coupling between errors of the data packets in the data stream. The protocol error injection configuration and the control signal error injection configuration of the data packets are used to respectively generate error injection data packets and error injection signals, so as to realize the separate control of error injection at the protocol layer and the signal layer, make the injection of complex combined errors more simple and convenient, and ensure the variety and flexibility of error injection. In addition, for the error injection data packets and the error injection signals that have completed error injection control, error injection is completed by driving into the wrong packet filtering circuit, the error injection control and driving are split, the difficulty of error injection is further reduced, and the efficiency of error injection is improved.

[0136] Based on the above embodiment, the error injection configuration information comprises directional configuration information of the data stream and a data stream template.

[0137] The directional configuration information comprises at least one of a protocol type, a data packet length, and an error type.

[0138] Based on any one of the above embodiments, the first scheduling unit is specifically configured to:

[0139] The protocol error injection configuration and the control signal error injection configuration of the data packets in the data stream are sequentially determined under the constraint of the directional configuration information based on the data stream template.

[0140] Based on any one of the above embodiments, the first error injection unit is specifically configured to:

[0141] determine protocol fault injection indications of protocol fault types based on the protocol fault injection configuration, the protocol fault injection indications indicating whether each protocol fault type is injected or not;

[0142] generate the fault injection data packet based on the protocol fault injection indications.

[0143] In any of the above embodiments, the first fault injection unit is specifically configured to:

[0144] The generating of the fault injection signal based on the control signal fault injection configuration comprises:

[0145] determine signal fault injection indications of signal fault types based on the control signal fault injection configuration, the signal fault injection indications indicating whether each signal fault type is injected or not;

[0146] generate the fault injection signal based on the signal fault injection indications.

[0147] In any of the above embodiments, the first scheduling unit is further configured to:

[0148] After the driving of the fault injection, if the fault injection data packet is not the last data packet of the data stream, determine protocol fault injection configuration and control signal fault injection configuration of a next data packet in the data stream based on the control fault injection configuration information.

[0149] Figure 6 is a structure diagram of a verification device of a fault packet filtering circuit provided by the present application, as shown in Figure 6 The device comprises:

[0150] The second configuration unit 610 is configured to obtain fault injection configuration information of a data stream.

[0151] The second scheduling unit 620 is configured to determine protocol fault injection configuration and control signal fault injection configuration of a data packet in the data stream based on the fault injection configuration information.

[0152] The second fault injection unit 630 is configured to generate a fault injection data packet based on the protocol fault injection configuration, and generate a fault injection signal based on the control signal fault injection configuration.

[0153] The second driving unit 640 is configured to drive the fault packet filtering circuit based on the fault injection data packet and the fault injection signal.

[0154] The verification unit 650 is configured to obtain output data of the fault packet filtering circuit, and perform performance verification on the fault packet filtering circuit based on the output data.

[0155] In the device provided by the embodiment of the application, the coupling between errors of data packets in a data stream is ensured by scheduling the data packets according to error injection configuration information of the data stream, error injection data packets and error injection signals are respectively generated based on protocol error injection configuration and control signal error injection configuration, the control of error injection at the protocol layer and the signal layer is realized, the injection of complex combined errors is more simple and convenient, the diversity and flexibility of error injection are ensured, and the integrity and reliability of the verification of the error packet filtering circuit are ensured.

[0156] Figure 7 An example of a schematic diagram of a physical structure of an electronic device is shown in Figure 7 The electronic device can include a processor 710, a communications interface 720, a memory 730 and a communications bus 740, wherein the processor 710, the communications interface 720 and the memory 730 complete mutual communication through the communications bus 740. The processor 710 can invoke a logical instruction in the memory 730 to execute an error injection method, which includes:

[0157] obtaining error injection configuration information of a data stream;

[0158] determining protocol error injection configuration and control signal error injection configuration of data packets in the data stream based on the error injection configuration information;

[0159] generating error injection data packets based on the protocol error injection configuration, and generating error injection signals based on the control signal error injection configuration;

[0160] driving error injection of an error packet filtering circuit based on the error injection data packets and the error injection signals.

[0161] Alternatively, the processor 710 can invoke a logical instruction in the memory 730 to execute a verification method of an error packet filtering circuit, which includes:

[0162] obtaining error injection configuration information of a data stream;

[0163] determining protocol error injection configuration and control signal error injection configuration of data packets in the data stream based on the error injection configuration information;

[0164] generating error injection data packets based on the protocol error injection configuration, and generating error injection signals based on the control signal error injection configuration;

[0165] driving error injection of an error packet filtering circuit based on the error injection data packets and the error injection signals.

[0166] Obtaining output data of the error packet filtering circuit, and performing performance verification on the error packet filtering circuit based on the output data.

[0167] In addition, the logic instructions in the memory 730 described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that make contributions to the related art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0168] On the other hand, the present application also provides a computer program product, which comprises a computer program, the computer program can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the error injection method provided by the above-mentioned methods, the method comprising:

[0169] Obtaining error injection configuration information of a data stream;

[0170] Based on the error injection configuration information, determining protocol error injection configuration and control signal error injection configuration of data packets in the data stream;

[0171] Generating error injection data packets based on the protocol error injection configuration, and generating error injection signals based on the control signal error injection configuration;

[0172] Based on the error injection data packets and the error injection signals, driving error injection on an error packet filtering circuit.

[0173] Alternatively, the computer can execute the verification method of the error packet filtering circuit provided by the above-mentioned methods, and the method comprises:

[0174] Obtaining error injection configuration information of a data stream;

[0175] Based on the error injection configuration information, determining protocol error injection configuration and control signal error injection configuration of data packets in the data stream;

[0176] Generating error injection data packets based on the protocol error injection configuration, and generating error injection signals based on the control signal error injection configuration;

[0177] Drive the error injection based on the error injection data packet and the error injection signal.

[0178] Obtain output data of the error packet filtering circuit, and perform performance verification on the error packet filtering circuit based on the output data.

[0179] In another aspect, the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the error injection method provided by the above method, and the method comprises:

[0180] Obtain error injection configuration information of the data stream;

[0181] Determine protocol error injection configuration and control signal error injection configuration of data packets in the data stream based on the error injection configuration information;

[0182] Generate an error injection data packet based on the protocol error injection configuration, and generate an error injection signal based on the control signal error injection configuration;

[0183] Drive the error packet filtering circuit based on the error injection data packet and the error injection signal.

[0184] Alternatively, the computer program is executed by a processor to implement the verification method of the error packet filtering circuit provided by the above method, and the method comprises:

[0185] Obtain error injection configuration information of the data stream;

[0186] Determine protocol error injection configuration and control signal error injection configuration of data packets in the data stream based on the error injection configuration information;

[0187] Generate an error injection data packet based on the protocol error injection configuration, and generate an error injection signal based on the control signal error injection configuration;

[0188] Drive the error packet filtering circuit based on the error injection data packet and the error injection signal.

[0189] Obtain output data of the error packet filtering circuit, and perform performance verification on the error packet filtering circuit based on the output data.

[0190] The apparatus embodiments described above are only schematic, wherein the units shown as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place or distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment scheme. Those skilled in the art can understand and implement without creative labor.

[0191] Those skilled in the art can clearly understand the implementation of the embodiments by means of software and necessary general hardware platforms through the description of the above embodiments, and of course, the embodiments can also be implemented by hardware. Based on such understanding, the above technical solutions or the part that contributes to the related art can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0192] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of error injection, the method comprising: The method comprises the following steps: obtaining error injection configuration information of a data stream; determining protocol error injection configuration and control signal error injection configuration of data packets in the data stream based on the error injection configuration information, wherein the protocol error injection configuration is used for configuring error injection information of the data packets at a protocol layer, and the control signal error injection configuration is used for configuring error injection information of the data packets at a signal layer; determining protocol error type protocol error injection indication based on the protocol error injection configuration, generating error injection data packets based on the protocol error injection indication, determining signal error type signal error injection indication based on the control signal error injection configuration, and generating error injection signals based on the signal error injection indication; the protocol error injection indication indicates whether each protocol error type is injected or not, and the signal error injection indication indicates whether each signal error type is injected or not; the error injection data packets and the error injection signals are generated in parallel and independently of each other, and the error injection data packets and the error injection signals are used to realize separate control of error injection at the protocol layer and the signal layer; driving the error injection data packets into a error packet filtering circuit in the form of a data signal, and driving the error injection signals into the error packet filtering circuit in the form of a control signal.

2. The error injection method of claim 1, wherein, The error injection configuration information comprises directional configuration information and a data stream template of the data stream. The directional configuration information comprises at least one of a protocol type, a data packet length, and an error type.

3. The error injection method of claim 2, wherein, The determination of the protocol error injection configuration and the control signal error injection configuration based on the error injection configuration information comprises the following steps: sequentially determining the protocol error injection configuration and the control signal error injection configuration of each data packet in the data stream under the constraint of the directional configuration information based on the data stream template.

4. The error injection method according to any one of claims 1 to 3, characterized by, The method further comprises the following steps: after driving the error injection, if the error injection data packet is not the last data packet of the data stream, determining the protocol error injection configuration and the control signal error injection configuration of the next data packet in the data stream based on the error injection configuration information.

5. A method of verifying a mispack filter circuit, the method comprising: The method comprises the following steps: obtaining error injection configuration information of a data stream; determining protocol error injection configuration and control signal error injection configuration of data packets in the data stream based on the error injection configuration information, wherein the protocol error injection configuration is used for configuring error injection information of the data packets at a protocol layer, and the control signal error injection configuration is used for configuring error injection information of the data packets at a signal layer; determining protocol error type protocol error injection indication based on the protocol error injection configuration, generating error injection data packets based on the protocol error injection indication, determining signal error type signal error injection indication based on the control signal error injection configuration, and generating error injection signals based on the signal error injection indication; the protocol error injection indication indicates whether each protocol error type is injected or not, and the signal error injection indication indicates whether each signal error type is injected or not; the error injection data packets and the error injection signals are generated in parallel and independently of each other, and the error injection data packets and the error injection signals are used to realize separate control of error injection at the protocol layer and the signal layer; driving the error injection data packets into a error packet filtering circuit in the form of a data signal, and driving the error injection signals into the error packet filtering circuit in the form of a control signal. Obtaining output data of the error packet filtering circuit, and performing performance verification on the error packet filtering circuit based on the output data.

6. The method of claim 5, wherein, The error injection configuration information comprises directional configuration information of a data stream and a data stream template. The directional configuration information comprises at least one of a protocol type, a data packet length, and an error type.

7. The method of claim 6, wherein, The error injection configuration information comprises directional configuration information of a data stream and a data stream template. The error injection configuration information comprises directional configuration information of a data stream and a data stream template.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The processor executes the computer program to implement the error injection method of any one of claims 1 to 4 or the verification method of the error packet filtering circuit of any one of claims 5 to 7. 9.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the error injection method of any one of claims 1 to 4 or the verification method of the error packet filtering circuit of any one of claims 5 to 7.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the error injection method of any one of claims 1 to 4 or the verification method of the error packet filtering circuit of any one of claims 5 to 7.

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