Multi-channel data acquisition system and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of signal processing, and discloses a multichannel data acquisition system and method based on an FPGA (Field Programmable Gate Array), an acquisition module drives a global counter by using a global synchronous clock, writes acquired data into an annular buffer area with a physical address and a counter value in a linear mapping relationship, and establishes implicit time index storage. When a trigger event occurs, the system broadcasts the locked global trigger timestamp, and the acquisition module backtracks and reads historical data according to the global trigger timestamp, and packages the historical data into a sparse matrix type data packet in combination with the channel validity mask. And after receiving the data packet, the data processing module directly calculates a memory mapping address by using global time information in the data packet, and writes a data load into a corresponding position of the waveform reconstruction buffer area. According to the method, through strict binding of the physical address and the absolute time, independent time label redundancy is eliminated, high-precision synchronization of distributed multiple channels is ensured, and out-of-order automatic in-situ recombination and efficient waveform reconstruction of data of a receiving end are achieved.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, specifically to a multi-channel data acquisition method based on FPGA. Background Technology

[0002] Multi-channel data acquisition systems based on Field-Programmable Gate Arrays (FPGAs) are the infrastructure of modern high-performance signal processing, widely used in radar detection, industrial monitoring, and high-energy physics experiments. These systems typically utilize the high parallel processing capabilities of FPGAs to perform synchronous analog-to-digital conversion, buffering, and transmission of multiple analog signals, enabling accurate recording and analysis of the spatiotemporal characteristics of the measured object.

[0003] In existing multi-channel acquisition architectures, each acquisition node is typically configured with independent storage resources to buffer sampled data. To maintain data alignment across multiple channels, the system generally uses a unified clock source to distribute synchronization signals. During data transmission, the acquisition module encapsulates the sampled data into frames and appends a timestamp of the trigger time to the header of the data packet, or adds a local timestamp to each set of sampling points. After acquiring the data, the receiving host computer logically sorts and aligns the data from different channels based on these timestamp information, thereby recovering the timing relationship of the original signal.

[0004] However, this conventional approach does not establish an inherent mapping between data addresses and absolute time at the physical storage level, forcing sampled data to rely on additional timestamps for timing identification. This explicit time indexing mechanism not only consumes valuable storage and transmission bandwidth resources, but more importantly, when the system is scaled to a distributed multi-node architecture, the lack of a globally unified spatiotemporal reference strictly bound to physical addresses makes clock phase differences or transmission jitter between different nodes highly susceptible to causing timing deviations during data reassembly, making it difficult to meet the stringent time alignment requirements of high-precision synchronous acquisition. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a multi-channel data acquisition system and method based on FPGA, which solves the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a multi-channel data acquisition method based on FPGA; The first aspect of this invention provides a multi-channel data acquisition system based on FPGA.

[0007] The system employs a star topology, comprising a data processing and control module and multiple distributed multi-channel acquisition modules. The data processing and control module, serving as the system's central hub, integrates a master control field-programmable gate array (FPGA), a high-precision reference clock source, and a gigabit Ethernet physical layer transceiver chip. The high-precision reference clock source is directly connected to the master control FPGA, providing a single reference frequency source for the entire system. The multi-channel acquisition modules, acting as front-end sensing nodes, include acquisition FPGAs and analog-to-digital converters (ADCs). A point-to-point high-speed serial communication link is established between the data processing and control module and each multi-channel acquisition module via a physical transmission medium.

[0008] In this system, the main control field-programmable gate array (FPGA) is connected to the multi-channel acquisition module via a high-speed serial transceiver interface. The downlink transmits control commands and synchronization clock information, while the uplink transmits the acquired data. The system employs a source-synchronous clock architecture; the multi-channel acquisition module board does not have an independent crystal oscillator for driving FPGA logic or ADC sampling. It relies entirely on the clock signal recovered from the downlink, eliminating frequency drift between distributed nodes at the hardware level.

[0009] A second aspect of the present invention provides a multi-channel data acquisition method based on FPGA.

[0010] Based on the aforementioned system architecture, this method achieves high-precision synchronous acquisition and data reconstruction through the collaborative operation of the main control field-programmable gate array (FPGA) and the internal logic of the acquisition FPGA. The method specifically includes the following steps: S1: Physical link establishment and source synchronization clock recovery The data processing and control module sends an 8b / 10b encoded idle alignment sequence through the physical layer. The multi-channel acquisition module receives this sequence and uses the Clock Data Recovery (CDR) circuit integrated within the FPGA to lock the bitstream frequency. The synchronization clock signal extracted by the CDR circuit is then divided or multiplied by the global clock network to generate the local system clock. and analog-to-digital converter sampling drive clock At this time, the clock frequency of all acquisition nodes... With system reference clock frequency Maintain a strict lock-in relationship, that is (k is the frequency division ratio coefficient).

[0011] S2: Transmission Delay Measurement and Global Spatiotemporal Reference Establishment. To eliminate phase deviations caused by differences in physical cable lengths, the system performs precise transmission delay measurements. The data processing and control module performs these measurements at the local master global counter. A ranging frame is sent. The multi-channel acquisition module receives and processes this frame, introducing a fixed node processing delay. Then return via the same route. The data processing and control module operates locally. A return frame has been received. The internal logic unit calculates the one-way physical transmission delay using the following formula. : Subsequently, the data processing and control module calculates the phase compensation value. (in (This is an estimated value for the arrival time of the instruction), and it is sent via the link. Upon receiving the global synchronization reset instruction, the multi-channel acquisition module will update its local global counter. Force loading as This achieves alignment of all node counters in physical absolute time.

[0012] S3: A dual-path ring buffer and real-time feature monitoring multi-channel acquisition module construct a time-indexed ring storage unit. The system abandons the traditional independent address counter, directly using the low value of the local global counter. Bit values ​​are mapped to write addresses Establish a hard mapping relationship between time and storage space: Simultaneously, data flows into the pipeline differential logic for real-time feature monitoring. The logic unit calculates the current sampling point. Compared with the previous sampling point The absolute value of the difference, i.e., the rate of change of the signal. : like Greater than or equal to the preset trigger threshold Then a trigger signal is generated.

[0013] S4: Distributed backtracking triggering and time window reconstruction When the trigger condition is met, the acquisition module latches the current counter value as the trigger time. After the main control module broadcasts a global lock command, the acquisition module needs to backtrack historical data to retain waveform characteristics prior to the trigger. The backtracking read / write control unit determines the timing based on the trigger time. Pre-trigger depth and buffer depth , Calculate the starting pointer for reading historical data : This calculation process ensures that even after physical time has passed, the system can still accurately locate the corresponding historical moment data from the circular buffer.

[0014] S5: Data Alignment and Packaging The acquisition module encapsulates the read data into a data packet containing a reference timestamp, a channel validity mask, and a payload. Reference timestamp This corresponds to the absolute time of the first sampling point in the data packet. The data payload is arranged in a time-sliced ​​interleaved manner, does not contain redundant channel identifiers, and uses channel masks to achieve data demultiplexing, maximizing transmission efficiency.

[0015] S6: Upper Computer Panoramic Waveform Reconstruction After receiving the data packet, the host computer or data processing module performs direct memory access (DMA) mapping based on absolute time. The system allocates a global buffer in memory, based on the data packet's reference timestamp. and buffer start time Calculate the memory write offset address : Through this mapping mechanism, out-of-order data packets can directly fall into the correct physical memory address without the need for the CPU to participate in secondary sorting or splicing of the data, thus efficiently completing the task of reconstructing and acquiring panoramic waveforms.

[0016] This invention, through the above-mentioned technical solution, utilizes the high-speed parallel processing capability and transceiver characteristics of FPGA to achieve high-precision time synchronization and efficient data transmission in a multi-channel distributed acquisition system without the need for external high-cost synchronization hardware. This solves the technical problems faced by traditional acquisition systems in long-distance transmission, such as clock asynchrony and data alignment difficulties.

[0017] This invention provides a multi-channel data acquisition system and method based on FPGA. It has the following beneficial effects: 1. This invention establishes a linear mapping mechanism that strictly corresponds to the global counter value and the physical storage address, thereby realizing implicit time-indexed storage of data at the acquisition end. This mechanism eliminates the storage and transmission redundancy caused by attaching independent time tags to each sampling point in traditional methods, ensuring strict synchronization of the distributed multi-channel system under a unified absolute clock domain. It completely solves the data alignment deviation caused by node clock drift, significantly improving the reconstruction accuracy of multi-channel timing signals while reducing transmission bandwidth usage.

[0018] 2. This invention employs a sparse transmission protocol including a channel validity mask, combined with direct address calculation technology at the receiving end, to directly locate the physical write position of the waveform reconstruction buffer using the global reference time within the data frame. This method deeply couples data transmission with memory layout, allowing the receiving end to automatically reassemble out-of-order data in situ without software sorting or secondary copying, greatly reducing the computational load on the data processing unit and thus breaking through the throughput bottleneck of large-scale multi-channel real-time data acquisition and display.

[0019] 3. This invention constructs an adaptive waveform rendering logic based on time scaling ratio, automatically switching between the extreme value scanning mode of the macroscopic view and the smooth interpolation mode of the microscopic view. This method utilizes a segmented cross-boundary addressing algorithm to overcome the physical rollback obstacle of the circular buffer. While ensuring data reading continuity, it ensures that high-frequency narrow pulse characteristics over a large time span are not missed due to pixel downsampling, thereby accurately restoring the complete temporal details of the measured signal at any observation scale on the display terminal. Attached Figure Description

[0020] Figure 1 This is a flowchart of a multi-channel data acquisition method based on FPGA. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Example: Please see the appendix Figure 1 This invention provides an FPGA-based multi-channel data acquisition system, comprising a data processing and control module and N multi-channel acquisition modules, where N is a natural number greater than or equal to 1. The data processing and control module serves as the control core and data aggregation node of the entire distributed FPGA data acquisition system, while the multi-channel acquisition modules act as distributed signal sensing and digitization nodes. A point-to-point communication connection is established between the data processing and control module and each multi-channel acquisition module through an independent physical transmission medium.

[0023] The data processing and control module, in terms of hardware configuration, mainly includes a main control field-programmable gate array (FPGA), a gigabit Ethernet physical layer transceiver chip, and a high-precision reference clock source. The high-precision reference clock source generates the system's base clock signal, and its output is connected to the global clock pin or phase-locked loop (PLL) input pin of the main control FPGA, providing a unified time and frequency reference for the entire distributed system. The main control FPGA connects to the gigabit Ethernet physical layer transceiver chip via an RGMII or GMII interface and accesses the local area network (LAN) via an RJ45 or fiber optic interface to achieve high-speed data interaction with the host computer. Furthermore, the main control FPGA provides N sets of high-speed serial transceiver interfaces or low-voltage differential signal interfaces, each set of interfaces connecting to a multi-channel acquisition module, forming a downlink control link and an uplink data link.

[0024] The multi-channel acquisition module mainly comprises a field-programmable gate array (FPGA), an analog signal conditioning circuit, and an analog-to-digital converter (ADC). The analog signal conditioning circuit includes a signal amplification unit and an anti-aliasing filter unit. The analog signal output from the external sensor is amplified, its amplitude adjusted, and then input to the anti-aliasing filter unit. After filtering out high-frequency noise, the signal is input to the analog input terminal of the ADC. The digital output interface of the ADC is connected to the data receiving pin of the FPGA.

[0025] To achieve nanosecond-level global source synchronization and completely eliminate frequency deviations between channels, this embodiment features a specific design for the clock architecture of the multi-channel acquisition module: no independent active crystal oscillators for driving FPGA logic or ADC sampling are placed on the circuit board of the multi-channel acquisition module. The clock input of the acquisition field-programmable gate array (FPGA) is directly connected to the receiver of the physical transmission medium. The FPGA utilizes its internally integrated clock data recovery circuit, phase-locked loop, or mixed-mode clock management unit to extract a synchronization clock signal that is in phase and frequency with the system reference clock from the received downlink high-speed bitstream. This synchronization clock signal is then divided or multiplied by the FPGA's internal global clock network and output to the clock input pin of the analog-to-digital converter (ADC) as the sampling drive clock for the ADC. This hardware architecture ensures that the sampling operation of the multi-channel acquisition module is strictly controlled at the physical level by the clock source distributed by the data processing and control modules.

[0026] The physical transmission medium preferably uses twisted-pair cables or coaxial cables with independent shielding layers to meet the impedance matching and electromagnetic compatibility requirements of high-speed differential signal transmission. For the core processing chip, the main control field-programmable gate array (FPGA) and the acquisition FPGA can be FPGA chips with hardware serial transceiver resources or high-speed differential I / O resources, such as the Xilinx Kintex Artix series or the Intel Cyclone Arria series. This hardware topology provides the necessary physical foundation for the subsequent implementation of a global time base based on cable delay compensation and a backtracking trigger mechanism.

[0027] The main control field-programmable gate array of the data processing and control module is configured with a global clock distribution unit, a transmission delay measurement and control unit, an instruction arbitration and broadcast unit, and an Ethernet protocol stack interface unit through a hardware description language.

[0028] The input of the global clock distribution unit is connected to a high-precision reference clock source, and the output is connected to multiple high-speed serial transmit interfaces of the main control field-programmable gate array. The global clock distribution unit is configured with a hybrid-mode clock manager or phase-locked loop (PLL) for generating the system reference clock. The global clock distribution unit is also equipped with a line encoder to encode and embed the frequency information of the system reference clock into the downlink high-speed serial data stream for recovery by the acquisition nodes.

[0029] The transmission delay measurement and control unit is internally equipped with a high-bit-width master global counter and a bidirectional timestamp capture register. In round-trip delay measurement mode, the transmission delay measurement and control unit is configured to monitor the physical interface status in real time. When the transmission or reception time of the ranging frame header is detected, the current value of the master global counter is immediately latched. The transmission delay measurement and control unit is also connected to an arithmetic logic unit for calculation, which calculates the physical transmission delay of each channel based on the latched value and generates the corresponding phase compensation parameters.

[0030] The command arbitration and broadcast unit is connected to the high-speed serial receiving and transmitting interfaces. This unit is internally configured with priority arbitration logic. When trigger request frames from multiple multi-channel acquisition modules are received simultaneously or sequentially, the command arbitration and broadcast unit, based on the first-to-first principle or a preset channel priority, parses out the first valid trigger timestamp and immediately assembles a global locking command containing that trigger timestamp, broadcasting it in parallel to all multi-channel acquisition modules.

[0031] The multi-channel acquisition module's field-programmable gate array is equipped with a clock recovery and phase alignment unit, a feature extraction pipeline unit, a time-indexed ring storage unit, a backtracking read / write control unit, and a sparse data encapsulation unit.

[0032] The clock recovery and phase alignment unit directly utilizes the clock data recovery circuit in the FPGA hard-core serial transceiver to extract the synchronization clock from the received downlink serial bit stream and generate a local system clock through frequency division. Internally, this unit maintains a local global counter and a compensation value register. When a synchronization reset command is received from the master node, the local global counter is not cleared; instead, the preset phase compensation value stored in the compensation value register is loaded in parallel, thereby eliminating the count deviation caused by transmission delay.

[0033] The feature extraction pipeline unit is connected to the parallel data interface of the analog-to-digital converter. This unit contains multi-stage pipelined differential operation logic constructed from digital signal processing slices, configured to calculate the discrete rate of change of the sampled data in real time each clock cycle. The unit also compares the calculated rate of change with a preset threshold register, and when a trigger condition is met, sends a request frame containing the current local global counter value to the master node.

[0034] The time-indexed ring memory is the core storage component of this embodiment, constructed from the dual-port block random access memory within the acquisition field-programmable gate array (FPGA). The write address bus of the time-indexed ring memory is not connected to a conventional incrementing counter, but is directly physically connected to the low N bits of the local global counter, where N is determined by the address depth of the block random access memory. This configuration ensures that the physical storage address to which sampled data is written uniquely and consistently corresponds to the global time count value at its sampling moment, forming a direct time-address mapping.

[0035] The backtracking read / write control unit is connected to the read address port of the time-indexed ring memory unit. This unit internally contains a subtractor and a modulo operator. When it receives a signal containing the trigger time (… When a global lock instruction is executed, the read / write control unit performs the following operations: ( ,in The buffer depth is used to calculate the starting read address corresponding to the historical trigger moment. Subsequently, this unit controls the read pointer to increment from this starting read address, achieving complete extraction of historical waveform data before and after the trigger moment. The sparse data encapsulation unit is used to construct uplink Ethernet packets. This unit internally contains bitmask generation logic and a data alignment first-in-first-out (FIFO) queue. The bitmask generation logic generates a bitmap sequence corresponding to the time block based on the validity markers output by the feature extraction pipeline unit. The sparse data encapsulation unit packages the reference timestamp, the bitmap sequence, and a payload containing only valid data, and sends it to the master node through the Media Access Control (MAC) core.

[0036] This invention discloses a distributed FPGA adaptive data acquisition method, relying on a hardware platform composed of the aforementioned data processing and control module and a multi-channel acquisition module. Through the coordinated execution of the main control field-programmable gate array (FPGA) and the internal logic units of the acquisition FPGA, the method specifically includes the following steps: Step S1: Physical Link Establishment and Source Synchronization Clock Recovery. After system power-on initialization, the data processing and control module sends a physically layer-encoded idle alignment sequence to all connected multi-channel acquisition modules via the high-speed serial interface's transmission channel. The multi-channel acquisition modules receive the idle alignment sequence and, using the clock data recovery circuit or phase-locked loop within the acquisition field-programmable gate array (FPGA), lock the bit clock frequency in the input data stream and divide it to generate the local system clock and the analog-to-digital converter (ADC) sampling clock. Through this step, the operating frequencies of all multi-channel acquisition modules are frequency-locked with the high-precision reference clock source frequency of the data processing and control module, establishing a frequency synchronization reference for the entire system.

[0037] Step S2: Measurement of transmission delay based on round-trip delay and establishment of a global spatiotemporal reference After frequency synchronization is established, the data processing and control module initiates the round-trip delay measurement process. The data processing and control module uses its local main global counter at the specified time. Sending the ranging frame. After receiving the ranging frame, the multi-channel acquisition module processes it through a fixed hardware logic delay. The ranging frame is then looped back and sent to the data processing and control module. The data processing and control module then uses its local main global counter to... Upon receiving the return frame, the internal arithmetic logic unit calculates the distance from the master control node to the next node according to the formula. One-way physical transmission delay of each acquisition node After the calculation is completed, the data processing and control module determines the one-way physical transmission delay. The phase compensation value for each multi-channel acquisition module is calculated by multiplying the product with the system clock frequency. The phase compensation value is then sent to the corresponding multi-channel acquisition module via the downlink. Subsequently, the data processing and control module broadcasts a synchronization reset command. Upon receiving the synchronization reset command, the multi-channel acquisition module loads the value of its local global counter as the phase compensation value. This eliminates phase lag introduced by the transmission path, ensuring that the local global counter values ​​of all multi-channel acquisition modules are aligned with the main global counter values ​​of the data processing and control modules on the physical time axis, thus establishing a unified global time reference. .

[0038] Step S3: Dual-path circular buffer and real-time feature monitoring The multi-channel acquisition module enters parallel processing mode.

[0039] In the full-speed write path, the multi-channel acquisition module continuously writes the sampled data stream output from the analog-to-digital converter to the time-indexed circular memory unit. The write logic does not use a sequentially incrementing address counter; instead, it directly maps the low-order bits of the current local global counter to the write address of the time-indexed circular memory unit. Establish the following fixed mapping relationship: in For a moment The local global counter value, The storage depth of the circular buffer.

[0040] In the feature calculation path, the multi-channel acquisition module uses pipelined differential logic to calculate the signal rate of change in real time. The system then determines whether the signal change rate exceeds a preset trigger threshold. In the non-triggered state, the multi-channel acquisition module only performs downsampling processing on the data based on a preset extraction factor and uploads low-bandwidth monitoring data.

[0041] Step S4: Distributed backtracking triggering and time window reconstruction based on RTD parameters When any multi-channel acquisition module detects that the rate of change of the signal exceeds the preset trigger threshold, the multi-channel acquisition module immediately latches the current local global counter value as the trigger moment. And will trigger the time Send to the data processing and control module.

[0042] After receiving the trigger request, the data processing and control module broadcasts the trigger time to all multi-channel acquisition modules in the system. The global locking command.

[0043] When any multi-channel acquisition module receives a global lock command, although the current physical time is already lagging behind the trigger time... This multi-channel acquisition module uses the backtracking read / write control unit to calculate the historical read pointer. : The multi-channel acquisition module controls the read pointer from The system begins reading data from the time-indexed circular storage unit at the specified location, thereby retrieving the data starting from the trigger time. The historical waveform data enabled the complete capture of the signal state before the arrival of the global lock command.

[0044] Step S5: Data Alignment and Packaging Based on Global Timestamp Index. When uploading data, the multi-channel acquisition module uses a sparse data encapsulation protocol based on valid bit markers. The multi-channel acquisition module determines the base timestamp of the data packet. The system generates a bitmask sequence based on the feature extraction results. Each bit in the bitmask sequence corresponds to the validity of one sampling period. The multi-channel acquisition module combines the reference timestamp, bitmask sequence, and payload data into an Ethernet data frame and sends it to the data processing and control module, which then forwards it to the host computer.

[0045] Step S6: Panoramic waveform reconstruction by the host computer After receiving data packets from different multi-channel acquisition modules, the host computer parses the reference timestamps. The host computer determines the starting coordinates of the data block on the absolute time axis based on the reference timestamp, and maps the payload data to specific time coordinate points according to the index values ​​of the bitmask sequence. Through the global time reference established in step S2 and the backtracking alignment mechanism in step S4, the host computer can accurately restore the collected data distributed in different spatial locations to the same time-amplitude chart, eliminating the impact of network transmission delay and jitter on waveform phase consistency.

[0046] This invention utilizes the physical layer link training mechanism to establish a data path between the data processing and control module and the multi-channel acquisition module, and locks the physical layer transmission delay to a fixed value. This process mainly includes three stages: bit synchronization, word boundary alignment, and delay deterministic configuration, comprising the following steps: Step S101: After the system power-on reset, the data processing and control module configures its internal high-speed serial transmission interface to enter the reset initialization state. The data processing and control module controls the physical coding sublayer (PCS) to convert parallel data into a serial bit stream. In the initial link establishment phase, the data processing and control module controls the PCS to continuously transmit a preset idle alignment sequence. When the physical layer protocol is configured for 8b or 10b encoding, the data processing and control module transmits an ordered set containing K28.5 or K28.1 characters. This ordered set contains specific bit-flip sequences that do not appear in the normal data payload, serving as boundary indicators for the serial data stream. When the physical layer protocol is configured for 64b or 66b encoding, the data processing and control module transmits a synchronization header and scrambling sequence with specific transitions for the receiver to lock onto.

[0047] Step S102: The high-speed serial receiving interface of the multi-channel acquisition module receives the differential signal from the physical transmission medium. The clock data recovery circuit inside the multi-channel acquisition module performs oversampling and phase detection operations on the received differential signal. The clock data recovery circuit detects the level transition edge of the input signal and dynamically adjusts the output frequency and phase of the local voltage-controlled oscillator or digitally controlled oscillator so that the sampling edge of the locally recovered clock is aligned with the optimal sampling phase of the input data stream. When the clock data recovery circuit detects that the frequency deviation and phase jitter are lower than the preset lockout threshold, the clock data recovery circuit sets the receive lockout status signal, indicating that the multi-channel acquisition module has achieved frequency tracking and bit synchronization of the bit stream.

[0048] Step S103: Serial-to-Parallel Conversion and Word Boundary Alignment. After bit synchronization is completed, the physical coding sublayer of the multi-channel acquisition module initiates word boundary alignment logic. The word boundary alignment logic slides through the received continuous bit stream, searching for the boundary indicators described in step S101. When a preset number of boundary indicators are detected consecutively, the word boundary alignment logic determines the current parallel data truncation position and controls the serial-to-parallel converter to restore the serial bit stream to parallel data words according to that truncation position. During this process, to ensure the determinism of physical layer latency, the multi-channel acquisition module configures the receive elastic buffer in the physical coding sublayer to operate in bypass mode or fixed-delay mode. If the elastic buffer must be used, the multi-channel acquisition module monitors the phase difference between the write and read pointers and uses pointer reset logic to forcibly reset the depth of the elastic buffer to a fixed value, thereby eliminating random delay components caused by FIFO pointer drift.

[0049] Step S104: Two-way Handshake and Link Status Confirmation. After completing word boundary alignment and buffer phase reset, the multi-channel acquisition module sends a link ready response frame to the data processing and control module via the uplink. The link ready response frame contains a preset handshake feature code, which is distinct from the idle sequence. The data processing and control module receives and parses the link ready response frame. If the data processing and control module identifies the correct handshake feature code, it determines that the physical link of the channel has been successfully established and the delay has been fixed, and then switches the link state machine to the data transmission state.

[0050] For the specific hardware implementation of the high-speed serial transceiver, the data processing and control module and the multi-channel acquisition module can utilize the gigabit transceiver hard core integrated inside the field-programmable gate array. Those skilled in the art can implement the deterministic low-latency transmission mode described in step S103 by configuring the transceiver's attribute parameters, such as disabling the clock correction circuit at the receiving end and disabling the channel bonding function.

[0051] To achieve precise frequency synchronization between the multi-channel acquisition module and the data processing and control module, and to ensure that the sampling operation of the analog-to-digital converter is physically controlled by the high-precision reference clock source of the data processing and control module, this embodiment adopts a clock management architecture based on a cascaded clock data recovery circuit and a phase-locked loop. This architecture is configured to extract a low-jitter synchronization clock from the downlink high-speed serial data stream when the multi-channel acquisition module lacks a local independent reference crystal oscillator. The specific implementation process includes the following steps: Step S105: Bit clock extraction and clock generation recovery The high-speed serial receiving interface of the multi-channel acquisition module receives differential serial data streams from the data processing and control module. The multi-channel acquisition module utilizes the clock data recovery circuit integrated within the gigabit transceiver to process the input signal. The phase detector within the clock data recovery circuit continuously detects the signal transition edges of the differential serial data stream and calculates the phase error between the signal transition edge and the output signal of the local oscillator. The clock data recovery circuit dynamically adjusts the output frequency of the local oscillator based on the phase error, ensuring that the oscillation frequency of the local oscillator remains locked to the physical line rate of the differential serial data stream.

[0052] In locked state, the gigabit transceiver performs a serial-to-parallel conversion and frequency division on the high-speed serial clock, outputting a parallel recovered clock signal. The frequency of this parallel recovered clock signal... Physical line rate of differential serial data stream and serial bit width The following physical relationship exists between them: Due to physical line rate It is generated by the data processing and control module based on the frequency multiplication of its high-precision reference clock source. Therefore, the parallel recovery clock signal is directly traced back to the high-precision reference clock source of the data processing and control module in terms of frequency source, and the two maintain a fixed frequency ratio relationship.

[0053] Step S106: Clock dejittering and multiphase clock synthesis Given that the parallel recovered clock signal output directly from the clock data recovery circuit usually contains high-frequency jitter components introduced by transmission medium and circuit noise, the acquisition field programmable gate array does not directly use this parallel recovered clock signal as the driving source of the analog-to-digital converter.

[0054] The field-programmable gate array (FPGA) receives the parallel recovery clock signal input to its internal mixed-mode clock manager or phase-locked loop (PLL). To optimize clock quality, this mixed-mode clock manager or PLL is configured in low-bandwidth mode. In this mode, the mixed-mode clock manager utilizes an internal low-pass loop filter to significantly attenuate high-frequency jitter components in the parallel recovery clock signal, generating a jitter-free, stable clock signal through frequency synthesis.

[0055] The hybrid-mode clock manager uses its output divider to generate two clock signals from the same source: The first path is the local system clock ( ), used to drive the logic circuits inside the field-programmable gate array (FPGA) for data acquisition.

[0056] The second path is the sampling drive clock ( ), used to drive analog-to-digital converters.

[0057] Through this step, the multi-channel acquisition module obtains a low-jitter sampling clock that is completely synchronized with the frequency of the master control node without configuring a local crystal oscillator.

[0058] Step S107: Physical forwarding and phase adjustment of the sampling clock The FPGA transmits the sampling drive clock to the clock input of the analog-to-digital converter (ADC) via a high-speed differential output pin. To ensure signal integrity of the output clock and reduce duty cycle distortion, the FPGA instantiates a Double Data Rate (DDR) primitive in the output path. The DDR primitive's data input D1 is connected to a logic high level, its data input D2 is connected to a logic low level, and its clock input is connected to the internally generated sampling drive clock. The DDR primitive alternates between high and low levels on the rising and falling edges of the sampling drive clock, thereby reconstructing a physical clock signal with a duty cycle accuracy of 50% on the FPGA physical pins. Furthermore, to address the issue of insufficient setup and hold time margin caused by PCB trace delays, the FPGA utilizes the dynamic phase offset function of a mixed-mode clock manager. Based on preset calibration parameters, the FPGA finely adjusts the phase offset of the sampling drive clock relative to the local system clock with picosecond precision. This ensures that the data interface of the analog-to-digital converter meets timing constraints.

[0059] To establish a high-precision global spatiotemporal reference in a distributed FPGA data acquisition system, it is necessary to accurately measure the physical transmission delay between the data processing and control modules and each multi-channel acquisition module. This embodiment employs a hardware round-trip delay (RTD) measurement model based on the physical layer parallel clock domain. This measurement logic is entirely deployed within the underlying physical interface logic of the FPGA, bypassing the upper-layer protocol stack and software interrupt handling, thereby ensuring the determinism of the measurement results. The steps include: Step S201: Ranging frame transmission and transmission timestamp latching The transmission delay measurement and control unit initiates the measurement process. The transmission delay measurement and control unit controls the high-speed serial transmission interface of the data processing and control module to send ranging frames. The ranging frames contain preset physical layer alignment characters as a frame header.

[0060] The transmission delay measurement and control unit monitors the data stream at the parallel data transmission interface between the physical coding sublayer and the gigabit transceiver. When a valid indication signal for the ranging frame header is detected to be valid on the rising edge of the user clock at the transmitting end's physical layer, the transmission delay measurement and control unit immediately latches the current value of the main global counter and records it as the transmission timestamp. Since the master global counter is directly driven by the physical layer user clock at the transmitting end, the transmission timestamp... The clock cycle time at which the ranging frame leaves the FPGA logic layer is precisely marked.

[0061] Step S202: Deterministic hardware loopback and fixed processing delay The multi-channel acquisition module receives the ranging frame. To ensure measurement accuracy, the multi-channel acquisition module is configured in physical layer fast loopback mode.

[0062] The high-speed serial receiving interface of the multi-channel acquisition module performs serial-to-parallel conversion and byte alignment on the received ranging frames. Instead of passing through upper-layer parsing logic, it directly transmits the data to the high-speed serial transmitting interface via an internal fixed-pipeline path, and then sends it back to the data processing and control module. During this process, the total number of clock cycles experienced by the signal through the receiving physical layer, internal logic routing, and transmitting physical layer of the multi-channel acquisition module is defined as the node processing delay. .

[0063] Based on the bypass or reset operation of the transceiver elastic buffer in step S103 above, this node processes latency. It is a fixed constant whose value is determined by the pipeline stage of the transceiver hardware architecture and is predetermined through circuit simulation or datasheet.

[0064] Step S203: Return frame reception and reception timestamp latch The high-speed serial receiving interface of the data processing and control module receives the ranging frames looped back from the multi-channel acquisition module. The transmission delay measurement and control unit monitors the returned frames at the parallel data receiving interface of the Physical Coding Sublayer (PCS). When a returned frame is detected... When the frame header valid indication signal is valid on the rising edge of the physical layer user clock at the receiving end, the transmission delay measurement and control unit immediately latches the current value of the main global counter and records it as the reception timestamp. The transmission delay measurement and control unit will acquire the transmission timestamp. With the received timestamp It is then fed into the arithmetic logic unit for further calculations.

[0065] Step S204: One-way physical transmission delay calculation model The arithmetic logic unit calculates the unidirectional physical transmission delay from the data processing and control module to the specific multi-channel acquisition module based on the round-trip time difference. .

[0066] According to the physical transmission model, the total round-trip time includes the bidirectional link transmission time and node processing delay. The arithmetic logic unit performs the following calculation: in: and The counter latch value is measured in clock cycles. The node processing delay constant is expressed in clock cycles. The period time of the physical layer user clock is used to convert the count value into nanosecond-level physical time; This is the final calculated one-way physical transmission delay time. To further reduce the impact of quantization errors and clock jitter, the transmission delay measurement and control unit continuously executes the above measurement steps M times. The arithmetic logic unit is equipped with an accumulator and a shift register to calculate the arithmetic mean of the M measurement results, and uses this arithmetic mean as the final one-way physical transmission delay parameter. This parameter provides a quantitative basis for subsequent accurate phase compensation and global time synchronization of the multi-channel acquisition module.

[0067] After obtaining accurate unidirectional physical transmission delay parameters through the aforementioned round-trip delay measurement steps, the data processing and control module and the multi-channel acquisition module collaboratively perform phase compensation operations on the global counter. This operation compensates for the time lag introduced by physical signal transmission and logic processing by setting a preset bias value. The specific steps are as follows: Step S205: Refined calculation of phase compensation parameters The data processing and control module uses its internal arithmetic logic unit to calculate the comprehensive phase compensation value for each multi-channel acquisition module. To ensure nanosecond-level alignment accuracy, the arithmetic logic unit considers not only the physical transmission delay measured in step S304. In addition, there are inherent system-wide instruction parsing and loading path latency constants. The constant This represents the fixed number of clock cycles required from the arrival of the synchronization command at the physical pin of the multi-channel acquisition module, through serial-to-parallel conversion and protocol parsing, to the loading port of the local global counter. The arithmetic logic unit performs the following calculation formula: in, For the system clock cycle. Calculation results. It accurately characterizes the time lead of the master node's global counter relative to the slave node when the data processing and control module issues a synchronization command and the command takes effect.

[0068] Step S206: Issuance and storage of compensation parameters The data processing and control module will calculate the comprehensive phase compensation value. It is encapsulated into a configuration data frame and sent to the corresponding multi-channel acquisition module through a high-speed serial transmission interface.

[0069] The multi-channel acquisition module receives configuration data frames and parses out the comprehensive phase compensation value. This information is then written to the shadow register or phase compensation register inside the field programmable gate array (FPGA). At this point, the local global counter of the multi-channel acquisition module is in a free-running state, but its count value is not yet aligned with the master control node.

[0070] Step S207: Point-to-point broadcast of synchronization command Once all multi-channel acquisition modules in the system have completed the configuration of phase compensation parameters, the data processing and control module initiates the global synchronization process.

[0071] The data processing and control module configures its internal transmission logic to broadcast global synchronization characters in parallel to all multi-channel acquisition modules during the same clock cycle when the main global counter flips to the preset alignment time.

[0072] The global synchronization character is sent through a low-latency channel at the physical layer, ensuring that the transmission time strictly corresponds to a specific count value of the master global counter.

[0073] Step S208: Synchronous loading and execution of local counters The high-speed serial receiving interface of the multi-channel acquisition module detected the global synchronization character. The physical encoding sublayer inside the multi-channel acquisition module directly outputs a single-clock-cycle synchronization trigger pulse.

[0074] The synchronization trigger pulse is directly connected to the synchronization loading terminal of the local global counter. The local global counter is configured in synchronization preset mode, and its data input terminal is physically connected to the phase compensation register configured in step S206.

[0075] When the synchronization trigger pulse is valid, the local global counter does not increment by 1 on the next rising edge of the clock; instead, it increments the value in the phase compensation register. Parallel loading into the counter register.

[0076] Starting from the next clock cycle after loading is complete, the local global counter begins to accumulate continuously based on the loaded value, thereby logically eliminating the time consumption of the transmission process.

[0077] Step S209: Timing verification of alignment effect Based on the above mechanism, this embodiment achieves logical timing alignment across the entire system. The timing relationship is as follows: Assume the data processing and control module is at the main global counter... A synchronization command is constantly being issued. This command takes physical transmission time. and receiver logical delay time (i.e. After that, at physical time The multi-channel acquisition module is triggered to load. At this point, physical time has already elapsed. The main global counter of the data processing and control module is in The value of the time should be The multi-channel acquisition module is in The values ​​loaded at any given time are as follows: (Note: If Then the formula simplifies to the form of step S205).

[0078] Therefore, at the instant the loading action is completed, the local global counter value of the multi-channel acquisition module and the main global counter value of the data processing and control module are completely equal within the allowable error range, thus realizing global time synchronization of distributed nodes.

[0079] To achieve real-time caching of high-speed continuous sampling data and retrospective access to historical data, while reducing storage resource consumption, this embodiment constructs a time-indexed circular buffer within the field-programmable gate array (FPGA) of the multi-channel acquisition module. This time-indexed circular buffer establishes a fixed linear mapping relationship between physical time and storage space through hardware interconnect logic, including the following steps: Step S301: Construction of Dual-Port Storage Architecture The multi-channel acquisition module utilizes the block random access memory or very large-scale random access memory resources within the acquisition field-programmable gate array (FPGA) to construct a physical storage array. The multi-channel acquisition module configures this physical storage array in a simple dual-port mode, which includes a set of independent write ports and a set of independent read ports.

[0080] The write port is configured for full-speed continuous write mode, and its bit width is configured as follows: Deep configuration as .depth Select 2 power ( ),in This represents the bit width of the address bus.

[0081] The clock input of the write port is connected to the local system clock. The clock input of the read port can be connected to the local system clock or, depending on the subsequent processing requirements, to an independent read clock, enabling data extraction across clock domains.

[0082] Step S302: Direct address mapping based on global counter The multi-channel acquisition module eliminates the independent write pointer counter logic required by traditional FIFOs. Instead, it uses the low-frequency input from the local global counter's output bus. The bit is directly connected to the write address input port of the time-indexed circular buffer via physical wiring. .

[0083] Thus, the sampling time was established. With storage address A rigid linear mapping relationship between them: in, For a moment The local global counter value, This indicates that the lowest value is truncated. 1 bit.

[0084] Under this mapping mechanism, the write address bus automatically increments by 1 for each clock cycle the local global counter increases. When the local global counter goes low... When a bit overflow occurs, the write address automatically rolls back to the zero address, thus achieving automatic circular overwrite writing at the hardware level without software intervention.

[0085] Step S303: Data bit width adaptation and pipelined writing The bit width of the raw sampled data output by the analog-to-digital converter Typically smaller than the storage word width of the buffer. The multi-channel acquisition module deploys data stitching units on the write path. The data stitching units are located in... Collect within one clock cycle sampling points ( ), and will this Each sampling point is concatenated in parallel to form a wide bus data word. To maintain strict address-time correspondence, the data concatenation unit outputs a write enable signal. The write enable signal goes high only when the data concatenation unit has collected a complete wide bus data word, and simultaneously, the low-order address corresponding to the local global counter is updated, writing the data word into the buffer. Note: If the system is designed to write every clock cycle, there is no need to enable the write signal; keeping it constantly active is sufficient.

[0086] Step S304: Implicit timestamp recording and absolute time reconstruction Based on the above mapping relationship, stored at address The sampled data at that location corresponds to the low acquisition time. Bit must equal address Therefore, the multi-channel acquisition module does not explicitly store 64-bit timestamp data in memory, thus saving storage space. When it is necessary to backtrack to data from a specific historical moment, the data processing and control module reconstructs the absolute time using a combination of a trigger time snapshot and an address index. Specifically, for data stored at address... The data, its absolute physical time Reconstructed from the following formula: in, Indicates bit concatenation operation. This is the high-order bit of the global counter latched when the trigger event occurs. By combining the memory address with the separately latched high-order bit counter, the system can recover the precise absolute physical time of each frame of data without loss.

[0087] Step S305: Configure read / write conflict protection Since the full-speed write port and the random read port share the same physical storage medium, physical layer conflicts may occur due to the same read and write addresses. When configuring the block random access memory, the field-programmable gate array (FPGA) sets the write mode attribute to read-priority or write-priority to determine the data output behavior of the read port when a conflict occurs. In this embodiment, the write mode is preferably configured as read-priority. That is, when the read address and write address overlap, the read port outputs the older data in the storage unit, i.e., the historical data before it was overwritten by the new data. This ensures the logical atomicity and integrity of the data read back. Simultaneously, the backtracking read / write control unit has a safe distance comparison logic to ensure that the read pointer does not exceed the valid historical window defined by the current write pointer.

[0088] To achieve nanosecond-level real-time monitoring of specific signal features without interrupting continuous data stream storage, this embodiment of the invention constructs a real-time feature extraction pipeline independent of the storage path within the programmable gate array at the acquisition site. This real-time feature extraction pipeline employs a parallel computing architecture to process high-speed, wide-bus data and uses a hardware finite state machine to determine trigger events, including the following steps: Step S306: Branching and Parallel Access of Data Flow The multi-channel acquisition module introduces parallel sampled data streams from analog-to-digital converters or data stitching units into two independent hardware paths.

[0089] The first hardware path is connected to the write data port of the time-indexed circular buffer described in step S401 above, and is used for full cyclic recording of the original data.

[0090] The second hardware path connects to the input port of the feature extraction pipeline for real-time signal analysis.

[0091] The feature extraction pipeline receives data in bit-width format. A parallel vector. This parallel vector contains within each system clock cycle. Data from consecutive sampling points ,in This is the parallelism factor.

[0092] Step S307: Parallel Differential Calculation Across Periodic Boundaries The feature extraction pipeline is internally configured with a parallel differential computation unit. This unit is designed to calculate the rate of change of amplitude between adjacent sampling points to identify rapid transitions in the signal. For adjacent points within the parallel vector, i.e. and ,in Parallel differential computing units utilize Each hardware subtractor directly performs parallel subtraction operations. This is done at the boundary point of the parallel vector, i.e., the first sampling point of the current clock cycle. The differential calculation requires the data from the last sample point of the previous clock cycle. The parallel differential calculation unit is configured with a boundary holding register. This boundary holding register latches the last sample point of the current parallel vector at the end of each clock cycle. In the next clock cycle, the parallel differential computation unit will perform the current vector calculation. With historical sampling points stored in the boundary holding register Subtraction is performed to ensure the continuity of differentiation at the clock cycle boundary. The parallel differentiation formula executed by the parallel differentiation computation unit is as follows: in, Indicates the first Within the clock cycle, the th Differential results at each position, This represents the sampled data for the current period. This represents the sampling data from the previous period.

[0093] Step S308: Threshold Comparison and Trigger Mask Generation The parallel differential computing unit will calculate the result Differential result Simultaneously, the data is fed into a multi-channel numerical comparator.

[0094] The multi-channel numerical comparator compares the absolute value of each derivative result with the value in the preset trigger threshold register. Compare them.

[0095] If a certain differential result The absolute value is greater than or equal to The multi-channel comparator sets the corresponding comparison result to logic 1, otherwise it sets it to logic 0. The multi-channel comparator outputs a bit-width value in each clock cycle. The trigger mask vector. This trigger mask vector identifies the index of feature points in the current parallel data block that meet the trigger conditions by the position of the bits.

[0096] Step S309: Finite State Machine and Event Locking The feature extraction pipeline uses a trigger-controlled finite state machine to process the trigger mask vector. The trigger-controlled finite state machine includes an idle state, a pre-filled state, a trigger search state, and a trigger lock state.

[0097] After the system starts data acquisition, the trigger control finite state machine enters the pre-fill state, waiting for the amount of data written to the time-indexed circular buffer to reach the user-preset pre-trigger depth.

[0098] Once the pre-trigger depth meets the requirements, the trigger control finite state machine jumps to the trigger search state.

[0099] In the triggered search state, when at least one logic 1 appears in the trigger mask vector, the trigger control finite state machine executes the priority encoding logic to identify the index value corresponding to the least significant logic 1 in the trigger mask vector. The trigger control finite state machine immediately captures the current local global counter value. and combined with index value Generate precise trigger timestamps: in, This is a coarse-grained count value for the system clock. This is a fine-grained phase offset within the parallel data. The trigger timestamp... The resolution is equivalent to the original sampling period of the analog-to-digital converter, achieving sub-cycle event localization that is superior to the FPGA system clock cycle.

[0100] Step S310: Post-trigger counting and data acquisition stop Once a trigger timestamp is generated, the trigger control finite state machine transitions to the trigger-locked state and starts the internal post-trigger counter.

[0101] The post-trigger counter loads the user-preset post-trigger depth value and decrements each clock cycle. During this period, the multi-channel acquisition module continues to write data to the time-indexed circular buffer to record waveform details after the trigger event occurs.

[0102] When the trigger counter decrements to zero, the trigger control finite state machine outputs a data acquisition completion signal. In response to this signal, the multi-channel acquisition module pulls down the write enable signal of the time-indexed circular buffer, stopping data writing and thus completing a full waveform capture operation. And buffer data, reconstruct a waveform view containing complete information before and after the trigger.

[0103] Based on the nanosecond-level global time synchronization and real-time feature extraction mechanism established in steps S201 to S310 above, this embodiment of the invention uses absolute timestamp anchoring technology to solve the trigger synchronization problem in distributed systems. This technology utilizes a globally counter with phase compensation completed as a unified time reference system, decoupling the triggering event from transmission delay at the physical level. The specific implementation process includes the following steps: Step S401: Event anchoring and uploading of the main trigger node When the trigger control finite state machine of one of the multi-channel acquisition modules in the system enters the trigger lock state, the trigger control finite state machine immediately locks the current global counter value and generates a 64-bit global trigger timestamp. The protocol processing engine of the master triggering node constructs a trigger request frame. This frame uses a polarity-reversed K28.5 character as the frame start delimiter at the physical layer to ensure high-priority transmission on the link. The frame payload contains a global trigger timestamp. In addition to the physical address identifier of the main trigger node, the main trigger node sends the trigger request frame to the data processing and control module through the high-speed serial transmission interface. During this process, the main trigger node continues to write subsequent data into the time-indexed circular buffer and uses the internal post-trigger counter to maintain the local acquisition window until the post-trigger count reaches zero.

[0104] Step S402: Arbitration and Broadcast Distribution by the Master Node The data processing and control module receives trigger request frames from the main trigger node. The trigger arbitration controller within the data processing and control module parses the received requests. If the system is configured for global synchronous trigger mode, the trigger arbitration controller extracts the global trigger timestamp from the trigger request frame. The data processing and control module constructs a global backtracking broadcast frame. This broadcast frame contains a specific broadcast opcode and a 64-bit global trigger timestamp. The data processing and control module distributes the global backtracking broadcast frame in parallel to all multi-channel acquisition modules within the system through its multi-channel high-speed serial transmission interface. Due to the different lengths of the physical links, the physical arrival time of the global backtracking broadcast frame varies from node to node.

[0105] Step S403: Extract from asynchronous reception and timestamp of the trigger node A global backtracking broadcast frame is received from the high-speed serial receive interface of the triggering node. Assume that the frame is received from the triggering node N at its local physical time. Upon receiving the broadcast frame, the local global counter value of trigger node N is currently [value missing]. Since global time synchronization has been completed in step S209, the local global counter of the triggering node is strictly aligned with that of the master triggering node. Therefore, the broadcast frame carries... In the local time coordinate system of triggering node N, this corresponds precisely to the same physical historical moment when the triggering event occurred at the primary triggering node. The protocol parsing logic of triggering node N extracts the data from the broadcast frame. And store it in the target backtrack register.

[0106] Step S404: Backtrack address mapping and align with acquisition window From trigger node N Calculate the backtracking pointer address in the local time-indexed circular buffer. : Simultaneously, the acquisition window alignment calculation is performed from trigger node N to determine the moment to stop acquisition. The theoretical stop timestamp is calculated from trigger node N. : in The user-preset post-trigger depth, starting from the trigger node. Compare the current local global counters With theoretical stop timestamp 1. If This indicates that the data collection window has not yet ended. (From the trigger node) Difference The locally loaded trigger counter continues to collect data until the counter reaches zero, thus completing the waveform data after the trigger.

[0107] 2. If This indicates that due to broadcast delay, the acquisition window has theoretically ended, and some extra data has been written to the buffer (overshoot occurred). From the trigger node Immediately pull the write enable signal low to stop data acquisition, and... The corresponding address is marked as the end address of valid data. Through this mechanism, regardless of fluctuations in broadcast frame transmission latency, the data segments ultimately captured by all nodes strictly begin at [the specified time]. The previous pre-triggered depth, and ended at The subsequent post-trigger depth enables distributed waveform alignment based on absolute time.

[0108] Step S405: Data Validation and Coverage Verification After determining the backtracking address, from the trigger node Perform data coverage verification.

[0109] From the trigger node Calculate the time lag caused by command propagation delay. : From the trigger node Will Maximum physical depth of time-indexed circular buffer Comparison: like If the backtracking operation is successful, the historical data is still stored in the buffer.

[0110] like If a backtracking overflow occurs, it means that the corresponding historical data has been overwritten by the latest loop write, starting from the trigger node. Report a trigger failure error to the data processing and control module.

[0111] Step S406: Retrace back to the absolute position at the start time Once the multi-channel acquisition module determines that the backtracking operation is valid, that is, after passing the validity verification in step S405, the direct memory access controller inside the multi-channel acquisition module starts the read pointer reconstruction process.

[0112] The DMA controller first reads the user-preset pre-trigger depth register to obtain the pre-trigger depth value. .

[0113] The DMA controller uses the arithmetic logic unit to calculate the absolute backtrack start timestamp. : in, This refers to the global trigger timestamp extracted in step S403.

[0114] Subsequently, the DMA controller will use the absolute backtracking start timestamp. Mapped to the initial physical read address of the time-indexed circular buffer Because the buffer uses a direct mapping mechanism based on the low-order bits of the global counter, the calculation of the initial physical read address does not require a complex lookup table, but only a bit truncation operation: in, The physical depth of the circular buffer. This is the address bus width. This is the initial physical read address. Precisely points to the period before the triggering event occurred. The memory unit corresponding to each clock cycle.

[0115] Step S407: Read Length Calculation and Segmentation Strategy Generation DMA controller based on pre-trigger depth and user-preset post-trigger depth Calculate the total length of data to be read in this backtracking operation. : Because the physical address space of a time-indexed circular buffer is circularly continuous, a logically continuous time window may span the physical end address of the buffer. ) and roll back to the first address (0).

[0116] The boundary cross-switching logic inside the DMA controller calculates the initial physical read address. With total data length The sum, and with physical depth Compare them.

[0117] like The boundary cross-checking logic determines that it is in SingleSegment Mode. The DMA controller is configured with a single transfer descriptor, starting from address... Start continuous reading Each data word.

[0118] like The boundary crossover detection logic determines that it is in DualSegmentWrapMode. At this point, the DMA controller automatically generates two consecutively executed transfer descriptors: First descriptor segment: read starting address is The read length is This segment corresponds to the historical data at the physical tail of the buffer.

[0119] Second descriptor: Read starting address is 0, read length is... This segment corresponds to the historical data in the physical header of the buffer. Through this segmentation strategy, the DMA controller shields the physical boundary characteristics of the circular buffer at the hardware level, providing a logically linear and continuous data flow to the back-end processing logic.

[0120] Step S408: Phase identification and reconstruction of the time period To reconstruct the absolute time of each sampling point without storing timestamps, the DMA controller utilizes the absolute backtracking start timestamp. The high-order portion serves as a periodic phase identifier.

[0121] DMA controller extraction High-order value: in, Indicates right shift Bit operations. This characterizes the number of complete cycles the global counter has completed through the circular buffer at the time of data writing. For the second segment of data in the dual-segment cross-volume mode (i.e., data after the physical address has rolled back to 0), since its physical write time has entered the next buffer cycle, the DMA controller automatically updates the cycle phase flag when outputting this segment of data. When the data processing and control module receives the uploaded data packet, it uses this periodic phase identifier. Relative offset of data packets in the buffer This allows for lossless reconstruction of any sampling point. absolute physical time : Or adjust when crossing the boundary This mechanism ensures that even after long periods of continuous operation, the timing information of the backtracking data can still be accurately matched to a global spatiotemporal reference at the nanosecond level.

[0122] Step S409: High-speed burst read and bus arbitration After configuring the transfer descriptor, the DMA controller initiates a burst read request to the read port of the time-indexed circular buffer. Since the time-indexed circular buffer uses a simple dual-port architecture, the read operation and the full-speed write operation in step S401 are executed concurrently at the physical level. To prevent the read pointer from falling behind the write pointer (i.e., the read speed is too fast, resulting in reading invalid future data) or the write pointer from overwriting the read pointer (i.e., the read speed is too slow, resulting in data loss), the DMA controller implements safe distance flow control. The DMA controller monitors the distance between its local global counter (representing the write pointer position) and the current DMA read pointer in real time. Only when the distance between the two remains within a safe threshold range will the DMA controller perform data transfer. The read backtracking data is packaged and uploaded to the data processing and control module via the high-speed bus interface, completing a full distributed backtracking trigger process. Step S501: Construct a self-describing global index frame header When assembling each uploaded data packet, the protocol processing engine first generates a fixed-length protocol frame header. The protocol frame header is configured with an absolute time reference field, ensuring that each individual data packet can be mapped to a unique position in the global data matrix.

[0123] The protocol frame header contains the following fields: Frame synchronization word: A specific code pattern used by the physical layer to identify the start of a frame.

[0124] Data packet sequence number: Used by the receiving end to detect packet loss during transmission.

[0125] Global Baseline Timestamp The value is taken from the 64-bit absolute global counter corresponding to the first sampling point in the data packet payload. Since steps S301 to S305 have established a linear mapping between the global counter and physical time, The absolute starting coordinates of the data packet in the time dimension are defined.

[0126] Sampling depth indication : Indicates the number of consecutive sampling clock cycles contained in this data packet.

[0127] Step S502: Generation of dynamic channel mask The protocol frame header integrates a bit-width... Channel validity mask ,in This corresponds to the maximum number of physical channels in the multi-channel acquisition module.

[0128] Each bit in the channel validity mask uniquely corresponds to a physical acquisition channel. When a channel is enabled and contains valid data within the current time window, the protocol processing engine sets the corresponding bit in the channel validity mask to logic 1; if the channel is disabled, it is set to logic 0.

[0129] The channel validity mask is used to indicate the set of channel data included in subsequent data payloads. By combining the global reference timestamp with the channel validity mask, the data processing and control module can determine the spatiotemporal distribution structure of the sampled data.

[0130] Step S503: Tightly packed packaging of multi-channel data The protocol processing engine concatenates the raw parallel data read from the time-indexed circular buffer based on the channel validity mask to generate the data payload.

[0131] To facilitate parallel hardware processing, the data payload is arranged in a time-slice interleaving manner.

[0132] The specific encapsulation rules are as follows: For each sampling time (in ): The protocol processing engine iterates through the channel validity mask. If the... If the bit is "1", then the channel will be... At any moment Sampling data Write payload; if the first If the bit is "0", then skip the channel.

[0133] Completion Time After all valid channel data has been written, the protocol processing engine continues writing the time. Data until completion Data encapsulation at each moment.

[0134] No separators or padding bits are inserted between data from different channels or at different times in the data payload. The total length of the data payload is... (In bytes) Determined by the following formula: in, This represents the number of set bits in the channel validity mask. The byte width of a single sampling point.

[0135] Step S504: Integrity check and frame end closing The protocol processing engine appends a frame check sequence after the data payload. The frame check sequence is calculated using a 32-bit cyclic redundancy check algorithm, and the calculation range covers all bytes from the protocol frame header to the end of the data payload.

[0136] Finally, the protocol processing engine inserts a frame end delimiter at the end of the data packet to complete the data packet encapsulation.

[0137] The encapsulated data packets are sent to the data processing and control module via a high-speed serial transmission interface. Each data packet's header carries an independent global reference timestamp. With the channel mask, the data processing and control module at the receiving end does not need to rely on the order in which data packets are received, and can directly... The memory offset address is calculated, and the parsed waveform data is filled into the corresponding position in the host computer's memory, supporting stateless parsing of out-of-order data streams.

[0138] To address the issue in traditional data acquisition systems where receiving software consumes computational resources to sort, splice, and align out-of-order data packets, this invention implements a direct memory access mapping mechanism based on absolute time in the data processing and control module. This mechanism utilizes a global reference timestamp carried in the data packet protocol to directly write discrete transmission data packets to the corresponding physical address in the host memory, achieving copy-free reconstruction of waveform data. The mechanism includes the following steps: Step S505: Construction and initialization of the global waveform buffer Before receiving data, the data processing and control module allocates a contiguous physical storage space in the system memory as a global waveform reconstruction buffer.

[0139] The global waveform reconstruction buffer is logically structured as a two-dimensional matrix, where the row dimension corresponds to the physical time axis and the column dimension corresponds to the physical channel index. To accommodate high-speed parallel writes, the memory layout employs a time-interleaved pattern.

[0140] Total size of global waveform reconstruction buffer in bytes Determined by the following formula: in, The desired time window length (in the number of sampling points). This refers to the single-row span. The single-row span is defined as the maximum total number of physical channels supported by the system. With a single sample point byte width The product of, i.e. The data processing and control module records the base address pointer of the global waveform reconstruction buffer. and the global time origin corresponding to the starting address of the buffer. .

[0141] Step S506: Calculation of time offset of received packet The high-speed interface driver of the data processing and control module receives data packets from the multi-channel acquisition module. The data processing and control module performs a CRC check. After the check passes, the data processing and control module extracts the global reference timestamp from the protocol frame header. Sampling depth indication and channel validity mask ; The data processing and control module calculates the relative time offset of the current data packet with respect to the time origin of the global waveform reconstruction buffer. : like If the data exceeds the buffer limit, the data processing and control module will perform a circular rollback calculation according to a preset strategy. Mapped to Within the range, a cyclic waveform display can be achieved.

[0142] Step S507: Calculation of target physical address mapping Based on the calculated relative time offset The data processing and control module calculates the target and writes it to the starting address for the data payload in the data packet. For time-interleaved mode, the time... The corresponding row start address The calculation is as follows: This address directly points to the beginning of the row in the memory matrix at the first sampling moment in the data packet. The physical location of each sampling point in memory depends only on its absolute time offset at the time of generation and its corresponding channel index, and is independent of the arrival order of the data packets during network transmission.

[0143] Step S508: Fixed-point step writing of sparse data The data processing and control module parses the data packet payload and performs a double-loop write operation to complete the data reconstruction.

[0144] Outer loop (time dimension): for each sampling moment contained in the data packet. (in The data processing and control module calculates the row write address at the current moment. : Inner loop (channel dimension): at the current moment The data processing and control module iterates through the channel validity mask. For each channel in the mask that is set to 1 (in The data processing and control module will process the corresponding sampled data words in the payload. Write to address: For channels with a value of 0 in the mask, the data processing and control module skips the corresponding address write operation, keeping the original value of that memory region unchanged. Through these steps, even if multiple data packets arrive out of order, the data processing and control module can still accurately fill them into the correct coordinates of the global waveform reconstruction buffer. The host computer display software only needs to read the global waveform reconstruction buffer at a fixed refresh rate to obtain multi-channel waveform data with strict timing alignment, without performing layer-level sorting or linked list reorganization operations, thereby reducing the CPU load and shortening the end-to-end latency from acquisition to display.

[0145] Based on the direct memory mapping based on the global reference timestamp completed in step S508 above, a two-dimensional data matrix consisting of physical channels and absolute time has been established in the memory space of the data processing and control module. To convert the two-dimensional data matrix into a waveform view and ensure strict timing alignment of multi-channel waveforms at nanosecond precision, this embodiment of the invention implements an absolute time axis mapping and restoration process at the host computer software layer, including the following steps: Step S601: Absolute time definition of the view window The waveform display software receives display control parameters. These parameters include the time scaling ratio. Units: Global clock cycles / pixel and view center time point Unit: Global clock count value.

[0146] Waveform display software obtains the horizontal pixel resolution of the current display area. .

[0147] Waveform display software calculates the absolute time span covered by the current view window. and the absolute timestamp of the view start : Through the above calculations, the waveform display software converts the pixel coordinate system of the user interface into the underlying global counter time coordinate system, thus determining the range of data that needs to be retrieved from the global waveform reconstruction buffer.

[0148] Step S602: Reverse addressing from screen pixels to the circular buffer To draw each horizontal pixel on the screen (in The waveform display software calculates the target global time index corresponding to this pixel. : The waveform display software performs data validity checks. The waveform display software obtains the maximum physical depth of the global waveform reconstruction buffer. And the latest write pointer timestamp .

[0149] like This indicates the target global time index. The corresponding historical data has been overwritten by the latest data, and the waveform display software marks the pixel as invalid.

[0150] If the data is valid, the waveform display software performs a circular buffer mapping calculation. Because the global waveform reconstruction buffer uses a circular overwrite mechanism, the waveform display software calculates the target global time index relative to the buffer's global time origin. Physical offset index : in, This indicates a modulo operation, ensuring that the calculated index value always falls within the range of 0. Within the legal physical address space.

[0151] For each physical channel to be displayed The waveform display software combines the base address pointer recorded in step S505 above. and single-row span Calculate memory read address : This formula realizes the mapping transformation from linearly growing global absolute time to finite cyclic physical memory addresses.

[0152] Step S603: Physical time coordinate calibration and rendering Waveform display software reads the waveform from the calculated memory address using direct memory access or memory copy instructions. Read the voltage sample value and plot the waveform points in the vertical direction of the display buffer.

[0153] Waveform display software will target global time index Convert to physical time value Used to draw timeline scales: in, The period constant is the global synchronization clock, since the waveform data of all channels are based on the same... index calculated During the reading process, the waveforms from different channels are inherently kept in phase alignment on the display screen. Regardless of whether there are differences in transmission delay between channels or reversals in the order of data packet arrival during data acquisition, after the reverse addressing in step S602 and the unified calibration in step S603, the final waveform view reconstructs the physical phase relationship of all signals at the sampling time.

[0154] To present waveform data containing high-frequency transient characteristics on the host computer display interface and adapt to observation needs at different time scales, this embodiment of the invention configures adaptive sampling rendering logic in the waveform display software. This logic automatically switches between peak detection mode and subsampling interpolation mode based on the current time scaling parameters. The specific implementation steps are as follows: Step S604: Range extremum aggregation based on scaling ratio Waveform display software obtains the current time scaling ratio Unit: Global clock cycles / pixel. The waveform display software will... With the preset aggregation threshold Compare them.

[0155] when This indicates that a single screen pixel corresponds to multiple physical sampling points in the global waveform reconstruction buffer. To prevent the loss of high-frequency pulse signals, the waveform display software performs peak scanning. For each horizontal pixel coordinate on the screen... The waveform display software determines the logical global time range covered by the pixel. The waveform display software reconstructs the depth of the buffer based on the global waveform. and the origin of time The logical time range is mapped to a physical address offset range. If the logical time range crosses the physical boundary of the circular buffer (i.e., a rollback occurs), the waveform display software divides the lookup operation into a first physical segment (from the start of the mapping to the end of the buffer) and a second physical segment (from the beginning of the buffer to the end of the mapping). The waveform display software traverses and reads sampled data within the calculated physical address range, calculating the local maximum value within that interval. and local minimum Waveform display software will and Convert to screen vertical coordinates and in the current horizontal coordinates A vertical line segment connecting the two is drawn at the point where the nanosecond-level signal transition characteristics identified by step S307 are displayed in the form of an extreme value envelope, thus achieving lossless downsampling.

[0156] Step S605: Subpixel-level smooth interpolation when This indicates that multiple pixels on the screen are distributed between two adjacent physical sampling points. To provide smooth waveform details, the waveform display software performs interpolation rendering. This is done for the screen pixel coordinates. The waveform display software calculates its corresponding floating-point global time position. The waveform display software determines the global time indices of two adjacent integers before and after this time position: left index. and right-hand index : The waveform display software calculates the corresponding physical read address. For the index on the right... The waveform display software performs a modulo operation boundary check: Waveform display software uses the aforementioned base address and physical offset Read the corresponding sample value and .

[0157] The waveform display software calculates the display value of the current pixel based on a preset interpolation algorithm. .

[0158] If a linear interpolation algorithm is used, the calculation formula is: If the zero-order hold algorithm (applicable to digital logic signals) is used, the calculation formula is: The waveform display software will calculate The data is mapped to screen coordinates and rendered. Through the adaptive processing in steps S604 and S605, this embodiment of the invention fully utilizes the complete time-series data stored in the global waveform reconstruction buffer, ensuring the integrity of waveform signals at different observation scales.

[0159] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A multi-channel data acquisition system based on FPGA, characterized in that, Includes the following modules: The data processing and control module, serving as the control core and data aggregation node, includes a main control field-programmable gate array, a high-precision reference clock source, and a gigabit Ethernet physical layer transceiver chip. The high-precision reference clock source is used to generate the system's reference clock signal; Multiple multi-channel acquisition modules serve as distributed signal sensing and digitization nodes, with each multi-channel acquisition module including a field-programmable gate array (FPGA) and an analog-to-digital converter (ADC). A physical transmission medium is used to establish a point-to-point communication connection between the data processing and control module and each of the multi-channel acquisition modules; wherein, the data processing and control module distributes clocks and instructions to the multi-channel acquisition modules through the physical transmission medium, and the multi-channel acquisition modules transmit data back to the data processing and control module through the physical transmission medium.

2. The FPGA-based multi-channel data acquisition method according to claim 1, characterized in that, The system applied to the FPGA-based multi-channel data acquisition system of claim 1 includes the following steps: Step S1: Physical link establishment and source synchronization clock recovery; The data processing and control module sends the physical layer encoded idle alignment sequence; The multi-channel acquisition module receives the idle alignment sequence, uses the clock data recovery circuit inside the acquisition field programmable gate array to lock the frequency in the received downlink serial bit stream, and divides the frequency to generate the local system clock and the analog-to-digital converter sampling drive clock, thereby achieving frequency locking with the system reference clock signal; Step S2: Transmission delay measurement and global spatiotemporal reference establishment; the data processing and control module measures the round-trip delay between itself and the multi-channel acquisition module, calculates the phase compensation value and sends it to the multi-channel acquisition module; the multi-channel acquisition module adjusts its local global counter according to the phase compensation value to establish a unified global time reference; Step S3: Dual-path ring buffer and real-time feature monitoring; The multi-channel acquisition module continuously writes the sampled data stream output by the analog-to-digital converter to the time-indexed ring storage unit, and uses pipelined differential logic to calculate the signal change rate in real time; Step S4: Distributed backtracking triggering and time window reconstruction; when the signal change rate exceeds the preset trigger threshold, the multi-channel acquisition module latches the trigger moment and sends a request; the data processing and control module broadcasts a global lock command; the multi-channel acquisition module backtracks and reads historical waveform data according to the global lock command; Step S5: Data alignment and packaging; The multi-channel acquisition module generates a data packet containing a reference timestamp, bitmask sequence, and payload, and sends it to the data processing and control module; Step S6: Panoramic waveform reconstruction by the host computer; The host computer receives the data packet forwarded by the data processing and control module, and reconstructs the waveform data according to the reference timestamp and the bit mask sequence, thereby completing the FPGA-based multi-channel data acquisition.

3. The FPGA-based multi-channel data acquisition method according to claim 2, characterized in that, In step S1, the clock architecture of the multi-channel acquisition module is designed as follows: The circuit board of the multi-channel acquisition module does not have an independent active crystal oscillator for driving FPGA logic or ADC sampling. The field-programmable gate array (FPGA) for data acquisition uses the internally integrated clock data recovery circuit to extract a synchronous clock signal that is in phase and frequency with the system reference clock signal from the received downlink high-speed bit stream. The synchronous clock signal is divided or multiplied by the global clock network and then output to the clock input pin of the analog-to-digital converter as the sampling drive clock of the analog-to-digital converter.

4. The FPGA-based multi-channel data acquisition method according to claim 2, characterized in that, The specific process of measuring transmission delay in step S2 includes: The data processing and control module sends a ranging frame at the time of sending the local main global counter; The multi-channel acquisition module receives the ranging frame, processes it through a fixed node delay, and then sends it back along the original path. The data processing and control module receives the return frame at the time of receiving the local main global counter; The data processing and control module uses its internal arithmetic logic unit to calculate the one-way physical transmission delay. The calculation method is as follows: subtract the receiving time from the sending time to obtain the round-trip time difference, subtract the node processing delay from the round-trip time difference, and divide the result by two.

5. The FPGA-based multi-channel data acquisition method according to claim 2, characterized in that, The specific process of establishing the global spatiotemporal reference in step S2 includes: The data processing and control module calculates the phase compensation value based on the calculated one-way physical transmission delay, and sends the phase compensation value to the corresponding multi-channel acquisition module through the downlink control link. The data processing and control module broadcasts a synchronous reset command. When the multi-channel acquisition module receives the synchronous reset command, it loads the value of the local global counter as the phase compensation value, so that the local global counter is aligned with the main global counter of the data processing and control module on the physical time axis.

6. The FPGA-based multi-channel data acquisition method according to claim 2, characterized in that, The specific process of writing the time-indexed ring storage unit in step S3 is as follows: The multi-channel acquisition module does not use a sequentially incrementing address counter. Instead, it directly maps the low-order value of the current local global counter to the write address of the time-indexed ring storage unit, thus establishing a fixed mapping relationship between the sampling time and the storage address. When the low-order value of the local global counter overflows, the write address automatically rolls back, achieving a circular overwrite write.

7. The FPGA-based multi-channel data acquisition method according to claim 2, characterized in that, The real-time feature monitoring in step S3 includes: The multi-channel acquisition module uses the pipelined differential logic to perform parallel differential calculations, calculates the difference between the sampled data of the current clock cycle and the sampled data of the previous position, and obtains the signal change rate. The multi-channel acquisition module compares the absolute value of the signal change rate with the preset trigger threshold. If it is greater than or equal to the preset trigger threshold, a trigger mask vector is generated.

8. The FPGA-based multi-channel data acquisition method according to claim 2, characterized in that, The specific process of step S4 includes: When the multi-channel acquisition module detects a trigger condition, it latches the current value of the local global counter as the trigger moment. When the multi-channel acquisition module receives the global locking command, even though the current physical time is already behind the trigger time, it uses the backtracking read / write control unit to calculate the historical read pointer. The calculation method is: subtract the pre-trigger depth from the trigger time and perform a modulo operation on the buffer depth of the time-indexed ring storage unit. The multi-channel acquisition module controls the read pointer to start reading data from the time-indexed ring storage unit from the position corresponding to the historical read pointer.

9. The FPGA-based multi-channel data acquisition method according to claim 2, characterized in that, The format of the data packet generated in step S5 includes: The protocol frame header includes the reference timestamp, which is taken from the absolute global counter value corresponding to the first sampling point in the data packet payload; Channel validity mask, where each bit uniquely corresponds to a physical acquisition channel, is used to indicate the set of channel data contained in the subsequent data payload; The data payload is arranged in a time-sliced ​​interleaving manner, continuously splicing the raw parallel data read from the time-indexed ring storage unit, without inserting separators between data from different channels and at different times.

10. The FPGA-based multi-channel data acquisition method according to claim 2, characterized in that, In step S6, the data processing and control module executes a direct memory access mapping mechanism based on absolute time, including: The data processing and control module allocates a global waveform reconstruction buffer in the system memory; The data processing and control module parses the received data packet and extracts the reference timestamp; The data processing and control module calculates the relative time offset of the current data packet with respect to the time origin of the global waveform reconstruction buffer, and calculates the target write start address based on the relative time offset. The data processing and control module directly writes the data payload to the physical memory address corresponding to the target write start address, without needing to sort or reorganize the data.

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