Pixel driving circuit and display substrate

Abstract

The invention relates to the technical field of display, and discloses a pixel driving circuit and a display substrate, the pixel driving circuit comprises a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a driving transistor and a first capacitor, the first end of the first switch transistor and the first end of the second switch transistor are both coupled with the control end of the driving transistor, the first end of the third switch transistor and the first end of the fourth switch transistor are both coupled with the first end of the first capacitor, and the second end of the first capacitor is coupled with the second end of the driving transistor. The control end of the first switch transistor and the control end of the fourth switch transistor are both coupled with the first scanning control end, the control end of the second switch transistor and the control end of the third switch transistor are both coupled with the second scanning control end, and the control ends of the different switch transistors are connected with the same scanning control end. Layout and wiring are optimized, and formation of a narrow frame is facilitated.

Description

Pixel driving circuit and display substrate

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 28, 2024, with application number PCT / CN2024 / 084427 and application name “A pixel circuit, display substrate and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology and provides a pixel driving circuit and a display substrate. Background Art

[0004] In the related art, as shown in FIG1 , the switching transistors M1 , M2 and M3 in the pixel driving circuit need to be connected to signal lines of different groups of shift registers, which results in a complicated layout and wiring in the display panel and is not conducive to forming a narrow frame. Summary of the Invention

[0005] The embodiments of the present disclosure provide a pixel driving circuit and a display substrate for optimizing layout and wiring, thereby facilitating the formation of a narrow frame.

[0006] The specific technical solutions provided by this disclosure are as follows:

[0007] In a first aspect, an embodiment of the present disclosure provides a pixel driving circuit, comprising: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a driving transistor, and a first capacitor;

[0008] The first terminal of the first switch transistor and the first terminal of the second switch transistor are both coupled to the control terminal of the driving transistor;

[0009] The first end of the third switch transistor and the first end of the fourth switch transistor are both coupled to the first end of the first capacitor, and the second end of the first capacitor is coupled to the second end of the driving transistor;

[0010] The control end of the first switch transistor and the control end of the fourth switch transistor are both coupled to the first scan control end;

[0011] The control end of the second switch transistor and the control end of the third switch transistor are both coupled to the second scan control end.

[0012] In some possible implementations provided by the present disclosure, a second capacitor is further included, wherein a first end of the second capacitor is coupled to the control end of the driving transistor, and a second end of the second capacitor is coupled to the second end of the first capacitor.

[0013] In some possible implementations provided in the present disclosure, the second end of the first switching transistor is coupled to the first reference signal end, the second end of the second switching transistor is coupled to the second reference signal end, the second end of the third switching transistor is coupled to the data signal end, and the second end of the fourth switching transistor is coupled to the third reference signal end.

[0014] In some possible implementations provided by the present disclosure, a first light-emitting control subcircuit is further included, wherein the first light-emitting control subcircuit is connected between the second terminal of the driving transistor and the anode of the light-emitting device;

[0015] The first light emitting control sub-circuit is configured to connect the second terminal of the driving transistor and the anode of the light emitting device in response to the light emitting control signal at the first light emitting control signal terminal.

[0016] In some possible implementations provided by the present disclosure, the first light emitting control subcircuit includes: a fifth switching transistor;

[0017] The control terminal of the fifth switch transistor is coupled to the first light emitting control signal terminal, the first terminal of the fifth switch transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth switch transistor is coupled to the anode of the light emitting device.

[0018] In some possible implementations provided by the present disclosure, the device further includes a first reset subcircuit coupled to the anode of the light-emitting device;

[0019] The first reset sub-circuit is configured to provide a signal from the first initialization signal terminal to the anode of the light emitting device in response to a signal from the first reset control terminal.

[0020] In some possible implementations provided by the present disclosure, the first reset sub-circuit includes: a sixth switch transistor;

[0021] The control terminal of the sixth switch transistor is coupled to the first reset control terminal, the first terminal of the sixth switch transistor is coupled to the anode of the light emitting device, and the second terminal of the sixth switch transistor is coupled to the first initialization signal terminal.

[0022] In some possible implementations provided by the present disclosure, a third capacitor is further included, wherein a first end of the third capacitor is coupled to the control end of the driving transistor, and a second end of the third capacitor is coupled to the first end of the first capacitor.

[0023] In some possible implementations provided in the present disclosure, the second end of the first switching transistor is coupled to the fourth reference signal end, the second end of the second switching transistor is coupled to the first end of the driving transistor, the second end of the third switching transistor is coupled to the fifth reference signal end, and the second end of the fourth switching transistor is coupled to the sixth reference signal end.

[0024] In some possible implementations provided by the present disclosure, a data writing sub-circuit is further included, the data writing sub-circuit being coupled to the first end of the first capacitor, the second end of the third capacitor, the first end of the third switch transistor, and the second end of the fourth switch transistor;

[0025] The data writing subcircuit is configured to provide the signal of the data sending end to the first end of the first capacitor, the second end of the third capacitor, the first end of the third switch transistor and the second end of the fourth switch transistor in response to the signal of the data control end.

[0026] In some possible implementations provided by the present disclosure, the data writing sub-circuit includes: a seventh switch transistor;

[0027] The control end of the seventh switch transistor is coupled to the data control end, the first end of the seventh switch transistor is coupled to the data sending end, and the second end of the seventh switch transistor is coupled to the first end of the first capacitor, the second end of the third capacitor, the first end of the third switch transistor, and the second end of the fourth switch transistor.

[0028] In some possible implementations provided by the present disclosure, a second reset subcircuit is further included, the second reset subcircuit being coupled to the second terminal of the driving transistor and the second terminal of the first capacitor;

[0029] The second reset sub-circuit is configured to provide a signal from the second initialization signal terminal to the second terminal of the driving transistor and the second terminal of the first capacitor in response to a signal from the second reset control terminal.

[0030] In some possible implementations provided by the present disclosure, the second reset sub-circuit includes: an eighth switch transistor;

[0031] The control terminal of the eighth switch transistor is coupled to the second reset control terminal, the first terminal of the eighth switch transistor is coupled to the second terminal of the driving transistor and the second terminal of the first capacitor, and the second terminal of the eighth switch transistor is coupled to the second initialization signal terminal.

[0032] In some possible implementations provided by the present disclosure, a second light-emitting control subcircuit is further included;

[0033] The second light emitting control subcircuit is coupled to the first terminal of the driving transistor and the first power terminal, and is configured to provide a signal from the first power terminal to the first terminal of the driving transistor in response to a light emitting control signal from the second light emitting control signal terminal.

[0034] In some possible implementations provided by the present disclosure, the second light emitting control subcircuit includes: a ninth switching transistor;

[0035] The control terminal of the ninth switch transistor is coupled to the second light emitting control signal terminal, the first terminal of the ninth switch transistor is coupled to the first power terminal, and the second terminal of the ninth switch transistor is coupled to the first terminal of the driving transistor.

[0036] In a second aspect, an embodiment of the present disclosure further provides a display substrate comprising multiple rows and columns of pixel driving circuits such as any one of the above items.

[0037] In some possible implementations provided by the present disclosure, at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal, and at least two rows of pixel driving circuits are electrically connected to the same second scan control terminal.

[0038] In some possible embodiments provided by the present disclosure, the display substrate includes at least two rows of pixel driving circuits electrically connected to the same first scan control terminal, at least two rows of pixel driving circuits electrically connected to the same second scan control terminal, at least two rows of pixel driving circuits electrically connected to the same second reset control terminal, and at least two rows of pixel driving circuits electrically connected to the same second light-emitting control signal terminal.

[0039] In some possible implementations provided by the present disclosure, at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same second scan control terminal, and at least two rows of pixel driving circuits are electrically connected to the same second light emitting control signal terminal.

[0040] In some possible implementations provided by the present disclosure, at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal, and at least two rows of pixel driving circuits are electrically connected to the same second light emitting control signal terminal.

[0041] In some possible embodiments provided by the present disclosure, the display substrate includes at least two rows of pixel driving circuits electrically connected to the same first scan control terminal, at least two rows of pixel driving circuits electrically connected to the same second scan control terminal, and at least two rows of pixel driving circuits electrically connected to the same second light-emitting control signal terminal.

[0042] In some possible embodiments provided by the present disclosure, the display substrate includes a first display area and a second display area, the refresh rate of the first display area is different from the refresh rate of the second display area; the pixel driving circuit is electrically connected to the first scan control terminal, the second scan control terminal, the data control terminal, the second reset control terminal, and the second light-emitting control signal terminal, respectively;

[0043] The pixel driving circuit of the kth row included in the display substrate is adjacent to the pixel driving circuit of the k+1th row included in the display substrate;

[0044] The pixel driving circuit of the kth row is arranged in the first display area, and the pixel driving circuit of the k+1th row is arranged in the second display area; k is a positive integer;

[0045] The display substrate includes a first GOA module, a second GOA module, a third GOA module, a fourth GOA module and a light emitting control signal generating module;

[0046] The first GOA module includes a multi-stage first GOA circuit, the second GOA module includes a multi-stage second GOA circuit, the third GOA module includes a multi-stage third GOA circuit, the fourth GOA module includes a multi-stage fourth GOA circuit, and the light control signal generation module includes a multi-stage light control signal generation circuit;

[0047] The first GOA module is used to provide a signal to the second scan control terminal, the second GOA module is used to provide a signal to the first scan control terminal, the third GOA module is used to provide a signal to the data control terminal, the fourth GOA module is used to provide a signal to the second reset control terminal, and the light control signal generation module is used to provide a light control signal;

[0048] The k-th level first GOA circuit included in the first GOA module and the k+1-th level first GOA circuit included in the first GOA module are not cascaded, the k-th level second GOA circuit included in the second GOA module and the k+1-th level second GOA circuit included in the second GOA module are not cascaded, and the k-th level third GOA circuit included in the third GOA module and the k+1-th level third GOA circuit included in the third GOA module are not cascaded.

[0049] In some possible embodiments provided in the present disclosure, the k-th level fourth GOA circuit included in the fourth GOA module and the k+1-th level fourth GOA circuit included in the fourth GOA module are cascaded, and the k-th level light-emitting control signal generating circuit included in the light-emitting control signal generating module and the k+1-th level light-emitting control signal generating circuit included in the light-emitting control signal generating module are cascaded.

[0050] In some possible implementations provided by the present disclosure, the k-th level first GOA circuit is used to provide a second scanning signal for the k-th row pixel driving circuit, and the k+1-th level first GOA circuit is used to provide a second scanning signal for the k+1-th row pixel driving circuit;

[0051] The k-th level second GOA circuit is used to provide a first scanning signal for the k-th row pixel driving circuit, and the k+1-th level second GOA circuit is used to provide a first scanning signal for the k+1-th row pixel driving circuit;

[0052] The k-th level third GOA circuit is used to provide a signal of the data control end for the k-th row pixel driving circuit, and the k+1-th level third GOA circuit is used to provide a signal of the data control end for the k+1-th row pixel driving circuit;

[0053] The k-th level fourth GOA circuit is used to provide a signal of the second reset control terminal for the k-th row pixel driving circuit, and the k+1-th level fourth GOA circuit is used to provide a signal of the second reset control terminal for the k+1-th row pixel driving circuit;

[0054] The kth level light emitting control signal generating circuit is used to provide a second light emitting control signal for the kth row pixel driving circuit, and the k+1th level light emitting control signal generating circuit is used to provide a second light emitting control signal for the k+1th row pixel driving circuit.

[0055] The beneficial effects of the present disclosure are as follows:

[0056] In summary, an embodiment of the present disclosure provides a pixel driving circuit and a display substrate, which includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a driving transistor and a first capacitor, the first end of the first switching transistor and the first end of the second switching transistor are both coupled to the control end of the driving transistor, the first end of the third switching transistor and the first end of the fourth switching transistor are both coupled to the first end of the first capacitor, the second end of the first capacitor is coupled to the second end of the driving transistor, the control end of the first switching transistor and the control end of the fourth switching transistor are both coupled to the first scan control end, the control end of the second switching transistor and the control end of the third switching transistor are both coupled to the second scan control end, and the control end of the first switching transistor and the control end of the fourth switching transistor are connected to the same scan control end, which optimizes the layout and wiring and is conducive to the formation of a narrow frame.

[0057] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0059] FIG1 is a circuit connection diagram of a pixel driving circuit in the related art;

[0060] FIG2 is a connection diagram of a first pixel driving circuit according to an embodiment of the present disclosure;

[0061] FIG3 is a circuit connection diagram of a first pixel driving circuit in an embodiment of the present disclosure;

[0062] FIG4 is a connection diagram of a second pixel driving circuit according to an embodiment of the present disclosure;

[0063] FIG5 is a circuit connection diagram of a second pixel driving circuit in an embodiment of the present disclosure;

[0064] FIG6 is a connection diagram of a third pixel driving circuit according to an embodiment of the present disclosure;

[0065] FIG7 is a circuit connection diagram of a third pixel driving circuit in an embodiment of the present disclosure;

[0066] FIG8 is a connection diagram of a fourth pixel driving circuit according to an embodiment of the present disclosure;

[0067] FIG9 is a circuit connection diagram of a fourth pixel driving circuit in an embodiment of the present disclosure;

[0068] FIG10 is a connection diagram of a fifth pixel driving circuit according to an embodiment of the present disclosure;

[0069] FIG11 is a circuit connection diagram of a fifth pixel driving circuit according to an embodiment of the present disclosure;

[0070] FIG12 is a connection diagram of a sixth pixel driving circuit according to an embodiment of the present disclosure;

[0071] FIG13 is a circuit connection diagram of a sixth pixel driving circuit in an embodiment of the present disclosure;

[0072] FIG14 is a circuit connection diagram of a seventh pixel driving circuit in an embodiment of the present disclosure;

[0073] FIG15 is a first timing diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0074] FIG16 is a circuit connection diagram of an eighth pixel driving circuit according to an embodiment of the present disclosure;

[0075] FIG17 is a second timing diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0076] FIG18 is a circuit connection diagram of a ninth pixel driving circuit according to an embodiment of the present disclosure;

[0077] FIG19 is a circuit connection diagram of a tenth pixel driving circuit according to an embodiment of the present disclosure;

[0078] FIG20 is a third timing diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0079] FIG21 is a circuit connection diagram of an eleventh pixel driving circuit according to an embodiment of the present disclosure;

[0080] FIG22 is a circuit connection diagram of a twelfth pixel driving circuit according to an embodiment of the present disclosure;

[0081] FIG23 is a circuit connection diagram of a thirteenth pixel driving circuit according to an embodiment of the present disclosure;

[0082] FIG24 is a circuit connection diagram of a fourteenth pixel driving circuit according to an embodiment of the present disclosure;

[0083] FIG25 is a circuit connection diagram of a fifteenth pixel driving circuit according to an embodiment of the present disclosure;

[0084] FIG26 is a circuit connection diagram of a sixteenth pixel driving circuit according to an embodiment of the present disclosure;

[0085] FIG27 is a circuit connection diagram of a seventeenth pixel driving circuit according to an embodiment of the present disclosure;

[0086] FIG28 is a circuit connection diagram of an eighteenth pixel driving circuit according to an embodiment of the present disclosure;

[0087] FIG29 is a circuit diagram of pixel driving circuits located in two adjacent rows in a display substrate according to at least one embodiment of the present disclosure;

[0088] FIG30 is an operation timing diagram of at least one embodiment shown in FIG29;

[0089] FIG31 is a circuit diagram of pixel driving circuits located in two adjacent rows in a display substrate according to at least one embodiment of the present disclosure;

[0090] FIG32 is an operation timing diagram of at least one embodiment shown in FIG31;

[0091] 33 is a circuit diagram of pixel driving circuits located in two adjacent rows in a display substrate according to at least one embodiment of the present disclosure;

[0092] FIG34 is a timing diagram of the operation of at least one embodiment shown in FIG33 during a refresh frame;

[0093] FIG35 is a timing diagram of the operation of at least one embodiment shown in FIG33 in a hold frame;

[0094] FIG36 is a schematic diagram showing at least one embodiment of FIG33 in which GOA (Gate On Array, a gate drive circuit disposed on an array substrate) modules are additionally provided;

[0095] FIG37 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0096] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the technical solutions of the present disclosure, but not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments described in this disclosure without making any creative efforts shall fall within the scope of protection of the technical solutions of the present disclosure.

[0097] The terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present disclosure described herein can be practiced in orders other than those illustrated or described herein.

[0098] In the display field, the demand for narrow borders is increasing. In the related art, as shown in FIG1 , the control terminal of a switching transistor M1 in a pixel driving circuit is connected to a signal line SCAN1, the control terminal of a switching transistor M2 is connected to a signal line SCAN2, and the control terminal of a switching transistor M3 is connected to a signal line SCAN3. In other words, different switching transistors in the pixel driving circuit are connected to signal lines of different groups of shift registers. This results in a complex layout and wiring in the display panel, which is not conducive to achieving a narrow border.

[0099] The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0100] 2 and 3 , a pixel driving circuit proposed in an embodiment of the present application includes: a first switch transistor T1 , a second switch transistor T2 , a third switch transistor T3 , a fourth switch transistor T4 , a driving transistor DTFT and a first capacitor C1 .

[0101] The first terminal of the first switch transistor T1 and the first terminal of the second switch transistor T2 are both coupled to the control terminal of the driving transistor DTFT.

[0102] A first end of the third switch transistor T3 and a first end of the fourth switch transistor T4 are both coupled to the first end of the first capacitor C1 , and a second end of the first capacitor C1 is coupled to the second end of the driving transistor DTFT.

[0103] The control terminal of the first switch transistor T1 and the control terminal of the fourth switch transistor T4 are both coupled to the first scan control terminal GC(n).

[0104] The control terminal of the second switch transistor T2 and the control terminal of the third switch transistor T3 are both coupled to the second scan control terminal GW(n).

[0105] In summary, in the embodiment of the present application, the first switching transistor T1 and the fourth switching transistor T4 share the first scan control terminal GC(n), and the second switching transistor T2 and the third switching transistor T3 share the second scan control terminal GW(n). This method of connecting the two switching transistors to the same scan control terminal eliminates the need for two scan control terminals, optimizes layout and wiring, and facilitates the formation of a narrow bezel.

[0106] 2 and 3 , the pixel driving circuit further includes a second capacitor C2 , a first end of the second capacitor C2 coupled to the control end of the driving transistor DTFT, and a second end of the second capacitor C2 coupled to the second end of the first capacitor C1 .

[0107] During implementation, the voltages across the second capacitor C2 vary with the voltages of the first node N1 and the second node N2 , thereby completing operations such as initialization and data writing on the control terminal of the driving transistor DTFT.

[0108] 2 and 3 , a second terminal of the first switch transistor T1 is coupled to the first reference signal terminal Vref1, a second terminal of the second switch transistor T2 is coupled to the second reference signal terminal Vref2, a second terminal of the third switch transistor T3 is coupled to the data signal terminal Vdata, and a second terminal of the fourth switch transistor T4 is coupled to the third reference signal terminal Vref3.

[0109] In summary, the setting of the above-mentioned first switch transistor T1 and the second switch transistor T2 can initialize the control end of the driving transistor DTFT, the third switch transistor T3 is used to provide the data voltage of the data signal end Vdata to the third node N3, and the setting of the fourth switch transistor T4 can initialize the third node N3.

[0110] 2 and 3 , the pixel driving circuit further includes a first light emitting control subcircuit 10 . The first light emitting control subcircuit 10 is connected between the second terminal of the driving transistor DTFT and the anode of the light emitting device OLED.

[0111] The first light emitting control sub-circuit 10 is configured to connect the second terminal of the driving transistor DTFT and the anode of the light emitting device OLED in response to the light emitting control signal of the first light emitting control signal terminal EM1 (n).

[0112] During implementation, when the light emitting control signal of the first light emitting control signal terminal EM1 (n) is valid, the second terminal of the driving transistor DTFT is connected to the anode of the light emitting device OLED via the first light emitting control sub-circuit 10 .

[0113] 3 , the first light emitting control sub-circuit 10 includes a fifth switch transistor T5 .

[0114] The control terminal of the fifth switch transistor T5 is coupled to the first light emitting control signal terminal EM1(n), the first terminal of the fifth switch transistor T5 is coupled to the second terminal of the driving transistor DTFT, and the second terminal of the fifth switch transistor T5 is coupled to the anode of the light emitting device OLED.

[0115] Exemplarily, the fifth switch transistor T5 can be turned on under the control of the active level of the first light-emitting control signal terminal EM1(n), and can be turned off under the control of the inactive level of the first light-emitting control signal terminal EM1(n). Exemplarily, if the fifth switch transistor T5 is configured as an N-type transistor, the active level of the signal at the first light-emitting control signal terminal EM1(n) is a high level, and the inactive level of the signal at the first light-emitting control signal terminal EM1(n) is a low level. Alternatively, if the fifth switch transistor T5 is configured as a P-type transistor, the active level of the signal at the first light-emitting control signal terminal EM1(n) is a low level, and the inactive level of the signal at the first light-emitting control signal terminal EM1(n) is a high level.

[0116] 3 , the fifth switch transistor T5 is an N-type transistor. When the light emitting control signal at the first light emitting control signal terminal EM1(n) is at a high level, the fifth switch transistor T5 is turned on, and the second end of the driving transistor DTFT is connected to the anode of the light emitting device OLED via the turned-on fifth switch transistor T5.

[0117] 4 and 5 , the pixel driving circuit further includes a first reset sub-circuit 20 . The first reset sub-circuit 20 is coupled to the anode of the light emitting device OLED.

[0118] The first reset sub-circuit 20 is configured to provide a signal of a first initialization signal terminal Vint1 to the anode of the light emitting device OLED in response to a signal of the first reset control terminal GI(n).

[0119] During implementation, when the signal of the first reset control terminal GI(n) is valid, the first reset sub-circuit 20 is turned on, and the signal of the first initialization signal terminal Vint1 is provided to the anode of the light-emitting device OLED via the turned-on first reset sub-circuit 20 .

[0120] 5 , the first reset sub-circuit 20 includes a sixth switch transistor T6 .

[0121] A control terminal of the sixth switch transistor T6 is coupled to the first reset control terminal GI(n), a first terminal of the sixth switch transistor T6 is coupled to the anode of the light emitting device OLED, and a second terminal of the sixth switch transistor T6 is coupled to the first initialization signal terminal Vint1.

[0122] Exemplarily, the sixth switch transistor T6 can be turned on under the control of the active level of the first reset control terminal GI(n), and can be turned off under the control of the inactive level of the first reset control terminal GI(n). Exemplarily, if the sixth switch transistor T6 is configured as an N-type transistor, the active level of the signal at the first reset control terminal GI(n) is a high level, and the inactive level of the signal at the first reset control terminal GI(n) is a low level. Alternatively, if the sixth switch transistor T6 is configured as a P-type transistor, the active level of the signal at the first reset control terminal GI(n) is a low level, and the inactive level of the signal at the first reset control terminal GI(n) is a high level.

[0123] 5 , the sixth switch transistor T6 is an N-type transistor. When the signal at the first reset control terminal GI(n) is at a high level, the sixth switch transistor T6 is turned on, and the signal at the first initialization signal terminal Vint1 is provided to the anode of the light-emitting device OLED via the turned-on sixth switch transistor T6.

[0124] 6 and 7 , the pixel driving circuit further includes a third capacitor C3 , a first terminal of the third capacitor C3 is coupled to the control terminal of the driving transistor DTFT, and a second terminal of the third capacitor C3 is coupled to the first terminal of the first capacitor C1 .

[0125] The third capacitor C3 can maintain the stability of the potentials of the fourth node N4 and the fifth node N5.

[0126] 7 , a second terminal of the first switch transistor T1 is coupled to the fourth reference signal terminal Vref4, a second terminal of the second switch transistor T2 is coupled to the first terminal of the driving transistor DTFT, a second terminal of the third switch transistor T3 is coupled to the fifth reference signal terminal Vref5, and a second terminal of the fourth switch transistor T4 is coupled to the sixth reference signal terminal Vref6.

[0127] In summary, the setting of the first switch transistor T1 can initialize the fourth node N4, which is the control end of the driving transistor DTFT, the setting of the second switch transistor T2 can connect the control end of the driving transistor DTFT and the first end of the driving transistor DTFT, and the setting of the third switch transistor T3 and the fourth switch transistor T4 can initialize the fifth node N5.

[0128] 8 and 9 , the pixel driving circuit further includes a data writing subcircuit 30 coupled to a first terminal of the first capacitor C1, a second terminal of the third capacitor C3, a first terminal of the third switch transistor T3, and a second terminal of the fourth switch transistor T4.

[0129] The data writing sub-circuit 30 is configured to provide the signal of the data sending end Data(k) to the first end of the first capacitor C1, the second end of the third capacitor C3, the first end of the third switching transistor T3 and the second end of the fourth switching transistor T4 in response to the signal of the data control end GW(k).

[0130] During implementation, when the signal at the data control terminal GW(k) is a valid signal, the data writing sub-circuit 30 is turned on, and the signal at the data sending terminal Data(k) is provided to the first end of the first capacitor C1, the second end of the third capacitor C3, the first end of the third switch transistor T3, and the second end of the fourth switch transistor T4 through the turned-on data writing sub-circuit 30.

[0131] 9 , the data writing sub-circuit 30 includes a seventh switch transistor T7 .

[0132] A control terminal of the seventh switch transistor T7 is coupled to the data control terminal GW(k), a first terminal of the seventh switch transistor T7 is coupled to the data transmitting terminal Data(k), and a second terminal of the seventh switch transistor T7 is coupled to the first terminal of the first capacitor C1, the second terminal of the third capacitor C3, the first terminal of the third switch transistor T3, and the second terminal of the fourth switch transistor T4.

[0133] Exemplarily, the seventh switch transistor T7 can be turned on under the control of the active level of the data control terminal GW(k), and can be turned off under the control of the inactive level of the data control terminal GW(k). Exemplarily, if the seventh switch transistor T7 is configured as an N-type transistor, the active level of the signal at the data control terminal GW(k) is a high level, and the inactive level of the signal at the data control terminal GW(k) is a low level. Alternatively, if the seventh switch transistor T7 is configured as a P-type transistor, the active level of the signal at the data control terminal GW(k) is a low level, and the inactive level of the signal at the data control terminal GW(k) is a high level.

[0134] As shown in FIG9 , the seventh switch transistor T7 is an N-type transistor. When the signal at the data control terminal GW(k) is at a high level, the seventh switch transistor T7 is turned on, and the signal at the data transmitting terminal Data(k) is provided to the first terminal of the first capacitor C1, the second terminal of the third capacitor C3, the first terminal of the third switch transistor T3, and the second terminal of the fourth switch transistor T4 via the turned-on seventh switch transistor T7.

[0135] 10 and 11 , the pixel driving circuit further includes a second reset sub-circuit 40 . The second reset sub-circuit 40 is coupled to the second terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 .

[0136] The second reset sub-circuit 40 is configured to provide a signal of the second initialization signal terminal Vint2 to the second terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 in response to a signal of the second reset control terminal GI2 (k).

[0137] During implementation, when the signal of the second reset control terminal GI2(k) is valid, the second reset sub-circuit 40 is turned on, and the signal of the second initialization signal terminal Vint2 is provided to the second terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 through the turned-on second reset sub-circuit 40.

[0138] Referring to FIG. 11 , the second reset sub-circuit 40 includes an eighth switch transistor T8 .

[0139] The control terminal of the eighth switch transistor T8 is coupled to the second reset control terminal GI2(k), the first terminal of the eighth switch transistor T8 is coupled to the second terminal of the driving transistor DTFT and the second terminal of the first capacitor C1, and the second terminal of the eighth switch transistor T8 is coupled to the second initialization signal terminal Vint2.

[0140] Exemplarily, the eighth switch transistor T8 can be turned on under the control of the active level of the second reset control terminal GI2(k), and can be turned off under the control of the inactive level of the second reset control terminal GI2(k). Exemplarily, if the eighth switch transistor T8 is configured as an N-type transistor, the active level of the signal at the second reset control terminal GI2(k) is a high level, and the inactive level of the signal at the second reset control terminal GI2(k) is a low level. Alternatively, if the eighth switch transistor T8 is configured as a P-type transistor, the active level of the signal at the second reset control terminal GI2(k) is a low level, and the inactive level of the signal at the second reset control terminal GI2(k) is a high level.

[0141] 11 , the eighth switch transistor T8 is an N-type transistor. When the signal at the second reset control terminal GI2(k) is at a high level, the eighth switch transistor T8 is turned on, and the signal at the second initialization signal terminal Vint2 is provided to the second terminal of the driving transistor DTFT and the second terminal of the first capacitor C1 via the turned-on eighth switch transistor T8.

[0142] 7 , 12 and 13 , the pixel driving circuit further includes a second light emitting control sub-circuit 50 .

[0143] The second light emitting control subcircuit 50 is coupled to the first terminal of the driving transistor DTFT and the first power supply terminal ELVDD, and is configured to provide the signal of the first power supply terminal ELVDD to the first terminal of the driving transistor DTFT in response to the light emitting control signal of the second light emitting control signal terminal EM2(n).

[0144] During implementation, when the light control signal of the second light control signal terminal EM2(n) is valid, the second light control sub-circuit 50 is turned on, and the signal of the first power supply terminal ELVDD is provided to the first terminal of the driving transistor DTFT through the turned-on second light control sub-circuit 50.

[0145] 7 and 13 , the second light emitting control sub-circuit 50 includes a ninth switch transistor T9 .

[0146] A control terminal of the ninth switch transistor T9 is coupled to the second light emitting control signal terminal EM2(n), a first terminal of the ninth switch transistor T9 is coupled to the first power supply terminal ELVDD, and a second terminal of the ninth switch transistor T9 is coupled to the first terminal of the driving transistor DTFT.

[0147] Exemplarily, the ninth switch transistor T9 can be turned on under the control of the active level of the second light-emitting control signal terminal EM2(n), and can be turned off under the control of the inactive level of the second light-emitting control signal terminal EM2(n). Exemplarily, if the ninth switch transistor T9 is configured as an N-type transistor, the active level of the signal at the second light-emitting control signal terminal EM2(n) is a high level, and the inactive level of the signal at the second light-emitting control signal terminal EM2(n) is a low level. Alternatively, if the ninth switch transistor T9 is configured as a P-type transistor, the active level of the signal at the second light-emitting control signal terminal EM2(n) is a low level, and the inactive level of the signal at the second light-emitting control signal terminal EM2(n) is a high level.

[0148] 7 and 13 , the ninth switch transistor T9 is an N-type transistor. When the signal at the second light-emitting control signal terminal EM2(n) is at a high level, the ninth switch transistor T9 is turned on, and the signal at the first power supply terminal ELVDD is provided to the first terminal of the driving transistor DTFT via the turned-on ninth switch transistor T9.

[0149] In addition, as shown in FIG. 14 , the pixel driving circuit further includes a tenth switching transistor T10. The tenth switching transistor T10 is configured primarily to initialize the second terminal of the driving transistor DTFT. A control terminal of the tenth switching transistor T10 is coupled to the first reset control terminal GI(n), a first terminal of the tenth switching transistor T10 is coupled to the second terminal of the driving transistor DTFT, and a second terminal of the tenth switching transistor T10 is coupled to the third initialization signal terminal Vint3.

[0150] 14 , the tenth switch transistor T10 is an N-type transistor. During implementation, when the signal at the first reset control terminal GI(n) is at a high level, the tenth switch transistor T10 is turned on, and the signal at the third initialization signal terminal Vint3 is provided to the second terminal of the driving transistor DTFT via the turned-on tenth switch transistor T10, thereby resetting the second terminal of the driving transistor DTFT.

[0151] In addition, it should be noted that Vref1 2 3 Vint1 3 can all be the same signal terminal.

[0152] The working process of the pixel driving circuit in the embodiment of the present application is described in detail below in conjunction with Figure 14 and the timing diagram 15.

[0153] Timing stage T1: EM1(n) = 1, EM2(n) = 0, GC(n) = 1, GI(n) = 1, GW(n) = 0

[0154] When the signal at the first scan control terminal GC(n) is at a high level, the first switching transistor T1 and the fourth switching transistor T4 are both turned on. The signal at the first reference signal terminal Vref1 is provided to the control terminal of the driving transistor DTFT and the first terminal of the second capacitor C2 via the turned-on first switching transistor T1, thereby initializing the first node N1. Simultaneously, the signal at the third reference signal terminal Vref3 is provided to the second terminal of the first capacitor C1 via the turned-on fourth switching transistor T4, thereby initializing the third node N3. When the signal at the first reset control terminal GI(n) is at a high level, the sixth switching transistor T6 and the tenth switching transistor T10 are turned on. When the signal at the first light-emitting control signal terminal EM1(n) is at a high level, the fifth switching transistor T5 is turned on, thereby resetting the anode of the light-emitting device OLED and the second terminal of the driving transistor DTFT, respectively.

[0155] Timing T2 stage: EM1(n) = 0, EM2(n) = 1, GC(n) = 1, GI(n) = 1, GW(n) = 0

[0156] When the signal at the first scan control terminal GC(n) is high, the first switching transistor T1 and the fourth switching transistor T4 are both turned on. The signal at the first reference signal terminal Vref1 is provided to the control terminal of the driving transistor DTFT and the first terminal of the first capacitor C1 via the turned-on first switching transistor T1, thereby initializing the first node N1. Simultaneously, the signal at the third reference signal terminal Vref3 is provided to the second terminal of the first capacitor C1 via the turned-on fourth switching transistor T4, thereby initializing the third node N3. When the signal at the first reset control terminal GI(n) is high, the sixth switching transistor T6 is turned on. When the signal at the second emission control signal terminal EM2(n) is high, the ninth switching transistor T9 is turned on, and the first power supply terminal ELVDD is provided to the first terminal of the driving transistor DTFT via the turned-on ninth switching transistor T9, thereby increasing the voltage at the second node N2 until the voltage at the second node N2 equals Vref1-Vth, completing the threshold voltage compensation of the driving transistor DTFT. It should be noted that to ensure that the compensation is complete and the driving transistor DTFT is turned off, it is necessary to meet Vref1-ELVDD. <Vth。

[0157] Timing stage T3: EM1(n) = 0, EM2(n) = 0, GC(n) = 0, GI(n) = 1, GW(n) = 1

[0158] When the signal of the second scan control terminal GW(n) is at a high level, the second switching transistor T2 and the third switching transistor T3 are both turned on, and the signal of the second reference signal terminal Vref2 is provided to the first node N1 via the turned-on second switching transistor T1, that is, VN1=Vref1, and the signal of the data signal terminal Vdata is provided to the third node N3 via the turned-on third switching transistor T3, that is, VN3=Vdata. In this case, the voltage of the second node N2 is VN2=Vref1-Vth+C2*(Vdata-Vint2) / (C1+C2).

[0159] Timing stage T4: EM1(n) = 1, EM2(n) = 1, GC(n) = 0, GI(n) = 0, GW(n) = 0

[0160] When the signal at the first light-emitting control signal terminal EM1(n) is at a high level, the fifth switch transistor T5 is turned on. When the signal at the second light-emitting control signal terminal EM2(n) is at a high level, the ninth switch transistor T9 is turned on. A circuit connecting the first power supply terminal ELVDD, the ninth switch transistor T9, the drive transistor DTFT, the fifth switch transistor T5, and the light-emitting device OLED is electrically connected. After the circuit is electrically connected, the voltage at the anode of the light-emitting device OLED gradually increases until stable light emission occurs. At this point, the anode voltage is Voled. Ideally, the voltage changes across the two plates of the first capacitor C1 are equal, so Vgs remains unchanged. VN1=Vref1, VN2=Vref1-Vth+C2*(Vdata-Vint2) / (C1+C2), Vgs=VN1-VN2=Vref1-[Vref1-Vth+C2(Vdata-Vinit2) / (C1+C2)]=C2(Vdata-Vinit2) / (C1+C2)+Vth, so the current flowing through the light-emitting device OLED is I=k(Vgs-Vth) 2 =k(Vdata-(Vref-Vth)-Vth) 2 =k[C2(Vdata-Vinit2) / (C1+C2] 2

[0161] In at least one embodiment of the pixel driving circuit shown in FIG. 16 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0162] When at least one embodiment of the pixel driving circuit shown in Figure 16 is in operation, the capacitance between the control terminal of the driving transistor DTFT and the second terminal of the driving transistor DTFT is a first capacitor C1. The capacitance of C1 is relatively high, and the charge retention capability between the control terminal of the driving transistor DTFT and the second terminal of the driving transistor DTFT is better, thereby avoiding large fluctuations in the control terminal voltage of the driving transistor DTFT caused by changes in the anode voltage of the light-emitting device OLED when charging the anode of the light-emitting device OLED during the light-emitting stage.

[0163] In at least one embodiment of the pixel driving circuit shown in FIG16 , the first end of the fourth switch transistor T4 can be connected to the fifth reference signal end Vref5 , the second initialization signal end Vint2 , the first power end ELVDD or the second power end ELVSS, but is not limited thereto.

[0164] As shown in FIG17 , when at least one embodiment of the pixel driving circuit of FIG16 of the present invention is in operation, a display cycle may include a refresh frame TS, and the refresh frame TS may include an initialization phase S1, a compensation phase S2, a data writing phase S3, and a light emitting phase S4, which are sequentially arranged.

[0165] In the initialization phase S1, the second light-emitting control signal terminal EM2(k) provides a low voltage signal, the second reset control terminal GI2(k) provides a high voltage signal, the first scan control terminal GIL1(k) provides a high voltage signal, the second scan control terminal GC(k) provides a low voltage signal, and the data control terminal GW(k) provides a low voltage signal. The eighth switch transistor T8 is turned on to output the signal provided by the second initialization signal terminal Vint2 to the anode of the light-emitting device OLED to clear the residual charge on the anode of the light-emitting device OLED. The first switch transistor T1 and the fourth switch transistor T4 are both turned on, the signal provided by the fourth reference signal terminal Vref4 is written to the fourth node N4, and the signal provided by the sixth reference signal terminal Vref6 is output to the fifth node N5, so that the driving transistor DTFT can be turned on when the compensation phase S2 begins.

[0166] In the compensation phase S2, the second light-emitting control signal terminal EM(k) provides a low voltage signal, the second reset control terminal GI2(k) provides a high voltage signal, the first scan control terminal GIL1(k) provides a low voltage signal, the second scan control terminal GC(k) provides a high voltage signal, the data control terminal GW(k) provides a low voltage signal, the eighth switch transistor T8 is turned on, and the signal provided by the second initialization signal terminal Vint2 is output to the anode of the light-emitting device OLED; the second switch transistor T2 and the third switch transistor T3 are turned on, the fourth node N4 is connected to the seventh node N7, and the signal provided by the sixth reference signal terminal Vref6 is output to the fifth node N5;

[0167] At the beginning of the compensation phase S2, the driving transistor DTFT is turned on, changing the potential of the fourth node N4 until the potential of the fourth node N4 becomes Vref6+Vth, and the driving transistor DTFT is turned off to perform threshold voltage compensation; wherein Vth is the threshold voltage of the driving transistor DTFT;

[0168] In the data writing phase S3, the second light emitting control signal terminal EM(k) provides a low voltage signal, the second reset control terminal GI2(k) provides a high voltage signal, the first scan control terminal GIL1(k) provides a low voltage signal, the second scan control terminal GC(k) provides a low voltage signal, the data control terminal GW(k) provides a high voltage signal, the eighth switch transistor T8 is turned on, and the signal provided by the second initialization signal terminal Vint2 is output to the anode of the light emitting device OLED to clear the residual charge on the anode of the light emitting device OLED; the seventh switch transistor T7 is turned on, and the data sending terminal Data(k) provides the data voltage Vdata to the fifth node N5;

[0169] In the light-emitting stage S4, the second light-emitting control signal terminal EM2(k) provides a high voltage signal, the second reset control terminal GI2(k) provides a low voltage signal, the first scan control terminal GIL1(k) provides a low voltage signal, the second scan control terminal GC(k) provides a low voltage signal, the data control terminal GW(k) provides a low voltage signal, the ninth switching transistor T9 is turned on, and the driving transistor DTFT drives the light-emitting device OLED to emit light.

[0170] As shown in FIG17 , when at least one embodiment of the pixel driving circuit shown in FIG16 of the present invention is in operation, a display period may include at least one hold frame TK provided after the refresh frame TS;

[0171] The holding frame TK may include a holding setting phase SK1 and a holding light emitting phase SK2 which are arranged successively;

[0172] In the hold setting phase SK1, the second light emitting control signal terminal EM(k), the second scan control terminal GC(k), the first scan control terminal GIL1(k), and the data control terminal GW(k) all provide low voltage signals, the second reset control terminal GI2(k) provides a high voltage signal, the eighth switch transistor T8 is turned on, and the second initialization signal terminal Vint2 provides a signal to the anode of the light emitting device OLED to clear the residual charge on the anode of the light emitting device OLED;

[0173] In the light-maintaining stage SK2, the second light-emitting control signal terminal EM2(k) provides a high voltage signal, the second scan control terminal GC(k), the first scan control terminal GIL1(k), the data control terminal GW(k) and the second reset control terminal GI2(k) all provide low voltage signals, the ninth switching transistor T9 is turned on, and the driving transistor DTFT drives the light-emitting device OLED to emit light.

[0174] When at least one embodiment of the pixel driving circuit shown in FIG16 of the present invention is in operation, during the hold setting stage included in the hold frame, the potential of the anode of the light-emitting device OLED is initialized at high frequency through the eighth switching transistor T8, thereby improving the flicker phenomenon caused by inconsistent luminous brightness after the driving frequency changes.

[0175] The difference between at least one embodiment of the pixel driving circuit shown in FIG. 18 of the present invention and at least one embodiment of the pixel driving circuit shown in FIG. 16 of the present invention is that:

[0176] The second end of the third switch transistor T3 is electrically connected to the second end of the driving transistor DTFT.

[0177] As shown in FIG19 , based on at least one embodiment of the pixel driving circuit shown in FIG18 , the driving circuit includes a driving transistor DTFT, the first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a third capacitor C3, compensation control of the circuit is implemented by the second switch transistor T2, initialization of the fourth node N4 is implemented by the first switch transistor T1, initialization of the fifth node N5 is implemented by the fourth switch transistor T4, and voltage stabilization of the circuit is implemented by the seventh switch transistor T7; the light-emitting element is a light-emitting device OLED;

[0178] The control terminal of the driving transistor DTFT is electrically connected to the fourth node N4, the first terminal of the driving transistor DTFT is electrically connected to the seventh node N7, and the second terminal of the driving transistor DTFT is electrically connected to the anode of the light-emitting device OLED through the sixth node N6;

[0179] A first end of the third capacitor C3 is electrically connected to the fourth node N4, and a second end of the third capacitor C3 is electrically connected to the fifth node N5;

[0180] A first end of the first capacitor C1 is electrically connected to a fifth node N5, and a second end of the first capacitor C1 is electrically connected to a sixth node N6;

[0181] The control terminal of the first switch transistor T1 is electrically connected to the first scan control terminal GIL1(k), the first terminal of the first switch transistor T1 is electrically connected to the fourth reference signal terminal Vref4, and the second terminal of the first switch transistor T1 is electrically connected to the fourth node N4; the fourth reference signal terminal Vref4 is used to provide a reference voltage Vref4;

[0182] The control end of the second switch transistor T2 is electrically connected to the second scan control end GC(k), the first end of the second switch transistor T2 is electrically connected to the fourth node N4, and the second end of the second switch transistor T2 is electrically connected to the seventh node N7;

[0183] The control end of the third switch transistor T3 is electrically connected to the second scan control end GC(k), the first end of the third switch transistor T3 is electrically connected to the fifth reference signal end Vref5, and the second end of the third switch transistor T3 is electrically connected to the fifth node N5;

[0184] The control terminal of the fourth switch transistor T4 is electrically connected to the first scan control terminal GIL1(k), the first terminal of the fourth switch transistor T4 is electrically connected to the sixth reference signal terminal Vref6, and the second terminal of the fourth switch transistor T4 is electrically connected to the fifth node N5;

[0185] The data writing circuit includes a seventh switch transistor T7;

[0186] The control end of the seventh switch transistor T7 is electrically connected to the data control end GW(k), the first end of the seventh switch transistor T7 is electrically connected to the data sending end Data(k), and the second end of the seventh switch transistor T7 is electrically connected to the fifth node N5;

[0187] The second reset sub-circuit includes an eighth switch transistor T8;

[0188] The control terminal of the eighth switch transistor T8 is electrically connected to the second reset control terminal GI2(k), the first terminal of the eighth switch transistor T8 is electrically connected to the second initialization signal terminal Vint2, the second terminal of the eighth switch transistor T8 is electrically connected to the anode of the light-emitting device OLED; and the cathode of the light-emitting device OLED is electrically connected to the second power supply terminal ELVSS;

[0189] The second light emitting control subcircuit includes a ninth switch transistor T9;

[0190] The control end of the ninth switch transistor T9 is electrically connected to the second light emitting control signal end EM2(k), the first end of the ninth switch transistor T9 is electrically connected to the first power supply end ELVDD, and the second end of the ninth switch transistor T9 is electrically connected to the seventh node N7.

[0191] In at least one embodiment of the pixel driving circuit shown in FIG. 19 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0192] As shown in FIG20 , when at least one embodiment of the pixel driving circuit shown in FIG19 of the present invention is in operation, a display cycle may include a refresh frame TS, and the refresh frame TS may include an initialization phase S1, a compensation phase S2, a data writing phase S3, and a light emitting phase S4, which are sequentially arranged;

[0193] In the initialization phase S1, the second light-emitting control signal terminal EM2(k) provides a low voltage signal, the second reset control terminal GI2(k) provides a high voltage signal, the first scan control terminal GIL1(k) provides a high voltage signal, the second scan control terminal GC(k) provides a low voltage signal, and the data control terminal GW(k) provides a low voltage signal. As shown in FIG21 , the eighth switch transistor T8 is turned on, and the signal provided by the second initialization signal terminal Vint2 is output to the anode of the light-emitting device OLED to clear the residual charge on the anode of the light-emitting device OLED. The first switch transistor T1 and the fourth switch transistor T4 are turned on, the fourth reference signal terminal Vref4 provides a reference voltage to the fourth node N4, and the signal provided by the sixth reference signal terminal Vref6 is output to the fifth node N5, so that the driving transistor DTFT can be turned on when the compensation phase S2 begins.

[0194] In the compensation phase S2, the second light-emitting control signal terminal EM2(k) provides a low voltage signal, the second reset control terminal GI2(k) provides a high voltage signal, the first scan control terminal GIL1(k) provides a low voltage signal, the second scan control terminal GC(k) provides a high voltage signal, and the data control terminal GW(k) provides a low voltage signal. As shown in FIG22 , the eighth switch transistor T8 is turned on, the second initialization signal terminal Vint2 provides a signal to the anode of the light-emitting device OLED to clear the residual charge on the anode of the light-emitting device OLED. The second switch transistor T2 and the third switch transistor T3 are turned on, the fourth node N4 is connected to the seventh node N7, and the signal provided by the fifth reference signal terminal Vref5 is output to the fifth node N5.

[0195] At the beginning of the compensation phase S2, the driving transistor DTFT is turned on, changing the potential of the fourth node N4 until the potential of the fourth node N4 becomes Vref5+Vth, and the driving transistor DTFT is turned off to perform threshold voltage compensation; wherein Vth is the threshold voltage of the driving transistor DTFT;

[0196] In the data writing phase S3, the second light emitting control signal terminal EM2(k) provides a low voltage signal, the second reset control terminal GI2(k) provides a high voltage signal, the first scan control terminal GIL1(k) provides a low voltage signal, the second scan control terminal GC(k) provides a low voltage signal, and the data control terminal GW(k) provides a high voltage signal. As shown in FIG23 , the eighth switch transistor T8 is turned on, and the signal provided by the second initialization signal terminal Vint2 is output to the anode of the light emitting device OLED to clear the residual charge on the anode of the light emitting device OLED. The seventh switch transistor T7 is turned on, and the data sending terminal Data(k) provides the data voltage Vdata to the fifth node N5.

[0197] In the light-emitting stage S4, the second light-emitting control signal terminal EM2(k) provides a high voltage signal, and the second reset control terminal GI2(k), the first scan control terminal GIL1(k), the second scan control terminal GC(k) and the data control terminal GW(k) all pass through low voltage signals. As shown in Figure 24, the ninth switching transistor T9 is turned on, and the driving transistor DTFT drives the light-emitting device OLED to emit light.

[0198] When at least one embodiment of the pixel driving circuit shown in FIG. 20 of the present invention is in operation, a display period may include at least one hold frame TK arranged after the refresh frame;

[0199] The holding frame TK may include a holding setting phase SK1 and a holding light emitting phase SK2 which are arranged successively;

[0200] In the hold setting phase SK1, the second light emitting control signal terminal EM2(k), the second scan control terminal GC(k), the first scan control terminal GIL1(k), and the data control terminal GW(k) all provide low voltage signals, the second reset control terminal GI2(k) provides a high voltage signal, the eighth switch transistor T8 is turned on, and the signal provided by the second initialization signal terminal Vint2 is output to the anode of the light emitting device OLED to clear the residual charge on the anode of the light emitting device OLED;

[0201] In the light-maintaining stage SK2, the second light-emitting control signal terminal EM2(k) provides a high voltage signal, the second scan control terminal GC(k), the first scan control terminal GIL1(k), the data control terminal GW(k) and the second reset control terminal GI2(k) all provide low voltage signals, the ninth switching transistor T9 is turned on, and the driving transistor DTFT drives the light-emitting device OLED to emit light.

[0202] When at least one embodiment of the pixel driving circuit shown in Figure 20 of the present invention is in operation, during the hold setting stage included in the hold frame, the potential of the anode of the light-emitting device OLED is initialized at high frequency through the eighth switching transistor T8, which can improve the flicker phenomenon caused by inconsistent light brightness after the driving frequency changes.

[0203] The difference between at least one embodiment of the pixel driving circuit shown in FIG25 and at least one embodiment of the pixel driving circuit shown in FIG19 is that:

[0204] A first terminal of the fourth switch transistor T4 is electrically connected to the fourth node N4.

[0205] The difference between at least one embodiment of the pixel driving circuit shown in FIG26 and at least one embodiment of the pixel driving circuit shown in FIG19 is that:

[0206] A first end of the fourth switch transistor T4 is electrically connected to the first reference signal end Vref1 , ie, the first end of the first switch transistor T1 , and a second end of the first switch transistor T1 is electrically connected to the fourth node N4 .

[0207] The difference between at least one embodiment of the pixel driving circuit shown in FIG27 and at least one embodiment of the pixel driving circuit shown in FIG16 is that:

[0208] A first terminal of the fourth switch transistor T4 is electrically connected to the fourth node N4.

[0209] The difference between at least one embodiment of the pixel driving circuit shown in FIG28 and at least one embodiment of the pixel driving circuit shown in FIG16 is that:

[0210] A first end of the first switch transistor T1 is electrically connected to a second end of the seventh switch transistor T7 .

[0211] Based on the same inventive concept, an embodiment of the present disclosure provides a display substrate comprising multiple rows and columns of pixel driving circuits such as any one of the above.

[0212] In at least one embodiment of the present invention, the at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal GIL1(k), and the at least two rows of pixel driving circuits are electrically connected to the same second scan control terminal GC(k).

[0213] In a specific implementation, the at least two rows of pixel driving circuits can be electrically connected to the same first scan control terminal GIL1(k), and the at least two rows of pixel driving circuits can be electrically connected to the same second scan control terminal GC(k), so as to reduce the number of GOA circuits generating scan signals located in the border area and reduce the area of ​​the border area.

[0214] In at least one embodiment of the present invention, the at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal GIL1(k), the at least two rows of pixel driving circuits are electrically connected to the same second scan control terminal GC(k), the at least two rows of pixel driving circuits are electrically connected to the same second reset control terminal GI2(k), and the at least two rows of pixel driving circuits are electrically connected to the same second light-emitting control signal terminal EM2(k).

[0215] In a specific implementation, the at least two rows of pixel driving circuits can be electrically connected to the same first scan control terminal GIL1(k), the at least two rows of pixel driving circuits can be electrically connected to the same second scan control terminal GC(k), the at least two rows of pixel driving circuits can be electrically connected to the same second reset control terminal GI2(k), and the at least two rows of pixel driving circuits can be electrically connected to the same second light-emitting control signal terminal EM2(k), so as to reduce the number of GOA circuits generating scan signals located in the border area and reduce the area of ​​the border area.

[0216] In at least one embodiment of the present invention, the at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same second scanning control terminal GC(k), and the at least two rows of pixel driving circuits are electrically connected to the same second light emitting control signal terminal EM2(k).

[0217] In a specific implementation, the at least two rows of pixel driving circuits can be electrically connected to the same second scan control terminal GC(k), and the at least two rows of pixel driving circuits can be electrically connected to the same second light-emitting control signal terminal EM2(k), so as to reduce the number of GOA circuits generating scan signals located in the border area and reduce the area of ​​the border area.

[0218] In at least one embodiment of the present invention, the at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal GIL1(k), and the at least two rows of pixel driving circuits are electrically connected to the same second light emitting control signal terminal EM2(k).

[0219] In a specific implementation, the at least two rows of pixel driving circuits can be electrically connected to the same first scan control terminal GIL1(k), and the at least two rows of pixel driving circuits can be electrically connected to the same second light-emitting control signal terminal EM2(k), so as to reduce the number of GOA circuits generating scan signals located in the border area and reduce the area of ​​the border area.

[0220] In at least one embodiment of the present invention, the at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal GIL1(k), the at least two rows of pixel driving circuits are electrically connected to the same second scan control terminal GC(k), and the at least two rows of pixel driving circuits are electrically connected to the same second light-emitting control signal terminal EM2(k).

[0221] In at least one embodiment of the present invention, the display substrate includes at least two rows of pixel driving circuits electrically connected to the same first scan control terminal GIL1(k), at least two rows of pixel driving circuits electrically connected to the same second scan control terminal GC(k), and at least two rows of pixel driving circuits electrically connected to the same second light-emitting control signal terminal EM2(k).

[0222] In a specific implementation, the at least two rows of pixel driving circuits can be electrically connected to the same first scan control terminal GIL1(k), the at least two rows of pixel driving circuits can be electrically connected to the same second scan control terminal GC(k), and the at least two rows of pixel driving circuits can be electrically connected to the same second light-emitting control signal terminal EM2(k), so as to reduce the number of GOA circuits generating scan signals located in the border area and reduce the area of ​​the border area.

[0223] As shown in FIG29 , the pixel driving circuit located in the kth row may include a first light-emitting device OLED1, a first first switching transistor T11, a first second switching transistor T21, a first third switching transistor T31, a first fourth switching transistor T41, a first seventh switching transistor T71, a first eighth switching transistor T81, a first ninth switching transistor T91, a first driving transistor DTFT1, a first first capacitor C11, and a first third capacitor C31; k is a positive integer;

[0224] A control terminal of the first driving transistor DTFT1 is electrically connected to the first fourth node N41, a first terminal of DTFT1 is electrically connected to the first seventh node N71, a second terminal of DTFT1 is electrically connected to the anode of the light emitting device OLED1 via the first sixth node N61; and a cathode of the light emitting device OLED1 is electrically connected to the second power supply terminal ELVSS1.

[0225] A first end of the first capacitor C11 is electrically connected to the first fifth node N51, and a second end of the first capacitor C11 is electrically connected to the first sixth node N61;

[0226] A first end of the third capacitor C31 is electrically connected to the first fourth node N41, and a second end of the third capacitor C31 is electrically connected to the first fifth node N51;

[0227] a control terminal of the first switch transistor T11 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the first switch transistor T11 electrically connected to the fourth reference signal terminal Vref41, and a second terminal of the first switch transistor T11 electrically connected to the first fourth node N41; the fourth reference signal terminal Vref41 is used to provide a fourth reference signal Vref4;

[0228] a control terminal of the second switch transistor T21 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the second switch transistor T21 electrically connected to the first fourth node N41, and a second terminal of the second switch transistor T21 electrically connected to the first seventh node N71;

[0229] a control terminal of the third switch transistor T31 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the third switch transistor T31 electrically connected to the fifth reference signal terminal Vref51, and a second terminal of the third switch transistor T31 electrically connected to the first fifth node N51;

[0230] a control terminal of the fourth switch transistor T41 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the fourth switch transistor T41 electrically connected to the sixth reference signal terminal Vref61, and a second terminal of the fourth switch transistor T41 electrically connected to the first fifth node N51;

[0231] a control terminal of the seventh switch transistor T71 electrically connected to the k-th row data control terminal GW1(k), a first terminal of the seventh switch transistor T71 electrically connected to the data transmitting terminal Data1(k), and a second terminal of the seventh switch transistor T71 electrically connected to the first fifth node N51;

[0232] A control terminal of the eighth switch transistor T81 is electrically connected to the second reset control terminal GI2(k) of the kth row, a second terminal of the eighth switch transistor T81 is electrically connected to the second initialization signal terminal Vint21, a first terminal of the eighth switch transistor T81 is electrically connected to the anode of the light-emitting device OLED1; and a cathode of the light-emitting device OLED1 is electrically connected to the second power supply terminal ELVSS1.

[0233] The control end of the ninth switch transistor T91 is electrically connected to the second light emitting control signal end EM2(k) of the kth row, the first end of the ninth switch transistor T91 is electrically connected to the first power supply end ELVDD1, and the second end of the ninth switch transistor T91 is electrically connected to the first seventh node N71.

[0234] The pixel driving circuit located in the k+1th row may include a second light-emitting device OLED2, a second first switching transistor T12, a second second switching transistor T22, a second third switching transistor T32, a second fourth switching transistor T42, a second seventh switching transistor T72, a second eighth switching transistor T82, a second ninth switching transistor T92, a second driving transistor DTFT2, a second first capacitor C12, and a second third capacitor C32;

[0235] A control terminal of the second driving transistor DTFT2 is electrically connected to the second fourth node N42, a first terminal of the second driving transistor DTFT2 is electrically connected to the second seventh node N72, a second terminal of the second driving transistor DTFT2 is electrically connected to the anode of the light-emitting device OLED2 via the second sixth node N62; and a cathode of the light-emitting device OLED2 is electrically connected to the second power supply terminal ELVSS2.

[0236] A first end of the first capacitor C12 is electrically connected to the second fifth node N52, and a second end of the first capacitor C12 is electrically connected to the second sixth node N62;

[0237] A first end of the third capacitor C32 is electrically connected to the second fourth node N42, and a second end of the third capacitor C32 is electrically connected to the second fifth node N52;

[0238] a control terminal of the first switch transistor T12 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the first switch transistor T12 electrically connected to the fourth reference signal terminal Vref42, and a second terminal of the first switch transistor T12 electrically connected to the second fourth node N42; the fourth reference signal terminal Vref42 is used to provide a reference voltage Vref42;

[0239] a control terminal of the second switch transistor T22 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the second switch transistor T22 electrically connected to the second fourth node N42, and a second terminal of the second switch transistor T22 electrically connected to the second seventh node N72;

[0240] a control terminal of the third switch transistor T32 electrically connected to the second scan control terminal GC1(k) of the kth row, a second terminal of the third switch transistor T32 electrically connected to the fifth reference signal terminal Vref52, and a first terminal of the third switch transistor T32 electrically connected to the second fifth node N52;

[0241] a control terminal of the fourth switch transistor T42 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the fourth switch transistor T42 electrically connected to the sixth reference signal terminal Vref62, and a second terminal of the fourth switch transistor T42 electrically connected to the second fifth node N52;

[0242] a control terminal of the seventh switch transistor T72 electrically connected to the data control terminal GW2(k) of the k+1th row, a first terminal of the seventh switch transistor T72 electrically connected to the data transmitting terminal Data2(k), and a second terminal of the seventh switch transistor T72 electrically connected to the second fifth node N52;

[0243] a control terminal of the eighth switch transistor T82 electrically connected to the second reset control terminal GI22(k) of the k+1th row, a second terminal of the eighth switch transistor T82 electrically connected to the second initialization signal terminal Vint22, and a second terminal of the eighth switch transistor T82 electrically connected to the anode of the light-emitting device OLED2;

[0244] The control end of the ninth switch transistor T92 is electrically connected to the second light-emitting control signal end EM2(k+1) of the k+1th row, the first end of the ninth switch transistor T92 is electrically connected to the first power supply end ELVDD2, and the second end of the ninth switch transistor T92 is electrically connected to the second seventh node N72.

[0245] In at least one embodiment shown in FIG. 29 , the pixel driving circuit located in the kth row and the pixel driving circuit located in the k+1th row can share GC1(k) and GIL1(k), so as to reduce the number of GOA circuits used in the border area, thereby reducing the area of ​​the border area.

[0246] FIG. 30 is an operation timing diagram of at least one embodiment shown in FIG. 29 .

[0247] In FIG30 , the phase labeled S1-k is the kth initialization phase, the phase labeled S2-k is the kth compensation phase, the phase labeled S3-k is the kth data writing phase, and the phase labeled S4-k is the kth light emitting phase;

[0248] The phase labeled S1-k+1 is the k+1th initialization phase, the phase labeled S2-k+1 is the k+1th compensation phase, the phase labeled S3-k+1 is the k+1th data writing phase, and the phase labeled S4-k+1 is the k+1th light-emitting phase.

[0249] S1-k and S1-k+1 are in the same time period, and S2-k and S2-k+1 are in the same time period.

[0250] As shown in FIG31 , the pixel driving circuit located in the kth row may include a first light-emitting device OLED1, a first first switching transistor T11, a first second switching transistor T21, a first third switching transistor T31, a first fourth switching transistor T41, a first seventh switching transistor T71, a first eighth switching transistor T81, a first ninth switching transistor T91, a first driving transistor DTFT1, a first first capacitor C11, and a first third capacitor C31;

[0251] A control terminal of the first driving transistor DTFT1 is electrically connected to the first fourth node N41, a first terminal of the first driving transistor DTFT1 is electrically connected to the first seventh node N71, a second terminal of the first driving transistor DTFT1 is electrically connected to the anode of the light emitting device OLED1 via the first sixth node N61; and a cathode of the light emitting device OLED1 is electrically connected to the second power supply terminal ELVSS1.

[0252] A first end of the first capacitor C11 is electrically connected to the first fifth node N51, and a second end of the first capacitor C11 is electrically connected to the first sixth node N61;

[0253] A first end of the third capacitor C31 is electrically connected to the first fourth node N41, and a second end of the third capacitor C31 is electrically connected to the first fifth node N51;

[0254] a control terminal of the first switch transistor T11 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the first switch transistor T11 electrically connected to the fourth reference signal terminal Vref41, and a second terminal of the first switch transistor T11 electrically connected to the first fourth node N41; the fourth reference signal terminal Vref41 is used to provide a reference voltage Vref41;

[0255] a control terminal of the second switch transistor T21 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the second switch transistor T21 electrically connected to the first fourth node N41, and a second terminal of the second switch transistor T21 electrically connected to the first seventh node N71;

[0256] a control terminal of the third switch transistor T31 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the third switch transistor T31 electrically connected to the fifth reference signal terminal Vref51, and a second terminal of the third switch transistor T31 electrically connected to the first fifth node N51;

[0257] a control terminal of the fourth switch transistor T41 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the fourth switch transistor T41 electrically connected to the sixth reference signal terminal Vref61, and a second terminal of the fourth switch transistor T41 electrically connected to the first fifth node N51;

[0258] a control terminal of the seventh switch transistor T71 electrically connected to the k-th row data control terminal GW1(k), a first terminal of the seventh switch transistor T71 electrically connected to the data transmitting terminal Data1(k), and a second terminal of the seventh switch transistor T71 electrically connected to the first fifth node N51;

[0259] A control terminal of the eighth switch transistor T81 is electrically connected to the second reset control terminal GI2(k) of the kth row, a second terminal of the eighth switch transistor T81 is electrically connected to the second initialization signal terminal Vint21, a first terminal of the eighth switch transistor T81 is electrically connected to the anode of the light-emitting device OLED1; and a cathode of the light-emitting device OLED1 is electrically connected to the second power supply terminal ELVSS1.

[0260] A control terminal of the ninth switch transistor T91 is electrically connected to the second light emitting control signal terminal EM2(k), a first terminal of the ninth switch transistor T91 is electrically connected to the first power supply terminal ELVDD1, and a second terminal of the ninth switch transistor T91 is electrically connected to the first seventh node N71.

[0261] The pixel driving circuit located in the k+1th row may include a second light-emitting device OLED2, a second first switching transistor T12, a second second switching transistor T22, a second third switching transistor T32, a second fourth switching transistor T42, a second seventh switching transistor T72, a second eighth switching transistor T82, a second ninth switching transistor T92, a second driving transistor DTFT2, a second first capacitor C12, and a second third capacitor C32;

[0262] A control terminal of the second driving transistor DTFT2 is electrically connected to the second fourth node N42, a first terminal of the second driving transistor DTFT2 is electrically connected to the second seventh node N72, a second terminal of the second driving transistor DTFT2 is electrically connected to the anode of the light-emitting device OLED2 via the second sixth node N62; and a cathode of the light-emitting device OLED2 is electrically connected to the second power supply terminal ELVSS2.

[0263] A first end of the first capacitor C12 is electrically connected to the second fifth node N52, and a second end of the first capacitor C12 is electrically connected to the second sixth node N62;

[0264] A first end of the third capacitor C32 is electrically connected to the second fourth node N42, and a second end of the third capacitor C32 is electrically connected to the second fifth node N52;

[0265] a control terminal of the first switch transistor T12 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the first switch transistor T12 electrically connected to the fourth reference signal terminal Vref42, and a second terminal of the first switch transistor T12 electrically connected to the second fourth node N42; the fourth reference signal terminal Vref42 is used to provide a reference voltage Vref42;

[0266] a control terminal of the second switch transistor T22 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the second switch transistor T22 electrically connected to the second fourth node N42, and a second terminal of the second switch transistor T22 electrically connected to the second seventh node N72;

[0267] a control terminal of the third switch transistor T32 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the third switch transistor T32 electrically connected to the fifth reference signal terminal Vref52, and a second terminal of the third switch transistor T32 electrically connected to the second fifth node N52;

[0268] a control terminal of the fourth switch transistor T42 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the fourth switch transistor T42 electrically connected to the sixth reference signal terminal Vref62, and a second terminal of the fourth switch transistor T42 electrically connected to the second fifth node N52;

[0269] a control terminal of the seventh switch transistor T72 electrically connected to the data control terminal GW2(k) of the k+1th row, a first terminal of the seventh switch transistor T72 electrically connected to the data transmitting terminal Data2(k), and a second terminal of the seventh switch transistor T72 electrically connected to the second fifth node N52;

[0270] a control terminal of the eighth transistor T82 electrically connected to the second reset control terminal GI22(k) of the kth row, a second terminal of the eighth transistor T82 electrically connected to the second initialization signal terminal Vint22, and a second terminal of the eighth transistor T82 electrically connected to the anode of the light-emitting device OLED2;

[0271] The control end of the ninth transistor T92 is electrically connected to the second light emitting control signal end EM2(k) of the kth row, the first end of the ninth transistor T92 is electrically connected to the first power end ELVDD2, and the second end of the ninth transistor T92 is electrically connected to the second seventh node N72.

[0272] In at least one embodiment shown in FIG31 , the pixel driving circuit located in the kth row and the pixel driving circuit located in the k+1th row can share GC1(k), GIL1(k), GI2(k) and EM2(k), so as to reduce the number of GOA circuits used in the border area, thereby reducing the area of ​​the border area.

[0273] FIG. 32 is an operation timing diagram of at least one embodiment shown in FIG. 31 .

[0274] In FIG32 , the phase labeled S1-k is the kth initialization phase, the phase labeled S2-k is the kth compensation phase, the phase labeled S3-k is the kth data writing phase, and the phase labeled S4-k is the kth light emitting phase;

[0275] The phase labeled S1-k+1 is the k+1th initialization phase, the phase labeled S2-k+1 is the k+1th compensation phase, the phase labeled S3-k+1 is the k+1th data writing phase, and the phase labeled S4-k+1 is the k+1th light-emitting phase.

[0276] S1-k and S1-k+1 are in the same time period, S2-k and S2-k+1 are in the same time period, and S4-k and S4-k+1 are in the same time period.

[0277] In at least one embodiment of the present disclosure, the display substrate includes a first display area and a second display area, and the refresh rate of the first display area is different from the refresh rate of the second display area; the pixel driving circuit is electrically connected to the first scan control terminal GIL1(k), the second scan control terminal GC1(k), the data control terminal Data1(k), the second reset control terminal GI2(k), and the second light-emitting control signal terminal EM2(k), respectively;

[0278] The pixel driving circuit of the kth row included in the display substrate is adjacent to the pixel driving circuit of the k+1th row included in the display substrate;

[0279] The pixel driving circuit of the kth row is arranged in the first display area, and the pixel driving circuit of the k+1th row is arranged in the second display area; k is a positive integer;

[0280] The display substrate includes a first GOA module, a second GOA module, a third GOA module, a fourth GOA module and a light emitting control signal generating module;

[0281] The first GOA module includes a multi-stage first GOA circuit, the second GOA module includes a multi-stage second GOA circuit, the third GOA module includes a multi-stage third GOA circuit, the fourth GOA module includes a multi-stage fourth GOA circuit, and the light control signal generation module includes a multi-stage light control signal generation circuit;

[0282] The first GOA module is used to provide a signal of the second scan control terminal GC1(k), the second GOA module is used to provide a signal of the first scan control terminal GIL1(k), the third GOA module is used to provide a signal of the data control terminal Data1(k), the fourth GOA module is used to provide a signal of the second reset control terminal GI2(k), and the light control signal generation module is used to provide a signal of the second light control signal terminal EM2(k);

[0283] The k-th first GOA circuit included in the first GOA module and the k+1-th first GOA circuit included in the first GOA module are not cascaded, the k-th second GOA circuit included in the second GOA module and the k+1-th second GOA circuit included in the second GOA module are not cascaded, and the k-th third GOA circuit included in the third GOA module and the k+1-th third GOA circuit included in the third GOA module are not cascaded.

[0284] Optionally, the kth level fourth GOA circuit included in the fourth GOA module is cascaded with the k+1th level fourth GOA circuit included in the fourth GOA module, and the kth level light-emitting control signal generating circuit included in the light-emitting control signal generating module is cascaded with the k+1th level light-emitting control signal generating circuit included in the light-emitting control signal generating module.

[0285] In at least one embodiment of the present disclosure, the k-th level first GOA circuit is used to provide a signal of the second scan control terminal GC1(k) for the k-th row pixel driving circuit, and the k+1-th level first GOA circuit is used to provide a signal of the second scan control terminal GC1(k) for the k+1-th row pixel driving circuit;

[0286] The k-th level second GOA circuit is used to provide the k-th row pixel driving circuit with the signal of the first scanning control terminal GIL1(k), and the k+1-th level second GOA circuit is used to provide the k+1-th row pixel driving circuit with the signal of the first scanning control terminal GIL1(k);

[0287] The k-th level third GOA circuit is used to provide a signal of the data control terminal Data1(k) for the k-th row pixel driving circuit, and the k+1-th level third GOA circuit is used to provide a signal of the data control terminal Data1(k) for the k+1-th row pixel driving circuit;

[0288] The k-th level fourth GOA circuit is used to provide a signal of the second reset control terminal GI2(k) for the k-th row pixel driving circuit, and the k+1-th level fourth GOA circuit is used to provide a signal of the second reset control terminal GI2(k) for the k+1-th row pixel driving circuit;

[0289] The kth level light emitting control signal generating circuit is used to provide a light emitting control signal for the kth row pixel driving circuit, and the k+1th level light emitting control signal generating circuit is used to provide a signal of the second light emitting control signal terminal EM2(k) for the k+1th row pixel driving circuit.

[0290] As shown in FIG33 , the pixel driving circuit located in the kth row may include a first light-emitting device OLED1, a first first switching transistor T11, a first second switching transistor T21, a first third switching transistor T31, a first fourth switching transistor T41, a first seventh switching transistor T71, a first eighth switching transistor T81, a first ninth switching transistor T91, a first driving transistor DTFT1, a first first capacitor C11, and a first third capacitor C31;

[0291] A control terminal of the first driving transistor DTFT1 is electrically connected to the first fourth node N41, a first terminal of DTFT1 is electrically connected to the first seventh node N71, a second terminal of the first driving transistor DTFT1 is electrically connected to the anode of the light emitting device OLED1 via the first sixth node N61; and a cathode of the light emitting device OLED1 is electrically connected to the second power supply terminal ELVSS1.

[0292] A first end of the first capacitor C11 is electrically connected to the first fifth node N51, and a second end of the first capacitor C11 is electrically connected to the first sixth node N61;

[0293] A first end of the third capacitor C31 is electrically connected to the first fourth node N41, and a second end of the third capacitor C31 is electrically connected to the first fifth node N51;

[0294] a control terminal of the first switch transistor T11 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the first switch transistor T11 electrically connected to the fourth reference signal terminal Vref41, and a second terminal of the first switch transistor T11 electrically connected to the first fourth node N41; the fourth reference signal terminal Vref41 is used to provide a reference voltage Vref41;

[0295] a control terminal of the second switch transistor T21 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the second switch transistor T21 electrically connected to the first fourth node N41, and a second terminal of the second switch transistor T21 electrically connected to the first seventh node N71;

[0296] a control terminal of the third switch transistor T31 electrically connected to the second scan control terminal GC1(k) of the kth row, a first terminal of the third switch transistor T31 electrically connected to the fifth reference signal terminal Vref51, and a second terminal of the third switch transistor T31 electrically connected to the first fifth node N51;

[0297] a control terminal of the fourth switch transistor T41 electrically connected to the first scan control terminal GIL1(k) of the kth row, a first terminal of the fourth switch transistor T41 electrically connected to the sixth reference signal terminal Vref61, and a second terminal of the fourth switch transistor T41 electrically connected to the first fifth node N51;

[0298] a control terminal of the seventh switch transistor T71 electrically connected to the k-th row data control terminal GW1(k), a first terminal of the seventh switch transistor T71 electrically connected to the data transmitting terminal Data1(k), and a second terminal of the seventh switch transistor T71 electrically connected to the first fifth node N51;

[0299] A control terminal of the eighth switch transistor T81 is electrically connected to the second reset control terminal GI2(k) of the kth row, a second terminal of the eighth switch transistor T81 is electrically connected to the second initialization signal terminal Vint21, a first terminal of the eighth switch transistor T81 is electrically connected to the anode of the light-emitting device OLED1; and a cathode of the light-emitting device OLED1 is electrically connected to the second power supply terminal ELVSS1.

[0300] A control terminal of the ninth switch transistor T91 is electrically connected to the second light emitting control signal terminal EM2(k), a first terminal of the ninth switch transistor T91 is electrically connected to the first power supply terminal ELVDD1, and a second terminal of the ninth switch transistor T91 is electrically connected to the first seventh node N71.

[0301] The pixel driving circuit located in the k+1th row may include a second light-emitting device OLED2, a second first switching transistor T12, a second second switching transistor T22, a second third switching transistor T32, a second fourth switching transistor T42, a second seventh switching transistor T72, a second eighth switching transistor T82, a second ninth switching transistor T92, a second driving transistor DTFT2, a second first capacitor C12, and a second third capacitor C32;

[0302] A control terminal of the second driving transistor DTFT2 is electrically connected to the second fourth node N42, a first terminal of the second driving transistor DTFT2 is electrically connected to the second seventh node N72, a second terminal of the second driving transistor DTFT2 is electrically connected to the anode of the light-emitting device OLED2 via the second sixth node N62; and a cathode of the light-emitting device OLED2 is electrically connected to the second power supply terminal ELVSS2.

[0303] A first end of the first capacitor C12 is electrically connected to the second fifth node N52, and a second end of the first capacitor C12 is electrically connected to the second sixth node N62;

[0304] A first end of the third capacitor C32 is electrically connected to the second fourth node N42, and a second end of the third capacitor C32 is electrically connected to the second fifth node N52;

[0305] A control terminal of the first switch transistor T12 is electrically connected to the first scan control terminal GIL1(k) of the k+1th row, a first terminal of the first switch transistor T12 is electrically connected to the fourth reference signal terminal Vref41, and a second terminal of the first switch transistor T12 is electrically connected to the second fourth node N42; the fourth reference signal terminal Vref41 is used to provide a reference voltage Vref41;

[0306] a control end of the second switch transistor T22 electrically connected to the second scan control end GC1(k) of the k+1th row, a first end of the second switch transistor T22 electrically connected to the second fourth node N42, and a second end of the second switch transistor T22 electrically connected to the second seventh node N72;

[0307] a control terminal of the third switch transistor T32 electrically connected to the second scan control terminal GC1(k) of the k+1th row, a first terminal of the third switch transistor T32 electrically connected to the fifth reference signal terminal Vref52, and a second terminal of the third switch transistor T32 electrically connected to the second fifth node N52;

[0308] a control terminal of the fourth switch transistor T42 electrically connected to the first scan control terminal GIL1(k) of the k+1th row, a first terminal of the fourth switch transistor T42 electrically connected to the sixth reference signal terminal Vref62, and a second terminal of the fourth switch transistor T42 electrically connected to the second fifth node N52;

[0309] a control terminal of the seventh switch transistor T72 electrically connected to the data control terminal GW2(k) of the k+1th row, a first terminal of the seventh switch transistor T72 electrically connected to the data transmitting terminal Data1(k+1), and a second terminal of the seventh switch transistor T72 electrically connected to the second fifth node N52;

[0310] a control terminal of the eighth transistor T82 electrically connected to the second reset control terminal GI2(k) of the kth row, a second terminal of the eighth transistor T82 electrically connected to the second initialization signal terminal Vint22, and a second terminal of the eighth transistor T82 electrically connected to the anode of the light-emitting device OLED2;

[0311] a control terminal of the ninth transistor T92 electrically connected to the second light emitting control signal terminal EM2(k) of the kth row, a first terminal of the ninth transistor T92 electrically connected to the first power supply terminal ELVDD1, and a second terminal of the ninth transistor T92 electrically connected to the second seventh node N72;

[0312] k is a positive integer.

[0313] In at least one embodiment shown in FIG33 , the pixel driving circuit of the kth row is located in the first display area A1, and the pixel driving circuit of the k+1th row is located in the second display area A2. The first display area A1 is a high-frequency refresh area, and the second display area A2 is a low-frequency display area.

[0314] FIG34 is a timing diagram of the operation of at least one embodiment shown in FIG33 during a refresh frame;

[0315] FIG35 is a timing diagram illustrating the operation of at least one embodiment shown in FIG33 in a hold frame.

[0316] As shown in FIG36 , the display substrate according to at least one embodiment of the present disclosure includes a first GOA module, a second GOA module, a third GOA module, a fourth GOA module, and a light emitting control signal generating module;

[0317] The first GOA module includes a first-stage first GOA circuit G11, a k-th-stage first GOA circuit Gk1, a k+1-th-stage first GOA circuit Gk+11, and an n-th-stage first GOA circuit Gn1; k is a positive integer, and n is a positive integer greater than k+1;

[0318] The second GOA module includes a first-stage second GOA circuit G12, a k-th-stage second GOA circuit Gk2, a k+1-th-stage second GOA circuit Gk+12, and an n-th-stage second GOA circuit Gn2;

[0319] The third GOA module includes a first-stage third GOA circuit G13, a k-th-stage third GOA circuit Gk3, a k+1-th-stage third GOA circuit Gk+13, and an n-th-stage third GOA circuit Gn3;

[0320] The fourth GOA module includes a first-stage fourth GOA circuit G14, a k-th-stage fourth GOA circuit Gk4, a k+1-th-stage fourth GOA circuit Gk+14, and an n-th-stage fourth GOA circuit Gn4;

[0321] The light emitting control signal generating module includes a first-stage second light emitting control signal generating circuit EM2, a k-th-stage light emitting control signal generating circuit EMk, a k+1-th-stage light emitting control signal generating circuit EMk+1, and an n-th-stage light emitting control signal generating circuit EMn;

[0322] Gk1 is electrically connected to the second scan control terminal GC1(k) and provides the second scan control terminal GC1(k) with a signal of the second scan control terminal GC1(k) of the kth row. Gk+11 is electrically connected to the second scan control terminal GC1(k+1) and provides the second scan control terminal GC1(k+1) with a signal of the second scan control terminal GC1(k+1) of the k+1th row.

[0323] Gk2 is electrically connected to the first scan control terminal GIL1(k) and provides the first scan control terminal GIL1(k) with a signal of the first scan control terminal GIL1(k) of the kth row. Gk+12 is electrically connected to the first scan control terminal GIL1(k+1) and provides the first scan control terminal GIL1(k+1) with a signal of the first scan control terminal GIL1(k+1) of the k+1th row.

[0324] Gk3 is electrically connected to the data control terminal GW1(k) and provides the data control terminal GW1(k) with the signal of the data control terminal GW1(k) of the kth row. Gk+13 is electrically connected to the data control terminal GW1(k+1) and provides the data control terminal GW1(k+1) with the signal of the data control terminal GW1(k+1) of the k+1th row.

[0325] Gk4 is electrically connected to the second reset control terminal GI2(k) and provides the second reset control terminal GI2(k) with the signal of the second reset control terminal GI2(k) of the kth row. Gk+14 is electrically connected to the second reset control terminal GI2(k+1) and provides the second reset control terminal GI22(k) with the signal of the second reset control terminal GI22(k) of the k+1th row.

[0326] EMk is electrically connected to the second light-emitting control signal terminal EM2(k) and provides the light-emitting control signal of the k-th row to the second light-emitting control signal terminal EM2(k); EMk+1 is electrically connected to the second light-emitting control signal terminal EM2(k+1) and provides the light-emitting control signal of the k+1-th row to the second light-emitting control signal terminal EM2(k+1);

[0327] EMk and EMk+1 are cascaded with each other, and Gk4 and Gk+4 are cascaded with each other;

[0328] Gk1 and Gk+11 are not cascaded, Gk2 and Gk+12 are not cascaded, and Gk3 and Gk+13 are not cascaded.

[0329] In at least one embodiment shown in FIG36 , adjacent first GOA circuits from the first-stage first GOA circuit included in the first GOA module to the k-th first GOA circuit included in the first GOA module may be cascaded to each other, and adjacent first GOA circuits from the k+1-th first GOA circuit included in the first GOA module to the n-th first GOA circuit included in the first GOA module may be cascaded to each other.

[0330] The first-stage second GOA circuit included in the second GOA module to the adjacent second GOA circuits in the k-th stage second GOA circuit included in the second GOA module can be cascaded to each other, and the k+1-th stage second GOA circuit included in the second GOA module to the adjacent second GOA circuits in the n-th stage second GOA circuit included in the second GOA module can be cascaded to each other;

[0331] The first-stage third GOA circuit included in the third GOA module to the adjacent third GOA circuits in the k-th stage third GOA circuit included in the third GOA module can be cascaded to each other, and the k+1-th stage third GOA circuit included in the third GOA module to the adjacent third GOA circuits in the n-th stage third GOA circuit included in the third GOA module can be cascaded to each other;

[0332] Adjacent fourth GOA circuits from the first-stage fourth GOA circuit included in the fourth GOA module to the k-th-stage fourth GOA circuit included in the fourth GOA module can be cascaded to each other, and adjacent fourth GOA circuits from the k+1-th-stage fourth GOA circuit included in the fourth GOA module to the n-th-stage fourth GOA circuit included in the fourth GOA module can be cascaded to each other;

[0333] The adjacent light-emitting control signal generating circuits from the first-level light-emitting control signal generating circuit included in the light-emitting control signal generating module to the k-th level light-emitting control signal generating circuit included in the light-emitting control signal generating module can be cascaded with each other, and the adjacent light-emitting control signal generating circuits from the k+1-th level light-emitting control signal generating circuit included in the light-emitting control signal generating module to the n-th level light-emitting control signal generating circuit included in the light-emitting control signal generating module can be cascaded with each other.

[0334] In Figure 36, the signal labeled ESTV is the light-emitting control starting voltage signal, the signal labeled GSTV1 is the first starting voltage signal, the signal labeled GSTV2 is the second starting voltage signal, the signal labeled GSTV3 is the third starting voltage signal, and the signal labeled GSTV4 is the fourth starting voltage signal.

[0335] In at least one embodiment shown in FIG36 , by controlling Gk1 and Gk+11 not to be cascaded, Gk2 and Gk+12 not to be cascaded, and Gk3 and Gk+13 not to be cascaded at the junction of the first display area A1 and the second display area A2, and by disconnecting the cascade relationship between the two-stage driving circuits at the junction of the display areas with different refresh rates of the first GOA module, the second GOA module, and the third GOA module, different refresh rates are achieved in different display areas, thereby saving power consumption.

[0336] As shown in FIG37 , the display substrate includes a first display area A1 and a second display area A2;

[0337] The first display area A1 may be a high-frequency refresh display area, and the second display area A2 may be a low-frequency refresh display area.

[0338] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0339] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

[0340] In summary, in an embodiment of the present disclosure, a pixel driving circuit and a display substrate are provided. The pixel driving circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a driving transistor and a first capacitor. The first end of the first switching transistor and the first end of the second switching transistor are both coupled to the control end of the driving transistor, the first end of the third switching transistor and the first end of the fourth switching transistor are both coupled to the first end of the first capacitor, the second end of the first capacitor is coupled to the second end of the driving transistor, the control end of the first switching transistor and the control end of the fourth switching transistor are both coupled to the first scan control end, the control end of the second switching transistor and the control end of the third switching transistor are both coupled to the second scan control end, and the control end of the first switching transistor and the control end of the fourth switching transistor are connected to the same scan control end, which optimizes the layout and wiring and is conducive to the formation of a narrow frame.

[0341] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0342] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0343] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0344] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0345] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A pixel driving circuit, wherein: include: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a driving transistor, and a first capacitor; The first terminal of the first switch transistor and the first terminal of the second switch transistor are both coupled to the control terminal of the driving transistor; The first end of the third switch transistor and the first end of the fourth switch transistor are both coupled to the first end of the first capacitor, and the second end of the first capacitor is coupled to the second end of the driving transistor; The control end of the first switch transistor and the control end of the fourth switch transistor are both coupled to the first scan control end; The control end of the second switch transistor and the control end of the third switch transistor are both coupled to the second scan control end.

2. The pixel driving circuit according to claim 1, wherein: A second capacitor is further included, wherein a first end of the second capacitor is coupled to the control end of the driving transistor, and a second end of the second capacitor is coupled to the second end of the first capacitor.

3. The pixel driving circuit according to claim 2, wherein: The second end of the first switch transistor is coupled to the first reference signal end, the second end of the second switch transistor is coupled to the second reference signal end, the second end of the third switch transistor is coupled to the data signal end, and the second end of the fourth switch transistor is coupled to the third reference signal end.

4. The pixel driving circuit according to claim 2, wherein: Also included is a first light emitting control subcircuit, the first light emitting control subcircuit being connected between the second terminal of the driving transistor and the anode of the light emitting device; The first light emitting control sub-circuit is configured to connect the second terminal of the driving transistor and the anode of the light emitting device in response to a light emitting control signal at a first light emitting control signal terminal.

5. The pixel driving circuit according to claim 4, wherein: The first light emitting control subcircuit includes: a fifth switching transistor; The control terminal of the fifth switch transistor is coupled to the first light-emitting control signal terminal, the first terminal of the fifth switch transistor is coupled to the second terminal of the driving transistor, and the second terminal of the fifth switch transistor is coupled to the anode of the light-emitting device.

6. The pixel driving circuit according to claim 2, wherein: Also included is a first reset subcircuit coupled to the anode of the light emitting device; The first reset sub-circuit is configured to provide a signal from a first initialization signal terminal to the anode of the light emitting device in response to a signal from a first reset control terminal.

7. The pixel driving circuit according to claim 6, wherein: The first reset sub-circuit includes: a sixth switch transistor; The control terminal of the sixth switch transistor is coupled to the first reset control terminal, the first terminal of the sixth switch transistor is coupled to the anode of the light emitting device, and the second terminal of the sixth switch transistor is coupled to the first initialization signal terminal.

8. The pixel driving circuit according to claim 1, wherein: A third capacitor is further included, wherein a first end of the third capacitor is coupled to the control end of the driving transistor, and a second end of the third capacitor is coupled to the first end of the first capacitor.

9. The pixel driving circuit according to claim 8, wherein: The second end of the first switch transistor is coupled to the fourth reference signal end, the second end of the second switch transistor is coupled to the first end of the driving transistor, the second end of the third switch transistor is coupled to the fifth reference signal end, and the second end of the fourth switch transistor is coupled to the sixth reference signal end.

10. The pixel driving circuit according to claim 8, wherein: Also included is a data writing subcircuit, the data writing subcircuit being coupled to the first end of the first capacitor, the second end of the third capacitor, the first end of the third switch transistor, and the second end of the fourth switch transistor; The data writing sub-circuit is configured to provide the signal of the data sending end to the first end of the first capacitor, the second end of the third capacitor, the first end of the third switching transistor and the second end of the fourth switching transistor in response to the signal of the data control end.

11. The pixel driving circuit according to claim 10, wherein: The data writing sub-circuit includes: a seventh switching transistor; The control end of the seventh switch transistor is coupled to the data control end, the first end of the seventh switch transistor is coupled to the data sending end, and the second end of the seventh switch transistor is coupled to the first end of the first capacitor, the second end of the third capacitor, the first end of the third switch transistor, and the second end of the fourth switch transistor.

12. The pixel driving circuit according to claim 8, wherein: Also comprising a second reset subcircuit, the second reset subcircuit being coupled to the second terminal of the driving transistor and the second terminal of the first capacitor; The second reset sub-circuit is configured to provide a signal from a second initialization signal terminal to the second terminal of the driving transistor and the second terminal of the first capacitor in response to a signal from a second reset control terminal.

13. The pixel driving circuit according to claim 12, wherein: The second reset sub-circuit includes: an eighth switch transistor; The control end of the eighth switch transistor is coupled to the second reset control end, the first end of the eighth switch transistor is coupled to the second end of the driving transistor and the second end of the first capacitor, and the second end of the eighth switch transistor is coupled to the second initialization signal end.

14. The pixel driving circuit according to any one of claims 1 to 13, wherein: Also includes a second light-emitting control subcircuit; The second light emitting control subcircuit is coupled to the first terminal of the driving transistor and the first power supply terminal, and is configured to provide the signal of the first power supply terminal to the first terminal of the driving transistor in response to the light emitting control signal of the second light emitting control signal terminal.

15. The pixel driving circuit according to claim 14, wherein: The second light emitting control subcircuit includes: a ninth switching transistor; The control end of the ninth switch transistor is coupled to the second light emitting control signal end, the first end of the ninth switch transistor is coupled to the first power supply end, and the second end of the ninth switch transistor is coupled to the first end of the driving transistor.

16. A display substrate, wherein: The pixel driving circuit comprises multiple rows and columns according to any one of claims 1 to 15.

17. The display substrate according to claim 16, wherein: At least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal, and the at least two rows of pixel driving circuits are electrically connected to the same second scan control terminal.

18. The display substrate according to claim 16, wherein: The at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal, the at least two rows of pixel driving circuits are electrically connected to the same second scan control terminal, the at least two rows of pixel driving circuits are electrically connected to the same second reset control terminal, and the at least two rows of pixel driving circuits are electrically connected to the same second light-emitting control signal terminal.

19. The display substrate according to claim 16, wherein: At least two rows of pixel driving circuits included in the display substrate are electrically connected to the same second scanning control terminal, and the at least two rows of pixel driving circuits are electrically connected to the same second light emitting control signal terminal.

20. The display substrate according to claim 16, wherein At least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scanning control terminal, and the at least two rows of pixel driving circuits are electrically connected to the same second light emitting control signal terminal.

21. The display substrate according to claim 16, wherein The at least two rows of pixel driving circuits included in the display substrate are electrically connected to the same first scan control terminal, the at least two rows of pixel driving circuits are electrically connected to the same second scan control terminal, and the at least two rows of pixel driving circuits are electrically connected to the same second light emitting control signal terminal.

22. The display substrate according to claim 16, wherein: The display substrate includes a first display area and a second display area, and the refresh rate of the first display area is different from the refresh rate of the second display area; the pixel driving circuit is electrically connected to the first scan control terminal, the second scan control terminal, the data control terminal, the second reset control terminal and the second light emitting control signal terminal respectively; The pixel driving circuit of the kth row included in the display substrate is adjacent to the pixel driving circuit of the k+1th row included in the display substrate; The pixel driving circuit of the kth row is arranged in the first display area, and the pixel driving circuit of the k+1th row is arranged in the second display area; k is a positive integer; The display substrate includes a first GOA module, a second GOA module, a third GOA module, a fourth GOA module and a light emitting control signal generating module; The first GOA module includes a multi-stage first GOA circuit, the second GOA module includes a multi-stage second GOA circuit, the third GOA module includes a multi-stage third GOA circuit, the fourth GOA module includes a multi-stage fourth GOA circuit, and the light control signal generation module includes a multi-stage light control signal generation circuit; The first GOA module is used to provide a signal for the second scan control terminal, the second GOA module is used to provide a signal for the first scan control terminal, the third GOA module is used to provide a signal for the data control terminal, the fourth GOA module is used to provide a signal for the second reset control terminal, and the light control signal generation module is used to provide a light control signal; The k-th first GOA circuit included in the first GOA module and the k+1-th first GOA circuit included in the first GOA module are not cascaded, the k-th second GOA circuit included in the second GOA module and the k+1-th second GOA circuit included in the second GOA module are not cascaded, and the k-th third GOA circuit included in the third GOA module and the k+1-th third GOA circuit included in the third GOA module are not cascaded.

23. The display substrate according to claim 22, wherein: The k-th level fourth GOA circuit included in the fourth GOA module is cascaded with the k+1-th level fourth GOA circuit included in the fourth GOA module, and the k-th level light-emitting control signal generating circuit included in the light-emitting control signal generating module is cascaded with the k+1-th level light-emitting control signal generating circuit included in the light-emitting control signal generating module.

24. The display substrate according to claim 23, wherein: The k-th level first GOA circuit is used to provide a second scanning signal for the k-th row pixel driving circuit, and the k+1-th level first GOA circuit is used to provide a second scanning signal for the k+1-th row pixel driving circuit; The k-th level second GOA circuit is used to provide a first scanning signal for the k-th row pixel driving circuit, and the k+1-th level second GOA circuit is used to provide a first scanning signal for the k+1-th row pixel driving circuit; The k-th level third GOA circuit is used to provide a signal of the data control end for the k-th row pixel driving circuit, and the k+1-th level third GOA circuit is used to provide a signal of the data control end for the k+1-th row pixel driving circuit; The k-th level fourth GOA circuit is used to provide a signal of the second reset control terminal for the k-th row pixel driving circuit, and the k+1-th level fourth GOA circuit is used to provide a signal of the second reset control terminal for the k+1-th row pixel driving circuit; The k-th level light emitting control signal generating circuit is used to provide a second light emitting control signal for the k-th row pixel driving circuit, and the k+1-th level light emitting control signal generating circuit is used to provide a second light emitting control signal for the k+1-th row pixel driving circuit.

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