Error amplifier circuit, error amplifier, switching power supply chip and electronic device

Abstract

The application belongs to the field of electronic circuits and provides an error amplification circuit, an error amplifier, a switching power supply chip and an electronic device. The circuit comprises an input module, an active load module and a transconductance-adjustable output module; the active load module is connected with the input module and the transconductance-adjustable output module respectively. The input module outputs a first current and a second current according to a feedback voltage and a reference voltage. The active load module outputs a third current and a fourth current according to the first current and the second current. The transconductance-adjustable output module outputs an error voltage according to the third current and the fourth current; and also receives a transconductance control signal to adjust the transconductance of the error amplification circuit according to the transconductance control signal. The application expands the applicable range of the input voltage: compared with the limitation in the prior art that "the transconductance-adjustable error amplifier needs to work normally when the input voltage is greater than 600 mV or so", the error amplification circuit proposed in the application can work normally only when the input voltage is greater than zero.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to an error amplifier circuit, an error amplifier, a switching power supply chip, and an electronic device. Background Technology

[0002] In switching power supply chips, a transconductance adjustable error amplifier (EA) is typically used to amplify and output the difference between the feedback voltage VFB of the output voltage VOUT and the reference voltage VREF.

[0003] However, currently, transconductance-adjustable error amplifiers can only work properly when the input voltage (including the feedback voltage VFB and the reference voltage VREF) is relatively large (generally greater than 600mV); when the input voltage is less than 600mV, they cannot work properly. Summary of the Invention

[0004] This application provides an error amplifier circuit, an error amplifier, a switching power supply chip, and an electronic device, which can solve the problem that current transconductance adjustable error amplifiers cannot work properly when the input voltage is low.

[0005] In a first aspect, embodiments of this application provide an error amplifier circuit, including an input module, an active load module, and a transconductance-adjustable output module; the active load module is connected to both the input module and the transconductance-adjustable output module.

[0006] The input module is used to receive feedback voltage and reference voltage, and output a first current and a second current according to the feedback voltage and the reference voltage; the active load module is used to output a third current and a fourth current according to the first current and the second current; the transconductance adjustable output module is used to output an error voltage according to the third current and the fourth current, and is also used to receive a transconductance control signal, and adjust the transconductance of the error amplifier circuit according to the transconductance control signal.

[0007] The input module includes a current source, a first transistor, and a second transistor. The input terminal of the current source receives a power supply voltage. The output terminal of the current source, the source of the first transistor, and the source of the second transistor are connected to a first node. The gate of the first transistor is used to receive a feedback voltage, and the gate of the second transistor is used to receive a reference voltage. The drain of the first transistor and the drain of the second transistor are respectively connected to the active load module.

[0008] The active load module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the source of the third transistor and the source of the fourth transistor are both grounded, the gate of the third transistor and the gate of the fourth transistor receive a first bias voltage, the drain of the third transistor, the source of the fifth transistor and the drain of the first transistor are connected to a second node, the drain of the fourth transistor, the source of the sixth transistor and the drain of the second transistor are connected to a third node, the gate of the fifth transistor and the gate of the sixth transistor receive a second bias voltage, and the drain of the fifth transistor and the drain of the sixth transistor are respectively connected to the transconductance adjustable output module.

[0009] In one possible implementation of the first aspect, the active load module includes a first resistor, a second resistor, a fifth transistor, and a sixth transistor; a first terminal of the first resistor and a first terminal of the second resistor are both grounded; a second terminal of the first resistor, the source of the fifth transistor, and the drain of the first transistor are connected to a second node; a second terminal of the second resistor, the source of the sixth transistor, and the drain of the sixth transistor are connected to a third node; the gates of the fifth transistor and the sixth transistor receive a second bias voltage; and the drains of the fifth transistor and the sixth transistor are respectively connected to the transconductance-adjustable output module.

[0010] In one possible implementation of the first aspect, the transconductance-adjustable output module includes an output unit and a transconductance adjustment unit; the output unit is connected to the active load module and the transconductance adjustment unit, respectively.

[0011] The output unit is used to output an error voltage based on the third current and the fourth current; the transconductance adjustment unit is used to receive a transconductance control signal and adjust the transconductance of the error amplifier circuit according to the transconductance control signal.

[0012] In one possible implementation of the first aspect, the output unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the source of the seventh transistor, the source of the eighth transistor, the source of the ninth transistor, and the source of the eleventh transistor all receive a power supply voltage; the gate of the seventh transistor is connected to the gate of the ninth transistor, the drain of the seventh transistor, and the drain of the fifth transistor, respectively; the gate of the eighth transistor is connected to the gate of the eleventh transistor, the drain of the eighth transistor, the drain of the sixth transistor, and the transconductance adjustment unit, respectively; the drain of the ninth transistor is connected to the drain of the tenth transistor, the gate of the tenth transistor, the gate of the twelfth transistor, and the transconductance adjustment unit, respectively; the drain of the eleventh transistor is connected to the drain of the twelfth transistor and the transconductance adjustment unit, respectively; and the source of the tenth transistor and the source of the twelfth transistor are both grounded.

[0013] In one possible implementation of the first aspect, the transconductance regulation unit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a first switch, a second switch, a third switch, and a fourth switch; the source of the thirteenth transistor and the source of the fifteenth transistor both receive a power supply voltage; the gate of the thirteenth transistor is connected to the gate of the fifteenth transistor and the gate of the eleventh transistor, respectively; the drain of the thirteenth transistor is connected to the first terminal of the second switch; the drain of the fifteenth transistor is connected to the first terminal of the fourth switch; and the second terminal of the second switch is connected to the first terminal of the first switch, the second terminal of the fourth switch, and the first terminal of the third switch, respectively. The first switch is connected to the drain of the eleventh transistor, the second terminal of the first switch is connected to the drain of the fourteenth transistor, the second terminal of the third switch is connected to the drain of the sixteenth transistor, the gate of the fourteenth transistor is connected to the gate of the sixteenth transistor and the gate of the twelfth transistor, and the source of the fourteenth transistor and the source of the sixteenth transistor are both grounded. The control terminal of the first switch is used to receive the first signal in the transconductance control signal, the control terminal of the second switch is used to receive the second signal in the transconductance control signal, the control terminal of the third switch is used to receive the third signal in the transconductance control signal, and the control terminal of the fourth switch is used to receive the fourth signal in the transconductance control signal.

[0014] In one possible implementation of the first aspect, the output unit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, and a twenty-eighth transistor; the sources of the seventeenth transistor, the nineteenth transistor, the twenty-first transistor, and the twenty-fifth transistor all receive a power supply voltage; the gate of the seventeenth transistor is connected to the gate of the twenty-first transistor, the drain of the eighteenth transistor, and the drain of the fifth transistor, respectively; the drain of the seventeenth transistor is connected to the source of the eighteenth transistor; the drain of the twenty-first transistor is connected to the source of the twenty-second transistor; and the gate of the nineteenth transistor is connected to the gate of the twenty-fifth transistor, the drain of the twenty-second transistor, the drain of the sixth transistor, and the drain of the twenty-sixth transistor, respectively. The drain of the 22nd transistor, the drain of the 18th transistor, the gate of the 20th transistor, the gate of the 26th transistor, and the gate of the 27th transistor are all connected to the transconductance adjustment unit. The drain of the 19th transistor is connected to the source of the 20th transistor. The drain of the 25th transistor is connected to the source of the 26th transistor. The gate of the 22nd transistor, the gate of the 18th transistor, the gate of the 20th transistor, the gate of the 26th transistor, and the transconductance adjustment unit all receive a third bias voltage. The drain of the 22nd transistor is connected to the drain of the 23rd transistor, the gate of the 24th transistor, the gate of the 28th transistor, and the transconductance adjustment unit. The gate of the 23rd transistor, the gate of the 27th transistor, and the transconductance adjustment unit all receive a fourth bias voltage. The source of the 23rd transistor is connected to the drain of the 24th transistor. The source of the 27th transistor is connected to the drain of the 28th transistor. The sources of the 24th transistor and the 28th transistor are both grounded.

[0015] In one possible implementation of the first aspect, the transconductance regulation unit includes a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 33rd transistor, a 34th transistor, a 35th transistor, a 36th transistor, a first switch, a second switch, a third switch, and a fourth switch; the sources of the 29th transistor and the 31st transistor both receive a power supply voltage; the gate of the 29th transistor is connected to the gate of the 31st transistor and the gate of the 25th transistor, respectively; the drain of the 29th transistor is connected to the source of the 30th transistor; the drain of the 31st transistor is connected to the source of the 32nd transistor; the gates of the 30th transistor and the 32nd transistor both receive a third bias voltage; the drain of the 30th transistor is connected to the first terminal of the second switch; the drain of the 32nd transistor is connected to the first terminal of the fourth switch; and the second terminal of the second switch is connected to the second terminal of the fourth switch and the first switch, respectively. The first terminal of the switch, the first terminal of the third switch, and the drain of the twenty-sixth transistor are connected. The second terminal of the first switch is connected to the drain of the thirty-third transistor, and the second terminal of the third switch is connected to the drain of the thirty-fourth transistor. The gates of the thirty-third and thirty-fourth transistors both receive a fourth bias voltage. The source of the thirty-third transistor is connected to the drain of the thirty-fifth transistor, and the source of the thirty-fourth transistor is connected to the drain of the thirty-sixth transistor. The gate of the thirty-fifth transistor is connected to the gate of the thirty-sixth transistor and the gate of the twenty-eighth transistor, respectively. The sources of the thirty-fifth and thirty-sixth transistors are both grounded. The control terminal of the first switch is used to receive the first signal in the transconductance control signal, the control terminal of the second switch is used to receive the second signal in the transconductance control signal, the control terminal of the third switch is used to receive the third signal in the transconductance control signal, and the control terminal of the fourth switch is used to receive the fourth signal in the transconductance control signal.

[0016] Secondly, embodiments of this application provide an error amplifier, including the error amplifier circuit described in any one of the first aspects.

[0017] Thirdly, embodiments of this application provide a switching power supply chip, including the error amplifier described in any one of the second aspects.

[0018] Fourthly, embodiments of this application provide an electronic device including the switching power supply chip described in any one of the third aspects.

[0019] The beneficial effects of the embodiments of this application compared with the prior art are:

[0020] This application provides an error amplifier circuit, including an input module, an active load module, and a transconductance-adjustable output module; the active load module is connected to both the input module and the transconductance-adjustable output module.

[0021] The input module receives the feedback voltage VFB and the reference voltage VREF, and outputs a first current and a second current based on these voltages. The active load module outputs a third current and a fourth current based on the first and second currents. The transconductance-adjustable output module outputs an error voltage based on the third and fourth currents, and also receives a transconductance control signal to adjust the transconductance of the error amplifier circuit.

[0022] The input module includes a current source, a first transistor, and a second transistor. The input terminal of the current source receives the power supply voltage. The output terminal of the current source, the source of the first transistor, and the source of the second transistor are connected to the first node A. The gate of the first transistor is used to receive the feedback voltage VFB, and the gate of the second transistor is used to receive the reference voltage VREF. The drain of the first transistor and the drain of the second transistor are respectively connected to the active load module.

[0023] The active load module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The sources of the third and fourth transistors are grounded. The gates of the third and fourth transistors receive a first bias voltage. The drains of the third transistor, the source of the fifth transistor, and the drain of the first transistor are connected to a second node B. The drains of the fourth transistor, the source of the sixth transistor, and the drain of the second transistor are connected to a third node C. The gates of the fifth and sixth transistors receive a second bias voltage. The drains of the fifth and sixth transistors are respectively connected to a transconductance-adjustable output module.

[0024] During the normal operation of the error amplifier circuit, the voltage VB at the second node B is the drain-source voltage Vds3 of the third transistor. To ensure the normal operation of the third transistor, Vds3 should be greater than Vdsat3 (Vdsat3 is the minimum voltage required between the drain and source of the third transistor when it is operating in the saturation region) + 150mV (150mV is the voltage safety margin to ensure the normal operation of the third transistor). The voltage VC at the third node C is the drain-source voltage Vds4 of the fourth transistor. To ensure the normal operation of the fourth transistor, Vds4 should be greater than Vds3. ds4 > Vdsat4 (Vdsat4 is the minimum voltage required between the drain and source when the fourth transistor is operating in the saturation region) + 150mV (150mV is the voltage safety margin to ensure the normal operation of the fourth transistor); the voltage at the first node A is VA = Vds1 (Vds1 is the drain-source voltage of the first transistor) + VB = Vds2 (Vds2 is the drain-source voltage of the second transistor) + VC, then VA should be guaranteed to be > Vds1 + Vdsat3 + 150mV or > Vds2 + Vdsat4 + 150mV. To ensure the normal operation of the first and second transistors, Vds1 should be greater than Vdsat1 (Vdsat1 is the minimum voltage required between the drain and source of the first transistor when it is operating in the saturation region) + 100mV (100mV is the voltage safety margin to ensure the normal operation of the first transistor), and Vds2 should be greater than Vdsat2 (Vdsat2 is the minimum voltage required between the drain and source of the second transistor when it is operating in the saturation region) + 100mV (100mV is the voltage safety margin to ensure the normal operation of the second transistor). Therefore, VA should be greater than Vdsat1 + 100mV + Vdsat3 + 150mV or greater than Vdsat2 + 100mV + Vdsat4 + 150mV. Since VA = VFB + Vgs1 (Vgs1 is the gate-source voltage of the first transistor), VFB = VA - Vgs1. It should be ensured that VFB > Vdsat1 + 100mV + Vdsat3 + 150mV - Vgs1. Under normal circumstances, Vdsat1 = 100mV and Vdsat3 = 150mV, so it should be ensured that VFB > 500mV - Vgs1. Vgs1 > Vth1 (Vth1 is the threshold voltage of the first transistor). Since Vth1 is generally greater than 500mV, 500mV - Vgs1 is less than zero.Similarly: VA = VREF + Vgs2 (where Vgs2 is the gate-source voltage of the second transistor), therefore VREF = VA - Vgs2. VREF should be greater than Vdsat2 + 100mV + Vdsat4 + 150mV - Vgs2. Typically, Vdsat2 = 100mV and Vdsat4 = 150mV, so VREF should be greater than 500mV - Vgs2. Since Vgs2 is greater than Vth2 (where Vth2 is the threshold voltage of the second transistor), and Vth2 is generally greater than 500mV, 500mV - Vgs2 is less than zero. That is, as long as the feedback voltage VFB and the reference voltage VREF (where VFB and VREF are the input voltages of the error amplifier circuit) are greater than zero, the error amplifier circuit can operate normally.

[0025] Therefore, the error amplifier circuit provided in this application expands the applicable range of input voltage: compared with the limitation in the prior art that "the transconductance adjustable error amplifier can only work normally when the input voltage is greater than about 600mV", the error amplifier circuit proposed in this application can work normally as long as the input voltage is greater than zero.

[0026] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a circuit diagram of an error amplifier circuit provided in an embodiment of this application;

[0029] Figure 2 This is a circuit diagram of an error amplifier circuit provided in another embodiment of this application;

[0030] Figure 3 This is a circuit diagram of an error amplifier circuit provided in another embodiment of this application;

[0031] Figure 4 This is a circuit diagram of an error amplifier circuit provided in another embodiment of this application;

[0032] Figure 5 This is a circuit diagram of an error amplifier circuit provided in another embodiment of this application;

[0033] Figure 6This is a circuit diagram of an error amplifier circuit provided in another embodiment of this application.

[0034] In the diagram: 10, Input module; 20, Active load module; 30, Transconductance adjustable output module; 31, Output unit; 32, Transconductance adjustment unit. Detailed Implementation

[0035] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0036] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0037] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0038] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0039] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0041] To address the problem that current transconductance-adjustable error amplifiers cannot function properly when the input voltage is low (i.e., less than 600mV), this application provides an error amplifier circuit, such as... Figure 1 As shown, the error amplifier circuit includes an input module 10, an active load module 20, and a transconductance-adjustable output module 30; the active load module 20 is connected to the input module 10 and the transconductance-adjustable output module 30, respectively.

[0042] Specifically, input module 10 receives feedback voltage VFB and reference voltage VREF, and outputs a first current and a second current based on VFB and VREF. Active load module 20 outputs a third current and a fourth current based on the first and second currents. Transconductance-adjustable output module 30 outputs an error voltage VEA based on the third and fourth currents, and also receives a transconductance control signal V. GMC And according to the transconductance control signal V GMC Adjust the transconductance of the error amplifier circuit.

[0043] The input module 10 includes a current source, a first transistor M1, and a second transistor M2. The input terminal of the current source receives the power supply voltage VIN. The output terminal of the current source, the source of the first transistor M1, and the source of the second transistor M2 are connected to the first node A. The gate of the first transistor M1 is used to receive the feedback voltage VFB, and the gate of the second transistor M2 is used to receive the reference voltage VREF. The drain of the first transistor M1 and the drain of the second transistor M2 are respectively connected to the active load module 20.

[0044] The active load module 20 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The source of the third transistor M3 and the source of the fourth transistor M4 are both grounded. The gate of the third transistor M3 and the gate of the fourth transistor M4 receive a first bias voltage Vbias1. The drain of the third transistor M3, the source of the fifth transistor M5, and the drain of the first transistor M1 are connected to the second node B. The drain of the fourth transistor M4, the source of the sixth transistor M6, and the drain of the second transistor M2 are connected to the third node C. The gate of the fifth transistor M5 and the gate of the sixth transistor M6 receive a second bias voltage Vbias2. The drain of the fifth transistor M5 and the drain of the sixth transistor M6 are respectively connected to the transconductance adjustable output module 30.

[0045] During the normal operation of the error amplifier circuit, the voltage VB at the second node B is the drain-source voltage Vds3 of the third transistor M3. To ensure the normal operation of the third transistor M3, Vds3 should be greater than Vdsat3 (Vdsat3 is the minimum voltage required between the drain and source of the third transistor M3 when it is operating in the saturation region) + 150mV (150mV is a voltage safety margin to ensure the normal operation of the third transistor; it should be noted that this voltage safety margin can be adjusted according to the actual application. In this application, this voltage safety margin is set to 150mV). The voltage VC at the third node C is the drain-source voltage Vds4 of the fourth transistor M4. To ensure the normal operation of the fourth transistor M4, Vds3 should be greater than Vdsat3 (Vdsat3 is the minimum voltage required between the drain and source of the third transistor M3 when it is operating in the saturation region) + 150mV (150mV is a voltage safety margin to ensure the normal operation of the third transistor; it should be noted that this voltage safety margin can be adjusted according to the actual application. In this application, this voltage safety margin is set to 150mV). To ensure that Vds4 > Vdsat4 (Vdsat4 is the minimum voltage required between the drain and source of the fourth transistor M4 when it is operating in the saturation region) + 150mV (150mV is a voltage safety margin to ensure the normal operation of the fourth transistor; it should be noted that this voltage safety margin can be adjusted according to the actual application. In this application, this voltage safety margin is set to 150mV); the voltage at the first node A is VA = Vds1 (Vds1 is the drain-source voltage of the first transistor M1) + VB = Vds2 (Vds2 is the drain-source voltage of the second transistor M2) + VC. Therefore, VA should be guaranteed to be > Vds1 + Vdsat3 + 150mV or > Vds2 + Vdsat4 + 150mV. To ensure the normal operation of the first transistor M1 and the second transistor M2, Vds1 should be greater than Vdsat1 (Vdsat1 is the minimum voltage required between the drain and source of the first transistor M1 when it is operating in the saturation region) + 100mV (100mV is a voltage safety margin to ensure the normal operation of the first transistor M1; it should be noted that this voltage safety margin can be adjusted according to the actual application. In this application, this voltage safety margin is set to 100mV), and Vds2 should be greater than Vdsat2 ...100mV is the minimum voltage required between the drain and source of the first transistor M1 when it is operating in the saturation region). 2 is the minimum voltage required between the drain and source of the second transistor M2 when it is operating in the saturation region) +100mV (100mV is the voltage safety margin to ensure the normal operation of the second transistor M2. It should be noted that this voltage safety margin can be adjusted according to the actual application. In this application, the voltage safety margin is set to 100mV). Then, it should be ensured that VA > Vdsat1 + 100mV + Vdsat3 + 150mV or > Vdsat2 + 100mV + Vdsat4 + 150mV.Since VA = VFB + Vgs1 (Vgs1 is the gate-source voltage of the first transistor M1), VFB = VA - Vgs1. It should be ensured that VFB > Vdsat1 + 100mV + Vdsat3 + 150mV - Vgs1. Under normal circumstances, Vdsat1 = 100mV and Vdsat3 = 150mV, so it should be ensured that VFB > 500mV - Vgs1. Vgs1 > Vth1 (Vth1 is the threshold voltage of the first transistor M1). Since Vth1 is generally greater than 500mV, 500mV - Vgs1 is less than zero. Similarly: VA = VREF + Vgs2 (Vgs2 is the gate-source voltage of the second transistor M2), therefore VREF = VA - Vgs2. VREF should be greater than Vdsat2 + 100mV + Vdsat4 + 150mV - Vgs2. Typically, Vdsat2 = 100mV and Vdsat4 = 150mV, so VREF should be greater than 500mV - Vgs2. Vgs2 > Vth2 (Vth2 is the threshold voltage of the second transistor M2). Since Vth2 is generally greater than 500mV, 500mV - Vgs2 is less than zero. That is, as long as the feedback voltage VFB and the reference voltage VREF (the feedback voltage VFB and the reference voltage VREF are the input voltages of the error amplifier circuit) are greater than zero, the error amplifier circuit can operate normally.

[0046] Therefore, the error amplifier circuit provided in this application expands the applicable range of input voltage: compared with the limitation in the prior art that "the transconductance adjustable error amplifier can only work normally when the input voltage is greater than about 600mV", the error amplifier circuit proposed in this application can work normally as long as the input voltage is greater than zero.

[0047] like Figure 2 As shown, the active load module 20 includes a first resistor R1, a second resistor R2, a fifth transistor M5, and a sixth transistor M6. The first terminals of the first resistor R1 and the second resistor R2 are both grounded. The second terminal of the first resistor R1, the source of the fifth transistor M5, and the drain of the first transistor M1 are connected to the second node B. The second terminal of the second resistor R2, the source of the sixth transistor M6, and the drain of the second transistor M2 are connected to the third node C. The gates of the fifth transistor M5 and the sixth transistor M6 receive a second bias voltage Vbias2. The drains of the fifth transistor M5 and the sixth transistor M6 are respectively connected to the transconductance-adjustable output module 30. Specifically, to expand the applicable range of the input voltage, the third transistor M3 and the fourth transistor M4 in the active load module 20 can be replaced by the first resistor R1 and the second resistor R2 to serve as the load for the first transistor M1 and the second transistor M2.

[0048] like Figure 2As shown, the transconductance adjustable output module 30 includes an output unit 31 and a transconductance adjustment unit 32; the output unit 31 is connected to the active load module 20 and the transconductance adjustment unit 32 respectively.

[0049] Specifically, output unit 31 is used to output error voltage VEA based on the third current and the fourth current; transconductance adjustment unit 32 is used to receive transconductance control signal V GMC And according to the transconductance control signal V GMC Adjust the transconductance of the error amplifier circuit.

[0050] like Figure 3 As shown, the output unit 31 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The sources of the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the eleventh transistor M11 all receive the power supply voltage VIN. The gate of the seventh transistor M7 is connected to the gate of the ninth transistor M9, the drain of the seventh transistor M7, and the drain of the fifth transistor M5, respectively. The gate of the eighth transistor M8... The drain of transistor M9 is connected to the gate of the eleventh transistor M11, the drain of the eighth transistor M8, the drain of the sixth transistor M6, and the transconductance adjustment unit 32, respectively. The drain of transistor M9 is connected to the drain of the tenth transistor M10, the gate of the tenth transistor M10, the gate of the twelfth transistor M12, and the transconductance adjustment unit 32, respectively. The drain of transistor M11 is connected to the drain of the twelfth transistor M12 and the transconductance adjustment unit 32, respectively. The sources of transistors M10 and M12 are both grounded. It should be noted that... Figure 3 The structure of the front-end module of the output unit 31 shown: the active load module 20 can be as follows Figure 3 The structure shown can also be as follows: Figure 6 The structure shown.

[0051] Specifically, the differential current output by the active load module 20, namely the third current and the fourth current, is mirrored to the eleventh transistor M11 and the twelfth transistor M12 through the seventh transistor M7 and the eighth transistor M8, respectively, to form a single-ended output.

[0052] like Figure 3As shown, the transconductance adjustment unit 32 includes a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The sources of both the thirteenth transistor M13 and the fifteenth transistor M15 receive the power supply voltage VIN. The gate of the thirteenth transistor M13 is connected to the gates of the fifteenth transistor M15 and the eleventh transistor M11, respectively. The drain of the thirteenth transistor M13 is connected to the first terminal of the second switch S2, and the drain of the fifteenth transistor M15 is connected to the first terminal of the fourth switch S4. The second terminal of the second switch S2 is connected to the first terminal of the first switch S1, the second terminal of the fourth switch S4, the first terminal of the third switch S3, and the drain of the eleventh transistor M11. The second terminal of the first switch S1 is connected to the drain of the fourteenth transistor M14. The second terminal of the third switch S3 is connected to the drain of the sixteenth transistor M16. The gate of the fourteenth transistor M14 is connected to the gate of the sixteenth transistor M16 and the gate of the twelfth transistor M12. The sources of the fourteenth transistor M14 and the sixteenth transistor M16 are both grounded. The control terminal of the first switch S1 is used to receive the transconductance control signal V. GMC The first signal V1 and the control terminal of the second switch S2 are used to receive the transconductance control signal V. GMC The second signal V2 and the control terminal of the third switch S3 are used to receive the transconductance control signal V. GMC The third signal V3 and the control terminal of the fourth switch S4 are used to receive the transconductance control signal V. GMC The fourth signal V4 in the series.

[0053] Specifically, through the transconductance control signal V GMC The current is adjusted by controlling the switching states of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, thereby adjusting the transconductance of the error amplifier circuit. It should be noted that the number of switches can be set according to the requirements of the transconductance adjustment level and is not limited to the structure shown in this application.

[0054] like Figure 4As shown, the output unit 31 includes the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23, the twenty-fourth transistor M24, the twenty-fifth transistor M25, the twenty-sixth transistor M26, the twenty-seventh transistor M27, and the twenty-eighth transistor M28; the source of the seventeenth transistor M17, the source of the nineteenth transistor M19, the source of the twenty-first transistor M21, and the twenty-fifth transistor M25. The sources of all transistors receive the power supply voltage VIN. The gate of the seventeenth transistor M17 is connected to the gate of the twenty-first transistor M21, the drain of the eighteenth transistor M18, and the drain of the fifth transistor M5. The drain of the seventeenth transistor M17 is connected to the source of the eighteenth transistor M18. The drain of the twenty-first transistor M21 is connected to the source of the twenty-second transistor M22. The gate of the nineteenth transistor M19 is connected to the gate of the twenty-fifth transistor M25, the drain of the twenty-second transistor M20, the drain of the sixth transistor M6, and the drain of the twenty-sixth transistor M21. The drain of transistor M6, the drain of transistor M27, and the transconductance adjustment unit 32 are connected. The drain of transistor M19 is connected to the source of transistor M20. The drain of transistor M25 is connected to the source of transistor M26. The gates of transistor M22, M18, M20, and M26, as well as the transconductance adjustment unit 32, all receive the third bias voltage Vbias3. The drain of transistor M22 is connected to the source of transistor M26. The drain of transistor M23, the gate of transistor M24, the gate of transistor M28, and the transconductance adjustment unit 32 are connected. The gate of transistor M23, the gate of transistor M27, and the transconductance adjustment unit 32 all receive the fourth bias voltage Vbias4. The source of transistor M23 is connected to the drain of transistor M24, the source of transistor M27 is connected to the drain of transistor M28, and the source of transistor M24 and the source of transistor M28 are both grounded.

[0055] Specifically, this application provides another structure for the output unit 31. Figure 3 The seventh transistor M7 can be replaced by a common-source, common-gate structure composed of the seventeenth transistor M17 and the eighteenth transistor M18. Figure 3 The eighth transistor M8 can be replaced by a common-source, common-gate structure composed of the nineteenth transistor M19 and the twentieth transistor M20. Figure 3 The ninth transistor M9 can be replaced by a common-source, common-gate structure composed of the twenty-first transistor M21 and the twenty-second transistor M22. Figure 3The eleventh transistor M11 can be replaced by a common-source, common-gate structure composed of the twenty-fifth transistor M25 and the twenty-sixth transistor M26. Figure 3 The tenth transistor M10 can be replaced by a common-source, common-gate structure composed of the twenty-third transistor M23 and the twenty-fourth transistor M24. Figure 3 The twelfth transistor M12 can be replaced by a common-source, common-gate structure composed of the twenty-seventh transistor M27 and the twenty-eighth transistor M28. Its operating principle is the same as... Figure 3 The same applies, so I won't repeat it here. It should be noted that... Figure 4 The structure of the front-end module of the output unit 31 shown: the active load module 20 can be as follows Figure 4 The structure shown can also be as follows: Figure 5 The structure shown.

[0056] like Figure 4As shown, the transconductance adjustment unit 32 includes a 29th transistor M29, a 30th transistor M30, a 31st transistor M31, a 32nd transistor M32, a 33rd transistor M33, a 34th transistor M34, a 35th transistor M35, a 36th transistor M36, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The sources of both the 29th transistor M29 and the 31st transistor M31 receive a power supply voltage VIN. The gate of the 29th transistor M29 is connected to the gate of the 31st transistor M31 and the gate of the 25th transistor M25. The drain of the 29th transistor M29 is connected to the source of the 30th transistor M30, and the drain of the 31st transistor M31 is connected to the source of the 32nd transistor M32. The gates of both the 30th transistor M30 and the 32nd transistor M32 receive a third bias voltage Vbias3. The drain of the 30th transistor M30 is connected to the first terminal of the second switch S2. The drain of transistor M32 is connected to the first terminal of the fourth switch S4. The second terminal of the second switch S2 is connected to the second terminal of the fourth switch S4, the first terminal of the first switch S1, the first terminal of the third switch S3, and the drain of the 26th transistor M26. The second terminal of the first switch S1 is connected to the drain of the 33rd transistor M33. The second terminal of the third switch S3 is connected to the drain of the 34th transistor M34. The gates of both the 33rd and 34th transistors receive the fourth bias voltage Vbias4. The source of the 33rd transistor M33 is connected to the drain of the 35th transistor M35. The source of the 34th transistor M34 is connected to the drain of the 36th transistor M36. The gate of the 35th transistor M35 is connected to the gate of the 36th transistor M36 and the gate of the 28th transistor M28. The sources of both the 35th and 36th transistors are grounded. The control terminal of the first switch S1 is used to receive the transconductance control signal V. GMC The first signal V1 and the control terminal of the second switch S2 are used to receive the transconductance control signal V. GMC The second signal V2 and the control terminal of the third switch S3 are used to receive the transconductance control signal V. GMC The third signal V3 and the control terminal of the fourth switch S4 are used to receive the transconductance control signal V. GMC The fourth signal V4 in the series.

[0057] Specifically, this application provides another structure for the transconductance adjustment unit 32. Figure 3 The thirteenth transistor M13 can be replaced by a common-source, common-gate structure composed of the twenty-ninth transistor M29 and the thirtieth transistor M30. Figure 3The fifteenth transistor M15 can be replaced by a common-source, common-gate structure composed of the thirty-first transistor M31 and the thirty-second transistor M32. Figure 3 The fourteenth transistor M14 can be replaced by a common-source, common-gate structure composed of the thirty-third transistor M33 and the thirty-fifth transistor M35. Figure 3 The sixteenth transistor M16 can be replaced by a common-source, common-gate structure composed of the thirty-fourth transistor M34 and the thirty-sixth transistor M36. Its operating principle is the same as... Figure 3 The same applies, so I will not repeat it here.

[0058] The following is an example Figure 3 Taking an example, the principles of this application will be explained in detail.

[0059] Without considering the load structure of the first transistor M1 and the second transistor M2, the first transistor M1 and the second transistor M2 require the same Vds (Vds is the gate-source voltage of the transistor) when they are working normally. If we want the error amplifier circuit to have a wider range of applicable input voltages when it is working normally, the operating voltage range of VA needs to be larger. The upper limit of VA is determined by the power supply voltage VIN. The lower the lower limit voltage, the wider the operating voltage range of VA, and thus the wider the applicable range of input voltages.

[0060] In this application, the loads of the first transistor M1 and the second transistor M2 are the third transistor M3 and the fourth transistor M4, respectively. When the third transistor M3 is operating normally, its Vds3 must be greater than Vdsat3 + 150mV. Normally, Vdsat3 = 150mV, therefore Vds3 > 300mV. Similarly, when the fourth transistor M4 is operating normally, its Vds4 must be greater than Vdsat4 + 150mV. Normally, Vdsat4 = 150mV, therefore Vds4 > 300mV, meaning VB and VC should both be greater than 300mV. When the first transistor M1 is operating normally, its Vds1 must be greater than Vdsat1 + 100mV. Normally, Vdsat1 = 100mV, therefore Vds1 > 200mV. Similarly, when the second transistor M2 is working normally, it is necessary to ensure that its Vds2 > Vdsat2 + 100mV. Under normal circumstances, Vdsat2 = 100mV, so Vds2 > 200mV.

[0061] Since VA = VB + Vds1, then VA > 500mV; Vds1 = VA - VB = Vgs1 + VFB - Vdsat3 - 150mV. Based on the above, Vdsat3 = 150mV, therefore Vds1 = Vgs1 + VFB - 300mV. Furthermore, since the threshold voltage Vth1 of the first transistor M1 is generally greater than 500mV, and Vgs1 > Vth1, even when the feedback voltage VFB is very small, Vds1 can still be guaranteed to be greater than 200mV, meeting the voltage requirements for the first transistor M1 to operate normally.

[0062] Since VA = VC + Vds2, then VA > 500mV; Vds2 = VA - VC = Vgs2 + VREF - Vdsat4 - 150mV. Based on the above, Vdsat4 = 150mV, therefore Vds2 = Vgs2 + VREF - 300mV. Furthermore, since the threshold voltage Vth2 of the second transistor M2 is generally greater than 500mV, and Vgs2 > Vth2, even when the reference voltage VREF is very small, Vds2 can still be guaranteed to be greater than 200mV, meeting the voltage requirements for normal operation of the second transistor M2. Therefore, the error amplifier circuit provided in this embodiment can operate normally even when the input voltage is very low.

[0063] To achieve transconductance adjustment, this application mirrors the differential current (i.e., the third and fourth currents output by the active load module 20) to the eleventh transistor M11 and the twelfth transistor M12 through the seventh transistor M7 and the eighth transistor M8, respectively, to form a single-ended output. The transconductance can be adjusted by adjusting the size of the output PMOS and NMOS (i.e., by controlling the size of the output PMOS and NMOS through the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4, and the specific number of switches can be set according to the transconductance adjustment level requirements).

[0064] In summary, the error amplifier circuit provided in this application expands the applicable range of input voltage: compared with the limitation in the prior art that "the transconductance adjustable error amplifier can only work normally when the input voltage is greater than about 600mV", the error amplifier circuit proposed in this application can work normally as long as the input voltage is greater than zero.

[0065] This application also provides an error amplifier, including the error amplification circuit described above. Since the switching power supply chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon further here.

[0066] This application also provides a switching power supply chip, including the error amplifier described above. Since the switching power supply chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0067] This application also provides an electronic device including the aforementioned switching power supply chip. Since the electronic device provided in this application employs all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated upon further here. The electronic device provided in this application can be any electronic device containing the aforementioned switching power supply chip.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0069] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An error amplifier circuit, characterized in that, It includes an input module, an active load module, and a transconductance-adjustable output module; the active load module is connected to both the input module and the transconductance-adjustable output module. The input module is used to receive feedback voltage and reference voltage, and output a first current and a second current according to the feedback voltage and the reference voltage; the active load module is used to output a third current and a fourth current according to the first current and the second current; the transconductance adjustable output module is used to output an error voltage according to the third current and the fourth current, and is also used to receive a transconductance control signal, and adjust the transconductance of the error amplifier circuit according to the transconductance control signal. The input module includes a current source, a first transistor, and a second transistor. The input terminal of the current source receives a power supply voltage. The output terminal of the current source, the source of the first transistor, and the source of the second transistor are connected to a first node. The gate of the first transistor is used to receive a feedback voltage, and the gate of the second transistor is used to receive a reference voltage. The drain of the first transistor and the drain of the second transistor are respectively connected to the active load module. The active load module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the source of the third transistor and the source of the fourth transistor are both grounded, the gate of the third transistor and the gate of the fourth transistor receive a first bias voltage, the drain of the third transistor, the source of the fifth transistor and the drain of the first transistor are connected to a second node, the drain of the fourth transistor, the source of the sixth transistor and the drain of the second transistor are connected to a third node, the gate of the fifth transistor and the gate of the sixth transistor receive a second bias voltage, and the drain of the fifth transistor and the drain of the sixth transistor are respectively connected to the transconductance adjustable output module; The transconductance-adjustable output module includes an output unit and a transconductance adjustment unit; the output unit is connected to the active load module and the transconductance adjustment unit respectively; The output unit is used to output an error voltage based on the third current and the fourth current; the transconductance adjustment unit is used to receive a transconductance control signal and adjust the transconductance of the error amplifier circuit according to the transconductance control signal. The output unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The sources of the seventh transistor, the eighth transistor, the ninth transistor, and the eleventh transistor all receive a power supply voltage. The gate of the seventh transistor is connected to the gate of the ninth transistor, the drain of the seventh transistor, and the drain of the fifth transistor. The gate of the eighth transistor is connected to the gate of the eleventh transistor, the drain of the eighth transistor, the drain of the sixth transistor, and the transconductance adjustment unit. The drain of the ninth transistor is connected to the drain of the tenth transistor, the gate of the tenth transistor, the gate of the twelfth transistor, and the transconductance adjustment unit. The drain of the eleventh transistor is connected to the drain of the twelfth transistor and the transconductance adjustment unit. The sources of the tenth transistor and the twelfth transistor are both grounded.

2. The error amplifier circuit according to claim 1, characterized in that, The transconductance adjustment unit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a first switch, a second switch, a third switch, and a fourth switch. The sources of the thirteenth and fifteenth transistors both receive a power supply voltage. The gate of the thirteenth transistor is connected to the gates of the fifteenth and eleventh transistors, respectively. The drain of the thirteenth transistor is connected to the first terminal of the second switch. The drain of the fifteenth transistor is connected to the first terminal of the fourth switch. The second terminal of the second switch is connected to the first terminal of the first switch, the second terminal of the fourth switch, the first terminal of the third switch, and the eleventh transistor, respectively. The drain of the transistor is connected, the second terminal of the first switch is connected to the drain of the fourteenth transistor, the second terminal of the third switch is connected to the drain of the sixteenth transistor, the gate of the fourteenth transistor is connected to the gate of the sixteenth transistor and the gate of the twelfth transistor, and the source of the fourteenth transistor and the source of the sixteenth transistor are both grounded. The control terminal of the first switch is used to receive the first signal in the transconductance control signal, the control terminal of the second switch is used to receive the second signal in the transconductance control signal, the control terminal of the third switch is used to receive the third signal in the transconductance control signal, and the control terminal of the fourth switch is used to receive the fourth signal in the transconductance control signal.

3. An error amplifier circuit, characterized in that, It includes an input module, an active load module, and a transconductance-adjustable output module; the active load module is connected to both the input module and the transconductance-adjustable output module. The input module is used to receive feedback voltage and reference voltage, and output a first current and a second current according to the feedback voltage and the reference voltage; the active load module is used to output a third current and a fourth current according to the first current and the second current; the transconductance-adjustable output module is used to output an error voltage according to the third current and the fourth current, and is also used to receive a transconductance control signal, and adjust the transconductance of the error amplifier circuit according to the transconductance control signal; wherein, the reference voltage and the feedback voltage are provided by a switching power supply chip; The input module includes a current source, a first transistor, and a second transistor. The input terminal of the current source receives a power supply voltage. The output terminal of the current source, the source of the first transistor, and the source of the second transistor are connected to a first node. The gate of the first transistor is used to receive a feedback voltage, and the gate of the second transistor is used to receive a reference voltage. The drain of the first transistor and the drain of the second transistor are respectively connected to the active load module. The active load module includes a first resistor, a second resistor, a fifth transistor, and a sixth transistor; the first terminal of the first resistor and the first terminal of the second resistor are both grounded; the second terminal of the first resistor, the source of the fifth transistor, and the drain of the first transistor are connected to a second node; the second terminal of the second resistor, the source of the sixth transistor, and the drain of the sixth transistor are connected to a third node; the gates of the fifth transistor and the sixth transistor receive a second bias voltage; and the drains of the fifth transistor and the sixth transistor are respectively connected to the transconductance adjustable output module. The transconductance-adjustable output module includes an output unit and a transconductance adjustment unit; the output unit is connected to the active load module and the transconductance adjustment unit respectively; The output unit is used to output an error voltage based on the third current and the fourth current; the transconductance adjustment unit is used to receive a transconductance control signal and adjust the transconductance of the error amplifier circuit according to the transconductance control signal. The output unit includes transistors seventeen, eighteen, nineteen, twentieth, twenty-first, twenty-second, twenty-third, twenty-fourth, twenty-fifth, twenty-sixth, twenty-seventh, and twenty-eighth. The sources of transistors seventeen, nineteen, twenty-first, and twenty-fifth all receive a power supply voltage. The gate of transistor seventeen is connected to the gate of transistor twenty-first, the drain of transistor eighteen, and the drain of transistor five, respectively. The drain of transistor seventeen is connected to the source of transistor eighteen, and the drain of transistor twenty-first is connected to the source of transistor twenty-second. The gate of transistor nineteen is connected to the gate of transistor twenty-fifth, the drain of transistor twenty-second, the drain of transistor sixth, the drain of transistor twenty-sixth, and the gate of transistor twenty-seventh. The drain of the body transistor is connected to the transconductance adjustment unit. The drain of the nineteenth transistor is connected to the source of the twentieth transistor. The drain of the twenty-fifth transistor is connected to the source of the twenty-sixth transistor. The gates of the twenty-second transistor, the eighteenth transistor, the twentieth transistor, the twenty-sixth transistor, and the transconductance adjustment unit all receive a third bias voltage. The drain of the twenty-second transistor is connected to the drain of the twenty-third transistor, the gate of the twenty-fourth transistor, the gate of the twenty-eighth transistor, and the transconductance adjustment unit. The gates of the twenty-third transistor, the twenty-seventh transistor, and the transconductance adjustment unit all receive a fourth bias voltage. The source of the twenty-third transistor is connected to the drain of the twenty-fourth transistor. The source of the twenty-seventh transistor is connected to the drain of the twenty-eighth transistor. The sources of the twenty-fourth transistor and the twenty-eighth transistor are both grounded.

4. The error amplifier circuit according to claim 3, characterized in that, The transconductance adjustment unit includes a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 33rd transistor, a 34th transistor, a 35th transistor, a 36th transistor, a first switch, a second switch, a third switch, and a fourth switch. The sources of the 29th and 31st transistors both receive a power supply voltage. The gate of the 29th transistor is connected to the gates of the 31st and 25th transistors, respectively. The drain of the 29th transistor is connected to the source of the 30th transistor, and the drain of the 31st transistor is connected to the source of the 32nd transistor. The gates of the 30th and 32nd transistors both receive a third bias voltage. The drain of the 30th transistor is connected to the first terminal of the second switch, and the drain of the 32nd transistor is connected to the first terminal of the fourth switch. The second terminal of the second switch is connected to the second terminal of the fourth switch, the first terminal of the first switch, and the fourth switch. The first terminal of the third switch is connected to the drain of the twenty-sixth transistor, the second terminal of the first switch is connected to the drain of the thirty-third transistor, the second terminal of the third switch is connected to the drain of the thirty-fourth transistor, the gates of the thirty-third and thirty-fourth transistors both receive a fourth bias voltage, the source of the thirty-third transistor is connected to the drain of the thirty-fifth transistor, the source of the thirty-fourth transistor is connected to the drain of the thirty-sixth transistor, the gate of the thirty-fifth transistor is connected to the gate of the thirty-sixth transistor and the gate of the twenty-eighth transistor, respectively, and the sources of the thirty-fifth and thirty-sixth transistors are both grounded. The control terminal of the first switch is used to receive the first signal in the transconductance control signal, the control terminal of the second switch is used to receive the second signal in the transconductance control signal, the control terminal of the third switch is used to receive the third signal in the transconductance control signal, and the control terminal of the fourth switch is used to receive the fourth signal in the transconductance control signal.

5. An error amplifier, characterized in that, Includes the error amplifier circuit as described in any one of claims 1-4.

6. A switching power supply chip, characterized in that, Includes the error amplifier as described in claim 5.

7. An electronic device, characterized in that, Includes the switching power supply chip as described in claim 6.

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