A high-precision mask alignment back contact cell preparation method and cell thereof

Abstract

The present application belongs to the technical field of back contact cells, and particularly relates to a back contact cell preparation method with high mask alignment precision and a cell thereof, comprising: S103, polishing or secondary texturing treatment is performed on the back surface of a silicon wafer; S104, an intrinsic amorphous silicon layer is deposited on the back surface of the silicon wafer; S105, a hard mask plate is first aligned with a preset first semiconductor region on the back surface of the silicon wafer to form a first semiconductor layer; then the hard mask plate is moved and aligned with a preset second semiconductor region on the back surface of the silicon wafer to form a second semiconductor layer; then a positioning point is formed; S106, a conductive film layer is deposited on the back surface of the silicon wafer; S107, a chemical etching or dry etching technology is used to accurately position between the first semiconductor layer and the second semiconductor layer to form an isolation groove through the positioning point around the silicon wafer; and an etching insulation region is formed at the same time. The present application can improve the mask alignment precision, ensure the insulation effect and passivation effect, and improve the cell conversion efficiency.

Description

Technical Field

[0001] This invention belongs to the field of back contact battery technology, specifically relating to a method for preparing a back contact battery with high-precision mask alignment and the battery thereof. Background Technology

[0002] Existing back-contact solar cells generally undergo the following fabrication processes: S101, double-sided polishing of the silicon wafer; S102, deposition of a first mask layer on the back of the silicon wafer for protection; S103, texturing and cleaning of the silicon wafer, forming a pyramidal textured surface opposite the first mask layer, followed by removal of the first mask layer to form a silicon wafer with a single-sided texturing and single-sided polishing structure; S104, sequential deposition of a first semiconductor layer and a second mask layer on the back of the silicon wafer; S105, using a conventional mask A, laser- or etched openings are made on the back of the silicon wafer to remove the second mask layer and part of the first semiconductor layer, forming a second semiconductor opening region; S106, silicon wafer cleaning to remove the first semiconductor layer within the second semiconductor opening region; S107, sequential formation of a passivation layer and an anti-reflection layer on the front of the silicon wafer, and the back... A second semiconductor layer is formed on the back of the silicon wafer. When the first semiconductor layer is N-type, the second semiconductor layer is P-type, and when the first semiconductor layer is P-type, the second semiconductor layer is N-type. S108. Using a conventional mask B, laser openings or etching openings are made on the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening region that alternates with the second semiconductor opening region. S109. The silicon wafer is cleaned to remove the second mask layer in the first semiconductor opening region. S110. A conductive film layer is deposited on the back of the silicon wafer. S111. Using a conventional mask C, openings are etched on the conductive film layer between the first semiconductor region and the second semiconductor region to form an isolation trench. S112. Metal electrodes are formed outside the first semiconductor region and the second semiconductor region of the silicon wafer.

[0003] However, in the fabrication method of back contact battery, the first semiconductor layer and the second semiconductor layer need to be formed by two etching opening cleaning (i.e., S105 and S108 etching), which is complicated. In addition, after the S105 laser or etching opening on the back of the silicon wafer, removing the second mask layer and part of the first semiconductor layer to form the second semiconductor region opening, passivation defects are easily generated at the edge of the first semiconductor layer, which affects the battery efficiency.

[0004] Furthermore, existing rigid mask back-contact solar cells use different masks for the N / P semiconductor regions (i.e., the first semiconductor layer and the second semiconductor layer). The dimensional and alignment tolerances between these different masks reduce the mask alignment accuracy. Additionally, subsequent N / P insulation trenching to form isolation trenches is typically performed by aligning the silicon wafer edges. However, silicon wafers have significant dimensional tolerances, and this, combined with the tolerances of using different masks for the N / P region, drastically reduces the accuracy of the silicon wafer edge alignment. This affects the insulation effect between the N / P layers and ultimately impacts the cell conversion efficiency.

[0005] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing back contact battery manufacturing processes, such as cumbersome processes and easy passivation defects, as well as poor mask alignment accuracy affecting insulation and thus battery conversion efficiency. This invention provides a high-precision mask alignment back contact battery manufacturing method and battery thereof. This invention can improve mask alignment accuracy while ensuring insulation and passivation effects, thereby improving battery conversion efficiency.

[0007] To achieve the above objectives, in a first aspect, the present invention provides a method for fabricating a back contact battery with high-precision mask alignment, comprising the following steps:

[0008] S101, Provides silicon wafers with double-sided texturing;

[0009] S102. A passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer;

[0010] S103. Polish or perform secondary texturing on the back of the silicon wafer;

[0011] S104. Deposit an intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0012] S105. A rigid mask plate with a plurality of parallel first opening areas is provided, and the non-first opening area portion of the rigid mask plate is provided with hollow positioning points.

[0013] A rigid mask is first aligned with a predetermined first semiconductor region on the back of a silicon wafer to form a first semiconductor layer, and a first positioning layer is formed at the cut-out positioning points. Then, the rigid mask is moved and aligned with a predetermined second semiconductor region on the back of the silicon wafer to form a second semiconductor layer, which is at least partially alternated with the first semiconductor layer, and a second positioning layer is formed at the cut-out positioning points. Next, the first positioning layer and the second positioning layer are laser etched or inkjet printed to form positioning points.

[0014] S106. Deposit a conductive film layer on the back side of the silicon wafer;

[0015] S107. Using chemical etching or dry etching technology, by capturing the positioning points around the silicon wafer, the corresponding conductive film layer is precisely etched between the first semiconductor layer and the second semiconductor layer to form an isolation trench; at the same time, the conductive film layer corresponding to the positioning points around the silicon wafer is etched to form an etched insulating area; the size of the etched insulating area is not less than the size of the corresponding positioning point or the corresponding hollow positioning point.

[0016] S108. Form a metal electrode on the back side of the silicon wafer.

[0017] In some preferred embodiments of the present invention, a reinforcing rib is provided on the rigid mask plate, and the reinforcing rib divides the first opening area into a plurality of opening units along its length direction.

[0018] In some preferred embodiments of the present invention, the opening length W11 of the opening unit is 5-50 mm, and / or the length W12 of the reinforcing rib is 0.05-1 mm.

[0019] In some preferred embodiments of the present invention, the width W1 of the first opening region is 0.2-1 mm, and / or the length of the first opening region is less than the length of the silicon wafer.

[0020] In some preferred embodiments of the present invention, the cutout positioning points are dispersed around the rigid mask plate, and / or there are at least four cutout positioning points.

[0021] In some preferred embodiments of the present invention, the hollow positioning point is located inside the outermost first opening area, and / or the shape of the hollow positioning point is any one of circle, square, cross, triangle, rhombus, or polygon.

[0022] In some preferred embodiments of the present invention, the size R1 of the hollow positioning point is 0.1-1mm, and the size of the etched insulating area is 0.2-1.5mm.

[0023] In some preferred embodiments of the present invention, the size R1 of the hollow positioning point is smaller than the width W1 of the first opening area.

[0024] In some preferred embodiments of the present invention, the spacing width W2 between the first semiconductor layer and the second semiconductor layer is -0.3 mm to 0.3 mm. When W2 is negative, the first semiconductor layer and the second semiconductor layer partially overlap and the width of the overlapping area is the absolute value of W2.

[0025] In some preferred embodiments of the present invention, the method for preparing a back contact battery further includes at least one of the following processes:

[0026] In process 1, S105, the length by which the rigid mask moves is half the distance between the centers of two adjacent first opening areas in the direction perpendicular to the first opening area.

[0027] Process 2: The first semiconductor layer and the second semiconductor layer have the same width, and their width W1 is between 0.2-1mm;

[0028] Process 3: The thickness of the intrinsic amorphous silicon layer is 5-40nm, the thickness of the first semiconductor layer is 3-20nm, and the thickness of the second semiconductor layer is 3-20nm;

[0029] Process 4: Both the first semiconductor layer and the second semiconductor layer are deposited film layers attached to the outside of the intrinsic amorphous silicon layer, or both are partially doped regions of intrinsic amorphous silicon.

[0030] Process 5: The width W3 of the isolation groove is 0.03-0.25mm;

[0031] In process six, S105, both the first semiconductor layer and the second semiconductor layer are formed using deposition technology or ion implantation.

[0032] Process 7: The size of the etched insulating area is 1.05-2 times the size of the corresponding positioning point or the corresponding hollow positioning point.

[0033] In a second aspect, the present invention provides a back contact battery, which is prepared according to the high-precision mask alignment back contact battery preparation method described in the first aspect.

[0034] Beneficial effects:

[0035] In the preparation method of this invention, the first semiconductor layer and the second semiconductor layer are formed by using the above-mentioned technical solution, especially by using the same rigid mask plate with hollow positioning points to mask the same semiconductor layer. After one of the semiconductor layers is formed, it is only necessary to move the mask plate a certain distance in one direction (e.g., the moving length is 1 / 2 of the distance between the centers of two adjacent first opening areas in the direction perpendicular to the first opening area) to complete the alignment. Therefore, it is not necessary to use two rigid mask plates, thereby avoiding the introduction of dimensional and positional differences between the two mask plates and the cumulative tolerance of two positioning operations, and improving the accuracy of the preparation method. Furthermore, the hollowed-out positioning points allow for the formation of positioning points through etching (such as laser etching) or inkjet printing after the formation of the first and second semiconductor layers. This further improves the positioning accuracy in the S107 isolation trench formation step, thereby enhancing the alignment accuracy of the conductive film layer trenching. Simultaneously, etching away the corresponding conductive film layer at the positioning point forms an etched insulating region, ensuring insulation between the first and second semiconductor layers. Thus, while improving mask alignment accuracy, this invention also ensures insulation and passivation effects, thereby improving battery conversion efficiency. The invention further incorporates measures to ensure that the size of the etched insulating region is not smaller than the size of the corresponding positioning point or the corresponding hollowed-out positioning point. This facilitates excellent insulation between the reverse polarity semiconductor layers in the area where the mask hollowed-out positioning point is located, ensuring passivation and improving battery conversion efficiency.

[0036] The applicant further discovered that the opening of the mask plate generally reaches the length of the silicon wafer, which makes the mask plate easily deformable. Therefore, in the preferred embodiment of the present invention, the length direction of the first opening area on the rigid mask plate is divided into multiple opening units by setting reinforcing ribs, which further reduces the impact of the mask plate being easily deformed due to the excessive length of the opening, thereby further improving the alignment accuracy. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic diagram of the structure of a silicon wafer after double-sided texturing is provided for an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the structure of forming a passivation layer and an antireflection layer on the front side of a silicon wafer according to an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the structure of forming a polished surface on the back side of a silicon wafer according to an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of an intrinsic amorphous silicon layer deposited on the back side of a silicon wafer according to an embodiment of the present invention;

[0042] Figure 5 This is a cross-sectional view of the formation of a first semiconductor layer and a second semiconductor layer on the back side of a silicon wafer according to an embodiment of the present invention;

[0043] Figure 6 A schematic diagram of the structure of a mask plate with hollowed-out positioning points in an embodiment of the present invention;

[0044] Figure 7 This is a plan view of an embodiment of the present invention in which a first semiconductor layer is first formed on the back side of a silicon wafer;

[0045] Figure 8 For the embodiments of the present invention in Figure 7 A top plan view of the formation of a second semiconductor layer on the back side of a silicon wafer;

[0046] Figure 9 This is a planar schematic diagram of the formation of corresponding positioning points on the back side of a silicon wafer according to an embodiment of the present invention;

[0047] Figure 10 This is a cross-sectional view of a conductive film layer deposited on the back side of a silicon wafer according to an embodiment of the present invention;

[0048] Figure 11 This is a plan view of a conductive film layer deposited on the back side of a silicon wafer according to an embodiment of the present invention;

[0049] Figure 12 This is a schematic diagram of the structure of an isolation trench formed by etching an opening in the conductive film layer between the first semiconductor and the second semiconductor on the back side of a silicon wafer, according to an embodiment of the present invention.

[0050] Figure 13 This is a planar schematic diagram of an embodiment of the present invention showing the formation of an isolation trench and an etched insulating region in the conductive film layer between the first semiconductor and the second semiconductor on the back side of a silicon wafer.

[0051] Figure 14 for Figure 13 A partially enlarged planar schematic diagram;

[0052] Figure 15 This is a schematic diagram of the structure of forming a metal electrode on the back side of a silicon wafer according to an embodiment of the present invention.

[0053] Figure 16 The conventional mask used in the fabrication of back-contact batteries in the prior art.

[0054] Explanation of reference numerals in the attached figures

[0055] Silicon wafer 10, passivation layer 11, antireflection layer 12, intrinsic amorphous silicon layer 13, first semiconductor layer 14, second semiconductor layer 15, conductive film layer 16, metal electrode 17. Rigid mask 20, opening unit 21, hollow positioning point 22, reinforcing rib 23. Detailed Implementation

[0056] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0057] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0058] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0059] In this invention, the area closer to the silicon wafer is considered the inside, and the area farther from the silicon wafer is considered the outside.

[0060] In a first aspect, the present invention provides a method for fabricating a back contact battery with high-precision mask alignment, comprising the following steps:

[0061] S101, Provides silicon wafers with double-sided texturing;

[0062] S102. A passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer;

[0063] S103. Polish or perform secondary texturing on the back of the silicon wafer;

[0064] S104. Deposit an intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0065] S105. A rigid mask plate with a plurality of parallel first opening areas is provided, and the non-first opening area portion of the rigid mask plate is provided with hollow positioning points.

[0066] A rigid mask is first aligned with a predetermined first semiconductor region on the back of a silicon wafer to form a first semiconductor layer, and a first positioning layer is formed at the cut-out positioning points. Then, the rigid mask is moved and aligned with a predetermined second semiconductor region on the back of the silicon wafer to form a second semiconductor layer, which is at least partially alternated with the first semiconductor layer, and a second positioning layer is formed at the cut-out positioning points. Next, the first positioning layer and the second positioning layer are laser etched or inkjet printed to form positioning points.

[0067] S106. Deposit a conductive film layer on the back side of the silicon wafer;

[0068] S107. Using chemical etching or dry etching technology, by capturing the positioning points around the silicon wafer, the corresponding conductive film layer is precisely etched between the first semiconductor layer and the second semiconductor layer to form an isolation trench; at the same time, the conductive film layer corresponding to the positioning points around the silicon wafer is etched to form an etched insulating area; the size of the etched insulating area is not less than the size of the corresponding positioning point or the corresponding hollow positioning point.

[0069] S108. Form a metal electrode on the back side of the silicon wafer.

[0070] In S107 of this invention, the size of the etched insulating region being no less than the size of the corresponding positioning point or the corresponding hollowed-out positioning point means that, for the hollowed-out positioning point, the size after etching in S107 is no less than the size of the positioning point or the initial hollowed-out positioning point before etching. Preferably, the size of the etched insulating region is 1.05-2 times the size of the corresponding positioning point or the corresponding hollowed-out positioning point, which is more conducive to insulating semiconductors of different polarities, improving the insulation effect, and ensuring a high passivation level.

[0071] The silicon wafer in S101 can be a Czochralski single-crystal silicon wafer or a cast single-crystal silicon wafer, preferably an N-type single-crystal silicon wafer.

[0072] The texturing solution used in S101 for double-sided texturing can refer to existing technologies. For example, the texturing solution may include a mixture of alkali (such as potassium hydroxide or sodium hydroxide), texturing additives, and water, wherein the mass percentage of alkali is 0.5%-5%, and the mass percentage of texturing additives is 0.05%-1%. Further, the texturing conditions may include: a texturing time of 6-15 minutes and a texturing temperature of 70-90°C. The texturing additives are commercially available. After double-sided texturing in S101, conventional steps such as washing may also be included.

[0073] The types, thicknesses, and formation methods of the passivation layer and antireflection layer in S102 can all refer to existing technologies and can all be used in this invention. For example, the passivation layer can be a silicon dielectric passivation layer or an alumina passivation layer, etc., and for instance, the passivation layer can be at least one of amorphous silicon, silicon oxide, and aluminum oxide. More preferably, the passivation layer includes silicon oxide and amorphous silicon sequentially disposed. Further preferably, in the passivation layer, the thickness of the silicon oxide is 0.3-2 nm, and the thickness of the amorphous silicon is 2-10 nm. For example, the antireflection layer can be a silicon dielectric antireflection layer, such as at least one of silicon nitride, silicon oxynitride, and silicon oxide. Preferably, the antireflection layer includes silicon nitride, silicon oxynitride, and silicon oxide sequentially disposed. Further preferably, in the antireflection layer, the thickness of the silicon nitride is 50-100 nm, the thickness of the silicon oxynitride is 5-50 nm, and the thickness of the silicon oxide is 80-150 nm. The passivation layer and antireflection layer can be formed by equipment such as ALD, PECVD, and LPCVD. It is preferred to form them in one step by using tubular PECVD. More preferably, the deposition temperature of tubular PECVD is 400-560℃.

[0074] The polishing or secondary texturing process described in S103 refers to the ability to perform polishing or secondary texturing (primary texturing refers to the double-sided texturing in S101) to remove the wrapping layer generated in S102, while simultaneously creating a clean interface on the back of the silicon wafer.

[0075] The polishing or texturing liquid used in the polishing or secondary texturing process described in S103 can refer to existing technologies and can be used in this invention, as long as the target back structure can be obtained. For example, the texturing liquid used in the secondary texturing process may include a mixture of alkali (such as potassium hydroxide or sodium hydroxide), texturing additive, and water, wherein the mass percentage of alkali is 1%-10% and the mass percentage of texturing additive is 0.2%-3%. Further, the texturing conditions may include: a texturing time of 1-10 min and a texturing temperature of 70-90°C. The texturing additive can be commercially available. For example, the polishing liquid used in the polishing process may include a mixture of alkali (such as potassium hydroxide or sodium hydroxide), polishing additive, and water, wherein the mass percentage of alkali is 2%-10% and the mass percentage of polishing additive is 0%-1%, preferably 0.05%-1%. Further, the polishing conditions may include: a polishing time of 0.5-5 min and a polishing temperature of 70-90°C. The polishing additive can be commercially available.

[0076] The polishing or secondary texturing process described in S103 may also include conventional steps such as cleaning.

[0077] In some preferred embodiments of the present invention, reinforcing ribs are provided on the rigid mask plate, and the reinforcing ribs divide the first opening area into a plurality of opening units along its length direction. It is understood that, along the length direction, the reinforcing ribs are located between adjacent opening units to separate multiple opening units. In a preferred embodiment of the present invention, the length direction of the first opening area on the rigid mask plate is divided into multiple opening units by the provision of reinforcing ribs, further reducing the impact of deformation caused by excessively long mask openings, thereby further improving alignment accuracy and increasing battery conversion efficiency.

[0078] In some preferred embodiments of the present invention, the opening length W11 of the opening unit is 5-50 mm, specifically, it can be any value or a range between any values ​​such as 5 mm, 10 mm, 15 mm, 20 mm, 25 mm, 30 mm, 35 mm, 40 mm, 45 mm, and 50 mm, for example, 5-35 mm is preferred. Using an opening unit of suitable length is more conducive to reducing mask deformation, improving alignment accuracy, further enhancing insulation and passivation effects, and improving battery conversion efficiency.

[0079] In some preferred embodiments of the present invention, the length W12 of the reinforcing rib is 0.05-1 mm, specifically, it can be any value or a range between any values ​​such as 0.05 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, and 1 mm, for example, preferably 0.05-0.7 mm. Using a reinforcing rib of suitable length facilitates mask processing and reduces the impact on battery conversion efficiency.

[0080] In some preferred embodiments of the present invention, the width W1 of the first opening region is 0.2-1 mm. A first semiconductor layer or a second semiconductor layer is formed within the first opening region, so the width of the first opening region may be the same as or different from the width of the desired first semiconductor layer or second semiconductor layer.

[0081] In some preferred embodiments of the present invention, the length of the first opening area is less than the length of the silicon wafer, which is more conducive to reducing the influence of the mask opening being too long and easily deformed, thereby further improving the alignment accuracy.

[0082] In some preferred embodiments of the present invention, the hollow positioning points are distributed around the rigid mask plate, which is more conducive to positioning and thus further improves the alignment accuracy.

[0083] In some preferred embodiments of the present invention, there are at least four hollowed-out positioning points to facilitate positioning around the perimeter.

[0084] In some preferred embodiments of the present invention, the hollow positioning point is located inside the outermost first opening area, which is more conducive to improving the alignment accuracy.

[0085] In some preferred embodiments of the present invention, the shape of the hollowed-out positioning point is any one of the following: circle (including perfect circle and ellipse), square, cross, triangle, rhombus, and polygon.

[0086] In some preferred embodiments of the present invention, the size R1 of the hollow positioning point is between 0.1 and 1 mm. Using a hollow positioning point of suitable size is more conducive to the alignment etching of S107 and improves the alignment accuracy. Here, the size R1 of the hollow positioning point being between 0.1 and 1 mm means that the size of the hollow positioning point in any direction is within the range of 0.1 to 1 mm.

[0087] In some preferred embodiments of the present invention, the size of the etched insulating region is 0.2-1.5 mm.

[0088] In some preferred embodiments of the present invention, the size R1 of the hollow positioning point is smaller than the width W1 of the first opening area, which is more conducive to reducing the impact on battery conversion efficiency.

[0089] In this invention, it should be understood that the first semiconductor layer and the second semiconductor layer have opposite polarities, one being N-type and the other P-type; that is, when the first semiconductor layer is N-type, the second semiconductor layer is P-type, and when the first semiconductor layer is P-type, the second semiconductor layer is N-type. Preferably, the first semiconductor layer and the second semiconductor layer are two doped layers with different polarities, namely, a first doped layer and a second doped layer.

[0090] In some preferred embodiments of the present invention, the spacing width W2 between the first semiconductor layer and the second semiconductor layer is -0.3 mm to 0.3 mm, preferably 0-0.3 mm. When W2 is negative, the first semiconductor layer and the second semiconductor layer partially overlap, and the width of the overlapping area is the absolute value of W2. When W2 is 0, the edges of the first semiconductor layer and the second semiconductor layer are closely attached, and in this case, the isolation trench is located at the critical edge of their respective edges.

[0091] In some preferred embodiments of the first aspect of the present invention, in S105, both the first semiconductor layer and the second semiconductor layer are formed by deposition technology or ion implantation. Accordingly, both the first semiconductor layer and the second semiconductor layer are deposited films attached to the intrinsic amorphous silicon layer or are partially doped regions of intrinsic amorphous silicon.

[0092] In some preferred embodiments of the present invention, ion implantation is used instead of in-situ doping deposition, so that the outer surfaces of the first semiconductor layer and the second semiconductor layer are at the same height, which is more conducive to improving production yield.

[0093] In some preferred embodiments of the first aspect of the present invention, in S105, the length by which the rigid mask moves is half the distance between the centers of two adjacent first opening areas in the direction perpendicular to the first opening area, which makes alignment more convenient and improves alignment accuracy.

[0094] In some preferred embodiments of the first aspect of the present invention, the first semiconductor layer and the second semiconductor layer have the same width and their width W1 is between 0.2 and 1 mm.

[0095] In some preferred embodiments of the first aspect of the present invention, the thickness of the intrinsic amorphous silicon layer is 5-40 nm.

[0096] In some preferred embodiments of the first aspect of the present invention, the thickness of the first semiconductor layer is 3-20 nm, and the thickness of the second semiconductor layer is 3-20 nm.

[0097] The doping concentrations of the first and second semiconductor layers in this invention can be within the ranges specified in the prior art, and both can be used in this invention. For example, the effective doping concentration of the first semiconductor layer is greater than 5e18cm⁻¹. -3 The doping concentration of the second semiconductor layer is 2e18cm.-3 -5e20cm -3 .

[0098] The etching of the conductive film layer in S107 to form the isolation trench can be achieved, for example, by chemical etching or dry etching techniques. In some preferred embodiments of the first aspect of the invention, the width W3 of the isolation trench is 0.03-0.25 mm.

[0099] The thickness and type of the conductive film layer in this invention can refer to existing technologies and can all be used in this invention. For example, the thickness of the conductive film layer is 20-500 nm. The conductive film layer can be, for example, an indium oxide thin film doped with tungsten, tin, zinc or other elements, a zinc oxide thin film doped with aluminum, boron, gallium or other elements, or one or more combinations of metal thin films such as silver, copper, and aluminum. Physical vapor deposition is preferred for forming the conductive film layer.

[0100] It should be understood in this invention that there are several metal electrodes, which are respectively located on the outer surfaces of the first semiconductor layer and the second semiconductor layer; this is prior art and will not be described in detail here.

[0101] In a second aspect, the present invention provides a back contact battery, which is prepared according to the high-precision mask alignment back contact battery preparation method described in the first aspect.

[0102] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0103] Example 1

[0104] A back-contact battery is prepared by the following method:

[0105] S101, such as Figure 1 As shown, a silicon wafer 10 (specifically N-type monocrystalline silicon) after double-sided texturing is provided; specifically, the silicon wafer 10 is texturized for 10 minutes using a sodium hydroxide solution with a mass concentration of 1% at a temperature of 80°C and a texturing additive with a mass concentration of 0.15%, and then the surface of the silicon wafer 10 is cleaned.

[0106] S102, such as Figure 2 As shown, a passivation layer 11 and an antireflection layer 12 are formed on the front side of silicon wafer 10 in a single process using tubular PECVD at a deposition temperature of 450°C. Specifically, a 0.8 nm thick tunneling silicon oxide layer and a 5 nm thick amorphous silicon layer are sequentially formed on the front side of silicon wafer 10 as the passivation layer 11, followed by the formation of a 60 nm thick silicon nitride layer, a 10 nm thick silicon oxynitride layer, and an 80 nm thick silicon oxide layer as the antireflection layer 12.

[0107] S103, such as Figure 3As shown, the back side of silicon wafer 10 is polished to remove the coating layer generated by S102, thereby creating a clean interface on the back side of silicon wafer 10. The polishing process involves polishing silicon wafer 10 for 1 minute with a 2% sodium hydroxide solution at 80°C and a 0.3% polishing additive, followed by cleaning the surface of silicon wafer 10.

[0108] S104, such as Figure 4 As shown, an intrinsic amorphous silicon layer 13 with a thickness of 20 nm is deposited on the back side of silicon wafer 10 using PECVD technology;

[0109] S105, such as Figure 5 As shown, through hard materials such as Figure 6 The rigid mask 20 shown uses ion implantation to dope the intrinsic amorphous silicon layer 13 on the back side of the silicon wafer 10, forming alternating first semiconductor layer 14 (N-type) and second semiconductor layer 15 (P-type). The first semiconductor layer 14 and the second semiconductor layer 15 have the same width, W1, and a spacing of W2 between them. W1 is 0.4 mm, and W2 is 0.1 mm wide. The first semiconductor layer 14 has a thickness of 12 nm and an effective doping concentration of 1e20 cm⁻¹. -3 The second semiconductor layer 15 has a thickness of 12 nm and an effective doping concentration of 7e19 cm⁻¹. -3 .

[0110] Figure 6 The diagram shows the structure of the rigid photomask 20. The rigid photomask 20 has a first opening area, which is divided into multiple opening units 21 by reinforcing ribs 23. The length of the first opening area is equal to the length of the silicon wafer 10. The opening width W1 of the first opening area (or opening unit 21) is 0.4 mm, the opening length W11 of the opening unit 21 is 10 mm, the width W12 of the reinforcing ribs 23 is 0.15 mm, and four circular hollow positioning points 22 with a diameter of R1 are provided around the rigid photomask 20.

[0111] Specifically, such as Figure 7 , Figure 8 , Figure 9As shown, a hard mask 20 is first aligned with the silicon wafer 10 to form a first semiconductor layer 14, and a first positioning layer (i.e., the first semiconductor) is formed at the cutout positioning point 22. Then, the hard mask 20 is moved approximately half a pitch length R (i.e., half the distance between the centers of two adjacent first opening areas in the direction perpendicular to the first opening area) to form a second semiconductor layer 15 alternating with the first semiconductor layer 14, and a second positioning layer (i.e., the second semiconductor) is formed at the cutout positioning point 22. Subsequently, laser etching is used to etch within the first and second positioning layers, forming positioning points with diameters R1 and R2, respectively, where R1 is 0.3 mm and R2 is 0.3 mm. These positioning points are used for alignment of the insulating grooves after the conductive film layer 16 is deposited.

[0112] S106, such as Figure 10 , Figure 11 As shown, a conductive film layer 16 (ITO) with a thickness of 60 nm is deposited on the back side of silicon wafer 10 using physical vapor deposition technology.

[0113] S107, such as Figure 12 , Figure 13 , Figure 14 As shown, chemical etching technology is used to precisely etch the corresponding conductive film layer 16 between the first semiconductor layer 14 and the second semiconductor layer 15 by capturing the positioning points around the silicon wafer 10, forming an isolation trench with a width W3 of 0.07 mm. At the same time, the conductive film layer 16 at the positioning points of the four heterogeneous semiconductor layers with diameters R1 and R2 around the silicon wafer 10 is etched to form etched insulating regions with diameters R11 and R21, and R11 > R1, R21 > R2, with R11 being 0.4 mm and R21 being 0.4 mm.

[0114] S108, such as Figure 15 As shown, metal electrodes 17 are formed on the outer surfaces of the first semiconductor and the second semiconductor on the back side of the silicon wafer 10.

[0115] Example 2

[0116] The same procedure is followed as in Embodiment 1, except that the opening length W11 of the opening unit 21 is 40 mm.

[0117] Example 3

[0118] The same procedure was performed as in Example 1, except that the length W12 of the reinforcing rib 23 was 0.8 mm.

[0119] Example 4

[0120] The same procedure is followed as in Embodiment 1, except that the spacing width W2 between the first semiconductor layer 14 and the second semiconductor layer 15 is -0.1 mm, and the first semiconductor layer 14 and the second semiconductor layer 15 partially overlap, with the width of the overlapping area being the absolute value of W2.

[0121] Example 5

[0122] The process is carried out in accordance with Example 1, except that the first semiconductor layer 14 and the second semiconductor layer 15 are deposited on the outer surface of the intrinsic amorphous silicon layer 13 using a deposition technique, and are additional deposited film layers. The thickness of the first semiconductor layer 14 and the second semiconductor layer 15 is 16 nm, and the doping concentration remains unchanged.

[0123] Comparative Example 1

[0124] The procedure is carried out in accordance with Example 1, except that the masks for different semiconductor regions and the masks for the isolation trenches are all conventional mask plates (their structures are as follows). Figure 16 As shown, (relative to not setting hollow positioning points and reinforcing ribs), specifically, firstly, according to the alignment of the silicon wafer edge, a conventional mask A is used to form the first semiconductor layer, then according to the alignment of the silicon wafer edge, a conventional mask B is used to form the second semiconductor layer, and then according to the alignment of the silicon wafer edge, a conventional mask C is used to form the isolation trench.

[0125] Comparative Example 2

[0126] Referring to Example 1, the difference is that in S107, the size of the etched insulating region is smaller than the size of the corresponding positioning point or the corresponding hollow positioning point; the size of the etched insulating region, i.e., the diameter, is 0.2 mm. To meet this condition, the corresponding fabrication process parameters need to be adjusted as follows: In S107, the conductive film layer 16 at the positioning points corresponding to the four heterogeneous semiconductor layers with diameters R1 and R2 around the silicon wafer 10 is etched simultaneously to form etched insulating regions with diameters R11 and R21, and R11 < R1, R21 < R2, with R11 being 0.2 mm and R21 being 0.2 mm.

[0127] Test case

[0128] The back-contact batteries obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The alignment deviation test method was as follows: the maximum deviation between the actual alignment and the designed alignment between the first semiconductor layer, the second semiconductor layer, and the isolation trench was collected using a microscope. The larger the alignment deviation value, the smaller the alignment accuracy; the smaller the alignment deviation value, the larger the alignment accuracy.

[0129] Table 1

[0130]

[0131] The results above show that, compared with the comparative example, the embodiment of the present invention can improve the mask alignment accuracy while increasing the parallel resistance, thereby ensuring the insulation effect and improving the minority carrier lifetime to a certain high level, thereby improving the passivation effect and thus improving the battery conversion efficiency.

[0132] Furthermore, as can be seen from Embodiments 1 and 2-4, the preferred scheme of the present invention is more conducive to improving the mask alignment accuracy while ensuring the insulation and passivation effects, and also improving the battery conversion efficiency.

[0133] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combinations of various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A method for fabricating a back contact battery with high-precision mask alignment, characterized in that, Includes the following steps: S101, Provides silicon wafers with double-sided texturing; S102. A passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer; S103. Polish or perform secondary texturing on the back of the silicon wafer; S104. Deposit an intrinsic amorphous silicon layer on the back side of the silicon wafer; S105. A rigid mask plate with a plurality of parallel first opening areas is provided, and the non-first opening area portion of the rigid mask plate is provided with hollow positioning points. The rigid mask plate is provided with reinforcing ribs, which divide the first opening area into a plurality of opening units along its length direction. A rigid mask is first aligned with a predetermined first semiconductor region on the back of a silicon wafer to form a first semiconductor layer, and a first positioning layer is formed at the cut-out positioning points. Then, the rigid mask is moved and aligned with a predetermined second semiconductor region on the back of the silicon wafer to form a second semiconductor layer, which is at least partially alternated with the first semiconductor layer, and a second positioning layer is formed at the cut-out positioning points. Next, the first positioning layer and the second positioning layer are laser etched or inkjet printed to form positioning points. S106. Deposit a conductive film layer on the back side of the silicon wafer; S107. Using chemical etching or dry etching technology, by capturing the positioning points around the silicon wafer, the corresponding conductive film layer is precisely etched between the first semiconductor layer and the second semiconductor layer to form an isolation trench; at the same time, the conductive film layer corresponding to the positioning points around the silicon wafer is etched to form an etched insulating area; the size of the etched insulating area is not less than the size of the corresponding positioning point or the corresponding hollow positioning point. S108. Form a metal electrode on the back side of the silicon wafer.

2. The method for fabricating a back contact battery with high-precision mask alignment according to claim 1, characterized in that, The opening length W11 of the open unit is 5-50mm.

3. The method for fabricating a back contact battery with high-precision mask alignment according to claim 1, characterized in that, The length of the reinforcing rib, W12, is 0.05-1mm.

4. The method for fabricating a back contact battery with high-precision mask alignment according to claim 1, characterized in that, The width W1 of the first opening region is 0.2-1mm, and / or the length of the first opening region is less than the length of the silicon wafer.

5. The method for fabricating a back contact battery with high-precision mask alignment according to claim 1, characterized in that, The cutout positioning points are distributed around the rigid mask plate, and / or there are at least four cutout positioning points.

6. The method for fabricating a back contact battery with high-precision mask alignment according to claim 1 or 5, characterized in that, The cutout positioning point is located inside the outermost first opening area, and / or the shape of the cutout positioning point is any one of the following: circle, square, cross, triangle, or rhombus.

7. The method for fabricating a back contact battery with high-precision mask alignment according to claim 1, characterized in that, The dimension R1 of the hollowed-out positioning point is 0.1-1mm, and the dimension of the etched insulating area is 0.2-1.5mm; and / or, The size R1 of the hollow positioning point is smaller than the width W1 of the first opening area.

8. The method for fabricating a back contact battery with high-precision mask alignment according to claim 1, characterized in that, The spacing W2 between the first semiconductor layer and the second semiconductor layer is -0.3 mm to 0.3 mm. When W2 is negative, the first semiconductor layer and the second semiconductor layer partially overlap, and the width of the overlapping area is the absolute value of W2.

9. The method for fabricating a back contact battery with high-precision mask alignment according to claim 1, characterized in that, The back contact battery manufacturing method also includes at least one of the following processes: In process 1, S105, the length by which the rigid mask moves is half the distance between the centers of two adjacent first opening areas in the direction perpendicular to the first opening area. Process 2: The first semiconductor layer and the second semiconductor layer have the same width, and their width W1 is between 0.2-1mm; Process 3: The thickness of the intrinsic amorphous silicon layer is 5-40nm, the thickness of the first semiconductor layer is 3-20nm, and the thickness of the second semiconductor layer is 3-20nm; Process 4: Both the first semiconductor layer and the second semiconductor layer are deposited film layers attached to the outside of the intrinsic amorphous silicon layer, or both are partially doped regions of intrinsic amorphous silicon. Process 5: The width W3 of the isolation groove is 0.03-0.25mm; In process six, S105, both the first semiconductor layer and the second semiconductor layer are formed using deposition technology or ion implantation. Process 7: The size of the etched insulating area is 1.05-2 times the size of the corresponding positioning point or the corresponding hollow positioning point.

10. A back-contact battery, characterized in that, It is prepared according to the back contact cell preparation method with high-precision mask alignment as described in any one of claims 1-9.

Images