Pulse emission circuit, control method and related product

Abstract

The invention discloses a pulse emission circuit, a control method and a related product. The pulse transmitting circuit comprises a controller, a threshold voltage circuit, a comparator circuit, a biasing circuit and a pulse circuit; a plurality of input ends of the threshold voltage circuit are respectively connected with different voltage levels, an output end of the threshold voltage circuit is connected with a first input end of the comparator circuit, and a control end of the threshold voltage circuit is connected with the controller; the second input end of the comparator circuit is connected with the low-voltage domain output end of the pulse circuit, and the output end of the comparator circuit is connected with the input end of the biasing circuit; the output end of the biasing circuit is connected with the input end of the pulse circuit; and a controller configured to control the threshold voltage to change at least one of a frequency, an amplitude, and a number of steps of the pulse output by the pulse circuit. According to the pulse transmitting circuit in the embodiment of the invention, the frequency, the amplitude and the step number of the output pulse are controllable, and the ultrasonic imaging requirements of the PMUT for different penetration depths are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and in particular to a pulse transmitting circuit, a control method and related products. BACKGROUND

[0002] Ultrasonic imaging technology transmits and receives ultrasonic signals to the target medium to construct a target image, and is currently widely used in industrial material nondestructive testing, medical ultrasonic diagnosis and other fields. In the transmission stage, the ultrasonic transducer is mainly excited by a high-voltage electrical signal, and due to the inverse piezoelectric effect, the excited transducer generates high-frequency vibration to realize the transmission of ultrasonic waves in the target medium. As can be seen, the adaptability of the pulse transmitting circuit and the ultrasonic transducer (micromachined ultrasonic transducer, MUT) is the key to determine the transmission efficiency of ultrasonic imaging.

[0003] With the rapid development of microelectronic technology, piezoelectric micromachined ultrasonic transducers (PMUTs) have emerged. Due to the advantages of miniaturization, array, low power consumption and easy integration with complementary metal oxide semiconductor (CMOS) circuits, the efficient integration of PMUTs and CMOS transmitting circuits is crucial for the integration and miniaturization of future ultrasonic imaging systems with high transmission efficiency, high precision and large imaging depth.

[0004] In related technologies, the commonly used pulse transmitting circuit cannot adjust the frequency, amplitude or step number of the output pulse to adapt to the dual-frequency PMUT ultrasonic transducer, resulting in the inability to meet the PMUT's ultrasonic imaging requirements for different penetration depths. SUMMARY

[0005] Based on the above problems, the present application provides a pulse transmitting circuit, a control method and related products to meet the PMUT's ultrasonic imaging requirements for different penetration depths and improve the ultrasonic imaging quality of the PMUT.

[0006] The embodiments of the present application disclose the following technical solutions:

[0007] In a first aspect, the embodiments of the present application provide a pulse transmitting circuit, comprising: a controller, a threshold voltage circuit, a comparator circuit, a bias circuit and a pulse circuit;

[0008] The multiple input ends of the threshold voltage circuit are respectively connected to different voltage levels, the output end of the threshold voltage circuit is connected to the first input end of the comparator circuit, and the control end of the threshold voltage circuit is connected to the controller.

[0009] The second input end of the comparator circuit is connected to the low voltage domain output end of the pulse circuit, and the output end of the comparator circuit is connected to the input end of the bias circuit;

[0010] The output end of the bias circuit is connected to the input end of the pulse circuit;

[0011] The output end of the pulse circuit is used for connecting the dual-frequency piezoelectric micromechanical ultrasonic transducer;

[0012] The controller is configured to control the threshold voltage to change at least one of the frequency, the amplitude and the number of steps of the pulse output by the pulse circuit; wherein the frequency, the amplitude and the number of steps of the pulse are in positive correlation with the frequency, the amplitude and the number of steps of the threshold voltage, respectively.

[0013] In a possible implementation, the pulse circuit comprises a pull-up circuit and a pull-down circuit, the output end of the pull-up circuit and the output end of the pull-down circuit serving as the output end of the pulse generation circuit; the pull-up circuit comprises a level shifter and a first transistor; wherein the first input end and the second input end of the level shifter are connected to the first output end and the second output end of the bias circuit respectively, the output end of the level shifter is connected to the gate of the first transistor, and the power supply end of the level shifter is used for connecting the first power supply positive pole; the source of the first transistor is used for connecting the first power supply positive pole, and the drain of the first transistor serves as the output end of the pull-up circuit; the pull-down circuit comprises a second transistor, a third transistor and a fourth transistor; wherein the gate of the second transistor is connected to the third output end of the bias circuit, the source of the second transistor is used for connecting the second power supply positive pole, the drain of the second transistor is connected to the drain of the third transistor and the gate of the third transistor; the gate of the third transistor is connected to the gate of the fourth transistor, the source of the third transistor and the source of the fourth transistor are connected together to connect the first power supply negative pole, and the drain of the fourth transistor serves as the output end of the pull-down circuit.

[0014] In a possible implementation, the bias circuit includes a logic circuit, a first bias circuit, a second bias circuit and a first inverter; the first bias circuit includes a fifth transistor, a sixth transistor and a first switch device; the drain and the gate of the fifth transistor are connected together, and the fifth transistor is connected to a second positive electrode of a second current source through a first current source, the source of the fifth transistor is grounded, and the gate of the fifth transistor is connected to a first end of the first switch device; a second end of the first switch device is connected to the drain of the sixth transistor and a first input terminal of a level shifter, and the source of the sixth transistor is grounded; the second end of the first switch device is connected to a second input terminal of the level shifter through the first inverter; the second bias circuit includes a seventh transistor, an eighth transistor and a second switch device; the source of the seventh transistor is connected to the second positive electrode of the second current source, the drain and the gate of the seventh transistor are connected together, and the seventh transistor is grounded through a second current source, and the gate of the seventh transistor is connected to a first end of the second switch device; a second end of the second switch device is connected to the drain of the eighth transistor and the gate of the second transistor; the source of the eighth transistor is connected to the second positive electrode of the second current source; the logic circuit is configured to generate a first signal, a second signal, a third signal and a fourth signal according to an output signal of the comparator circuit and an enable signal; wherein the first signal and the second signal are used to control the first switch device to be turned on and the sixth transistor to be turned off, or the first switch device to be turned off and the sixth transistor to be turned on, and the third signal and the fourth signal are used to control the second switch device to be turned on and the eighth transistor to be turned off, or the second switch device to be turned off and the eighth transistor to be turned on.

[0015] In a possible implementation, the logic circuit includes a second inverter, a third inverter, a first AND gate, a second AND gate, a fourth inverter and a fifth inverter; an input terminal of the second inverter is connected to an enable terminal, and an output terminal of the second inverter is connected to a first input terminal of the first AND gate; a second input terminal of the first AND gate is connected to an output terminal of the third inverter, and an output terminal of the first AND gate is connected to an input terminal of the fourth inverter; an input terminal of the third inverter is connected to an output terminal of the comparator circuit, and an output terminal of the third inverter is connected to a first input terminal of the second AND gate; a second input terminal of the second AND gate is connected to the enable terminal, and an output terminal of the second AND gate is connected to an input terminal of the fifth inverter.

[0016] In a possible implementation, the threshold voltage circuit includes a multiplexer and a series resistance group string, the series resistance group string includes n resistors, n is an integer greater than or equal to 2; one input terminal of the multiplexer is used to be connected to a power supply, other input terminals are respectively connected to the intersection points of two resistors in the series resistance group string, and a control terminal of the multiplexer is connected to a controller; a first end of the series resistance group string is used to be connected to the power supply, and a second end of the series resistance group string is grounded.

[0017] In a possible implementation, the comparator circuit includes: a chopper modulation pre-switch, a first NOR gate, a second NOR gate, a sixth inverter, a seventh inverter, and m cascaded differential operational amplifiers, where m is an integer greater than or equal to 2; a first input terminal and a second input terminal of the chopper modulation pre-switch are connected to an output terminal of the threshold voltage circuit and a low-voltage domain output terminal of the pulse generation circuit respectively, a first output terminal and a second output terminal of the chopper modulation pre-switch are connected to a first input terminal and a second input terminal of a first differential operational amplifier in the m differential operational amplifiers respectively;

[0018] a first output terminal and a second output terminal of an mth differential operational amplifier in the m differential operational amplifiers are connected to an input terminal of the sixth inverter and an input terminal of the seventh inverter respectively; an output terminal of the sixth inverter is connected to a first input terminal of the first NOR gate, and an output terminal of the seventh inverter is connected to a second input terminal of the second NOR gate; an output terminal of the first NOR gate is connected to a first input terminal of the second NOR gate, and an output terminal of the second NOR gate is connected to a second input terminal of the first NOR gate.

[0019] In a possible implementation, the pulse emission circuit further includes: a first capacitor and a second capacitor; a first terminal of the first capacitor is connected to the low-voltage domain output terminal of the pulse generation circuit, a second terminal of the first capacitor is connected to a first terminal of the second capacitor and the second input terminal of the comparator circuit; and a second terminal of the second capacitor is grounded.

[0020] In a second aspect, an embodiment of the present application provides a control method of a pulse emission circuit, the pulse emission circuit including a threshold voltage circuit, a comparator circuit, a bias circuit, and a pulse circuit; wherein a plurality of input terminals of the threshold voltage circuit are connected to different voltage levels respectively, an output terminal of the threshold voltage circuit is connected to a first input terminal of the comparator circuit, and a control terminal of the threshold voltage circuit is connected to a controller; a second input terminal of the comparator circuit is connected to a low-voltage domain output terminal of the pulse circuit, and an output terminal of the comparator circuit is connected to an input terminal of the bias circuit; an output terminal of the bias circuit is connected to an input terminal of the pulse circuit; and an output terminal of the pulse circuit is used to connect a dual-frequency piezoelectric micromechanical ultrasonic transducer.

[0021] The method includes:

[0022] obtaining a target amplitude, a target frequency, and a target step number of an output pulse;

[0023] controlling the threshold voltage according to the amplitude, the frequency, or the step number of the target pulse, so as to change at least one of the frequency, the amplitude, and the step number of the output pulse; wherein the target frequency, the target amplitude, and the target step number of the output pulse are in positive correlation with the frequency, the amplitude, and the step number of the threshold voltage respectively.

[0024] In a third aspect, an embodiment of the present application provides a control device, comprising a processor and a memory, the memory being configured to store programs, instructions or codes, and the processor being configured to execute the programs, instructions or codes in the memory to complete the control method in the second aspect.

[0025] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is loaded by a processor to execute the control method in the second aspect.

[0026] In order to meet the needs of PMUT devices for ultrasonic imaging of different penetration depths and improve the ultrasonic imaging quality of PMUTs, an embodiment of the present application provides a pulse transmitting circuit, which controls the output signal of a threshold voltage generating circuit, i.e., the threshold voltage, and then controls at least one of the frequency, amplitude and step number of the output pulse of a pulse generating circuit; wherein the frequency, amplitude and step number of the output pulse are all adjustable, meeting the needs of PMUTs for ultrasonic imaging of different penetration depths. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0028] Figure 1 A schematic diagram of a pulse transmitting circuit provided by an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a comparator circuit provided by an embodiment of the present application;

[0030] Figure 3 A schematic diagram of a bias circuit provided by an embodiment of the present application;

[0031] Figure 4 A schematic diagram of a logic circuit provided by an embodiment of the present application;

[0032] Figure 5 A schematic diagram of a pulse circuit provided by an embodiment of the present application;

[0033] Figure 6 An equivalent circuit schematic diagram of a dual-frequency PMUT transducer provided by an embodiment of the present application;

[0034] Figure 7 A working timing diagram of a pulse transmitting circuit provided by an embodiment of the present application;

[0035] Figure 8 A three-order pulse schematic diagram provided for an embodiment of the present application;

[0036] Figure 9 A five-order pulse schematic diagram provided for an embodiment of the present application;

[0037] Figure 10 A seven-order pulse schematic diagram provided for an embodiment of the present application;

[0038] Figure 11 A control method flow chart of a pulse transmitting circuit provided for an embodiment of the present application;

[0039] Figure 12 A control device schematic diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application are the same as those commonly understood by those skilled in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments of the present application and are not intended to limit the present application.

[0042] It can be understood that the terms "first", "second" and the like used in the embodiments of the present application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the other element. For example, without departing from the scope of the present application, the first resistor can be referred to as the second resistor, and similarly, the second resistor can be referred to as the first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0043] It can be understood that "connection" in the following embodiments, if the circuits, modules, units and the like connected to each other have the transmission of electrical signals or data, it should be understood as "electrically connected", "communicatively connected" and the like.

[0044] It can be understood that "at least one" means one or more, and "a plurality of" means two or more. "At least part of the element" means part or all of the element.

[0045] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. Also, the term "and / or" includes any and all combinations of associated items.

[0046] The core of the pulse emission circuit is a pulse circuit Pulser for generating a high-voltage pulse signal, which usually needs to be implemented by using a BCD (Bipolar-CMOS-DMOS) process to meet the high-voltage requirement. However, a high-voltage transistor needs a larger chip area, and in order to reduce the chip size, a unipolar Pulser can be used. In the process of generating a pulse, a unipolar Pulser will generate relatively more high-frequency harmonic components. For example, some unipolar symmetric pulse current generators based on energy storage inductors and clamping circuits use the charging and discharging of energy storage inductors to generate pulse currents, and in the current rising and falling stages, high-frequency oscillation and other phenomena are prone to occur.

[0047] Therefore, a bipolar Pulser can be used. A bipolar Pulser alternately changes between two opposite potentials to form a positive-negative alternating pulse signal, and the rising edge and falling edge of the pulse are relatively steeper. Due to the symmetry of the positive-negative pulse, its frequency spectrum is more concentrated around the fundamental frequency, and there are relatively fewer high-frequency harmonics, effectively improving the signal-to-noise ratio of the Pulser. In PMUT applications, since PMUT needs to be zeroed when receiving a return wave, a zeroing switch is used. Under the same peak-to-peak voltage condition, the power consumption of the bipolar Pulser is lower than that of the unipolar Pulser.

[0048] In addition to unipolar and bipolar Pulser, in biomedical ultrasound, a multi-level Pulser is also needed, that is, the Pulser can generate multi-level pulses. Such multi-level pulses approach the linear transfer characteristic through "level ladder", and under the excitation of multi-level pulses, the output signal of the ultrasonic transducer is closer to the proportional scaling of the input waveform, improving the linearity, optimizing the nonlinear response of the microbubble contrast agent, making the amplitude difference between the microbubble echo and the tissue echo larger, and improving the image contrast. In addition, in ultrasonic harmonic imaging, using multi-level pulses to drive the transducer can effectively suppress harmonic distortion and reduce spectral leakage, thereby improving the quality of ultrasonic harmonic imaging.

[0049] In summary, for dual-frequency PMUT ultrasonic imaging, it is urgent to construct a frequency and amplitude adjustable pulse transmitting circuit based on CMOS process to generate frequency and amplitude adjustable multi-order high-frequency high-voltage bipolar pulse wave to drive dual-frequency PMUT, realize high-precision and large-imaging-depth ultrasonic imaging, and provide a chip-level technical solution for high-efficiency dual-frequency PMUT-ASIC integration.

[0050] In order to realize the frequency and phase adjustment of the multi-order high-frequency high-voltage bipolar pulse wave, the embodiment of the present application provides a pulse transmitting circuit, which comprises a controller, a threshold voltage circuit, a comparator circuit, a bias circuit and a pulse circuit; a plurality of input ends of the threshold voltage circuit are respectively connected with different voltage levels, an output end of the threshold voltage circuit is connected with a first input end of the comparator circuit, and a control end of the threshold voltage circuit is connected with the controller; a second input end of the comparator circuit is connected with a low-voltage domain output end (i.e. V PMUT V PMUT_L ) of the pulse circuit after being divided by the capacitor CP and the capacitor CN, and an output end of the comparator circuit is connected with an input end of the bias circuit; an output end of the bias circuit is connected with an input end of the pulse circuit; an output end of the pulse circuit is used for connecting the dual-frequency piezoelectric micro-machined ultrasonic transducer; the controller is configured to control the threshold voltage to change at least one of the frequency, the amplitude and the step number of the pulse output by the pulse circuit; wherein the frequency, the amplitude and the step number of the threshold voltage are in positive correlation with the frequency, the amplitude and the step number of the pulse, respectively.

[0051] In order to facilitate understanding of the technical scheme of the present application, the pulse transmitting circuit will be explained and described below in combination with the embodiment drawings.

[0052] Referring to Figure 1 , the figure is a pulse transmitting circuit provided by the embodiment of the present application, which comprises a controller (not shown in the figure), a threshold voltage circuit 100, a comparator circuit 200, a bias circuit 300 and a pulse circuit 400.

[0053] A plurality of input ends (a first input end VIN1, a second input end VIN2, …, a seventh input end VIN7 and an eighth input end VDDMUX) of the threshold voltage circuit 100 are respectively connected with different voltage levels, and an output end V MUX of the threshold voltage circuit 100 is connected with a first input end of the comparator circuit 200, and a control end EN_enable of the threshold voltage circuit 200 is connected with the controller (not shown in the figure); a second input end V PMUT_L of the comparator circuit 200 is connected with a low-voltage domain output end (i.e. V PMUT V PMUT_L ) of the pulse circuit 400 after being divided by the capacitor CP and the capacitor CN, and an output end V STA_COMThe input end of the biasing circuit 300 is connected to the input end of the pulse circuit 400 (the second output end Puse_U of the biasing circuit is connected to the second input end of the Level-Shifter in the pulse circuit, the first output end Puse_U of the biasing circuit is connected to the first input end of the Level-Shifter in the pulse circuit, and the third output end Puse_D of the biasing circuit is connected to the gate of the second transistor Q2 in the pulse circuit); and the output end V of the pulse circuit 400 is connected to the input end of the threshold voltage circuit 200. PMUT Connecting a dual-frequency piezoelectric micromechanical ultrasonic transducer (PMUT).

[0054] A controller is configured to control the threshold voltage to change at least one of a frequency, an amplitude and a step number of the pulse output by the pulse circuit 400; wherein the frequency, the amplitude and the step number of the pulse are in positive correlation with the frequency, the amplitude and the step number of the threshold voltage, respectively.

[0055] In the embodiment of the application, the threshold voltage circuit includes a multiplexer and a series resistance group string, the series resistance group string includes n resistors, n is an integer greater than or equal to 2; one input end of the multiplexer is used to connect a power supply, other input ends are respectively connected to the midpoints of two resistors in the series resistance group string, and the control end of the multiplexer is connected to the controller; the first end of the series resistance group string is used to connect the power supply, and the second end of the series resistance group string is grounded.

[0056] Again referring to Figure 1 Taking n=8 as an example, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are connected in series, one end of the eighth resistor R8 is connected to the voltage VDDMUX, and one end of the first resistor R1 is connected to the voltage VSSMUX. The intersection of the first resistor R1 and the second resistor R2 is connected to the first input end VIN1 of the multiplexer MUX, the intersection of the second resistor R2 and the third resistor R3 is connected to the second input end VIN2 of the multiplexer MUX, the intersection of the third resistor R3 and the fourth resistor R4 is connected to the third input end VIN3 of the multiplexer MUX, the intersection of the fourth resistor R4 and the fifth resistor R5 is connected to the fourth input end VIN4 of the multiplexer MUX, the intersection of the fifth resistor R5 and the sixth resistor R6 is connected to the fifth input end VIN5 of the multiplexer MUX, the intersection of the sixth resistor R6 and the seventh resistor R7 is connected to the sixth input end VIN6 of the multiplexer MUX, the intersection of the seventh resistor R7 and the eighth resistor R8 is connected to the seventh input end VIN7 of the multiplexer MUX, and the voltage VDDMUX is connected to the eighth input end of the multiplexer MUX.

[0057] For example, the controller can select the input of the multiplexer in the form of a digital code, for example, three digital codes A2, A1 and A0 change according to the rule of 000, 001, 010, 011, 100, 101, 110, 101, 100, 011, 010, 001, 000. Among them, during the process of changing the digital code from 000 to 110, the first input VIN1, the second input VIN2, the third input VIN3, the fourth input VIN4, the fifth input VIN5 and the sixth input VIN6, and the seventh input VIN7 are selected in turn; during the process of changing the digital code from 110 to 000, the seventh input VIN7, the sixth input VIN6, the fifth input VIN5, the fourth input VIN4, the third input VIN3, the second input VIN2 and the first input VIN1 are selected in turn, and the threshold voltage V MUX The threshold voltage is presented as a 7-step pulse, that is, corresponding to 7 steps. Among them, the number of steps of the threshold voltage increases, and the number of steps of the pulse output by the pulse circuit increases; the number of steps of the threshold voltage decreases, and the number of steps of the pulse output by the pulse circuit decreases.

[0058] In addition, the controller in the embodiment of the present application can also control the frequency of the threshold voltage. It should be understood that the frequency of the control signal is a mature technical means in the art, which will not be described here. The frequency of the threshold voltage increases, and the frequency of the pulse output by the pulse circuit increases; the frequency of the threshold voltage decreases, and the frequency of the pulse output by the pulse circuit decreases.

[0059] In addition, the controller in the embodiment of the present application can also control the amplitude of the threshold voltage. It should be understood that as the input (the first input VIN1, the second input VIN2, the third input VIN3, the fourth input VIN4, the fifth input VIN5, the sixth input VIN7, the seventh input VIN7 and the eighth input VDDMUX) is selected in turn, the amplitude of the pulse output by the pulse circuit increases.

[0060] In the embodiment of the present application, at least one of the frequency, amplitude and step number of the threshold voltage is controlled to change the frequency, amplitude and step number of the pulse output by the pulse circuit; wherein the frequency, amplitude and step number of the threshold voltage are positively correlated with the frequency, amplitude and step number of the pulse, respectively, so that the output pulse of the pulse emission circuit meets the ultrasonic imaging requirements of PMUT for different penetration depths, and the ultrasonic imaging quality of PMUT is improved.

[0061] In order to further understand the technical method of the present application, the comparator circuit, the bias circuit and the pulse circuit in the pulse emission circuit will be introduced below in combination with the embodiment drawings.

[0062] Referring to Figure 2The figure is a schematic diagram of a comparator circuit provided in an embodiment of this application.

[0063] like Figure 2 As shown, the comparator circuit includes: a chopper modulation preamplifier switch EN_enable, a first NOR gate NORgate1, a second NOR gate NORgate2, a sixth inverter NOTgate6, a seventh inverter NOTgate7, and m cascaded differential operational amplifiers OPA, where m is an integer greater than or equal to 2 (in this embodiment, m equals 4 as an example, and the four differential operational amplifiers are the first differential operational amplifier OPA1, the second differential operational amplifier OPA2, the third differential operational amplifier OPA3, and the fourth differential operational amplifier OPA4).

[0064] The first and second input terminals of the chopper modulation preamplifier switch EN_enable are respectively connected to the output terminal of the threshold voltage circuit and the low-voltage domain output terminal (i.e., V) of the pulse circuit. PMUT V after being divided by capacitors CP and CN PMUT_L The first and second output terminals of the chopper modulation preamplifier switch EN_enable are respectively connected to the first and second input terminals of the first differential operational amplifier OPA1.

[0065] The first and second output terminals of the first differential operational amplifier OPA1 are respectively connected to the first and second input terminals of the second differential operational amplifier OPA2.

[0066] The first and second output terminals of the second differential operational amplifier OPA2 are respectively connected to the first and second input terminals of the third differential operational amplifier OPA3.

[0067] The first and second output terminals of the third differential operational amplifier OPA3 are connected to the first and second input terminals of the fourth differential operational amplifier OPA4, respectively.

[0068] The first and second output terminals of the fourth differential operational amplifier OPA4 are connected to the input terminals of the sixth inverter NOTgate6 and the seventh inverter NOTgate7, respectively.

[0069] The output of the sixth inverter NOTgate6 is connected to the first input of the first NORgate1, and the output of the seventh inverter NOTgate7 is connected to the second input of the second NORgate2; the output of the first NORgate1 is connected to the first input of the second NORgate2, and the output of the second NORgate2 is connected to the second input of the first NORgate1.

[0070] When the enable signal EN of the chopper-modulated pre-switch EN_enable is high, i.e. the low voltage domain output pulse voltage V PMUT_L As the positive input end of the comparator circuit, the threshold voltage V MUX As the negative input end of the comparator circuit, the threshold voltage V MUX rises rapidly, the threshold voltage V PMUT_L is less than the output pulse voltage V MUX , the output signal V STA_COM of the comparator circuit is low.

[0071] When the enable signal EN of the chopper-modulated pre-switch EN_enable is low, i.e. the low voltage domain output pulse voltage V PMUT_L As the negative input end of the comparator, the threshold voltage V MUX As the positive input end of the comparator, the threshold voltage V MUX falls rapidly, the threshold voltage V MUX is less than the output pulse voltage V PMUT_L , the output signal V STA_COM of the comparator circuit is low.

[0072] Referring to Figure 3 , the figure is a schematic diagram of a bias circuit provided by an embodiment of the present application.

[0073] As shown in Figure 3 , the bias circuit comprises a logic circuit (not shown in the figure), a first bias circuit 310, and a second bias circuit 320.

[0074] The first bias circuit 310 comprises a fifth transistor Q5, a sixth transistor Q6, and a first switch device S1; the drain and gate of the fifth transistor Q5 are connected together, and the fifth transistor Q5 is connected to the second positive power supply VDD through a first current source IBP, the source of the fifth transistor Q5 is grounded VSS, and the gate of the fifth transistor Q5 is connected to the first end of the first switch device S1; the second end of the first switch device S1 is connected to the drain of the sixth transistor Q6 and the first input end of a level shifter Level-Shifter (not shown in the figure), and the source of the sixth transistor Q6 is grounded VSS; wherein Pulser_U is the output signal of the first bias circuit 310.

[0075] The second end of the first switch device S1 is connected to the second input end of the level shifter Level-Shifter through a first inverter NOTgate1 (not shown in the figure); wherein Pulser_U- is the second output signal of the first bias circuit 310.

[0076] The second bias circuit 320 comprises a seventh transistor Q7, an eighth transistor Q8 and a second switch device S2; the source of the seventh transistor Q7 is connected to the second power supply positive pole VDD, the drain and the gate of the seventh transistor Q7 are connected together and grounded to the second current source IBN VSS, and the gate of the seventh transistor Q7 is connected to the first end of the second switch device S2; the second end of the second switch device S2 is connected to the drain of the eighth transistor Q8; the source of the eighth transistor Q8 is connected to the second power supply positive pole VDD; wherein Pulser_D is the output signal of the second bias circuit 320.

[0077] The logic circuit (not shown in the figure) is configured to generate a first signal PulseP, a second signal PulseP-, a third signal PulseN and a fourth signal PulseN- according to the output signal V STA_COM and the enable signal EN; wherein the first signal PulseP and the second signal PulseP- are used to control the first switch device S1 to be turned on and the sixth transistor Q6 to be turned off, or the first switch device S1 to be turned off and the sixth transistor Q6 to be turned on; and the third signal PulseN and the fourth signal PulseN- are used to control the second switch device S2 to be turned on and the eighth transistor Q8 to be turned off, or the second switch device S2 to be turned off and the eighth transistor Q8 to be turned on.

[0078] When the logic circuit outputs the first signal PulseP as a high level, the first switch device S1 is turned on and the sixth transistor Q6 is turned off, and the first bias circuit 310 outputs the first signal Pulser_U as a high level and the second signal Pulser_U- as a low level; when the logic circuit outputs the second signal PulseP- as a high level, the first switch device S1 is turned off and the sixth transistor Q6 is turned on, and the first bias circuit 320 outputs the first signal Pulser_U as a low level and the second signal Pulser_U- as a high level.

[0079] When the logic circuit outputs the third signal PulseN as a high level, the second switch device S2 is turned on and the eighth transistor Q8 is turned off, and the second bias circuit 320 outputs Pulser_D as a low level; when the logic circuit outputs the third signal PulseN- as a high level, the second switch device S2 is turned off and the eighth transistor Q8 is turned on, and the second bias circuit 330 outputs Pulser_D as a high level.

[0080] Further, as shown in FIG. 3, the logic circuit comprises a second inverter NOTgate2, a third inverter NOTgate3, a first AND gate ANDgate1, a second AND gate ANDgate2, a fourth inverter NOTgate4 and a fifth inverter NOTgate5. Figure 4

[0081] ​An input terminal of a second NOT gate NOTgate2 is connected to the enable terminal EN, and an output terminal of the second NOT gate NOTgate2 is connected to a first input terminal of a first AND gate ANDgate1.

[0082] A second input terminal of the first AND gate ANDgate1 is connected to an output terminal of a third NOT gate NOTgate3, and an output terminal of the first AND gate ANDgate1 is connected to an input terminal of a fourth NOT gate NOTgate4.

[0083] An input terminal of the third NOT gate NOTgate3 is connected to the output terminal V STA_COM of the comparator circuit, and an output terminal of the third NOT gate NOTgate3 is connected to a first input terminal of a second AND gate ANDgate2.

[0084] A second input terminal of the second AND gate ANDgate2 is connected to the enable terminal EN, and an output terminal of the second AND gate ANDgate2 is connected to an input terminal of a fifth NOT gate NOTgate5.

[0085] In the embodiment, the logic circuit obtains a first signal PulseP, a second signal PulseP-, a third signal PulseN and a fourth signal PulseN- according to the enable signal EN and the output signal V STA_COM of the comparator circuit through the second NOT gate NOTgate2, the third NOT gate NOTgate3, the first AND gate ANDgate1, the second AND gate ANDgate2, the fourth NOT gate NOTgate4 and the fifth NOT gate NOTgate5, and then controls the pulse circuit.

[0086] The pulse circuit will be introduced in detail below with reference to the accompanying drawings.

[0087] Referring to Figure 5 , the figure is a schematic diagram of a pulse circuit provided in the embodiment.

[0088] As shown in Figure 5 , the pulse circuit includes a pull-up circuit and a pull-down circuit, and an output terminal of the pull-up circuit and an output terminal of the pull-down circuit are used as output terminals of the pulse generation circuit.

[0089] The pull-up circuit comprises a level shifter Level-Shifter and a first transistor Q1; wherein a first input end and a second input end of the level shifter Level-Shifter are connected to a first output end Pulse_U and a second output end Pulse_U- of the bias circuit respectively, an output end of the level shifter Level-Shifter is connected to a gate of the first transistor Q1, and a power supply end of the level shifter Level-Shifter is used for connecting a first power supply positive electrode VDD_HP; a source of the first transistor Q1 is used for connecting the first power supply positive electrode VDD_HP, and a drain of the first transistor Q1 serves as an output end of the pull-up circuit.

[0090] The pull-down circuit comprises a second transistor Q2, a third transistor Q3 and a fourth transistor Q4; wherein a gate of the second transistor Q2 is connected to a third output end Pulser_D of the bias circuit, a source of the second transistor Q2 is used for connecting a second power supply positive electrode VDD, a drain of the second transistor Q2 is connected to a drain of the third transistor Q3 and a gate of the third transistor Q3; the gate of the third transistor Q3 is connected to a gate of the fourth transistor Q4, a source of the third transistor Q3 and a source of the fourth transistor Q4 are connected together and connected to a first power supply negative electrode VSS_HN, and a drain of the fourth transistor Q4 serves as an output end of the pull-down circuit.

[0091] a high-voltage output pulse V PMUT In the pull-up process of the high-voltage output pulse V PMUT , Pulse_U- is low in the low-voltage domain, and the signal of Pulse_U- after being lifted by the level shifter Level-Shifter can control the first transistor Q1 to be turned on and completed, and the highest can rise to VDD_HP. In the pull-down process of the high-voltage output pulse V PMUT , Pulse_D is low in the low-voltage domain, the second transistor Q2 in the low-voltage domain VDD is first turned on, the drain level of the third transistor Q3 is raised, and then the fourth transistor Q4 below is turned on, so as to pull down V PMUT to VSS_HN. The electrode end connected to the PMUT device drives the ultrasonic transducer.

[0092] In order to verify the results of the pulse emission circuit in the embodiments of the present application, the embodiments of the present application construct an equivalent circuit schematic diagram of a dual-frequency PMUT transducer, as shown in Figure 6 .

[0093] As shown in Figure 6 , the equivalent circuit of the dual-frequency PMUT transducer comprises a ninth resistor R9, a tenth resistor R10, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first inductor L1 and a second inductor L2.

[0094] In this circuit, the first capacitor C1 forms the first branch; the ninth resistor R9, the second capacitor C2, and the first inductor L1 are connected in series to form the second branch; and the tenth resistor R10, the third capacitor C3, and the second inductor L2 are connected in series to form the third branch. The first, second, and third branches are connected in parallel, with the first terminal connected to V. PMUT The other end is grounded.

[0095] Taking a dual-frequency PMUT operating at 3MHz and 9.4MHz as an example, its impedance modulus frequency response is measured, and the series resonant frequency fs and parallel resonant frequency fp near its two resonant frequency points are observed. Combining the fractional bandwidth (e.g., BW=30%) of the PMUT device with the relationship between the quality factor Q and RLC, the values ​​of the ninth resistor R9, the tenth resistor R10, the first capacitor C1, the second capacitor C2, the third capacitor C3, the first inductor L1, and the second inductor L2 are calculated to simulate the PMUT as the load of the high-voltage Pulser output circuit.

[0096] The timing diagram of the dual-frequency amplitude-modulated multi-stage ultrasound imaging transmitter circuit is as follows: Figure 7 As shown, its working process is as follows:

[0097] In the first stage, control words are input to A2, A1, and A0 to control the MUX output of a stepped V-shaped output. MUX Voltage, such as V corresponding to control word 110. MUX The voltage is 3.6V. For a 7th order pulse wave, V MUX There are 7 steps, such as Figure 7 As shown.

[0098] In the second stage, the input EN enable signal is high, i.e., V PMUT_L As the positive input of the comparator, V MUX As the negative input of the comparator, the control word starts from 000 and increments accordingly. V MUX A rapid increase, then V PMUT_L Less than V MUX The comparator outputs V STA_COM When the voltage is low, Pulser_U follows V during this phase. STA_COM Subsequently, the Level-Shifter lifts the transistor, causing the first transistor Q1 to conduct, thus completing V. PMUT The signal pull-up process.

[0099] In the third stage, when the EN enable signal is set to low, i.e., V... PMUT_L As the negative input of the comparator, V MUX As the positive input of the comparator, the control word decreases from a large value. As the control word decreases, V... MUX A rapid decline results in V. MUX Less than V PMUT_L, the comparator output V STA_COM is low, Pulser_D follows V STA_COM , Q2 is turned on by Pulser_D, Q3 and Q4 are further turned on, and V PMUT is pulled down.

[0100] Taking 9.4MHz frequency as an example, the output of 3-order, 5-order and 7-order pulse signals are simulated respectively, as shown in Figure 8 , Figure 9 and Figure 10 . It can be seen that when EN is high, V PMUT is the pull-up stage, and when EN is low, it is the pull-down stage. The output of 3-order pulse, i.e. V PMUT has 3 level steps in the pull-up and pull-down processes respectively, as shown in Figure 8 ; the output of 5-order pulse, i.e. V PMUT has 5 level steps in the pull-up and pull-down processes respectively, as shown in Figure 9 ; the output of 7-order pulse, i.e. V PMUT has 7 level steps in the pull-up and pull-down processes respectively, as shown in Figure 10 . The greater the peak-to-peak value of the pulse is, the lower the frequency is, and the easier the multiple steps are to achieve.

[0101] Based on the pulse transmitting circuit proposed in the foregoing embodiments, the application provides a control method of the pulse transmitting circuit, and the corresponding flow chart is shown in Figure 11 .

[0102] As shown in Figure 11 , the control method of the pulse transmitting circuit comprises:

[0103] S1100: obtaining a target amplitude, a target frequency and a target step number of an output pulse.

[0104] S1200: controlling a threshold voltage according to the target amplitude, the target frequency or the target step number to change at least one of the frequency, the amplitude and the step number of the target pulse; wherein the target frequency, the target amplitude and the target step number of the output pulse are in positive correlation with the frequency, the amplitude and the step number of the threshold voltage respectively.

[0105] In the embodiments of the application, the threshold voltage is controlled to change at least one of the frequency, the amplitude and the step number of the pulse output by the pulse circuit; wherein the frequency, the amplitude and the step number of the threshold voltage are in positive correlation with the frequency, the amplitude and the step number of the pulse respectively, so that the output pulse PMUT of the pulse transmitting circuit improves the ultrasonic imaging quality of PMUT for different ultrasonic imaging requirements of different penetration depths.

[0106] In a possible implementation, the pulse circuit includes a pull-up circuit and a pull-down circuit, an output terminal of the pull-up circuit and an output terminal of the pull-down circuit serving as an output terminal of the pulse generation circuit; the pull-up circuit includes a level shifter and a first transistor; wherein a first input terminal and a second input terminal of the level shifter are connected to a first output terminal and a second output terminal of the bias circuit respectively, an output terminal of the level shifter is connected to a gate of the first transistor, and a power terminal of the level shifter is used to connect to a first power supply positive pole; a source of the first transistor is used to connect to the first power supply positive pole, and a drain of the first transistor serves as the output terminal of the pull-up circuit; the pull-down circuit includes a second transistor, a third transistor and a fourth transistor; wherein a gate of the second transistor is connected to a third output terminal of the bias circuit, a source of the second transistor is used to connect to a second power supply positive pole, a drain of the second transistor is connected to a drain of the third transistor and a gate of the third transistor; a gate of the third transistor is connected to a gate of the fourth transistor, a source of the third transistor and a source of the fourth transistor are connected together and connected to a first power supply negative pole, and a drain of the fourth transistor serves as the output terminal of the pull-down circuit.

[0107] In a possible implementation, the bias circuit includes a logic circuit, a first bias circuit, a second bias circuit and a first inverter; the first bias circuit includes a fifth transistor, a sixth transistor and a first switch device; a drain and a gate of the fifth transistor are connected together and connected to a second power supply positive pole through a first current source, a source of the fifth transistor is grounded, and a gate of the fifth transistor is connected to a first terminal of the first switch device; a second terminal of the first switch device is connected to a drain of the sixth transistor and a first input terminal of the level shifter, and a source of the sixth transistor is grounded; the second terminal of the first switch device is connected to a second input terminal of the level shifter through the first inverter; the second bias circuit includes a seventh transistor, an eighth transistor and a second switch device; a source of the seventh transistor is connected to the second power supply positive pole, a drain and a gate of the seventh transistor are connected together and grounded through a second current source, and a gate of the seventh transistor is connected to a first terminal of the second switch device; a second terminal of the second switch device is connected to a drain of the eighth transistor and a gate of the second transistor; a source of the eighth transistor is connected to the second power supply positive pole; the logic circuit is configured to generate a first signal, a second signal, a third signal and a fourth signal according to an output signal of the comparator circuit and an enable signal; wherein the first signal and the second signal are used to control the first switch device to be turned on and the sixth transistor to be turned off, or the first switch device to be turned off and the sixth transistor to be turned on, and the third signal and the fourth signal are used to control the second switch device to be turned on and the eighth transistor to be turned off, or the second switch device to be turned off and the eighth transistor to be turned on.

[0108] In a possible implementation, the logic circuit includes a second inverter, a third inverter, a first AND gate, a second AND gate, a fourth inverter, and a fifth inverter; an input end of the second inverter is connected to the enable end, and an output end of the second inverter is connected to a first input end of the first AND gate; a second input end of the first AND gate is connected to an output end of the third inverter, and an output end of the first AND gate is connected to an input end of the fourth inverter; an input end of the third inverter is connected to an output end of the comparator circuit, and an output end of the third inverter is connected to a first input end of the second AND gate; a second input end of the second AND gate is connected to the enable end, and an output end of the second AND gate is connected to an input end of the fifth inverter.

[0109] In a possible implementation, the threshold voltage circuit includes a multiplexer and a series resistor group string, the series resistor group string includes n resistors, n is an integer greater than or equal to 2; one of the input ends of the multiplexer is connected to the power supply, and the other input ends are respectively connected to the intersection points of two resistors in the series resistor group string, and a control end of the multiplexer is connected to the controller; a first end of the series resistor group string is connected to the power supply, and a second end of the series resistor group string is grounded.

[0110] In a possible implementation, the comparator circuit includes a first NOR gate, a second NOR gate, a sixth inverter, a seventh inverter, and m cascaded differential operational amplifiers, m is an integer greater than or equal to 2; a first input end and a second input end of a first differential operational amplifier are respectively connected to a node (i.e., a second end of a first capacitor) at which an output end of the threshold voltage circuit and an output end of the pulse generation circuit are connected through first capacitor voltage division after being chopped and modulated by a front-end switch, and a first output end and a second output end of an mth differential operational amplifier are respectively connected to an input end of the sixth inverter and an input end of the seventh inverter; an output end of the sixth inverter is connected to a first input end of the first NOR gate, and an output end of the seventh inverter is connected to a second input end of the second NOR gate; an output end of the first NOR gate is connected to a first input end of the second NOR gate, and an output end of the second NOR gate is connected to a second input end of the first NOR gate.

[0111] In a possible implementation, the pulse emission circuit further includes a first capacitor and a second capacitor; a first end of the first capacitor is connected to an output end of the pulse generation circuit, a second end of the first capacitor is connected to a first end of the second capacitor and a second input end of the comparator circuit; and a second end of the second capacitor is grounded.

[0112] In a possible implementation, referring to Figure 12 FIG. 1 is a schematic diagram of a control device provided by an embodiment of the present application.

[0113] The control device can include a memory 1011 and a processor 1012. The processor 1012 can be connected to the converter and can drive various transistors and switching devices in the pulse emission circuit to perform switching actions. For example, Figure 12As shown, the memory can be random access memory (RAM), flash memory, read only memory (ROM), EPROM memory, Electronic Programmable ROM (EPROM), registers, hard disks, removable disks, or the like.

[0114] The memory 1011 can store computer instructions, when the computer instructions stored in the memory 1011 are executed by the processor 1012, the processor 1012 can be configured to execute the control method of the pulse transmitting circuit. The memory 1011 can also store data, such as the preset range, the preset threshold, and the like information involved in the above embodiments.

[0115] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disks, hard disks, magnetic tapes), or semiconductor media (such as solid state disks (SSD)), etc.

[0116] The embodiments of the present application also provide a readable storage medium for storing the method provided by the above embodiments. For example, random access memory (RAM), flash memory, read only memory (ROM), EPROM memory, non-volatile read only memory (Electronic Programmable ROM, EPROM), registers, hard disks, removable disks, or any other form of storage medium in the art.

[0117] It should be noted that the various embodiments described in this specification are intended to be illustrative only and that the scope of the application is defined by the appended claims. Numerous modifications and adaptations thereof will be apparent to those skilled in the art without departing from the spirit and scope of the application.

[0118] The above description of disclosed embodiments is intended to be illustrative only and not limiting of the scope of the application. Numerous modifications of the embodiments described herein, as well as other embodiments, will be apparent to those skilled in the art without departing from the spirit or scope of the application. Therefore, the scope of the application is not to be limited to the embodiments shown in the figures but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pulse transmitting circuit, characterized in that, include: Controller, threshold voltage circuit, comparator circuit, bias circuit and pulse circuit; The threshold voltage circuit has multiple input terminals connected to different voltage levels, the output terminal of the threshold voltage circuit is connected to the first input terminal of the comparator circuit, and the control terminal of the threshold voltage circuit is connected to the controller. The second input terminal of the comparator circuit is connected to the low-voltage domain output terminal of the pulse circuit, and the output terminal of the comparator circuit is connected to the input terminal of the bias circuit. The output terminal of the bias circuit is connected to the input terminal of the pulse circuit; The output of the pulse circuit is used to connect to a dual-frequency piezoelectric micromechanical ultrasonic transducer. The controller is configured to control a threshold voltage to change at least one of the frequency, amplitude, and number of steps of the pulse output by the pulse circuit; wherein the frequency, amplitude, and number of steps of the pulse are positively correlated with the frequency, amplitude, and number of steps of the threshold voltage, respectively.

2. The pulse transmitting circuit according to claim 1, characterized in that, The pulse circuit includes a pull-up circuit and a pull-down circuit, and the output terminals of the pull-up circuit and the pull-down circuit serve as the output terminals of the pulse generation circuit. The pull-up circuit includes a level shifter and a first transistor; wherein, the first input terminal and the second input terminal of the level shifter are respectively connected to the first output terminal and the second output terminal of the bias circuit, the output terminal of the level shifter is connected to the gate of the first transistor, and the power supply terminal of the level shifter is used to connect to the positive terminal of the first power supply; the source terminal of the first transistor is used to connect to the positive terminal of the first power supply, and the drain terminal of the first transistor serves as the output terminal of the pull-up circuit. The pull-down circuit includes a second transistor, a third transistor, and a fourth transistor; wherein the gate of the second transistor is connected to the third output terminal of the bias circuit, the source of the second transistor is connected to the positive terminal of the second power supply, the drain of the second transistor is connected to the drain and gate of the third transistor; the gate of the third transistor is connected to the gate of the fourth transistor, the sources of the third transistor and the fourth transistor are connected together to the negative terminal of the first power supply, and the drain of the fourth transistor serves as the output terminal of the pull-down circuit.

3. The pulse transmitting circuit according to claim 2, characterized in that, The bias circuit includes a logic circuit, a first bias circuit, a second bias circuit, and a first inverter; The first bias circuit includes a fifth transistor, a sixth transistor, and a first switching device; the drain and gate of the fifth transistor are connected together and connected to the positive terminal of the second power supply through a first current source, the source of the fifth transistor is grounded, and the gate of the fifth transistor is connected to the first terminal of the first switching device; the second terminal of the first switching device is connected to the drain of the sixth transistor and the first input terminal of the level converter, and the source of the sixth transistor is grounded. The second terminal of the first switching device is connected to the second input terminal of the level converter through the first inverter; The second bias circuit includes a seventh transistor, an eighth transistor, and a second switching device; the source of the seventh transistor is connected to the positive terminal of the second power supply, the drain and gate of the seventh transistor are connected together and grounded through a second current source, and the gate of the seventh transistor is connected to the first terminal of the second switching device; the second terminal of the second switching device is connected to the drain of the eighth transistor and the gate of the second transistor; the source of the eighth transistor is connected to the positive terminal of the second power supply. The logic circuit is configured to generate a first signal, a second signal, a third signal, and a fourth signal based on the output signal and enable signal of the comparator circuit; wherein the first signal and the second signal are configured to control the first switching device to be turned on and the sixth transistor to be turned off, or the first switching device to be turned off and the sixth transistor to be turned on, and the third signal and the fourth signal are configured to control the second switching device to be turned on and the eighth transistor to be turned off, or the second switching device to be turned off and the eighth transistor to be turned on.

4. The pulse transmitting circuit according to claim 3, characterized in that, The logic circuit includes a second inverter, a third inverter, a first AND gate, a second AND gate, a fourth inverter, and a fifth inverter; The input terminal of the second inverter is connected to the enable terminal, and the output terminal of the second inverter is connected to the first input terminal of the first AND gate; The second input terminal of the first AND gate is connected to the output terminal of the third inverter, and the output terminal of the first AND gate is connected to the input terminal of the fourth inverter; The input terminal of the third inverter is connected to the output terminal of the comparator circuit, and the output terminal of the third inverter is connected to the first input terminal of the second AND gate; The second input terminal of the second AND gate is connected to the enable terminal, and the output terminal of the second AND gate is connected to the input terminal of the fifth inverter.

5. The pulse transmitting circuit according to any one of claims 1-4, characterized in that, The threshold voltage circuit includes: a multiplexer and a series resistor string, wherein the series resistor string includes n resistors, where n is an integer greater than or equal to 2; One of the input terminals of the multiplexer is connected to a power supply, and the other input terminals are respectively connected to the intersection of two resistors in the series resistor string. The control terminal of the multiplexer is connected to the controller. The first end of the series resistor string is used to connect to the power supply, and the second end of the series resistor string is grounded.

6. The pulse transmitting circuit according to any one of claims 1-4, characterized in that, The comparator circuit includes: a first NOR gate, a second NOR gate, a sixth inverter, a seventh inverter, a chopper modulation pre-switch, and m cascaded differential operational amplifiers, where m is an integer greater than or equal to 2. The first and second input terminals of the chopper modulation preamplifier switch are respectively connected to the output terminal of the threshold voltage circuit and the low voltage domain output terminal of the pulse generation circuit. The first and second output terminals of the chopper modulation preamplifier switch are respectively connected to the first and second input terminals of the first differential operational amplifier among the m differential operational amplifiers. The first and second output terminals of the m-th differential operational amplifier are respectively connected to the input terminal of the sixth inverter and the input terminal of the seventh inverter. The output of the sixth inverter is connected to the first input of the first NOR gate, and the output of the seventh inverter is connected to the second input of the second NOR gate. The output of the first NOR gate is connected to the first input of the second NOR gate, and the output of the second NOR gate is connected to the second input of the first NOR gate.

7. The pulse transmitting circuit according to claim 1, characterized in that, The pulse transmitting circuit also includes: a first capacitor and a second capacitor; The first terminal of the first capacitor is connected to the output terminal of the pulse generation circuit, and the second terminal of the first capacitor is connected to the first terminal of the second capacitor and the second input terminal of the comparator circuit. The second terminal of the second capacitor is grounded.

8. A control method for a pulse transmitting circuit, characterized in that, The pulse emission circuit includes a threshold voltage circuit, a comparator circuit, a bias circuit, and a pulse circuit. The multiple input terminals of the threshold voltage circuit are connected to different voltage levels. The output terminal of the threshold voltage circuit is connected to the first input terminal of the comparator circuit, and the control terminal of the threshold voltage circuit is connected to the controller. The output terminal of the comparator circuit is connected to the input terminal of the bias circuit. The output terminal of the bias circuit is connected to the input terminal of the pulse circuit. The output terminal of the pulse circuit is used to connect to a dual-frequency piezoelectric micromechanical ultrasonic transducer. The methods include: Obtain the target amplitude, target frequency, and target number of steps of the output pulse; The threshold voltage is controlled according to the target amplitude, the frequency, or the target number of steps to change at least one of the frequency, amplitude, and number of steps of the output pulse; wherein the target frequency, the target amplitude, and the target number of steps of the output pulse are positively correlated with the frequency, amplitude, and number of steps of the threshold voltage, respectively.

9. A control device, characterized in that, It includes a processor and a memory, the memory being used to store programs, instructions, or code, and the processor being used to execute the programs, instructions, or code in the memory to perform the control method as described in claim 8.

10. A computer-readable storage medium, characterized in that, The system contains a computer program that is loaded by a processor to execute the control method as described in claim 8.

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