Data reading and writing method, system, computer device and storage medium

Abstract

The application relates to the computer technical field, in particular to a data read-write method, system, computer device and storage medium. The data read-write method comprises the following steps: obtaining to-be-processed data in a main device, and splitting the to-be-processed data into multiple data units; determining data behaviors of data in each data unit; if the data behavior is a read data behavior, pre-fetching data corresponding to the read data behavior to a cache memory; if the data behavior is a write data behavior, writing corresponding data into the main memory; when a target device executes the read data behavior, reading data corresponding to the read data behavior from the cache memory based on a read behavior identifier; and when the target device executes the write data behavior, writing corresponding data into the main memory based on a write behavior identifier. An efficient data read-write method is provided.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a data reading and writing method, system, computer device, and storage medium. Background Technology

[0002] In recent years, with the rapid development of various enterprises' businesses, the amount of data carried, processed, and interacted between the systems and subsystems used by these enterprises has also grown rapidly. Although the systems used by these enterprises are developed using top-tier enterprise-level architectures and have many advantages, the ultra-rapid growth in business volume has brought new challenges of big data and high concurrency to enterprise systems, putting significant pressure on the performance and stability of the entire core system.

[0003] Computer systems consist of a wide variety of hardware, and their I / O access performance varies greatly. To address data transfer between hardware devices with different I / O performance, caching technology was invented, and a series of caching strategies were subsequently developed. Caching improves the hit rate of cached content through well-designed algorithms such as data block partitioning, prefetching, sequential prefetching, and cache replacement. During data read and write operations, if data is read directly from main memory (also known as RAM), which is relatively large, it typically takes hundreds or even thousands of cycles to retrieve a single piece of data, resulting in a significant time consumption.

[0004] Therefore, there is an urgent need for a more efficient data reading method. Summary of the Invention

[0005] This application provides a data reading and writing method, system, computer device, and storage medium.

[0006] A first aspect of this application provides a data read / write method applied to a SOC caching system, the SOC caching system comprising at least: a main memory and a cache memory, the method comprising at least:

[0007] Obtain the data to be processed from the main device, and split the data to be processed into multiple data units;

[0008] Determine the data behavior of the data in each data unit; wherein the data behavior includes at least one of reading data behavior and writing data behavior;

[0009] If the data action is a read data action, the data corresponding to the read data action is prefetched into the cache memory; if the data action is a write data action, the corresponding data is written into the main memory.

[0010] When the target device performs the read data action, it reads the data corresponding to the read data action from the cache memory based on the read data action identifier; when the target device performs the write data action, it writes the corresponding data to the main memory based on the write data action identifier.

[0011] In an optional embodiment of this application, obtaining the data to be processed in the master device includes:

[0012] By polling and arbitrating multiple master devices through the access bus module, the target data unit corresponding to the target access bus module obtained by arbitration is sent to the high-speed cache memory for processing.

[0013] In an optional embodiment of this application, the polling arbitration of the multiple master devices via the access bus module includes:

[0014] Data access to each of the access bus modules is performed either in a pre-selected configuration order or in a random order.

[0015] In one optional embodiment of this application, splitting the data to be processed into multiple data units includes:

[0016] The data to be processed is divided into multiple initial data units according to the cache unit;

[0017] The feature initial data unit that spans an address range among the multiple initial data units is split into multiple sub-data units to obtain multiple data units; wherein the cache unit address ranges of each data unit do not overlap.

[0018] In one optional embodiment of this application, the step of writing the corresponding data to the main memory if the data action is a write data action includes:

[0019] The data corresponding to the write operation is prefetched into a pre-configured temporary storage unit;

[0020] If the data corresponding to the write operation can fill the data unit in the cache memory, then the data corresponding to the write operation in the temporary storage unit is controlled to be written into the cache memory.

[0021] In an optional embodiment of this application, the step of writing the corresponding data to the main memory if the data action is a write data action further includes:

[0022] If new data written to the cache memory replaces the old data in the cache memory, the cache memory is controlled to store the old data to the main memory through the temporary storage unit.

[0023] In an optional embodiment of this application, the above data read / write method further includes:

[0024] If the data corresponding to the write data action cannot fill the data unit in the cache memory, the temporary storage unit is controlled to merge and package the data read from the cache memory and the data corresponding to the write data action and then write them into the cache memory.

[0025] A second aspect of this application provides a data read / write system applied to a SOC caching system, wherein the SOC caching system includes at least: a main memory and a cache memory, and the data read / write system includes at least:

[0026] The splitting module is used to acquire the data to be processed in the main device and split the data to be processed into multiple data units;

[0027] A determination module is used to determine the data behavior of data in each data unit; wherein the data behavior includes at least one of reading data behavior and writing data behavior;

[0028] The first read / write behavior determination module is used to prefetch the data corresponding to the read data behavior into the high-speed cache memory if the data behavior is a read data behavior.

[0029] The second read / write behavior judgment module is used to write the corresponding data into the main memory if the data behavior is a write data behavior.

[0030] The data reading module is used to read the data corresponding to the read data action from the cache memory based on the read action identifier when the target device performs the read data action;

[0031] The data writing module is used to write the corresponding data into the main memory based on the write behavior identifier when the target device performs the write data behavior.

[0032] A third aspect of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0033] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims.

[0034] This application provides a data read / write method. The method involves dividing the data to be processed in a main device into multiple data units, then determining the data behavior of the data in each data unit. If the data behavior is a read behavior, the data corresponding to the read behavior is prefetched into a cache memory; if the data behavior is a write behavior, the corresponding data is written into the main memory. When the target device executes the read behavior, it reads the data corresponding to the read behavior from the cache memory based on the read behavior identifier; when the target device executes the write behavior, it writes the corresponding data into the main memory based on the write behavior identifier. Main memory is relatively large, typically requiring hundreds or even thousands of cycles to read a single piece of data, resulting in a long processing time. The data read / write method provided in this application prefetches data into a cache memory during data caching, allowing direct data retrieval from the main memory, significantly reducing the lookup time and providing a more efficient data read / write method. Furthermore, the cache memory has an extremely fast data transfer speed, approaching that of a CPU, further improving the efficiency of the data read / write method provided in this application. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0036] Figure 1 This is a schematic diagram illustrating an application scenario of the data read / write method provided in one embodiment of this application;

[0037] Figure 2 A flowchart illustrating a data read / write method provided in one embodiment of this application;

[0038] Figure 3 A flowchart illustrating a data read / write method provided in one embodiment of this application;

[0039] Figure 4 This is a schematic diagram of a data read / write system structure provided in one embodiment of this application;

[0040] Figure 5 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0041] In the process of developing this application, the inventors discovered that there is an urgent need for a more efficient data reading method.

[0042] To address the aforementioned issues, this application provides a data reading and writing method, system, computer device, and storage medium.

[0043] The solutions in this application embodiment can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0044] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0045] The following is a brief description of the application environment of the data read / write method provided in the embodiments of this application:

[0046] Please see Figure 1 The data read / write method provided in this application is applied to a SOC caching system. The SOC caching system includes at least a main memory and a cache memory. When the data action is a read operation, the corresponding data is prefetched into the cache memory for the target device to read. When the data action is a write operation, the corresponding data is written into the main memory. Of course, the SOC caching system may also include... Figure 1 The data splitting module, data behavior recognition module, and cache control module in this embodiment of the data read / write method are implemented by different execution entities for each step. For example, the data splitting module is connected to each of the main devices through access bus modules. The data splitting module splits the data to be processed into multiple data units. The access bus module is a connection medium in a network topology where all network devices (nodes) are directly connected to a shared communication medium (i.e., a "bus"). This shared medium can be a coaxial cable, an optical fiber, or a printed circuit on a circuit board. The data splitting module can be a general-purpose processor, a smart network card, a multi-core processor, a storage controller, etc. For example, a programmable or multi-core processor, such as an FPGA or a multi-core ARM SoC, can be integrated on the network card. This embodiment of the application does not impose specific limitations and can be flexibly configured according to actual conditions. The data splitting module is as follows: Figure 1 In the bus2line, where, Figure 1In the term "bus2line," "bus" refers to a physical channel used to transmit data, addresses, or control signals. It also refers to a circuit or logic module that converts information on the bus into single-line signals. "2" stands for "to," indicating a conversion or connection. "line" refers to a cache line. "bus2line" means breaking down a long burst operation (which combines multiple fragmented, contiguous memory address operations into a single, continuous batch data transfer operation) that crosses cache line boundaries into multiple shorter burst operation lines that do not cross cache lines.

[0047] The data behavior recognition module is signal-connected to the data splitting module. The data behavior recognition module performs behavior recognition on the data in each data unit to determine the corresponding data behavior. The cache control module is signal-connected to the data behavior recognition module, the main memory, and the cache memory. When the data behavior is read data, the cache control module prefetches the corresponding data into the cache memory for the target device to read; when the data behavior is write data, it writes the corresponding data into the main memory. Of course, the execution entity for all steps of the data read / write method provided in this application embodiment can be a processor or a controller. The implementation of the data read / write method through this processor or controller is not specifically limited in this application embodiment and can be flexibly set according to actual conditions.

[0048] Please see Figure 2 The following embodiments use the aforementioned SOC caching system as the execution subject, and specifically illustrate the application of the data read / write method provided in this application to the aforementioned SOC caching system for data read / write. The data read / write method provided in this application includes the following steps 201-204:

[0049] Step 201: Obtain the data to be processed from the main device and split the data to be processed into multiple data units;

[0050] There are multiple master devices, each storing data to be processed. A master device is a component capable of initiating and controlling data transfer operations, corresponding to a slave device. Each master device can be a CPU, direct memory access controller, graphics processor, network controller, or storage controller, etc., without exhaustive list; any electronic device that requires internal data processing is acceptable. A data unit refers to a single, indivisible execution unit that bundles a series of operations into a single, undifferentiated unit that either all succeeds or all fails.

[0051] Step 202: Determine the data behavior of the data in each data unit; wherein the data behavior includes at least one of reading data behavior and writing data behavior;

[0052] In this embodiment, each master device's bus access module supports writestream / readstream functionality. The data behavior identification module includes at least two independent modules: a read behavior identification module and a write behavior identification module. The read behavior identification module is connected to the data splitting module, the cache control module, and the cache memory, and is used to identify and determine the read behavior of data in each data unit. The write behavior identification module is connected to the data splitting module, the cache control module, and the main memory, and is used to identify and determine the write behavior of data in each data unit. The readstream module can identify a large number of consecutive read operations and perform corresponding processing, such as predicting the data needed by the master device and pre-fetching the data into the cache memory to improve data reading efficiency. The writestream module can identify a large number of consecutive write operations and perform corresponding processing, such as writing downstream in cache lines and not allocating data to the cache memory, thereby improving data transfer efficiency.

[0053] The data behavior recognition module is used to perform behavior recognition on the data in each data unit and determine the corresponding data behavior.

[0054] Reading and writing data behaviors can be determined by signals, hardware circuits, or software, as shown in Table 1 below:

[0055] Table 1

[0056]

[0057] Step 203: If the data behavior is a read data behavior, then the data corresponding to the read data behavior is prefetched into the cache memory; if the data behavior is a write data behavior, then the corresponding data is written into the main memory.

[0058] After identifying a series of consecutive read data actions, the data is read back from the main memory in advance according to the read data address in the read data action and placed into the cache memory for future retrieval. In this embodiment, both the main memory and the cache memory are used as memory, and their characteristics differ as shown in Table 2 below:

[0059] Table 2

[0060]

[0061] Step 204: When the target device performs the read data action, it reads the data corresponding to the read data action from the cache memory based on the read data action identifier; when the target device performs the write data action, it writes the corresponding data to the main memory based on the write data action identifier.

[0062] This application provides a data read / write method. The method involves dividing the data to be processed in a main device into multiple data units, then determining the data behavior of the data in each data unit. If the data behavior is a read behavior, the data corresponding to the read behavior is prefetched into a cache memory; if the data behavior is a write behavior, the corresponding data is written into the main memory. When the target device executes the read behavior, it reads the data corresponding to the read behavior from the cache memory based on the read behavior identifier; when the target device executes the write behavior, it writes the corresponding data into the main memory based on the write behavior identifier. Main memory is relatively large, typically requiring hundreds or even thousands of cycles to read a single piece of data, resulting in a long processing time. The data read / write method provided in this application prefetches data into a cache memory during data caching, allowing direct data retrieval from the main memory, significantly reducing the lookup time and providing a more efficient data read / write method. Furthermore, the cache memory has an extremely fast data transfer speed, approaching that of a CPU, further improving the efficiency of the data read / write method provided in this application.

[0063] In an optional embodiment of this application, step 201, obtaining the data to be processed from the master device, includes the following steps:

[0064] By polling and arbitrating multiple master devices through the access bus module, the target data unit corresponding to the target access bus module obtained by arbitration is sent to the high-speed cache memory for processing.

[0065] In this embodiment, the arbitration mechanism for each access bus module connected to the master device is round-robin. The round-robin arbitration mechanism arbitrates each access bus module connected to the master device, and the target data unit corresponding to the target access bus module obtained through arbitration is sent to the cache memory for further processing. Round-robin arbitration allows for sequential querying of each access bus module, preventing low-priority master devices from being "starved." Under high load, even a very high-priority device must wait for its turn before accessing the device again, ensuring that other devices also receive service. Round-robin arbitration typically requires only a counter or a state machine, switching to the next master device in each clock cycle. This means low hardware resource consumption (fewer gate circuits), low power consumption, and easy verification of its correctness.

[0066] In an optional embodiment of this application, the above-described step of polling and arbitrating multiple master devices through the access bus module includes the following steps:

[0067] Data access to each of the access bus modules is performed either in a pre-selected configuration order or in a random order.

[0068] That is, in this embodiment, the data processing mechanism of each access bus module connected to the master device signal is either sequential processing or out-of-order processing. In other words, each master device bus supports out-of-order processing, multiple buses are independent of each other and do not affect each other, support different data processing mechanisms, have high compatibility, and can also improve the efficiency of data caching.

[0069] In one optional embodiment of this application, the cache memory may include multiple reserved storage spaces. Each reserved storage space refers to a small block of high-speed, low-latency memory dedicated to a specific processor or computing unit. That is, multiple ways (a subset or "column" of the cache containing multiple cache lines and operating in parallel with other "ways") are reserved in the cache for use as main memory, and can be called local memory. These reserved storage spaces serve as backup storage for the main memory, temporarily storing the most critical data to facilitate backup when main memory space is insufficient, thereby improving the stability and reliability of the SOC caching system in this embodiment.

[0070] Please see Figure 3 In an optional embodiment of this application, step 201, which involves splitting the data to be processed into multiple data units, includes the following steps 301-302:

[0071] Step 301: Divide the data to be processed into multiple initial data units according to the cache unit;

[0072] Step 302: Split the cross-address range feature initial data unit in the multiple initial data units into multiple sub-data units to obtain multiple data units; wherein the cache unit address ranges of each data unit do not overlap.

[0073] The cache can be connected to multiple master devices, which access the cache through their respective access bus modules. For ease of processing, the data splitting module splits data transactions that span the cacheline (the smallest unit of data managed by the CPU cache, typically a contiguous block of 64 bytes) address range into multiple data transactions. After splitting, each data transaction does not cross the cacheline address range, facilitating data processing and improving the cache efficiency of the SOC cache system in this embodiment.

[0074] In an optional embodiment of this application, step 203 above, the step of writing the corresponding data to the main memory if the data action is a write data action, includes the following steps:

[0075] The data corresponding to the write operation is prefetched into a pre-configured temporary storage unit;

[0076] This application embodiment can configure multiple temporary storage units (line buffers) in the cache control module, and can also configure a control unit. The control unit is used to prefetch the data corresponding to the write data operation into the multiple temporary storage units; the temporary storage units (line buffers) cache the data. The data read / write process may include the following three situations:

[0077] In the first scenario: if the data corresponding to the write operation can fill the data unit in the cache memory, then the control unit controls the data corresponding to the write operation in the temporary storage unit to be written into the cache memory.

[0078] In the second scenario: if new data written to the cache memory replaces the old data in the cache memory, the control unit controls the cache memory to store the old data to the main memory through the temporary storage unit.

[0079] The third scenario: If the data corresponding to the write data action cannot fill the data unit in the cache memory, the control unit controls the temporary storage unit to merge and package the data read from the cache memory or the main memory with the data corresponding to the write data action and then write it into the cache memory.

[0080] For example, a write burst operation (which merges multiple scattered, contiguous memory address write operations into a single, continuous data transfer operation) typically follows this process: First, the data splitting module bus2line splits the cross-cacheline data unit transaction into multiple data unit transactions. The split data unit transactions are then arbitrated and sequentially entered into the temporary storage area line buffer. For data unit transactions that can fill the entire cacheline, the temporary storage area line buffer directly writes the data to the cache. If this causes other cachelines to be replaced (e.g., the space in the same way of the cache becomes full), dirty data (i.e., old data) may be replaced. The buffer writes the replaced dirty data to main memory to prevent data loss. For data transactions that cannot fill the entire cache line, since both the temporary storage area line buffer and the cache process data in units of cache lines, the data needs to be read back from the cache and merged with the data written by the data transaction. Of course, if the cache line does not exist in the cache, it needs to be read back from main memory and then written to the cache.

[0081] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0082] Please see Figure 4 One embodiment of this application provides a data read / write system 400 applied to a SOC caching system. The SOC caching system includes at least a main memory and a cache memory. The data read / write system 400 includes at least a splitting module 410, a determination module 420, a read / write behavior judgment module 430, and a data read / write module 440, wherein:

[0083] The splitting module 410 is used to acquire the data to be processed in the main device and split the data to be processed into multiple data units;

[0084] The determining module 420 is used to determine the data behavior of the data in each data unit; wherein the data behavior includes at least one of reading data behavior and writing data behavior;

[0085] The read / write behavior determination module 430 is used to prefetch the data corresponding to the read data behavior into the cache memory if the data behavior is a read data behavior; and to write the corresponding data into the main memory if the data behavior is a write data behavior.

[0086] The data read / write module 440 is used to read data corresponding to the read data action from the cache memory based on the read data action identifier when the target device performs the read data action; and to write the corresponding data to the main memory based on the write data action identifier when the target device performs the write data action.

[0087] In an optional embodiment of this application, the splitting module 410 is specifically used to poll and arbitrate multiple master devices through the access bus module, and send the target data unit corresponding to the target access bus module obtained by arbitration to the cache memory for processing.

[0088] In one optional embodiment of this application, the splitting module 410 is specifically used to process or out-of-order data access to each of the access bus modules according to a pre-selected configuration order.

[0089] In an optional embodiment of this application, the splitting module 410 is specifically used to split the data to be processed into multiple initial data units according to the cache unit; split the feature initial data units that span address ranges among the multiple initial data units into multiple sub-data units to obtain multiple data units; wherein the cache unit address ranges of each data unit do not overlap.

[0090] In an optional embodiment of this application, the read / write behavior judgment module 430 is specifically used to prefetch the data corresponding to the write data behavior to a pre-configured temporary storage unit; if the data corresponding to the write data behavior can fill the data unit in the cache memory, then the control unit controls the data corresponding to the write data behavior in the temporary storage unit to be written into the cache memory.

[0091] In an optional embodiment of this application, the read / write behavior judgment module 430 is specifically used to, if new data written to the cache memory replaces old data in the cache memory, then the control unit controls the cache memory to store the old data to the main memory through the temporary storage unit.

[0092] In an optional embodiment of this application, the read / write behavior judgment module 430 is specifically used to, if the data corresponding to the write data behavior cannot fill the data unit in the cache memory, then the control unit controls the temporary storage unit to merge and package the data read from the cache memory and the data corresponding to the write data behavior and write them into the cache memory.

[0093] For specific limitations regarding the data read / write system 400, please refer to the limitations on the data read / write methods described above, which will not be repeated here. Each module in the data read / write system 400 can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0094] In one embodiment, a computer device is provided, the internal structure of which can be as follows: Figure 5As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements one of the data read / write methods described above. It includes: memory and a processor; the memory stores a computer program; and the processor executes the computer program to implement any step of the data read / write method described above.

[0095] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can perform any of the steps in the data read / write method described above.

[0096] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0097] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0098] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0099] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0100] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0101] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data read / write method, characterized by, The method is applied to an SOC cache system, and the SOC cache system at least comprises a main memory and a cache memory, and the method at least comprises: acquiring to-be-processed data in a host device, and splitting the to-be-processed data into a plurality of data units; wherein the data units are cache units; determining data behaviors of data in each data unit; wherein the data behaviors at least include at least one of a read data behavior and a write data behavior; if the data behavior is the read data behavior, pre-fetching data corresponding to the read data behavior to the cache memory; if the data behavior is the write data behavior, pre-fetching data corresponding to the write data behavior to a pre-configured temporary storage unit; if the data corresponding to the write data behavior can fill the data units in the cache memory, controlling the data corresponding to the write data behavior in the temporary storage unit to be written into the cache memory; if new data written into the cache memory replaces old data in the cache memory, controlling the cache memory to store the old data to the main memory through the temporary storage unit; if the data corresponding to the write data behavior cannot fill the data units in the cache memory, controlling the temporary storage unit to write data read from the cache memory or the main memory and the data corresponding to the write data behavior into the cache memory after the data is packed; when a target device executes the read data behavior, reading data corresponding to the read data behavior from the cache memory based on a read behavior identifier; when the target device executes the write data behavior, writing corresponding data into the main memory based on a write behavior identifier.

2. The data read / write method of claim 1, wherein, The acquiring to-be-processed data in the host device comprises: performing polling arbitration on a plurality of the host devices through an access bus module, and sending target data units corresponding to a target access bus module obtained through arbitration to the cache memory for processing.

3. The data read / write method of claim 2, wherein, The performing polling arbitration on a plurality of the host devices through an access bus module comprises: performing data access on each of the access bus modules in a processing or out-of-order manner according to a pre-configured order.

4. The data read / write method of claim 2, wherein, The splitting the to-be-processed data into a plurality of data units comprises: splitting the to-be-processed data into a plurality of initial data units according to cache units; splitting characteristic initial data units in a plurality of the initial data units that span address ranges into a plurality of sub-data units to obtain a plurality of the data units; wherein cache unit address ranges of each of the data units do not overlap.

5. A data read-write system characterized by, The method is applied to an SOC cache system, and the SOC cache system at least comprises a main memory and a cache memory, and the data read-write system at least comprises: a splitting module, configured to acquire to-be-processed data in a host device, and split the to-be-processed data into a plurality of data units; wherein the data units are cache units; a determining module, configured to determine data behaviors of data in each data unit; wherein the data behaviors at least include at least one of a read data behavior and a write data behavior; a pre-fetching module, configured to, if the data behavior is the read data behavior, pre-fetch data corresponding to the read data behavior to the cache memory; if the data behavior is the write data behavior, a writing module, configured to pre-fetch data corresponding to the write data behavior to a pre-configured temporary storage unit; if the data corresponding to the write data behavior can fill the data units in the cache memory, control the data corresponding to the write data behavior in the temporary storage unit to be written into the cache memory; a storing module, configured to, if new data written into the cache memory replaces old data in the cache memory, control the cache memory to store the old data to the main memory through the temporary storage unit; a packing module, configured to, if the data corresponding to the write data behavior cannot fill the data units in the cache memory, control the temporary storage unit to write data read from the cache memory or the main memory and the data corresponding to the write data behavior into the cache memory after the data is packed; a reading module, configured to, when a target device executes the read data behavior, read data corresponding to the read data behavior from the cache memory based on a read behavior identifier; when the target device executes the write data behavior, write corresponding data into the main memory based on a write behavior identifier. The read-write behavior judging module is configured to: if the data behavior is a read data behavior, pre-fetch data corresponding to the read data behavior to the cache memory; if the data behavior is a write data behavior, pre-fetch data corresponding to the write data behavior to a pre-configured temporary storage unit; if the data corresponding to the write data behavior can fill data units in the cache memory, control the data corresponding to the write data behavior in the temporary storage unit to be written into the cache memory; if new data written into the cache memory replaces old data in the cache memory, control the cache memory to store the old data into the main memory through the temporary storage unit; if the data corresponding to the write data behavior cannot fill the data units in the cache memory, control the temporary storage unit to write data read from the cache memory or the main memory and the data corresponding to the write data behavior into the cache memory after the data is packed. The data read-write module is configured to: when a target device executes the read data behavior, read data corresponding to the read data behavior from the cache memory based on a read behavior identifier; and when the target device executes the write data behavior, write corresponding data into the main memory based on a write behavior identifier.

6. A computer device comprising: A memory and a processor, the memory storing a computer program, wherein the processor executes the computer program to implement the steps of the method in any one of claims 1 to 4.

7. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 4.

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