Kernel page table creation methods, devices, equipment, and readable storage media

Abstract

This application provides a kernel page table creation method, apparatus, electronic device, and computer-readable storage medium, comprising: dividing a kernel page table to be created for a multi-core processor into multiple different first segments; the multi-core processor includes at least two processor cores; each first segment corresponds one-to-one with a processor core; the kernel page table is data used by the operating system kernel to manage the memory of the multi-core processor; and controlling each processor core to configure page table entries in each first segment of the kernel page table to be created, thereby obtaining a first kernel page table for the multi-core processor. Embodiments of this application can transform serial processing into parallel processing, with each processor core independently configuring page table entries in different first segments of the kernel page table to be created simultaneously, reducing kernel initialization time and improving the startup efficiency of the multi-core processor. Furthermore, since each processor core of the multi-core processor participates in page table construction, it avoids the situation where other cores are idle during single-core serial execution, thus improving the utilization of computing resources.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a kernel page table creation method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] In modern operating systems, the kernel needs to establish kernel-mode page tables during the initialization phase to provide a unified virtual address space for memory management, process scheduling, and operation of multi-core processors.

[0003] In related technologies, the entire kernel page table construction is usually completed independently by the bootstrap CPU in a multi-core processor.

[0004] However, in related technologies, the method of independently building the entire kernel page table by starting the processor core results in long kernel initialization time and low startup efficiency for multi-core processors. Summary of the Invention

[0005] This application provides a kernel page table creation method, apparatus, electronic device, and computer-readable storage medium to solve problems in related technologies.

[0006] In a first aspect, embodiments of this application provide a kernel page table creation method, the method comprising:

[0007] The kernel page table to be built for a multi-core processor is divided into multiple different first segments; the multi-core processor includes at least two processor cores; the first segment corresponds one-to-one with the processor core; the kernel page table is the data used by the operating system kernel to manage the memory of the multi-core processor.

[0008] The system controls each processor core to configure page table entries for each first segment of the kernel page table to be established, thereby obtaining the first kernel page table of the multi-core processor.

[0009] Secondly, embodiments of this application provide a kernel page table creation apparatus, the apparatus comprising: a partitioning module and a control module.

[0010] The partitioning module is used to divide the kernel page table to be built in a multi-core processor into multiple different first segments; the multi-core processor includes at least two processor cores; the first segment corresponds one-to-one with the processor core; the kernel page table is a data structure for the operating system kernel to manage the memory of the multi-core processor;

[0011] The control module is used to control each processor core to configure page table entries in each first segment of the kernel page table to be established, so as to obtain the first kernel page table of the multi-core processor.

[0012] Thirdly, embodiments of this application also provide an electronic device, including a processor;

[0013] Memory used to store the processor's executable instructions;

[0014] The processor is configured to execute the instructions to implement the method of the first aspect.

[0015] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0016] This embodiment of the application divides the kernel page table to be built in a multi-core processor into multiple different first segments, and controls each processor core to configure page table entries in each first segment of the kernel page table to be built, thus obtaining the first kernel page table of the multi-core processor. This can transform serial processing into parallel processing. Each processor core independently configures page table entries in different first segments of the kernel page table to be built simultaneously, reducing the kernel initialization time, improving the kernel page table construction efficiency, and shortening the multi-core processor startup time, thereby improving the multi-core processor startup efficiency. Furthermore, since all processor cores of the multi-core processor participate in page table construction, it can avoid the situation where other cores are idle when a single core executes serially, thus improving the utilization of computing resources.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the steps of a kernel page table creation method provided in an embodiment of this application.

[0020] Figure 2 This is a flowchart of another kernel page table creation method provided in an embodiment of this application;

[0021] Figure 3 This is a block diagram of a kernel page table creation apparatus provided in an embodiment of this application;

[0022] Figure 4 This is a block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0025] In modern operating systems, the kernel needs to establish kernel-mode page tables during the initialization phase to provide a unified virtual address space for memory management, process scheduling, and operation of multi-core processors.

[0026] In related technologies, the entire kernel page table construction is usually completed independently by the boot processor core in a multi-core processor.

[0027] However, in related technologies, the method of independently building the entire kernel page table by starting the processor core results in long kernel initialization time and low startup efficiency for multi-core processors.

[0028] For example, taking the Linux operating system as an example, during the initialization phase, the operating system kernel independently completes the construction of the entire kernel page table by starting the boot processor core. Only after the page table is established is it sequentially woken up and completes its initialization. The application processor core (AP) refers to the other processor cores in a multi-core processor besides the boot processor core.

[0029] However, as the number of processor cores increases, memory capacity gradually expands. The method of a single processor core independently completing the entire kernel page table construction has gradually exposed the following problems. First, initialization takes a long time: the establishment of the kernel page table requires traversing and mapping a large number of physical memory regions. Especially in large memory, multi-core processors, single-core execution of this process will significantly increase kernel initialization time, resulting in low initialization efficiency.

[0030] Secondly, resource utilization is low: during the kernel page table construction process, other processor cores are in a waiting state and fail to participate in the utilization of computing resources, resulting in a waste of multi-core processor resources.

[0031] Thirdly, there is insufficient scalability: as the system scales up and the physical memory capacity continues to increase, the performance bottleneck of building page tables with a single core becomes more and more prominent, which is not conducive to improving system startup efficiency.

[0032] Against this background, embodiments of this application provide a kernel page table creation method that can improve kernel initialization efficiency.

[0033] Figure 1 This is a flowchart illustrating the steps of a kernel page table creation method provided in an embodiment of this application. Figure 1 As shown, the method may include steps 101-102.

[0034] Step 101: Divide the kernel page table to be built in the multi-core processor into multiple different first segments.

[0035] In this embodiment of the application, the complete kernel page table to be built can be divided according to the preset partitioning rules to obtain multiple different independent sub-segments, namely the first segment, and each first segment is exclusively constructed by a processor core.

[0036] Among them, a multi-core processor is essentially a piece of hardware, which includes at least two processor cores and is the central processing unit of a computer.

[0037] The first segment corresponds one-to-one with the processor cores of a multi-core processor. The first segment can be understood as an independent sub-segment after the complete kernel page table to be built is logically divided, and each first segment is exclusively built by one processor core.

[0038] The kernel page table is the data used by the operating system kernel to manage the memory of a multi-core processor. Essentially, the kernel page table is a data structure created and maintained by the operating system kernel and stored in physical memory. The kernel page table records the mapping relationship between virtual addresses and physical addresses; for example, each entry in the kernel page table records the correspondence between a kernel virtual address segment and a physical address segment. The kernel page table must cover the entire kernel virtual address range to ensure that the virtual addresses of kernel code, data, stack, device addresses, etc., can all find their corresponding physical addresses.

[0039] The operating system kernel is essentially software used to manage all hardware resources (such as the memory of a multi-core processor).

[0040] Step 102: Control each processor core to configure page table entries for each first segment of the kernel page table to be established, and obtain the first kernel page table of the multi-core processor.

[0041] In this embodiment, after dividing the kernel page table to be built for a multi-core processor into multiple different first segments, each first segment can be assigned to each corresponding processor core. Each processor core can independently complete the page table entry configuration for its corresponding first segment. Each first segment can contain all page table entries required for mapping virtual addresses to physical addresses within the address range corresponding to that segment.

[0042] After each processor core has completed the page table entry configuration for each first segment of the kernel page table to be built, it can obtain the first kernel page table of the multi-core processor through the configured first segments. Each processor core of the multi-core processor can access the complete kernel address space through this first kernel page table.

[0043] This embodiment of the application divides the kernel page table to be built in a multi-core processor into multiple different first segments, and controls each processor core to configure page table entries in each first segment of the kernel page table to be built, thus obtaining the first kernel page table of the multi-core processor. This can transform serial processing into parallel processing. Each processor core independently configures page table entries in different first segments of the kernel page table to be built simultaneously, reducing the kernel initialization time, improving the kernel page table construction efficiency, and shortening the multi-core processor startup time, thereby improving the multi-core processor startup efficiency. Furthermore, since all processor cores of the multi-core processor participate in page table construction, it can avoid the situation where other cores are idle when a single core executes serially, thus improving the utilization of computing resources.

[0044] Figure 2 This is a flowchart illustrating the steps of another kernel page table creation method provided in an embodiment of this application. Figure 2 As shown, the method may include steps 201-202.

[0045] Step 201: Divide the kernel page table to be built for the multi-core processor into multiple different first segments; the multi-core processor includes at least two processor cores; the first segment corresponds one-to-one with the processor core; the kernel page table is the data of the operating system kernel for managing the memory of the multi-core processor.

[0046] Step 202: Control each processor core to configure page table entries for each first segment of the kernel page table to be established, and obtain the first kernel page table of the multi-core processor.

[0047] The specific implementation methods for steps 201-202 above can be found in the above description. Figure 1 Examples are not described here.

[0048] Optionally, step 202 above may include sub-steps 2021-2022.

[0049] Sub-step 2021: In response to the second processor core being in the running state, control the first processor core to send the instruction information for establishing the kernel page table to be established to the second processor core.

[0050] In this embodiment, the processor core includes a boot-type first processor core and an application-type second processor core. The boot-type first processor core can be understood as the first processor core in a multi-core processor to power on and execute the initialization program, capable of completing tasks from hardware initialization to waking up the second processor core and establishing the foundation for system operation. The first processor core can also be called the boot core. The application-type second processor core can be understood as any processor core in a multi-core processor other than the boot-type first processor core.

[0051] The instruction setup information is used to instruct each processor core to begin configuring page table entries for each first segment.

[0052] For example, after the first processor core wakes up the second processor core, the second processor core is in a running state. At this time, each of the second processor cores does not immediately begin page table entry configuration, but is in a state of waiting for instruction setup information. The first processor core can be controlled to send a start configuration signal to all second processor cores through an inter-processor interrupt (IPI), that is, to send instruction setup information.

[0053] Sub-step 2022: In response to the second processor core receiving the instruction to establish information, control the first processor core and the second processor core to configure page table entries for each first segment of the kernel page table to be established, so as to obtain the first kernel page table of the multi-core processor.

[0054] In this embodiment of the application, when the second processor core receives the instruction to establish information, it can control all second processor cores and the first processor core to start executing page table entry configuration simultaneously.

[0055] The system can control the first processor core to write the pre-defined first segments and their corresponding relationships with each processor core into a globally shared data structure. The correspondence between the first segments and each processor core can be represented by the correspondence between the identifier (ID) of each processor core and the start and end addresses of each first segment.

[0056] After the second processor core receives the instruction to establish the connection, the first and second processor cores can read the corresponding first segments in the shared data structure based on the correspondence between each first segment and each processor core. When the first and second processor cores read the corresponding first segments in the shared data structure, they can simultaneously begin configuring page table entries.

[0057] For example, if the first processor core is Core0, the second processor cores include Core1, Core2, Core3, Core4, Core5, Core6, Core7, and Core8. Core0 can send instruction setup information to Core1-Core8 respectively. After receiving the instruction setup information, Core1-Core8 can read their respective first segments in the shared data structure according to their respective processor core IDs, and configure page table entries for their respective first segments to obtain the first core page table of the multi-core processor.

[0058] In this embodiment, in response to the second processor core being in operation, the first processor core is controlled to send an instruction to the second processor core to establish a kernel page table. After receiving the instruction, the second processor core controls the first and second processor cores to configure page table entries for each first segment of the kernel page table to be established, thus obtaining the first kernel page table of the multi-core processor. This allows multiple processor cores to start configuring at the same time, with controllable differences in configuration progress, reducing the possibility of excessive progress differences, and fully utilizing the parallel capabilities of multi-core processors to maximize configuration efficiency.

[0059] Optionally, before the above sub-step 2021, the method may also include steps 203-205.

[0060] Step 203: Control the first processor core to establish the second kernel page table.

[0061] Step 204: Load and run the kernel initialization program for the multi-core processor according to the second kernel page table.

[0062] In this embodiment, regarding steps 203-204 above, the second kernel page table is used to support the basic data operation functions of the kernel initialization program for multi-core processors. The second kernel page table can also be understood as a minimal page table, which only ensures that the operating system can run the basic boot code and necessary memory accesses normally. The first processor core can construct a minimal page table through the boot code to ensure that the first processor core itself is in a normal operating state.

[0063] For example, after a system reset, the first processor core can enter the boot code, such as the Basic Input / Output System (BIOS) boot program or the kernel's head.S file. It first establishes a temporary page table covering only a 2MB memory region to load and run the kernel initialization program, ensuring the first processor core is in a normal operating state. This temporary page table guarantees that basic instructions and data access can proceed normally.

[0064] Step 205: Control the first processor core to send a first signal to the second processor core so that the second processor core is in running state.

[0065] In this embodiment, the first signal can also be understood as a wake-up signal. After the first processor core is in normal operating state, it can send the first signal to the second processor core to wake up the second processor core from hibernation state to runnable state, so that the second processor core can execute kernel initialization code, thereby enabling the second processor to participate in the subsequent kernel page table creation process.

[0066] For example, after the first processor core is running normally, it can identify the number and identifier (ID) of all second processor cores through a hardware interface to determine which second processor core needs to be woken up. Then, an Initialization Inter-Processor Interrupt (INITIPI) is sent to the second processor core to be woken up to put it into a hardware reset state. This INIPI forces the second processor core to stop its current execution, clears its internal registers (e.g., general-purpose registers, control registers), and puts it into a ready-to-start state. This INIPI does not specify where to start executing code; it simply prepares the second processor core to receive subsequent startup instructions. Subsequently, a startup address can be sent to the second processor core in the waiting-to-start state. Upon receiving the startup address, the second processor core jumps to that address and begins executing the startup code provided by the kernel, thus putting the second processor core into a running state.

[0067] This embodiment controls the first processor core to establish a second kernel page table, loads and runs the kernel initialization program of the multi-core processor according to the second kernel page table, and controls the first processor core to send a first signal to the second processor core to enable the second processor core to run. The configuration logic of the second kernel page table is simple, only needing to cover a small area of ​​critical memory, allowing the kernel initialization program to run first, avoiding the blocking of the initialization process due to dependence on complex multi-core configuration; it provides a software environment for multi-core parallel operation, and the first signal enables the multi-processor cores to start in an orderly manner, avoiding resource conflicts.

[0068] Optionally, step 202 above may also include sub-steps 2023-2024.

[0069] Sub-step 2023: Obtain the mapping rule data between the virtual address and physical memory corresponding to each processor core.

[0070] In this embodiment, the mapping rule data may include the translation relationship between virtual addresses and physical addresses, as well as attribute data such as access permissions (e.g., read permissions, write permissions, execute permissions, etc.) and caching policies. The memory management unit of a multi-core processor can achieve the translation from virtual addresses to physical addresses by querying the kernel page table when accessing memory.

[0071] For example, when obtaining the mapping rules data between virtual addresses and physical memory for each processor core, the virtual address space that needs to be mapped can first be determined. For instance, the entire kernel space from virtual address 0xC0000000 to 0xFFFFFFFF needs to be mapped. Available physical memory can be determined using information provided by the Basic Input / Output System (BIOS), the Unified Extensible Firmware Interface (UEFI), or the bootloader.

[0072] The offset is calculated based on the kernel's link address (i.e., virtual address) and actual load address (i.e., physical address). For example, the kernel code might be linked from address 0xC0000000, but actually loaded at physical address 0x1000000. Therefore, virtual address 0xC0000000 should map to physical address 0x1000000, virtual address 0xC0001000 should map to 0x1001000, and so on.

[0073] Based on the information generated above, the mapping rules data between virtual addresses and physical memory corresponding to each processor core can be obtained.

[0074] Sub-step 2024: Control each processor core to write each mapping rule data into the corresponding first segment to obtain the first kernel page table of the multi-core processor.

[0075] In this embodiment of the application, the mapping rule data may be organized into a temporary data structure or array. After obtaining each mapping rule data, each processor core can be controlled to determine the mapping rule data corresponding to the first segment, and then each processor core can be controlled to write each mapping rule data into the corresponding first segment.

[0076] For example, processor core 1 corresponds to the first segment a, processor core 2 corresponds to the first segment b, and processor core 3 corresponds to the first segment c. This can be understood as processor core 1 needing to fill page table entries in the first segment a, processor core 2 needing to fill page table entries in the first segment b, and processor core 3 needing to fill page table entries in the first segment c. After obtaining the mapping rule data between the virtual addresses and physical memory corresponding to processor cores 1, 2, and 3, processor core 1 can determine the mapping rule data corresponding to the first segment a and write it into the first segment a. Similarly, the mapping rule data corresponding to the first segment b can be written into the first segment b, and the mapping rule data corresponding to the first segment c can be written into the first segment c, thus obtaining the first core page table of the multi-core processor.

[0077] Optionally, the above sub-step 2024 may include sub-steps 20241-20242.

[0078] Sub-step 20241: Control each processor core to write each mapping rule data into the corresponding first segment, thereby obtaining each second segment of the first kernel page table.

[0079] Based on the above embodiments, for example, if processor core 1 corresponds to the first segment a, processor core 2 corresponds to the first segment b, and processor core 3 corresponds to the first segment c, then writing the mapping rule data corresponding to the first segment a into the first segment a will yield the second segment a', writing the mapping rule data corresponding to the first segment b into the first segment b will yield the second segment b', and writing the mapping rule data corresponding to the first segment c into the first segment c will yield the second segment c'.

[0080] Sub-step 20242: Perform synchronization processing on each second segment to obtain the first kernel page table.

[0081] In the embodiments of this application, the first kernel page table can be obtained by splicing or other synchronization processes on the above-mentioned second segments.

[0082] For example, mutexes can be used to synchronize the second sections, ensuring that only one core can enter the critical section at a time. By combining mutexes and counters, all cores are forced to wait within the critical section until they complete their page table configuration tasks before proceeding to the next operation. This synchronizes the execution progress of all cores, ensuring that all cores obtain the complete first kernel page table after completing their page table configuration tasks. The critical section is a core concept in operating systems and concurrent programming, referring to a code region that requires exclusive access to shared resources (such as memory, hardware, and data structures). In multi-core or multi-threaded environments, critical sections are used to resolve race conditions and ensure data consistency.

[0083] For example, if processor cores 1 through 5 execute page table entry configuration tasks simultaneously, and their execution progresses are different, each processor core can enter a critical section after finishing its execution and wait there. Once all processor cores 1 through 5 have finished executing their page table entry configuration tasks, they can be released together, thus obtaining the complete first kernel page table.

[0084] For example, a global barrier mechanism can also be used to synchronize the processing of each second segment. Specifically, a synchronization point can be determined first, forcing all cores to wait at the barrier point after completing the page table entry configuration task, until all cores reach that point. Taking the kernel page table construction of a multi-core processor as an example: each processor core works independently, filling its own page table segment in parallel; after each processor core completes its task, the global counter is decremented by one, and the processor core spins and waits at the barrier point until the counter reaches zero, indicating that all processor cores have completed the page table entry configuration task, at which point the first kernel page table can be determined.

[0085] Optionally, the above sub-step 20242 may include sub-steps 202421-202422.

[0086] Sub-step 202421: Obtain the synchronization identifier of each processor core.

[0087] Sub-step 202422: Under the condition that the synchronization identifier indicates that each processor core has written each mapping rule data into the corresponding first segment and obtained each second segment, determine the first kernel page table.

[0088] In this embodiment, the synchronization flag is used to indicate that the processor core has written the corresponding mapping rule data into the corresponding first segment. After each processor core completes the writing of the mapping data for its corresponding first segment, it updates the corresponding synchronization flag so that the synchronization flag indicates that the processor core has written the corresponding mapping rule data into the corresponding first segment. For example, when the processor cores include Core0-Core8, after Core0 completes the configuration of the page table entries for the corresponding first segment, it can update the synchronization flag to the "configured" flag; after Core1 completes the configuration of the page table entries for the corresponding first segment, it can update the synchronization flag to the "configured" flag; and so on. When Core0-Core8 have all updated their synchronization flags to the "configured" flag, the first kernel page table can be determined.

[0089] This embodiment obtains the synchronization flags of each processor core. Once the synchronization flags indicate that each processor core has written all mapping rule data into its corresponding first segment, and the second segments are obtained, the first kernel page table is determined. By checking all synchronization flags, it can be ensured that all mapping rule data for each first segment has been written, ensuring that the first kernel page table covers the entire address space, and subsequent memory accesses will not encounter errors due to missing segments.

[0090] Optionally, step 201 above may include sub-steps 2011-2013.

[0091] Sub-step 2011: Obtain the first range, start address, end address, and number of processor cores of the address space corresponding to the kernel page table to be built.

[0092] In this embodiment, the address space may include a virtual address space and a physical memory space. The first range can also be understood as the total address space size that the kernel page table needs to cover. For example, when the address space is physical memory space, if the physical memory is 64 gigabytes (GB), then the first range is 64GB. The total physical memory capacity can be read through the memory probe interface provided by the BIOS or UEFI (such as the e820 table).

[0093] The start address is the beginning of the address space, and the end address is the end of the address space. The number of processor cores refers to the total number of processor cores involved in page table construction in a multi-core processor (e.g., an 8-core processor has 8 cores). The number of processor cores can be determined through the Advanced Programmable Interrupt Controller (ACPI).

[0094] Sub-step 2012: Determine the second range of the address space corresponding to the first segment based on the first range of the address space and the number of processor cores.

[0095] In this embodiment of the application, the second range can be understood as the size of the address space covered by each first segment. The second range can be determined by the ratio of the first range to the number of processor cores, while also ensuring that each first segment is of equal size.

[0096] Sub-step 2013: Based on the start address, end address, and second range, divide the kernel page table to be built in the multi-core processor into multiple different first segments.

[0097] For example, taking the division of the kernel page table to be built into multiple different first segments based on the physical memory space as an example, when the physical memory capacity is 64GB and the number of processor cores is 8, the kernel page table to be built can be divided into 8 segments, each segment being 8GB in size. That is, each processor core configures page table entries for one 8GB page table segment. Specifically, Core0 can execute page table entry configuration for the 0GB~8GB segment; Core1 can execute page table entry configuration for the [8GB~16GB] segment; Core2 can execute page table entry configuration for the [16GB~24GB] segment; and so on, Core8 can execute page table entry configuration for the [56GB~64GB] segment.

[0098] In one embodiment, if the first range cannot be divided by the number of processor cores, for example, 65GB memory ÷ 8 cores = 8GB with a remainder of 1GB, then the size of the first segment corresponding to the first 7 processor cores can be controlled to be 8GB; the size of the first segment corresponding to the last processor core is 8GB + 1GB = 9GB, so that the last processor core takes on the remaining part, ensuring that the total range is fully covered.

[0099] This embodiment obtains the first range, start address, end address, and number of processor cores of the address space corresponding to the kernel page table to be built. Based on the first range and the number of processor cores, a second range of the address space corresponding to the first segment is determined. Then, based on the start address, end address, and second range, the kernel page table to be built for the multi-core processor is divided into multiple different first segments. This clear address range division ensures complete and non-overlapping kernel page table coverage, while also ensuring that the address space size responsible for each processor core is approximately consistent, reducing the risk of uneven resource allocation.

[0100] Optionally, step 201 above may also include sub-step 2014.

[0101] Sub-step 2014: If the number of levels of the kernel page table to be built is the same as the number of processor cores, divide each level of the kernel page table to be built into a first segment, resulting in multiple first segments.

[0102] In this embodiment, the kernel page table to be established includes at least two levels. When the number of levels of the kernel page table to be established is equal to the number of processor cores, each page table level can be directly assigned as a first segment to each processor core. Each processor core configures page table entries for each level of the kernel page table.

[0103] For example, modern processors typically employ a multi-level page table structure. Taking the x86_64 four-level page table as an example, the first level is the page global directory (PGD), the second level is the page upper directory (PUD), the third level is the page middle directory (PMD), and the fourth level is the page table entry (PTE). When there are four processor cores, a one-to-one correspondence can be used between the page table levels, the first segment, and the processor cores. For example, PGD corresponds to first segment 0 and Core0; PUD corresponds to first segment 1 and Core1; PMD corresponds to first segment 2 and Core2; and PTE corresponds to first segment 3 and Core3. This one-to-one correspondence allows each processor core to be assigned the task of building one level. After each level completes its construction, it needs to write its table base address to shared memory for the next level to populate the table entries.

[0104] In this embodiment, when the number of kernel page table levels to be built is the same as the number of processor cores, each level of the kernel page table to be built is divided into a first segment, resulting in multiple first segments. This provides a data foundation for the subsequent parallel construction of kernel page tables by multiple processor cores. At the same time, dividing the first segments according to the kernel page table levels can improve the parallel performance of multi-core systems in page table management operations.

[0105] Optionally, the above method may also include steps 206-207.

[0106] Step 206: According to the cache coherence protocol, mark the data in the page table storage area of ​​each processor core's cache as invalid data.

[0107] Step 207: Store the first kernel page table in the cache of each processor core.

[0108] In this embodiment, regarding steps 206-207, after the first page table is established, the private caches and Translation Lookaside Buffers (TLBs) of each processor core may still cache relevant data from the old kernel page table. This data can affect the operation of the operating system. For example, if Core0 modifies a page table entry but Core1's cache is not updated, it may use outdated mappings to access memory, leading to data errors or crashes. Alternatively, if Core0 changes the physical page at virtual address 0x1000 from A to B, but Core1's cache still retains the physical page at virtual address 0x1000 as A, this will also cause data errors or crashes.

[0109] This can be understood as marking or deleting this data according to the cache coherence protocol, or as causing all processor cores to discard cache copies of a specified memory range according to the cache coherence protocol. The first core page table is then stored in the caches of each processor core. This forces the data in the page table memory regions of all processor cores' caches to be consistent with main memory. The TLB (Page Table Buffer) is the page table cache of the Central Processing Unit (CPU), storing a fast mapping from virtual addresses to physical addresses. It can also be understood as caching frequently used data in the TLB.

[0110] This embodiment, based on the cache coherence protocol, marks the data in the page table storage area of ​​each processor core's cache as invalid data, and stores the first kernel page table in the cache of each processor core. This ensures global consistency of kernel page table data, avoids interference from dirty cache data, improves the efficiency of subsequent page table accesses, and reduces memory latency.

[0111] In summary, this embodiment of the application divides the kernel page table to be built in a multi-core processor into multiple different first segments, and controls each processor core to configure page table entries in each first segment of the kernel page table to be built, thus obtaining the first kernel page table of the multi-core processor. This transforms serial processing into parallel processing, with each processor core independently configuring page table entries in different first segments of the kernel page table to be built simultaneously. This reduces the kernel initialization time, improves the efficiency of kernel page table construction, and shortens the startup time of the multi-core processor, thereby improving the startup efficiency of the multi-core processor. Furthermore, since all processor cores of the multi-core processor participate in page table construction, it avoids the situation where other cores are idle during single-core serial execution, thus improving the utilization of computing resources.

[0112] This application also provides a kernel page table creation apparatus. Figure 3 This is a block diagram of a kernel page table creation apparatus provided in an embodiment of this application. Figure 3 As shown, the kernel page table creation device 300 may include a partitioning module 301 and a control module 302.

[0113] The partitioning module 301 is used to divide the kernel page table to be built in the multi-core processor into multiple different first segments; the multi-core processor includes at least two processor cores; the first segment corresponds one-to-one with the processor core; the kernel page table is a data structure for the operating system kernel to manage the memory of the multi-core processor;

[0114] The control module 302 is used to control each processor core to configure page table entries in each first segment of the kernel page table to be established, so as to obtain the first kernel page table of the multi-core processor.

[0115] Optionally, the processor core includes a first processor core of coordination type and a second processor core of execution type. The control module 302 is specifically used to control the first processor core to send an instruction to the second processor core to establish a kernel page table in response to the second processor core being in a running state; and to control the first processor core and the second processor core to configure page table entries in each first segment of the kernel page table to be established in response to the second processor core receiving the instruction to establish the kernel page table, thereby obtaining the first kernel page table of the multi-core processor.

[0116] Optionally, such as Figure 3 As shown, the kernel page table creation device 300 may further include a loading module 303.

[0117] The control module 302 is also used to control the first processor core to establish a second kernel page table; the second kernel page table is used to support the basic data operation functions of the kernel initialization program of the multi-core processor; the loading module 303 is used to load and run the kernel initialization program of the multi-core processor according to the second kernel page table; the control module 302 is also used to control the first processor core to send a first signal to the second processor core so that the second processor core is in the running state.

[0118] Optionally, the control module 302 is specifically used to obtain the mapping rule data between the virtual address and physical memory corresponding to each processor core; and to control each processor core to write the mapping rule data into the corresponding first segment to obtain the first kernel page table of the multi-core processor.

[0119] Optionally, the control module 302 is specifically used to control each processor core to write each mapping rule data into the corresponding first segment to obtain each second segment of the first kernel page table; and to perform synchronization processing on each second segment to obtain the first kernel page table.

[0120] Optionally, the control module 302 is specifically used to obtain the synchronization identifier of each processor core; the synchronization identifier is used to indicate that the processor core has written the corresponding mapping rule data into the corresponding first segment; when the synchronization identifier indicates that each processor core has written each mapping rule data into the corresponding first segment and obtains each second segment, the first kernel page table is determined.

[0121] Optionally, the partitioning module 301 is specifically used to obtain the first range, start address, end address, and number of processor cores of the address space corresponding to the kernel page table to be established; the address space includes virtual address space and physical memory space; based on the first range of the address space and the number of processor cores, the second range of the address space corresponding to the first segment is determined; based on the start address, end address, and second range, the kernel page table to be established for the multi-core processor is divided into multiple different first segments.

[0122] Optionally, the kernel page table to be established includes at least two levels. The partitioning module 301 is specifically used to divide each level of the kernel page table to be established into a first segment when the number of levels of the kernel page table to be established is the same as the number of processor cores, thereby obtaining multiple first segments.

[0123] Optionally, such as Figure 3 As shown, the kernel page table creation device 300 may further include a processing module 304.

[0124] The processing module 304 is used to mark the data in the page table storage area of ​​the cache of each processor core as invalid data according to the cache coherency protocol; and to store the first kernel page table into the cache of each processor core.

[0125] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0126] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0127] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0128] This application also provides a kernel page table creation apparatus, including a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors, and the one or more programs include methods for performing the methods described in one or more of the above embodiments.

[0129] This application also provides an electronic device. See also... Figure 4 , Figure 4 This is a block diagram illustrating an electronic device 400 according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0130] Reference Figure 4 The electronic device 400 may include one or more of the following components: processing component 402, memory 404, power supply component 406, multimedia component 408, audio component 410, input / output (I / O) interface 412, sensor component 414, and communication component 416.

[0131] Processing component 402 typically controls the overall operation of electronic device 400, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 402 may include one or more modules to facilitate interaction between processing component 402 and other components. For example, processing component 402 may include a multimedia module to facilitate interaction between multimedia component 408 and processing component 402.

[0132] Memory 404 is used to store various types of data to support the operation of electronic device 400. Examples of such data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, multimedia, etc. Memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0133] Power supply component 406 provides power to various components of electronic device 400. Power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 400.

[0134] Multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 408 includes a front-facing camera and / or a rear-facing camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a multimedia mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0135] Audio component 410 is used to output and / or input audio signals. For example, audio component 410 includes a microphone (MIC) used to receive external audio signals when electronic device 400 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 404 or transmitted via communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.

[0136] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0137] Sensor assembly 414 includes one or more sensors for providing state assessments of various aspects of electronic device 400. For example, sensor assembly 414 may detect the on / off state of electronic device 400, the relative positioning of components such as the display and keypad of electronic device 400, changes in position of electronic device 400 or a component of electronic device 400, the presence or absence of user contact with electronic device 400, orientation or acceleration / deceleration of electronic device 400, and temperature changes of electronic device 400. Sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 414 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0138] Communication component 416 facilitates wired or wireless communication between electronic device 400 and other devices. Electronic device 400 can access wireless networks based on communication standards, such as WiFi, carrier networks (such as 2G, 3G, 4G, or 5G), or combinations thereof. In one exemplary embodiment, communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 416 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0139] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of this application.

[0140] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, which can be executed by a processor 420 of an electronic device 400 to perform the above-described method. For example, the non-transitory storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0141] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the methods described in the above embodiments.

[0142] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0143] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for establishing a kernel page table, characterized in that, The method comprises: dividing a to-be-established kernel page table of a multi-core processor into a plurality of different first segments; the multi-core processor comprises at least two processor cores; the first segments correspond to the processor cores one by one; the kernel page table is data managed by an operating system kernel for managing memory of the multi-core processor; the processor cores comprise a first processor core of a coordination type and a second processor core of an execution type; controlling each of the processor cores to configure a page table entry for each of the first segments of the to-be-established kernel page table, to obtain a first kernel page table of the multi-core processor, comprising: in response to the second processor core being in a running state, controlling the first processor core to send indication establishment information of the to-be-established kernel page table to the second processor core; in response to the second processor core receiving the indication establishment information, controlling the first processor core and the second processor core to configure a page table entry for each of the first segments of the to-be-established kernel page table, to obtain the first kernel page table of the multi-core processor.

2. The method of claim 1, wherein, Before the step of controlling the first processor core to send the indication establishment information of the to-be-established kernel page table to the second processor core in response to the second processor core being in a running state, the method further comprises: controlling the first processor core to establish a second kernel page table; the second kernel page table is used to support a basic data running function of a kernel initialization program of the multi-core processor; loading and running the kernel initialization program of the multi-core processor according to the second kernel page table; controlling the first processor core to send a first signal to the second processor core, so that the second processor core is in a running state.

3. The method of claim 1, wherein, The step of controlling each of the processor cores to configure a page table entry for each of the first segments of the to-be-established kernel page table, to obtain a first kernel page table of the multi-core processor, comprises: obtaining each mapping rule data of a virtual address corresponding to each of the processor cores and a physical memory; controlling each of the processor cores to write each of the mapping rule data into a corresponding first segment, to obtain the first kernel page table of the multi-core processor.

4. The method of claim 3, wherein, The step of controlling each of the processor cores to write each of the mapping rule data into a corresponding first segment, to obtain the first kernel page table of the multi-core processor, comprises controlling each of the processor cores to write each of the mapping rule data into a corresponding first segment, to obtain each second segment of the first kernel page table; synchronizing each of the second segments, to obtain the first kernel page table.

5. The method of claim 4, wherein, The step of synchronizing each of the second segments, to obtain the first kernel page table, comprises: obtaining a synchronization identifier of each of the processor cores; the synchronization identifier is used to indicate that the processor core has written the corresponding mapping rule data into the corresponding first segment; in a case where the synchronization identifier indicates that each of the processor cores has written each of the mapping rule data into the corresponding first segment, to obtain each of the second segments, determining the first kernel page table.

6. The method of claim 1, wherein, The step of dividing a to-be-established kernel page table of a multi-core processor into a plurality of different first segments, comprises: obtaining a first range, a start address, an end address and a number of processor cores of an address space corresponding to the to-be-established kernel page table; the address space comprises a virtual address space and a physical memory space; determining a second range of the address space corresponding to the first section according to the first range of the address space and the number of processor cores; dividing the to-be-established kernel page table of the multi-core processor into a plurality of different first sections according to the start address, the end address and the second range.

7. The method of claim 1, wherein, The to-be-established kernel page table comprises at least two levels, and the dividing of the to-be-established kernel page table of the multi-core processor into a plurality of different first sections comprises: In a case where the number of levels of the to-be-established kernel page table is the same as the number of processor cores, each level of the to-be-established kernel page table is divided into a first section, thereby obtaining a plurality of first sections.

8. The method of claim 1, wherein, The method further comprises: According to a cache consistency protocol, marking data in a page table storage area in a cache of each processor core as invalid data; storing the first kernel page table into the cache of each processor core.

9. A kernel page table creation apparatus, characterized in that, The apparatus comprises: a division module configured to divide a to-be-established kernel page table of a multi-core processor into a plurality of different first sections; the multi-core processor comprises at least two processor cores; the first sections correspond to the processor cores one by one; the kernel page table is a data structure for operating system kernel management of memory of the multi-core processor; the processor cores comprise a first processor core of a coordination type and a second processor core of an execution type; a control module configured to control each processor core to perform page table entry configuration on each first section of the to-be-established kernel page table, thereby obtaining a first kernel page table of the multi-core processor, comprising: in response to the second processor core being in a running state, controlling the first processor core to send indication establishment information of the to-be-established kernel page table to the second processor core; in response to the second processor core receiving the indication establishment information, controlling the first processor core and the second processor core to perform page table entry configuration on each first section of the to-be-established kernel page table, thereby obtaining a first kernel page table of the multi-core processor.

10. An electronic device, comprising: comprise: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 8.

11. A computer readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method of any one of claims 1 to 8.

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