Gate drive circuit, display panel and display device

Abstract

The invention discloses a gate drive circuit, a display panel and a display device. In the gate drive circuit, an input module is electrically connected with an input signal end, a first clock end, a second clock end and a first node; the first node control module is electrically connected with an input signal end, a first clock end, a second clock end, a first power supply end, a second power supply end and a second node; the second node control module is electrically connected with a second node, a second power supply end and a third node respectively; the interlocking module is electrically connected with the first node, the third node and the first power supply end respectively; the output module is electrically connected with the first node, the third node, the first power supply end, the second power supply end and the output end; the first node control module comprises a target switch electrically connected with the second node, and the target switch is turned on in at least part of the time period when the input signal of the input signal end is the cut-off level. According to the embodiment of the invention, the stability of related nodes in the gate drive circuit can be improved, so that the performance of the gate drive circuit is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit, a display panel and a display device. BACKGROUND

[0002] The gate driving circuit is one of the indispensable circuits for driving the display panel to display. The gate driving circuit usually includes a plurality of shift registers cascaded, the shift registers are electrically connected with the sub-pixels of the display panel, and the signals output by the shift registers are used to control the state of the transistors in the sub-pixels, so as to drive the sub-pixels to emit light.

[0003] The stability of the signals output by the shift registers will affect the light emitting effect of the sub-pixels, therefore, how to optimize the performance of the shift registers is an important problem faced by the person skilled in the art. SUMMARY

[0004] The embodiments of the present application provide a gate driving circuit, a display panel and a display device, which can improve the stability of the related nodes in the gate driving circuit, thereby optimizing the performance of the gate driving circuit.

[0005] In a first aspect, the embodiments of the present application provide a gate driving circuit, including a plurality of shift registers cascaded, the shift registers including an input module, a first node control module, a second node control module, an interlocking module and an output module; the input module is electrically connected with an input signal end, a first clock end, a second clock end and a first node respectively, and is used to adjust the potential of the first node; the first node control module is electrically connected with the input signal end, the first clock end, the second clock end, a first power supply end, a second power supply end and a second node respectively, and is used to adjust the potential of the second node; the second node control module is electrically connected with the second node, the second power supply end and a third node respectively, and is used to adjust the potential of the third node; the interlocking module is electrically connected with the first node, the third node and the first power supply end respectively, and is used to control the potentials of the first node and the third node; the output module is electrically connected with the first node, the third node, the first power supply end, the second power supply end and an output end respectively, and is used to control the signal output by the output end; the first node control module includes a target switch electrically connected with the second node, and the target switch is turned on in at least part of the period when the input signal of the input signal end is at the off level.

[0006] In a possible implementation manner of the first aspect, the working process of the shift register includes a plurality of target periods in the period when the input signal of the input signal end is at the off level, and the target switch is turned on in the target periods.

[0007] In a possible implementation manner of the first aspect, the length of the target period is less than or equal to 2*H, and H is the row scanning length of the display panel.

[0008] In a possible implementation of the first aspect, the target period has a length less than or equal to n*T, T represents a period of a clock signal on the clock terminal, and n is less than or equal to 2.

[0009] In a possible implementation of the first aspect, n = 1.

[0010] In a possible implementation of the first aspect, the first node control module includes a first sub-control module and a second sub-control module. The first sub-control module is electrically connected to the first power terminal, the second power terminal, the input signal terminal, the first clock terminal, the second clock terminal, and the fourth node respectively, and is configured to adjust the potential of the fourth node. The second sub-control module is electrically connected to the input signal terminal, the first power terminal, the first clock terminal, the fourth node, and the second node respectively, and is configured to adjust the potential of the second node. The second sub-control module includes a target switch, a gate electrode of the target switch is electrically connected to the fourth node, and the fourth node is at an on level during at least a part of a period in which the input signal on the input signal terminal is at an off level.

[0011] In a possible implementation of the first aspect, during a period in which the input signal on the input signal terminal is at an off level, a signal on the second power terminal is written to the fourth node, and a signal on the first power terminal is not written to the fourth node.

[0012] In a possible implementation of the first aspect, when the input signal on the input signal terminal and a first clock signal on the first clock terminal are both at an on level, a signal on the first power terminal is written to the fourth node, and a signal on the second power terminal is not written to the fourth node.

[0013] In a possible implementation of the first aspect, the first sub-control module includes a first control unit and a second control unit. The first control unit is electrically connected to the input signal terminal, the first clock terminal, the first power terminal, and the fourth node respectively, and is configured to adjust the potential of the fourth node, and the input signal terminal and the first clock terminal are configured to control whether the first control unit is turned on. The second control unit is electrically connected to the second clock terminal, the second power terminal, and the fourth node respectively, and is configured to adjust the potential of the fourth node, and the second clock terminal is configured to control whether the second control unit is turned on.

[0014] In a possible implementation of the first aspect, an off level of the first clock terminal is the same as a level of the first power terminal.

[0015] In a possible implementation manner of the first aspect, the second sub-control module includes a first transistor and a second transistor, a gate of the first transistor is electrically connected with the input signal end, a first electrode of the first transistor is electrically connected with the first power supply end, and a second electrode of the first transistor is electrically connected with the second node; a gate of the second transistor is electrically connected with the fourth node, a first electrode of the second transistor is electrically connected with the first clock end, a second electrode of the second transistor is electrically connected with the second node, and the target switch includes the second transistor.

[0016] In a possible implementation manner of the first aspect, the second sub-control module further includes a first capacitor, and the first capacitor is electrically connected between the second node and the fourth node.

[0017] In a possible implementation manner of the first aspect, the first sub-control module includes a third transistor, a fourth transistor and a fifth transistor, a gate of the third transistor is electrically connected with the input signal end, a first electrode of the third transistor is electrically connected with the first power supply end, a second electrode of the third transistor is electrically connected with a first electrode of the fourth transistor, a gate of the fourth transistor is electrically connected with the first clock end, a second electrode of the fourth transistor is electrically connected with the fourth node, a gate of the fifth transistor is electrically connected with the second clock end, a first electrode of the fifth transistor is electrically connected with the second power supply end, and a second electrode of the fifth transistor is electrically connected with the fourth node.

[0018] In a possible implementation manner of the first aspect, the input module includes a sixth transistor and a second capacitor, a gate of the sixth transistor is electrically connected with the first clock end, a first electrode of the sixth transistor is electrically connected with the input signal end, a second electrode of the sixth transistor is electrically connected with the first node, a first electrode of the second capacitor is electrically connected with the first node, and a second electrode of the second capacitor is electrically connected with the second clock end.

[0019] In a possible implementation manner of the first aspect, the first node includes a first sub-node and a second sub-node, and the second electrode of the sixth transistor is electrically connected with the first sub-node. The input module further includes a seventh transistor, the first electrode of the second capacitor is electrically connected with the first sub-node through the seventh transistor, a gate of the seventh transistor and the first electrode of the second capacitor are electrically connected with the second sub-node, and the second sub-node is electrically connected with the interlocking module.

[0020] In a possible implementation manner of the first aspect, the input module further includes an eighth transistor, the second capacitor is electrically connected with the second clock end through the eighth transistor, and a gate of the eighth transistor is electrically connected with the second sub-node.

[0021] In a possible implementation manner of the first aspect, the input module further includes a ninth transistor, a gate of the ninth transistor is electrically connected with the first clock end, a first electrode of the ninth transistor is electrically connected with the input signal end, and a second electrode of the ninth transistor is electrically connected with the second sub-node.

[0022] In a possible implementation of the first aspect, the input module further includes a tenth transistor, a gate of the tenth transistor is electrically connected to the second electrode of the sixth transistor and the first sub-node, and a second electrode of the tenth transistor is electrically connected to the second power supply end.

[0023] In a possible implementation of the first aspect, the shift register further includes a reset module, the reset module is electrically connected to the reset signal end, the second power supply end and the third node respectively, and is configured to reset a potential of the third node.

[0024] In a possible implementation of the first aspect, the reset module is further electrically connected to the second node, and is configured to reset a potential of the second node.

[0025] In a possible implementation of the first aspect, the reset module includes an eleventh transistor, a gate of the eleventh transistor is electrically connected to the reset signal end, a first electrode of the eleventh transistor is electrically connected to the second power supply end, and a second electrode of the eleventh transistor is electrically connected to the third node.

[0026] In a possible implementation of the first aspect, the second node control module includes a twelfth transistor and a third capacitor, a gate of the twelfth transistor is electrically connected to the second node, a first electrode of the twelfth transistor is electrically connected to the second power supply end, and a second electrode of the twelfth transistor is electrically connected to the third node, and the third capacitor is electrically connected between the second power supply end and the second node.

[0027] In a possible implementation of the first aspect, the interlocking module includes a thirteenth transistor and a fourteenth transistor, a gate of the thirteenth transistor is electrically connected to the third node, a first electrode of the thirteenth transistor is electrically connected to the first power supply end, and a second electrode of the thirteenth transistor is electrically connected to the first node, and a gate of the fourteenth transistor is electrically connected to the first node, a first electrode of the fourteenth transistor is electrically connected to the first power supply end, and a second electrode of the fourteenth transistor is electrically connected to the third node.

[0028] In a possible implementation of the first aspect, the interlocking module further includes a fifteenth transistor, the first electrode of the thirteenth transistor is electrically connected to the first power supply end through the fifteenth transistor, and a gate of the fifteenth transistor is electrically connected to the second clock end.

[0029] In a possible implementation of the first aspect, the output module includes a sixteenth transistor, a seventeenth transistor and a fourth capacitor, a gate of the sixteenth transistor is electrically connected to the third node, a first electrode of the sixteenth transistor is electrically connected to the first power supply end, and a second electrode of the sixteenth transistor is electrically connected to the output end, a gate of the seventeenth transistor is electrically connected to the first node, a first electrode of the seventeenth transistor is electrically connected to the second power supply end, and a second electrode of the seventeenth transistor is electrically connected to the output end, and the fourth capacitor is electrically connected between the first power supply end and the third node.

[0030] In a possible implementation of the first aspect, the input signal at the input signal end includes an integer number of periods of the clock signal in the time period in which the input signal is at the on level.

[0031] In the second aspect, the embodiments of the present application further provide a display panel, including the gate drive circuit according to any one of the embodiments of the first aspect.

[0032] In a possible implementation of the second aspect, the display panel includes a pixel circuit, a first gate drive circuit and a second gate drive circuit, the pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module, the first gate drive circuit is configured to drive the pulse amplitude modulation module, the second gate drive circuit is configured to drive the pulse width modulation module, the first gate drive circuit includes the gate drive circuit according to any one of the embodiments of the first aspect, and / or, the second gate drive circuit includes the gate drive circuit according to any one of the embodiments of the first aspect.

[0033] In a possible implementation of the second aspect, the input signal at the input signal end of the first gate drive circuit and the input signal at the input signal end of the second gate drive circuit are different in pulse width.

[0034] In the third aspect, the embodiments of the present application further provide a display device, including the display panel according to any one of the embodiments of the second aspect.

[0035] According to the embodiments of the present application, the target switch is electrically connected to the second node, and the target switch is turned on in at least part of the time period in which the input signal at the input signal end is at the off level, and the voltage can be directly written to the second node through the turned-on target switch in the time period in which the input signal at the input signal end is at the off level, so that the second node is prevented from being in a floating state for a long time in the time period in which the input signal at the input signal end is at the off level for a long time, and the potential stability of the second node is improved, thereby improving the stability of the gate drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0036] Other characteristics, objectives, and advantages of the present application will become more apparent from the following detailed description of the non-restrictive embodiments with reference to the attached drawings, in which the same or similar characters denote the same or similar features, and the drawings are not drawn to scale.

[0037] Figure 1 Fig. 1 shows a structure schematic diagram of a shift register in the related art; Figure 2 Fig. 2 shows a structure schematic diagram of a display panel provided by an embodiment of the present application; Figure 3 Fig. 3 shows a structure schematic diagram of a shift register provided by an embodiment of the present application; Figure 4Another structure schematic diagram of the shift register provided by the embodiment of the present application is shown. Figure 5 Another structure schematic diagram of the shift register provided by the embodiment of the present application is shown. Figure 6 Another structure schematic diagram of the shift register provided by the embodiment of the present application is shown. Figure 7 Another structure schematic diagram of the shift register provided by the embodiment of the present application is shown. Figure 8 A timing schematic diagram of Figure 7 is shown. Figure 9 Another structure schematic diagram of the shift register provided by the embodiment of the present application is shown. Figure 10 Another structure schematic diagram of the shift register provided by the embodiment of the present application is shown. Figure 11 A timing schematic diagram of Figure 9 is shown. Figure 12 Another structure schematic diagram of the shift register provided by the embodiment of the present application is shown. Figure 13 A timing schematic diagram of Figure 6 is shown. Figure 14 Another structure schematic diagram of the display panel provided by the embodiment of the present application is shown. Figure 15 A structure schematic diagram of the pixel circuit provided by the embodiment of the present application is shown. Figure 16 A structure schematic diagram of the display device provided by the embodiment of the present application is shown. Figure 17 Another structure schematic diagram of the display device provided by the embodiment of the present application is shown. Figure 18 Another structure schematic diagram of the display device provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] The features and exemplary embodiments of various aspects of the present application will be described in detail below, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are configured only to explain the present application, and are not configured to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is merely to provide a better understanding of the present application by showing examples of the present application.

[0039] It should be noted that, in the present document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0040] It should be understood that when a layer, region or element is referred to as being "on" or "above" another layer, region or element, it can be directly on or above the other layer, region or element or intervening layers or regions can also be present. In addition, when an element is referred to as being "beneath" or "below" another element, it can be directly beneath or below the other element, or intervening layers or regions can also be present.

[0041] It should be understood that the term "and / or" as used herein merely means one or all of the associated listed items, for example, A and / or B can mean A alone, A and B together, or B alone.

[0042] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or can mean that two components are electrically connected via one or more other components. The term "drives" can mean "controls" or "operates". The display panel can be a display device or a module / part of a display device.

[0043] Various modifications and changes can be made to the present application without departing from the spirit and scope thereof. Accordingly, it is intended that the present application cover all such modifications and changes as fall within the scope of the corresponding claims (the technical solutions claimed in the patent application) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction, if possible.

[0044] For example, Figure 1As shown, node QB1' is the preceding node of other functional modules 01. The potential of node QB1' is adjusted by transistor M3' and capacitor C3'. The gate of transistor M3' is electrically connected to the input signal terminal IN. For example, transistor M3' is a P-type transistor. When the input signal terminal IN is at a high level for a long time, the potential control of node QB1' can only be achieved through the coupling of capacitor C3'. That is to say, when the input signal terminal IN is at a high level for a long time, no charge is directly charged into node QB1' through the transistor. This causes node QB1' to be in a floating state during the time when the input signal terminal IN is at a high level, resulting in an unstable potential of node QB1', which in turn affects the stability of the gate drive circuit.

[0045] To address the aforementioned technical problems, this application provides a gate driving circuit, a display panel, and a display device. The embodiments of this application will be described below with reference to the accompanying drawings.

[0046] like Figure 2 As shown, the gate driving circuit 10 provided in this embodiment includes a plurality of cascaded shift registers (VSRs). The gate driving circuit 10 can be disposed in the display panel 100, which includes pixel circuitry. Figure 2 (not shown in the image), the output of the shift register VSR is electrically connected to the gate of the transistor in the pixel circuit via the scan line GL.

[0047] like Figure 3 As shown, the shift register VSR includes an input module 1, a first node control module 2, a second node control module 3, an interlock module 4, and an output module 5.

[0048] Input module 1 is electrically connected to input signal terminal IN, first clock terminal CK, second clock terminal XCK, and first node Q, respectively. Input module 1 is used to adjust the potential of first node Q based on the signals of input signal terminal IN, first clock terminal CK, and second clock terminal XCK.

[0049] The first node control module 2 is electrically connected to the input signal terminal IN, the first clock terminal CK, the second clock terminal XCK, the first power supply terminal VGH, the second power supply terminal VGL, and the second node QB1. The first node control module 2 is used to adjust the potential of the second node QB1 based on the signals of the input signal terminal IN, the first clock terminal CK, the second clock terminal XCK, the first power supply terminal VGH, and the second power supply terminal VGL.

[0050] The second node control module 3 is electrically connected to the second node QB1, the second power supply terminal VGL, and the third node QB2. The second node control module 3 uses the signals from the second node QB1 and the second power supply terminal VGL to adjust the potential of the third node QB2.

[0051] The interlocking module 4 is electrically connected with the first node Q, the third node QB2 and the first power supply terminal VGH respectively, and is configured to control the potentials of the first node Q and the third node QB2. For example, the interlocking module 4 is configured to control the potentials of the first node Q and the third node QB2 to be opposite to each other.

[0052] The output module 5 is electrically connected with the first node Q, the third node QB2, the first power supply terminal VGH, the second power supply terminal VGL and the output terminal OUT respectively, and is configured to control the signal output by the output terminal OUT. For example, when the first node Q is at the on level, the output module 5 controls the output terminal OUT to output the signal of the second power supply terminal VGL; when the third node QB2 is at the on level, the output module 5 controls the output terminal OUT to output the signal of the first power supply terminal VGH.

[0053] The first node control module 2 includes a target switch 20 electrically connected with the second node QB1, and the target switch 20 is turned on during at least part of the period when the input signal of the input signal terminal IN is at the off level. For example, the other end of the target switch 20 is electrically connected with the first clock terminal CK.

[0054] The input signal provided by the input signal terminal IN is a start signal, and the shift register starts to work when the input signal of the input signal terminal IN is at the on level. In the plurality of cascaded shift registers, the input signal terminal IN of the first shift register is electrically connected with the driving chip, and the input signal terminal IN of the i+1th shift register is electrically connected with the output terminal OUT of the ith shift register, where i is an integer greater than 0. In other words, the signal output by the output terminal OUT of the ith shift register is used as the start signal of the i+1th shift register.

[0055] The first clock terminal CK and the second clock terminal XCK are configured to provide clock signals, and the clock signals include signals with high and low voltages alternately. The first clock signal of the first clock terminal CK and the second clock signal of the second clock terminal XCK are out of phase, for example, the first clock signal of the first clock terminal CK and the second clock signal of the second clock terminal XCK are opposite signals.

[0056] The first power supply terminal VGH is configured to provide a high voltage signal, and the second power supply terminal VGL is configured to provide a low voltage signal.

[0057] The input module 1, the first node control module 2, the second node control module 3, the interlocking module 4 and the output module 5 cooperate with each other to enable the output terminal OUT to output a scanning signal, which is used to drive a pixel circuit, and the pixel circuit is used to drive a light emitting element. The second node control module 3 is controlled by the second node QB1, and the voltage stability of the second node QB1 will affect the stability of the second node control module 3, and further affect the stability of the signal output by the output terminal OUT.

[0058] According to the embodiment of the present application, the target switch 20 is electrically connected to the second node QB1, and the target switch 20 is turned on during at least part of the period in which the input signal at the input signal terminal IN is at the off level. During the period in which the input signal at the input signal terminal IN is at the off level, the voltage can be directly written to the second node QB1 through the turned-on target switch 20, thereby avoiding the second node QB1 being in the floating state for a long time during the period in which the input signal at the input signal terminal IN is at the off level, improving the potential stability of the second node QB1, and thus improving the stability of the gate drive circuit.

[0059] In some embodiments, during the period in which the input signal at the input signal terminal IN is at the off level, the working process of the shift register can include a plurality of target periods, and the target switch 20 is turned on during each target period.

[0060] It can be understood that the length of a single target period is less than the length of the period in which the input signal at the input signal terminal IN is at the off level.

[0061] The target switch 20 is turned on multiple times during the period in which the input signal at the input signal terminal IN is at the off level, so that the voltage can be directly written to the second node QB1 through the target switch 20 multiple times, the frequency of writing the voltage to the second node QB1 directly through the target switch 20 is improved, and the second node QB1 is better avoided from being in the floating state for a long time, thereby better improving the potential stability of the QB1.

[0062] In some embodiments, the output terminal of the shift register is electrically connected to the pixel circuit of the display panel, and the display panel includes a plurality of rows of pixel circuits, the length of a row scanning period corresponding to a row of pixel circuits is H, and the length of the target period is less than or equal to 2*H. In this way, within 1-2 row scanning times, charges are directly injected into the second node QB1 through the target switch to stabilize the potential of the second node QB1.

[0063] In some embodiments, the length of the target period is less than or equal to n*T, T represents the period of the clock signal at the clock terminal, and n is less than or equal to 2. In this way, within 1-2 clock periods, charges are directly injected into the second node QB1 through the target switch to stabilize the potential of the second node QB1.

[0064] The periods of the first clock terminal CK and the second clock terminal XCK are the same, and the first clock terminal CK and the second clock terminal XCK can each include a plurality of periods during the period in which the input signal at the input signal terminal IN is at the off level.

[0065] In some embodiments, the target period has a length less than or equal to n*T, and n=1. In this embodiment, the charge can be directly injected into the second node QB1 through the target switch in every 1 clock cycle, which can further improve the frequency of the second node QB1 directly writing voltage through the target switch 20, better avoid the second node QB1 in the floating state for a long time, and better improve the QB1 potential stability.

[0066] In some embodiments, as shown in Figure 4 The first node control module 2 includes a first sub-control module 21 and a second sub-control module 22.

[0067] The first sub-control module 21 is electrically connected to the first power supply end VGH, the second power supply end VGL, the input signal end IN, the first clock end CK, the second clock end XCK, and the fourth node QB0, respectively. The first sub-control module 21 is configured to adjust the potential of the fourth node QB0 based on the signals of the first power supply end VGH, the second power supply end VGL, the input signal end IN, the first clock end CK, and the second clock end XCK.

[0068] The second sub-control module 22 is electrically connected to the input signal end IN, the first power supply end VGH, the first clock end CK, the fourth node QB0, and the second node QB1, respectively. The second sub-control module 22 is configured to adjust the potential of the second node QB1 based on the signals of the input signal end IN, the first power supply end VGH, the first clock end CK, and the fourth node QB0.

[0069] The second sub-control module 22 includes a target switch 20, and the gate of the target switch 20 is electrically connected to the fourth node QB0. During at least part of the period when the input signal of the input signal end IN is at the off level, the fourth node QB0 is at the on level. For example, the source-drain electrode of the target switch 20 is electrically connected to the second node QB1 and the first clock end CK, respectively. When the fourth node QB0 is at the on level, the target switch 20 is turned on, and the voltage of the first clock end CK is written to the second node QB1.

[0070] In this embodiment, the first node control module 2 is split into the first sub-control module 21 and the second sub-control module 22. The first sub-control module 21 is configured to adjust the potential of the fourth node QB0, and the potential of the fourth node QB0 affects the potential of the second node QB1. By splitting into multiple sub-control modules, the control precision can be improved.

[0071] In some embodiments, during the period when the input signal of the input signal end IN is at the off level, the signal of the second power supply end VGL is written to the fourth node QB0, and the signal of the first power supply end VGH is not written to the fourth node QB0.

[0072] For example, when the signal of the second power supply terminal VGL is written to the fourth node QB0, the fourth node QB0 is used to control the target switch 20 to be turned on.

[0073] In the embodiment, when the input signal of the input signal terminal IN is at the off level, the signal of the second power supply terminal VGL is written to the fourth node QB0 to ensure that the target switch 20 can be turned on, and the signal of the first power supply terminal VGH is not written to the fourth node QB0 to avoid that the fourth node QB0 cannot control the target switch 20 to be turned on.

[0074] In some embodiments, when the input signal of the input signal terminal IN and the first clock signal of the first clock terminal CK are both at the on level, the signal of the first power supply terminal VGH is written to the fourth node QB0, and the signal of the second power supply terminal VGL is not written to the fourth node QB0.

[0075] In the present application, the on level is a level for controlling a corresponding transistor to be turned on, and the off level is a level for controlling a corresponding transistor to be turned off. For example, the on level can be a low level, and the off level can be a high level.

[0076] When the input signal of the input signal terminal IN is at the low level, the signal of the first power supply terminal VGH is written to the second node QB1, and when the input signal of the input signal terminal IN and the first clock signal of the first clock terminal CK are both at the on level, the signal of the first power supply terminal VGH is written to the fourth node QB0, and the signal of the second power supply terminal VGL is not written to the fourth node QB0, thereby controlling the target switch 20 to be turned off, and avoiding that the signals of the first clock terminal CK and the first power supply terminal VGH are both written to the second node QB1, thereby avoiding that the signal of the second node QB1 is disordered.

[0077] In some embodiments, as shown in FIG. 2, the first control module 21 includes a first control unit 211 and a second control unit 212. Figure 5

[0078] The first control unit 211 is electrically connected to the input signal terminal IN, the first clock terminal CK, the first power supply terminal VGH and the fourth node QB0 respectively, and is used to adjust the potential of the fourth node QB0 based on the signals of the input signal terminal IN, the first clock terminal CK and the first power supply terminal VGH, and the input signal terminal IN and the first clock terminal CK are used to control whether the first control unit 211 is turned on.

[0079] The second control unit 212 is electrically connected to the second clock terminal XCK, the second power supply terminal VGL and the fourth node QB0 respectively, and is used to adjust the potential of the fourth node QB0 based on the second clock terminal XCK and the second power supply terminal VGL, and the second clock terminal XCK is used to control whether the second control unit 212 is turned on. ​

[0080] For example, when the signals at the input signal terminal IN and the first clock terminal CK are both at the conducting level, the first control unit 211 is turned on, and the signal at the first power supply terminal VGH is written to the fourth node QB0.

[0081] When the signal at the second clock terminal XCK is at the conducting level, the second control unit 212 is turned on, and the signal at the second power supply terminal VGL is written to the fourth node QB0.

[0082] The first control unit 211 and the second control unit 212 are not turned on at the same time, so as to avoid the signals at the first power supply terminal VGH and the second power supply terminal VGL being written to the fourth node QB0 at the same time, thereby avoiding the signal at the fourth node QB0 being disordered.

[0083] In this embodiment, the first sub-control module 21 is further split into the first control unit 211 and the second control unit 212, so as to achieve more precise control.

[0084] In some embodiments, the off level of the first clock terminal XCK is the same as the level of the first power supply terminal VGH.

[0085] For example, the off level of the first clock terminal XCK is equal to the level of the first power supply terminal VGH. The off level of the first clock terminal XCK and the level of the first power supply terminal VGH are both high levels.

[0086] In the working process of the shift register, if the off level of the first clock terminal XCK and the level of the first power supply terminal VGH are written to the second node QB1 at the same time, since the two levels are the same, this will not cause a problem with the signal at the second node QB1.

[0087] In some embodiments, as shown in FIG. 2B, the second sub-control module 22 includes a first transistor M1 and a second transistor M2. Figure 6 The gate of the first transistor M1 is electrically connected to the input signal terminal IN, the first electrode of the first transistor M1 is electrically connected to the first power supply terminal VGH, and the second electrode of the first transistor M1 is electrically connected to the second node QB1. The gate of the second transistor M2 is electrically connected to the fourth node QB0, the first electrode of the second transistor M2 is electrically connected to the first clock terminal CK, the second electrode of the second transistor M2 is electrically connected to the second node QB1, and the target switch 20 includes the second transistor M2.

[0088] For example, both the first transistor M1 and the second transistor M2 are P-type transistors. During at least a portion of the time when the input signal at the input signal terminal IN is at the cutoff level (high level), the fourth node QB0 is at the on level (low level), causing the second transistor M2 to be turned on. In this way, the first clock signal at the first clock terminal CK can be directly written to the second node QB1 through the second transistor M2, avoiding the second node QB1 from being in a floating state for a long time and improving the potential stability of the second node QB1.

[0089] In some embodiments, such as Figure 6 As shown, the second sub-control module 22 also includes a first capacitor C1, which is electrically connected between the second node QB1 and the fourth node QB0. Due to the bootstrap effect of the first capacitor C1, the potential of the fourth node QB0 can be further pulled down, allowing the second transistor M2 to conduct more fully. Here, the first capacitor C1 does not cause the potential of the fourth node QB0 to flip; for example, the first capacitor C1 does not cause the potential of the fourth node QB0 to change from negative to positive or from positive to negative. Similarly, the first capacitor C1 does not cause the potential of the second node QB1 to flip; for example, the first capacitor C1 does not cause the potential of the second node QB1 to change from negative to positive or from positive to negative.

[0090] In some embodiments, such as Figure 6 As shown, the first sub-control module 21 includes a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The gate of the third transistor M3 is electrically connected to the input signal terminal IN, the first electrode of the third transistor M3 is electrically connected to the first power supply terminal VGH, the second electrode of the third transistor M3 is electrically connected to the first electrode of the fourth transistor M4, the gate of the fourth transistor M4 is electrically connected to the first clock terminal CK, and the second electrode of the fourth transistor M4 is electrically connected to the fourth node QB0. The gate of the fifth transistor M5 is electrically connected to the second clock terminal XCK, the first electrode of the fifth transistor M5 is electrically connected to the second power supply terminal VGL, and the second electrode of the fifth transistor M5 is electrically connected to the fourth node QB0.

[0091] For example, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are P-type transistors. When the signals of the input signal end IN and the first clock end CK are both at the on level (low level), the signal of the first power supply end VGH can be written to the fourth node QB0; when the signal of at least one of the input signal end IN and the first clock end CK is at the off level (high level), the signal of the first power supply end VGH cannot be written to the fourth node QB0. When the signal of the second clock end XCK is at the on level (low level), the signal of the second power supply end VGL can be written to the fourth node QB0. The signals of the first clock end CK and the second clock end XCK are inverse signals, so the fourth transistor M4 and the fifth transistor M5 cannot be turned on at the same time, and the signals of the first power supply end VGH and the second power supply end VGL cannot be written to the fourth node QB0 at the same time.

[0092] In some embodiments, as shown in FIG. 1, the input module 1 comprises a sixth transistor M6 and a second capacitor C2. The gate of the sixth transistor M6 is electrically connected to the first clock end CK, the first pole of the sixth transistor M6 is electrically connected to the input signal end IN, and the second pole of the sixth transistor M6 is electrically connected to the first node Q. The first pole of the second capacitor C2 is electrically connected to the first node Q, and the second pole of the second capacitor C2 is electrically connected to the second clock end XCK. Figure 6

[0093] For example, the sixth transistor M6 is a P-type transistor, and when the first clock end CK is at the on level (low level), the signal of the input signal end IN is written to the first node Q. When the first clock end CK is at the off level (high level), the potential of the first node Q can also be adjusted through the coupling effect of the second capacitor C2.

[0094] In some embodiments, as shown in FIG. 1, the input module 1 comprises a sixth transistor M6 and a second capacitor C2. The gate of the sixth transistor M6 is electrically connected to the first clock end CK, the first pole of the sixth transistor M6 is electrically connected to the input signal end IN, and the second pole of the sixth transistor M6 is electrically connected to the first node Q. The first pole of the second capacitor C2 is electrically connected to the first node Q, and the second pole of the second capacitor C2 is electrically connected to the second clock end XCK. Figure 7

[0095] The input module 1 further comprises a seventh transistor M7, and the first pole of the second capacitor C2 is electrically connected to the first sub-node Q1 through the seventh transistor M7. The gate of the seventh transistor M7 and the first pole of the second capacitor C2 are electrically connected to the second sub-node Q2, and the second sub-node Q2 is electrically connected to the interlocking module 4. The second pole of the second capacitor C2 is electrically connected to the second clock end XCK.

[0096] The first pole of the seventh transistor M7 is electrically connected to the first sub-node Q1, the second pole of the seventh transistor M7 and the gate thereof are electrically connected to the second sub-node Q2, the seventh transistor M7 constitutes a diode structure, and the seventh transistor M7 and the second capacitor C2 of the diode structure constitute a charge pump structure.

[0097] Please refer to FIG. 1​​Figure 7 and Figure 8 At stage t2, the first clock terminal CK is at low level, at this time, the low level of the input signal terminal IN is written to the first sub-node Q1, and the seventh transistor M7 forms a diode structure. Due to the unidirectional conductivity of the diode, the potential of the first sub-node Q1 is lower than the potential of the first terminal of the second capacitor C2 (i.e. the second sub-node Q2), so that the transistor in the output module 5 controlled by the first sub-node Q1 is fully turned on, and the waveform output by the output terminal OUT is once dropped to the position, thereby improving or even eliminating the falling edge of the waveform output by the output terminal OUT.

[0098] In some embodiments, as shown in Figure 7 , the input module 1 further comprises an eighth transistor M8, the second capacitor C2 is electrically connected to the second clock terminal XCK through the eighth transistor M8, and the gate of the eighth transistor M8 is electrically connected to the second sub-node Q2.

[0099] When the second sub-node Q2 is at the on level, the eighth transistor M8 is turned on, and the second clock signal of the second clock terminal XCK can be written to the second terminal of the second capacitor C2; when the second sub-node Q2 is at the off level, the eighth transistor M8 is turned off, at this time, the level jump of the second clock terminal XCK will not affect the potential of the first sub-node Q1.

[0100] In some embodiments, as shown in Figure 7 , the input module 1 further comprises a ninth transistor M9, the gate of the ninth transistor M9 is electrically connected to the first clock terminal CK, the first terminal of the ninth transistor M9 is electrically connected to the input signal terminal IN, and the second terminal of the ninth transistor M9 is electrically connected to the second sub-node Q2.

[0101] The second sub-node Q2 is also electrically connected to the interlocking module 4, the interlocking module 4 is electrically connected to the first power supply terminal VGH, the first power supply terminal VGH is at high level, and the interlocking module 4 can only write the high level of the first power supply terminal VGH to the second sub-node Q2. In this embodiment, when the first clock terminal CK is at the on level, the ninth transistor M9 can write the low level of the input signal terminal IN to the second sub-node Q2, thereby realizing accurate control of the potential of the second sub-node Q2.

[0102] In some embodiments, as shown in Figure 7 , the input module 1 further comprises a tenth transistor M10, the tenth transistor M10 is electrically connected between the second terminal of the sixth transistor M6 and the first sub-node Q1, and the gate of the tenth transistor M10 is electrically connected to the second power supply terminal VGL.

[0103] The tenth transistor M10 is separated from the sixth transistor M6 and the first sub-node Q1, and the tenth transistor M10 is turned off when the level of the first sub-node Q1 is low, so that the sixth transistor M6 is prevented from being stressed too much, and the sixth transistor M6 is protected from being damaged, thereby improving the reliability of the shift register.

[0104] In some embodiments, as shown in Figure 9 or Figure 10 , the shift register further comprises a reset module 6 electrically connected to the reset signal terminal RST, the second power supply terminal VGL and the third node QB2 respectively, and the reset module 6 is configured to reset the potential of the third node QB2.

[0105] Exemplarily, a display device comprises the gate drive circuit of various embodiments of the present application, and when the display device is powered on, as shown in Figure 11 , the reset signal of the reset signal terminal RST is at a conduction level (low level), the reset module 6 is turned on, and the signal of the second power supply terminal VGL is written to the third node QB2 to initialize the potential of the third node QB2.

[0106] The reset signals inputted by the reset signal terminals RST of the various shift registers are the same, so that the various shift registers can be reset in the reset stage.

[0107] Figure 9 and Figure 10 The third node QB2 is electrically connected to the reset module 6, which is not used to limit the present application. In other embodiments, the reset module 6 is also electrically connected to the second node QB1, and the reset module 6 is also configured to reset the potential of the second node QB1. In this way, the reset module 6 can reset the third node QB2 and the second node QB1 at the same time.

[0108] In some embodiments, as shown in Figure 9 or Figure 10 , the reset module 6 comprises an eleventh transistor M11, the gate of the eleventh transistor M11 is electrically connected to the reset signal terminal RST, the first pole of the eleventh transistor M11 is electrically connected to the second power supply terminal VGL, and the second pole of the eleventh transistor M11 is electrically connected to the third node QB2.

[0109] It can be understood that the second pole of the eleventh transistor M11 can also be electrically connected to the second node QB1.

[0110] In some embodiments, as shown in Figure 6 , 7As shown in any of the figures 9 and 10, the second node control module 3 includes a twelfth transistor M12 and a third capacitor C3. The gate of the twelfth transistor M12 is electrically connected to the second node QB1, the first electrode of the twelfth transistor M12 is electrically connected to the second power supply terminal VGL, and the second electrode of the twelfth transistor M12 is electrically connected to the third node QB2. The third capacitor C3 is electrically connected between the second power supply terminal VGL and the second node QB1.

[0111] When the second node QB1 is at the on level (e.g., low level), the twelfth transistor M12 is turned on, and the voltage of the second power supply terminal VGL is written to the third node QB2 to achieve potential adjustment of the third node QB2.

[0112] The third capacitor, C3, acts as a voltage regulator, stabilizing the potential of the second node, QB1.

[0113] In some embodiments, such as Figure 6 , 7 As shown in any of the figures 9 and 10, the interlock module includes a thirteenth transistor M13 and a fourteenth transistor M14. The gate of the thirteenth transistor M13 is electrically connected to the third node, the first electrode of the thirteenth transistor M13 is electrically connected to the first power supply terminal VGH, and the second electrode of the thirteenth transistor M13 is electrically connected to the first node Q. The gate of the fourteenth transistor M14 is electrically connected to the first node Q, the first electrode of the fourteenth transistor M14 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourteenth transistor M14 is electrically connected to the third node QB2.

[0114] For example, both the thirteenth transistor M13 and the fourteenth transistor M14 are P-type transistors. When the voltage at the first power supply terminal VGH is high and the first node Q is low, the fourteenth transistor M14 is turned on, and the high level of the first power supply terminal VGH is written into the third node QB2, causing the potentials of the first node Q and the third node QB2 to be out of phase. When the third node QB2 is low, the thirteenth transistor M13 is turned on, and the high level of the first power supply terminal VGH is written into the first node Q, causing the potentials of the first node Q and the third node QB2 to be out of phase.

[0115] In some embodiments, such as Figure 12 As shown, the interlock module 4 also includes a fifteenth transistor M15. The first terminal of the thirteenth transistor M13 is electrically connected to the first power supply terminal VGH through the fifteenth transistor M15, and the gate of the fifteenth transistor M15 is electrically connected to the second clock terminal XCK.

[0116] The voltage of the second power supply end VGH can be written into the second sub-node Q2 when the second clock end XCK and the third node QB2 are both at a conduction level, and the voltage of the second power supply end VGH cannot be written into the second sub-node Q2 when at least one of the second clock end XCK and the third node QB2 is at a cut-off level. The potential inversion of the second sub-node Q2 caused by the interlocking module can be avoided by adding the fifteenth transistor M15.

[0117] In some embodiments, as shown in any one of the accompanying drawings of Figure 6 , 7 , 9, 10, 12, the output module 5 comprises a sixteenth transistor M16, a seventeenth transistor M17 and a fourth capacitor C4. The gate of the sixteenth transistor M16 is electrically connected to the third node QB2, the first pole of the sixteenth transistor M16 is electrically connected to the first power supply end VGH, and the second pole of the sixteenth transistor M16 is electrically connected to the output end OUT. The gate of the seventeenth transistor M17 is electrically connected to the first node Q, the first pole of the seventeenth transistor M17 is electrically connected to the second power supply end VGL, and the second pole of the seventeenth transistor M17 is electrically connected to the output end OUT. The fourth capacitor C4 is electrically connected between the first power supply end VGH and the third node QB2.

[0118] For example, the sixteenth transistor M16 and the seventeenth transistor M17 are P-type transistors. When the third node QB2 is at a low level, the sixteenth transistor M16 is turned on, and the high level of the first power supply end VGH is transmitted to the output end OUT. When the first node Q is at a low level, the seventeenth transistor M17 is turned on, and the low level of the second power supply end VGL is transmitted to the output end OUT.

[0119] The fourth capacitor C4 serves as a voltage stabilizing capacitor and can stabilize the potential of the third node QB2.

[0120] In the following, taking each transistor in the shift register as a P-type transistor as an example, the working process of the shift register is introduced in combination with Figure 6 and Figure 13 . At the t1 stage, the first clock end CK is at a high level, the second clock end XCK is at a low level, the input signal end IN is at a low level, the low level of the second power supply end VGL is written into the fourth node QB0 through the fifth transistor M5, the high level of the first clock end CK is written into the second node QB1 through the second transistor M2, the third node QB2 maintains a low level, the high level of the first power supply end VGH is written into the first node Q through the thirteenth transistor M13, and the output end OUT outputs a high level.

[0121] During the t1 stage, the second node QB1 and the fourth node QB0, the first node Q are directly guided into the voltage by the turned-on transistors.

[0122] In the t2 stage, the first clock end CK is low, the second clock end XCK is high, the input signal end IN is low, the high level of the first power supply end VGH is written into the fourth node QB0 through the third transistor M3 and the fourth transistor M4, the high level of the first power supply end VGH is written into the second node QB1 through the first transistor M1, the low level of the input signal end IN is written into the first node Q through the sixth transistor M6, the high level of the first power supply end VGH is written into the third node QB2 through the fourteenth transistor M14, and the output end OUT outputs low level.

[0123] In the t2 stage, the second node QB1 and the fourth node QB0, the third node QB2, the first node Q are directly introduced into the voltage by the conductive transistor.

[0124] In the t3 stage, the first clock end CK is high, the second clock end XCK is low, the input signal end IN is low, the low level of the second power supply end VGL is written into the fourth node QB0 through the fifth transistor M5, the high level of the first clock end CK is written into the second node QB1 through the second transistor M2, and the high level of the first power supply end VGH is written into the second node QB1 through the first transistor M1, the second clock end XCK jumps to low level, the potential of the first node Q is pulled to be lower through the coupling of the second capacitor C2, the high level of the first power supply end VGH is written into the third node QB2 through the fourteenth transistor M14, and the output end OUT outputs low level.

[0125] In the t3 stage, the second node QB1 and the fourth node QB0, the third node QB2 are directly introduced into the voltage by the conductive transistor.

[0126] The working process of the shift register in the subsequent t4 stage of the low level of the input signal end IN repeats the t2 stage and the t3 stage.

[0127] In the t5 stage, the first clock end CK is high, the second clock end XCK is low, the input signal end IN is high, the low level of the second power supply end VGL is written into the fourth node QB0 through the fifth transistor M5, the high level of the first clock end CK is written into the second node QB1 through the second transistor M2, the first node Q maintains low level, the high level of the first power supply end VGH is written into the third node QB2 through the fourteenth transistor M14, and the output end OUT outputs low level.

[0128] In the t5 stage, the second node QB1 and the fourth node QB0, the third node QB2 are directly introduced into the voltage by the conductive transistor.

[0129] During stage t6, the first clock terminal CK is low, the second clock terminal XCK is high, the input signal terminal IN is high, the fourth node QB0 remains low, the low level of the first clock terminal CK is written to the second node QB1 through the second transistor M2, and due to the coupling of the first capacitor C1, the potential of the fourth node QB0 is pulled even lower. The low level of the second power supply terminal VGL is written to the third node QB2, the high level of the input signal terminal IN is written to the first node Q through the sixth transistor M6, and the high level of the first power supply terminal VGH is written to the first node Q through the thirteenth transistor M13. The output terminal OUT outputs a high level.

[0130] During stage t6, the transistors at the second node QB1, the third node QB2, and the first node Q are all turned on and directly supplied with voltage.

[0131] During stage t7, the first clock terminal CK is high, the second clock terminal XCK is low, the input signal terminal IN is high, the low level of the second power supply terminal VGL is written to the fourth node QB0 through the fifth transistor M5, the high level of the first clock terminal CK is written to the second node QB1 through the second transistor M2, the third node QB2 remains low, the high level of the first power supply terminal VGH is written to the first node Q through the thirteenth transistor M13, and the output terminal OUT outputs a high level.

[0132] During stage t7, the transistors at the second node QB1, the fourth node QB0, and the first node Q are all turned on, and the voltage is directly applied.

[0133] The shift register repeats the operation of stages t6 and t7 in the subsequent stages after the input signal IN is high.

[0134] As described in the above embodiment, the second transistor M2 serves as the target transistor 20. During multiple target time periods when the input signal terminal IN is at a cutoff level (high level), the second transistor M2 is turned on. The target time periods include at least stages t5, t6, and t7. Since subsequent stages repeat stages t6 and t7, the target time periods include any one of the time periods when the input signal terminal IN is at a high level.

[0135] In some embodiments, such as Figure 13 As shown, the input signal at the IN terminal is at the on level (low level) for an integer number of clock signal cycles during the period.

[0136] Figure 13 As exemplarily shown, during the period when the input signal at the input signal terminal IN is at the on level (low level), the clock signals at the first clock terminal CK and the second clock terminal XCK both include 4 clock cycles.

[0137] For example, in order to meet the driving requirements of a high-resolution display panel, such as a micro Light Emitting Diode (micro LED) or an Organic Light Emitting Diode (OLED) display panel, a pixel circuit using a combination of Pulse Amplitude Modulation (PAM) and Pulse Width Modulation (PWM) is used to control the driving current intensity and the duration of the driving current to control the light emitting state of the light emitting element.

[0138] The pulse width of the on level of the output end is the same as the pulse width of the on level of the input signal end IN, and therefore, the period in which the signal of the output end is at the on level (low level) also includes an integer number of clock signal periods.

[0139] The output end of the shift register in the embodiments of the present application can provide a light emitting control signal (Emit signal) for the pixel circuit, and the pulse width of the on level of the output of the shift register is an integer number of clock signal periods, which can provide more options for the timing control of the micro LED.

[0140] Based on the same technical concept, the present application also provides a display panel. As shown in Figure 14 The display panel 100 includes the gate drive circuit 10 according to any one of the above embodiments. The display panel provided by the embodiments of the present application has the beneficial effects of the gate drive circuit provided by any one of the above embodiments, and specific descriptions can be referred to the specific descriptions of the gate drive circuit in the above embodiments, which will not be described here again.

[0141] In some embodiments, as shown in Figure 14 The display panel 100 includes a pixel circuit 30, a first gate drive circuit 11 and a second gate drive circuit 12, the pixel circuit 30 includes a pulse amplitude modulation module PAM and a pulse width modulation module PWM, the first gate drive circuit 11 is used to drive the pulse amplitude modulation module PAM, the second gate drive circuit 12 is used to drive the pulse width modulation module PWM, the first gate drive circuit 11 includes the gate drive circuit according to any one of the above embodiments, and / or, the second gate drive circuit 12 includes the gate drive circuit according to any one of the above embodiments.

[0142] The pixel circuit 30 generates a driving current under the control of the pulse amplitude modulation module PAM and the pulse width modulation module PWM. The pulse amplitude modulation module PAM can be used to control the amplitude of the driving current, and the pulse width modulation module PWM can be used to adjust the pulse width of the voltage applied to the first electrode of the light emitting element.

[0143] The pulse width modulation module PWM adjusts the pulse width of the voltage applied to the first electrode of the light emitting element, i.e. the pulse width modulation module PWM adjusts the actual emission period of the driving current applied to the light emitting element, while keeping the driving current applied to the light emitting device at a constant level to adjust the gray scale or brightness displayed by the light emitting device, instead of adjusting the gray scale or brightness displayed by the light emitting device only by adjusting the magnitude of the driving current applied to the light emitting device. Therefore, the pulse amplitude modulation module PAM can provide the driving current to the light emitting device so that the light emitting element is driven with optimal light emitting efficiency, and the gray scale or brightness displayed by the light emitting element is adjusted by the pulse width modulation module PWM adjusting the light emitting duty cycle of the light emitting element (i.e. the emission period of the light emitting element).

[0144] As an example, the structure of the pixel circuit 30 is as shown in Figure 15 The PWM module is electrically connected with the PAM module, and the PAM module is electrically connected with the first electrode of the light emitting element. Among them, PAM_S1, PAM_S2, PAM_EM, PWM_S1, PWM_S2, PWM_EM are all scanning signals, and PAM_EM and PWM_EM can also be called light emitting control signals.

[0145] For example, the first gate drive circuit 11 provides the first light emitting control signal PAM_EM for the pulse amplitude modulation module PAM, and the second gate drive circuit 12 provides the second light emitting control signal PWM_EM for the pulse width modulation module PWM.

[0146] It should be noted that Figure 15 The pixel circuit structure shown in Figure 15 Regardless of the specific structure of the pulse amplitude modulation module PAM and the pulse width modulation module PWM in the pixel circuit, both of them are usually driven by the gate drive circuit, so the design concept of the gate drive circuit in this application can also be applied to the pixel circuit of other structure forms except the structure shown in

[0147] Exemplarily, the light emitting element can be a current-driven self-luminous element, for example, can be any one of an Organic Light Emitting Diode (OLED), a Polymer Light-Emitting Diode (PLED), a Quantum Dot Light Emitting Diode (QLED), a Micro Light Emitting Diode (Micro LED), a MiNi Light Emitting Diode (MiNi LED), etc.

[0148] In some embodiments, the pulse width of the input signals of the input signal ends of the first gate driving circuit 11 and the second gate driving circuit 12 is different.

[0149] Here, the pulse width refers to the pulse width of the on level of the input signal.

[0150] The pulse width of the on level of the output end of the shift register is the same as the pulse width of the on level of the input signal end IN, and therefore in this embodiment, the pulse width of the output signals of the first gate driving circuit 11 and the second gate driving circuit 12 is different, so that different driving requirements of the first light emitting control signal PAM EM provided by the pulse amplitude modulation module PAM can be flexibly met.

[0151] Based on the same technical concept, the present application also provides a display device comprising the display panel provided by the present application. Please refer to Figure 16 , Figure 16 is a structural schematic diagram of a display device provided by an embodiment of the present application. Figure 16 The display device 1000 provided by the present application comprises the display panel 100 provided by any one of the above embodiments of the present application. Figure 16 The embodiments are only described by taking a mobile phone as an example, and the display device 1000 can be understood as a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with display functions, and the present application does not specifically limit this. The display device provided by the embodiments of the present application has the beneficial effects of the display panel provided by the embodiments of the present application, and specific descriptions can be referred to the specific descriptions of the display panel in the above embodiments, which will not be described herein again.

[0152] As an example, as shown in Figure 16 , the display device 1000 comprises a frame area (non-display area), and in this embodiment, the gate driving circuit can be located in the frame area of the display device.

[0153] As another example, as shown inFigure 17 As shown in FIG. 1, the display device 1000 is a bezel-less display device, and in this embodiment, the gate driving circuit can be located in the display area of the display device.

[0154] As another example, as shown in FIG. 2, the display device 1000 is a tiled display device, and the display device 1000 includes a plurality of display panels 100 tiled together. Figure 18

[0155] In accordance with the embodiments of the present application as described above, those embodiments are not described in detail with all of the details and are not limited to the specific embodiments described. It is apparent that many modifications and variations can be made to the above description. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their full scope and equivalents.​

Claims

1. A gate drive circuit characterized by comprising: The shift register comprises a plurality of cascaded shift registers, and each shift register comprises an input module, a first node control module, a second node control module, an interlocking module and an output module. The input module is electrically connected with an input signal end, a first clock end, a second clock end and a first node, and is configured to adjust the potential of the first node. The first node control module is electrically connected with the input signal end, the first clock end, the second clock end, a first power supply end, a second power supply end and a second node, and is configured to adjust the potential of the second node. The second node control module is electrically connected with the second node, the second power supply end and a third node, and is configured to adjust the potential of the third node. The interlocking module is electrically connected with the first node, the third node and the first power supply end, and is configured to control the potentials of the first node and the third node. The output module is electrically connected with the first node, the third node, the first power supply end, the second power supply end and an output end, and is configured to control the signal output by the output end. The first node control module comprises a target switch electrically connected with the second node, and the target switch is turned on in at least a part of a period in which the input signal of the input signal end is at a cutoff level.

2. The gate drive circuit according to claim 1, characterized by In a period in which the input signal of the input signal end is at a cutoff level, the working process of the shift register comprises a plurality of target periods, and the target switch is turned on in the target periods.

3. The gate drive circuit according to claim 2, characterized by The length of the target period is less than or equal to 2*H, and H is the length of row scanning of a display panel.

4. The gate drive circuit according to claim 3, characterized by The length of the target period is less than or equal to n*T, T represents the period of a clock signal on a clock end, and n is less than or equal to 2.

5. The gate drive circuit according to claim 4, characterized in that n=1。 6. The gate drive circuit according to claim 1, characterized by The first node control module comprises a first sub-control module and a second sub-control module. The first sub-control module is electrically connected with the first power supply end, the second power supply end, the input signal end, the first clock end, the second clock end and a fourth node, and is configured to adjust the potential of the fourth node. The second sub-control module is electrically connected with the input signal end, the first power supply end, the first clock end, the fourth node and the second node, and is configured to adjust the potential of the second node. The second sub-control module comprises the target switch, and a gate electrode of the target switch is electrically connected with the fourth node, and the fourth node is at a turn-on level in at least a part of a period in which the input signal of the input signal end is at a cutoff level.

7. The gate drive circuit according to claim 6, characterized in that In a period in which the input signal of the input signal end is at a cutoff level, the signal of the second power supply end is written into the fourth node, and the signal of the first power supply end is not written into the fourth node.

8. The gate drive circuit according to claim 6, characterized by When the input signal of the input signal end and the first clock signal of the first clock end are both at a turn-on level, the signal of the first power supply end is written into the fourth node, and the signal of the second power supply end is not written into the fourth node.

9. The gate drive circuit according to claim 6, characterized by The first sub-control module comprises a first control unit and a second control unit. The first control unit is electrically connected with the input signal end, the first clock end, the first power supply end and the fourth node respectively, and is used for adjusting the electric potential of the fourth node, and the input signal end and the first clock end are used for controlling whether the first control unit is turned on or not. The second control unit is electrically connected with the second clock end, the second power supply end and the fourth node respectively, and is used for adjusting the electric potential of the fourth node, and the second clock end is used for controlling whether the second control unit is turned on or not.

10. The gate drive circuit according to claim 6, characterized by The off level of the first clock end is the same as the level of the first power supply end.

11. The gate drive circuit according to claim 6, characterized by The second sub-control module comprises a first transistor and a second transistor, the gate of the first transistor is electrically connected with the input signal end, the first pole of the first transistor is electrically connected with the first power supply end, and the second pole of the first transistor is electrically connected with the second node; the gate of the second transistor is electrically connected with the fourth node, the first pole of the second transistor is electrically connected with the first clock end, and the second pole of the second transistor is electrically connected with the second node, and the target switch comprises the second transistor.

12. The gate drive circuit according to claim 11, characterized by The second sub-control module further comprises a first capacitor, which is electrically connected between the second node and the fourth node.

13. The gate drive circuit according to claim 6, characterized by The first sub-control module comprises a third transistor, a fourth transistor and a fifth transistor, the gate of the third transistor is electrically connected with the input signal end, the first pole of the third transistor is electrically connected with the first power supply end, the second pole of the third transistor is electrically connected with the first pole of the fourth transistor, the gate of the fourth transistor is electrically connected with the first clock end, the second pole of the fourth transistor is electrically connected with the fourth node, the gate of the fifth transistor is electrically connected with the second clock end, the first pole of the fifth transistor is electrically connected with the second power supply end, and the second pole of the fifth transistor is electrically connected with the fourth node.

14. The gate drive circuit of claim 1, wherein, The input module comprises a sixth transistor and a second capacitor, the gate of the sixth transistor is electrically connected with the first clock end, the first pole of the sixth transistor is electrically connected with the input signal end, the second pole of the sixth transistor is electrically connected with the first node, the first pole of the second capacitor is electrically connected with the first node, and the second pole of the second capacitor is electrically connected with the second clock end.

15. The gate drive circuit of claim 14, wherein, The first node comprises a first sub-node and a second sub-node, and the second pole of the sixth transistor is electrically connected with the first sub-node. The input module further comprises a seventh transistor, the first pole of the second capacitor is electrically connected with the first sub-node through the seventh transistor, the gate of the seventh transistor and the first pole of the second capacitor are electrically connected with the second sub-node, and the second sub-node is electrically connected with the interlocking module.

16. The gate drive circuit of claim 15, wherein, The input module further comprises an eighth transistor, the second capacitor is electrically connected with the second clock end through the eighth transistor, and the gate of the eighth transistor is electrically connected with the second sub-node.

17. The gate drive circuit of claim 16, wherein, The input module further comprises a ninth transistor, a gate of the ninth transistor is electrically connected with the first clock terminal, a first pole of the ninth transistor is electrically connected with the input signal terminal, and a second pole of the ninth transistor is electrically connected with the second sub-node.

18. The gate drive circuit of claim 17, wherein, The input module further comprises a tenth transistor, the tenth transistor is electrically connected between the second pole of the sixth transistor and the first sub-node, and a gate of the tenth transistor is electrically connected with the second power supply terminal.

19. The gate drive circuit of claim 1, wherein The shift register further comprises a reset module, the reset module is electrically connected with a reset signal terminal, the second power supply terminal and the third node respectively, and is used for resetting the potential of the third node.

20. The gate drive circuit of claim 19, wherein, The reset module is further electrically connected with the second node, and is used for resetting the potential of the second node.

21. The gate drive circuit of claim 19, wherein, The reset module comprises an eleventh transistor, a gate of the eleventh transistor is electrically connected with the reset signal terminal, a first pole of the eleventh transistor is electrically connected with the second power supply terminal, and a second pole of the eleventh transistor is electrically connected with the third node.

22. The gate drive circuit of claim 1, wherein The second node control module comprises a twelfth transistor and a third capacitor, a gate of the twelfth transistor is electrically connected with the second node, a first pole of the twelfth transistor is electrically connected with the second power supply terminal, and a second pole of the twelfth transistor is electrically connected with the third node. The third capacitor is electrically connected between the second power supply terminal and the second node.

23. The gate drive circuit of claim 1, wherein The interlocking module comprises a thirteenth transistor and a fourteenth transistor, a gate of the thirteenth transistor is electrically connected with the third node, a first pole of the thirteenth transistor is electrically connected with the first power supply terminal, and a second pole of the thirteenth transistor is electrically connected with the first node; a gate of the fourteenth transistor is electrically connected with the first node, a first pole of the fourteenth transistor is electrically connected with the first power supply terminal, and a second pole of the fourteenth transistor is electrically connected with the third node.

24. The gate drive circuit of claim 23, wherein, The interlocking module further comprises a fifteenth transistor, the first pole of the thirteenth transistor is electrically connected with the first power supply terminal through the fifteenth transistor, and a gate of the fifteenth transistor is electrically connected with the second clock terminal.

25. The gate drive circuit of claim 23, wherein, The output module comprises a sixteenth transistor, a seventeenth transistor and a fourth capacitor, a gate of the sixteenth transistor is electrically connected with the third node, a first pole of the sixteenth transistor is electrically connected with the first power supply terminal, and a second pole of the sixteenth transistor is electrically connected with the output terminal; a gate of the seventeenth transistor is electrically connected with the first node, a first pole of the seventeenth transistor is electrically connected with the second power supply terminal, and a second pole of the seventeenth transistor is electrically connected with the output terminal; The fourth capacitor is electrically connected between the first power supply terminal and the third node.

26. The gate drive circuit of claim 1, wherein The input signal of the input signal terminal comprises an integer number of periods of clock signals in the period of the on level.

27. A display panel comprising: The gate drive circuit comprises any one of claims 1-26. The gate drive circuit comprises any one of claims 1-26.

28. The display panel of claim 27, wherein, The display panel comprises pixel circuits, a first gate drive circuit and a second gate drive circuit, the pixel circuits comprise pulse amplitude modulation modules and pulse width modulation modules, the first gate drive circuit is configured to drive the pulse amplitude modulation modules, the second gate drive circuit is configured to drive the pulse width modulation modules, the first gate drive circuit comprises the gate drive circuit according to any one of claims 1-26, and / or the second gate drive circuit comprises the gate drive circuit according to any one of claims 1-26.

29. The display panel of claim 28, wherein, The input signals of the input signal ends of the first gate drive circuit and the second gate drive circuit are different in pulse width.

30. A display device comprising: The display panel according to any one of claims 27-29.

Images