Display driving method and display device

Abstract

The invention discloses a display driving method and display equipment, and the method comprises the steps: obtaining a first time point of a data signal and a second time point of the data signal in a first period of an eye pattern, and a third time point of a clock signal in the first period of the eye pattern based on the current eye pattern data of a display; calculating a first phase difference between the data signal and the clock signal and a second phase difference between the data signal and the clock signal based on the first time point, the second time point and the third time point; performing signal output control on a driving module of the display based on the first phase difference and the second phase difference; wherein in the eye pattern data, a negative junction time point of the data signal and the horizontal axis in the first period is a first time point, a positive junction time point of the data signal and the horizontal axis in the first period is a second time point, and a junction time point of the clock signal and the horizontal axis in the first period is a third time point. According to the invention, automatic signal output control can be carried out based on the eye pattern.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display driving method and display device. BACKGROUND

[0002] With the development of display products, more and more customers demand larger size products, and the data transmission rate required by the larger size products is higher, and the quality of product data signal transmission is higher. Therefore, how to ensure the stability, consistency and accuracy of data transmission of large size display products is a must control direction. Since the size of the display product is larger, the data to be transmitted is more, and the transmission rate per unit time is faster. The quality of high-speed transmission signal is usually measured by eye diagram. Eye diagram can reflect the quality of signal, and poor eye diagram can reflect the problems such as inter-symbol interference, voltage noise, duty cycle overshoot and signal jitter. Eye diagram itself does not affect the display effect, but eye diagram can show some display problems. At present, the output control of signal can be manually improved to improve the quality of eye diagram. When the quality of eye diagram is observed to meet the requirements, it is considered that the display effect of the current display meets the requirements. However, this way is time-consuming and laborious, and the efficiency is low. SUMMARY

[0003] The embodiment of the present application provides a display driving method and display device, which can automatically control the signal output based on the eye diagram.

[0004] In a first aspect, the present application provides a display driving method, which comprises: obtaining a first time point of a data signal and a second time point of the data signal in a first period of an eye diagram, and a third time point of a clock signal in the first period of the eye diagram based on current eye diagram data of a display; calculating a first phase difference between the data signal and the clock signal and a second phase difference between the data signal and the clock signal based on the first time point, the second time point and the third time point; and performing signal output control on a driving module of the display based on the first phase difference and the second phase difference; wherein in the eye diagram data, the first time point is a negative intersection time point of the data signal and the horizontal axis in the first period, the second time point is a positive intersection time point of the data signal and the horizontal axis in the first period, and the third time point is an intersection time point of the clock signal and the horizontal axis in the first period.

[0005] It can be seen that the first time point, the second time point and the third time point in the eye diagram can be obtained by detecting the current eye diagram data of the display, and the first phase difference and the second phase difference between the data signal and the clock signal can be calculated based on the first time point, the second time point and the third time point. The driving module of the display is automatically controlled by the first phase difference and the second phase difference, thereby improving the quality of the eye diagram and improving the display effect of the product.

[0006] In a possible implementation, the driving module comprises a driving chip, and the signal output control of the driving module of the display based on the first phase difference and the second phase difference can comprise: determining the output time of the data signal based on the first phase difference and the second phase difference; and outputting the data signal to the driving chip based on the output time of the data signal.

[0007] It can be seen that the output time of the data signal can be automatically controlled based on the obtained first phase difference and the second phase difference.

[0008] In a possible implementation, the determination of the output time of the data signal based on the first phase difference and the second phase difference can comprise: in a case where the first phase difference is less than a first threshold, determining the output time of the data signal based on the first phase difference and the first threshold; or in a case where the second phase difference is less than a second threshold, determining the output time of the data signal based on the second phase difference and the second threshold.

[0009] It can be seen that the output time of the data signal can be determined based on the first phase difference and the first threshold, and the output time of the data signal can also be determined based on the first phase difference and the first threshold.

[0010] In a possible implementation, the signal output control of the driving module of the display based on the first phase difference and the second phase difference can comprise: in a case where the first phase difference is less than a first threshold, determining delay time information of the data signal, and performing delay output processing on the data signal based on the delay time information; or in a case where the second phase difference is less than a second threshold, determining advance time information of the data signal, and performing advance output processing on the data signal based on the advance time information.

[0011] It can be seen that in a case where the first phase difference does not satisfy the threshold, the delay output processing is automatically performed on the data signal; and in a case where the second phase difference does not satisfy the threshold, the advance output processing is automatically performed on the data signal.

[0012] In a possible implementation, before the first time point of the data signal and the second time point of the data signal in the first period of the eye diagram and the third time point of the clock signal in the first period of the eye diagram are obtained based on the current eye diagram data of the display, the method can further comprise: sending a start signal to the driving chip, the start signal being used to instruct the driving chip to drive the display to display a target picture; and generating the current eye diagram data of the display when an end signal from the driving chip is received.

[0013] It can be seen that after the driving chip completes the display of the target picture, the current eye diagram data of the display can be generated, so that the timing control chip analyzes the current eye diagram data of the display and automatically controls the signal output based on the eye diagram.

[0014] In a possible implementation, the driving module includes a driving chip, and the signal output control of the driving module of the display based on the first phase difference and the second phase difference can include: sending an output adjustment signal to the driving chip in a case where the first phase difference or the second phase difference meets a control condition, and the output adjustment signal is used to control the driving chip to adjust the output time of the data signal according to a register parameter.

[0015] It can be seen that the timing control chip can also send an output adjustment signal to the driving chip in a case where the first phase difference or the second phase difference meets a control condition, and the output adjustment signal is used to control the driving chip to automatically adjust the output time of the data signal according to a register parameter, thereby reducing the computing power required by the timing control chip and reducing the cost required by the timing control chip.

[0016] In a possible implementation, the method can further include: in a case where the first phase difference and the second phase difference do not meet the control condition, setting the control pin to a low level.

[0017] It can be seen that the timing control chip can set the control pin to a low level in a case where the first phase difference or the second phase difference does not meet the control condition, thereby stopping the driving chip from performing signal output control on the driving module of the display.

[0018] In a second aspect, an embodiment of the present application provides a display device, which includes a driving module, the driving module including a timing control chip and a driving chip; the driving chip is configured to display an image picture through a display unit in response to control of the timing control chip; the timing control chip is configured to obtain a first time point of a data signal and a second time point of the data signal in a first period of an eye diagram, and a third time point of a clock signal in the first period of the eye diagram based on current eye diagram data of the display; the timing control chip is further configured to calculate a first phase difference between the data signal and the clock signal and a second phase difference between the data signal and the clock signal based on the first time point, the second time point and the third time point; the timing control chip is further configured to perform signal output control on the driving module of the display based on the first phase difference and the second phase difference; and in the eye diagram data, the first time point is a negative intersection time point of the data signal and a horizontal axis in the first period, the second time point is an intersection time point of the data signal and the horizontal axis in the first period, and the third time point is an intersection time point of the clock signal and the horizontal axis in the first period.

[0019] In a possible implementation, the timing control chip is further configured to send an output adjustment signal to the driving chip in a case where the first phase difference or the second phase difference meets a control condition, and the output adjustment signal is used to control the driving chip to adjust the output time of the data signal according to a register parameter.

[0020] In a possible implementation, the timing control chip is further configured to set the control pin to a low level when the first phase difference and the second phase difference do not satisfy the control condition.

[0021] In a third aspect, an electronic device is provided, which includes a memory configured to store a program, and a processor configured to execute the program stored in the memory. When the program is executed by the processor, the processor performs the method in any one of the possible implementation manners of the first aspect.

[0022] In a fourth aspect, a computer storage medium is provided, which stores a computer program. The computer program includes program instructions. When the program instructions are executed by a processor, the processor performs the method in the first aspect and any one of the possible implementation manners of the first aspect.

[0023] In a fifth aspect, a computer program product is provided, which includes instructions or a computer program. When the instructions or the computer program are executed, the method in the first aspect and any one of the possible implementation manners of the first aspect is implemented.

[0024] In a sixth aspect, a chip is provided, which includes a processor configured to execute instructions. When the processor executes the instructions, the chip performs the method in the first aspect and any one of the possible implementation manners of the first aspect. Optionally, the chip further includes an input / output interface configured to receive or send a signal. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0026] Figure 1 A structural schematic diagram of a display device is provided for the embodiments of the present application;

[0027] Figure 2 A flowchart of a display driving method is provided for the embodiments of the present application;

[0028] Figure 3 A schematic diagram of an eye diagram is provided for the embodiments of the present application;

[0029] Figure 4 A flowchart for signal output control of a timing control chip is provided for an embodiment of the present application.

[0030] Figure 5 A structural diagram of a timing control chip is provided for an embodiment of the present application.

[0031] Figure 6 A flowchart for signal output control of a driving chip is provided for an embodiment of the present application.

[0032] Figure 7 A structural diagram of a timing control chip and a driving chip is provided for an embodiment of the present application.

[0033] Figure 8 A structural diagram of an electronic device is provided for an embodiment of the present application.

[0034] Legend of reference signs:

[0035] 110 - driving module, 111 - timing control chip, 112 - first driving chip, 113 - second driving chip, 114 - third driving chip, 115 - Nth driving chip, 120 - display unit, 510 - data detection module, 520 - data analysis module, 530 - differential signal output module, 710 - data detection module, 720 - data analysis module, 730 - signal receiving module, 740 - register control module, 750 - differential signal output module, 810 - processor, 820 - communication interface, 830 - memory, 840 - bus. DETAILED DESCRIPTION

[0036] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0037] The terms "first", "second", "third", and "fourth" and the like in the description and in the claims of the present application and in the accompanying drawings are used to distinguish between similar objects, not to describe a particular sequential or chronological order. Furthermore, the terms "comprises", "comprising", "includes", "including", "has", "having" and the like are intended to cover a non-exclusive inclusion, such that any process, method, system, product or device that comprises, includes, has or includes certain steps or units is not limited to those steps or units, but can optionally further comprise, include or have other steps or units not listed. Furthermore, the terms "comprise", "comprising", "include", "including", "has", "having" and the like are intended to cover a non-exclusive inclusion, such that any process, method, system, product or device that comprises, includes, has or includes certain steps or units is not limited to those steps or units, but can optionally further comprise, include or have other steps or units not listed. Furthermore, the terms "comprise", "comprising", "include", "including", "has", "having" and the like are intended to cover a non-exclusive inclusion, such that any process, method, system, product or device that comprises, includes, has or includes certain steps or units is not limited to those steps or units, but can optionally further comprise, include or have other steps or units not listed.

[0038] It should be understood that, in the application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, "A and / or B" can mean: only A, only B, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including single item or any combination of multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0039] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor does it necessarily refer to a particular embodiment in an exclusive sense. It is explicitly and implicitly understood that the embodiments described herein can be combined with other embodiments.

[0040] The terms "component," "module," "system", and the like are used to generally refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed among one or more computers. Also, these components can execute from various computer-readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0041] A display device applicable to an embodiment of the application is introduced below.

[0042] Please refer to Figure 1 , Figure 1 A structural schematic diagram of a display device provided by an embodiment of the application is shown in FIG. 1. As shown in FIG. 1, the display device comprises a display panel 10, a backlight module 20, and a light guide plate 30. Figure 1As shown, the display device includes a driving module 110 and a display unit 120. The display device can be a display. Taking an example that the driving module 110 includes N driving chips, N is a positive integer, the driving module 110 includes a timing control chip 111, a first driving chip 112, a second driving chip 113, a third driving chip 114,..., and an Nth driving chip 115. The number of the timing control chip 111 and the number of the driving chips are used for example, and do not constitute a limitation to the embodiments of the present application.

[0043] The timing control chip 111 is configured to generate a data signal and a clock signal, and send the data signal and the clock signal to each driving chip. The driving chip is configured to convert the received data signal and the clock signal into a signal that can be understood by the display unit 120, and display an image picture through the display unit 120.

[0044] It should be noted that, Figure 1 The a-type line in the figure represents a data feedback path, Figure 1 The b-type line in the figure represents a control command path, Figure 1 The c-type line in the figure represents a data transmission path.

[0045] The timing control chip 111 can send a first start signal to the first driving chip 112 through the control command path, the first start signal is used to instruct the first driving chip 112 to drive the display unit 120 to display a first target picture through the data transmission path. After the first driving chip 112 completes the output of the first target picture, the first driving chip 112 can send a second start signal to the second driving chip 113 through the control command path, the second start signal is used to instruct the second driving chip 113 to drive the display unit 120 to display a second target picture through the data transmission path. After the second driving chip 113 completes the output of the second target picture, the second driving chip 113 can send a third start signal to the third driving chip 114 through the control command path. From the first driving chip 112 to the Nth driving chip 115, the output of the target picture is sequentially completed. A cascade structure is formed through the start signals between the timing control chip 111, the first driving chip 112, the second driving chip 113, the third driving chip 114,..., and the Nth driving chip 115.

[0046] After each driving chip completes the output of the target picture, an end signal can also be sent to the timing control chip 111 through the data feedback path. For example, after the first driving chip 112 completes the output of the first target picture, the first driving chip 112 can send a first end signal to the timing control chip 111 through the data feedback path, and the timing control chip 111 generates the current eye diagram data of the display device when receiving the first end signal from the first driving chip 112.

[0047] The display driving method provided by the embodiment of the application is described below.

[0048] Please refer to Figure 2 , Figure 2 The flowchart of the display driving method provided by the embodiment of the application is shown in FIG. 1. As shown in FIG. 1, the display driving method can include but is not limited to the following steps: Figure 2

[0049] S201, based on the current eye diagram data of the display, obtaining a first time point of a data signal in a first period of an eye diagram, a second time point of the data signal, and a third time point of a clock signal in the first period of the eye diagram.

[0050] The eye diagram is a statistical distribution diagram naturally formed by superimposing data bits at different positions of a high-speed digital signal according to time intervals, and the eye diagram can reflect the overall characteristics of all digital signals on the entire data signal transmission link. The eye diagram can also be said to be a superimposed display result of a series of different binary codes of a digital signal according to a certain rule. In the mini protocol, the eye diagram is composed of superimposed clock signals and data signals, and the eye width directly corresponds to the clock skew value of the clock signal to the data signal. The eye width is a core parameter in high-speed serial communication and signal integrity analysis, which is used to quantify the stable window of the digital signal in the time domain, and directly reflects the anti-interference ability and system reliability of the signal. The wider the eye width, the higher the tolerance of the system to clock jitter, data skew, and intersymbol interference. Therefore, the phase relationship between the clock signal and the data signal can be adjusted to dynamically correct the clock skew value of the clock signal to the data signal, so as to improve the eye width of the eye diagram and improve the quality of the eye diagram.

[0051] Among them, the clock signal and the data signal are transmitted in the form of differential signals. The differential signal is transmitted by two wires to transmit a pair of signals with equal amplitude and opposite phase, and the receiving end extracts the effective information by comparing the difference between the two. It is beneficial to resist common-mode noise and reduce crosstalk, etc.

[0052] The timing control chip can obtain a first time point of a data signal in a first period of an eye diagram, a second time point of the data signal, and a third time point of a clock signal in the first period of the eye diagram based on the current eye diagram data of the display.

[0053] ​In the eye diagram data, the first period can be any one period in the eye diagram. The negative intersection time point of the data signal and the horizontal axis in the first period is the first time point, that is, the time point at which the data signal first crosses the horizontal axis (zero voltage level) from the negative voltage region into the positive voltage region in the first period. The positive intersection time point of the data signal and the horizontal axis in the first period is the second time point, that is, the time point at which the data signal last crosses the horizontal axis from the positive voltage region into the negative voltage region in the first period. The intersection time point of the clock signal and the horizontal axis in the first period is the third time point, that is, the time point at which the clock signal crosses the horizontal axis in the first period (usually the rising edge).

[0054] In a possible implementation, the timing control chip can automatically identify the negative intersection time point of the data signal and the horizontal axis in the first period of the eye diagram based on the current eye diagram data of the display, and determine the negative intersection time point as the first time point. The timing control chip can automatically identify the positive intersection time point of the data signal and the horizontal axis in the first period of the eye diagram based on the current eye diagram data of the display, and determine the positive intersection time point as the second time point. The timing control chip can automatically identify the intersection time point of the clock signal and the horizontal axis in the first period of the eye diagram based on the current eye diagram data of the display, and determine the intersection time point as the third time point.

[0055] As shown in Figure 3 , Figure 3 is a schematic diagram of an eye diagram provided by an embodiment of the present application. The eye diagram is composed of the superposition of the clock signal and the data signal. In Figure 3 , the solid line represents the data signal, and the dashed line represents the clock signal. The part framed by the rectangular box is the first period. Optionally, the first period can also be any other period in the eye diagram.

[0056] The timing control chip can automatically identify the current eye diagram of the display, identify the negative intersection time point of the data signal and the horizontal axis in the first period, that is, T1 in Figure 3 , and determine T1 as the first time point. The timing control chip can identify the positive intersection time point of the data signal and the horizontal axis in the first period, that is, T2 in Figure 3 , and determine T2 as the second time point. The timing control chip can identify the intersection time point of the clock signal and the horizontal axis in the first period, that is, T3 in Figure 3 , and determine T3 as the third time point.

[0057] S202, based on the first time point, the second time point and the third time point, calculate the first phase difference between the data signal and the clock signal, and the second phase difference between the data signal and the clock signal.

[0058] In a possible implementation, the first phase difference between the data signal and the clock signal can be calculated based on the first time point and the third time point, and the second phase difference between the data signal and the clock signal can be calculated based on the second time point and the third time point. That is, the time difference between the first time point and the third time point is the first phase difference, and the time difference between the second time point and the third time point is the second phase difference.

[0059] The clock offset value of the clock signal to the data signal is the sum of the first phase difference and the second phase difference, and the eye width is the sum of the first phase difference and the second phase difference. The greater the sum of the first phase difference and the second phase difference, the greater the eye width, the higher the tolerance of the system to non-ideal factors such as clock jitter and transmission delay, the more reliable the signal quality, and the better the final display effect.

[0060] As shown in FIG. 1, Figure 3 the first phase difference is T3-T1, and the second phase difference is T2-T3. The eye width is T2-T1.

[0061] The first phase difference is the setup time of the data signal, and the second phase difference is the hold time of the data signal. The setup time is the minimum time during which the data signal must be stable before the arrival of the active edge (such as the rising edge or the falling edge) of the clock signal, which is used to ensure that the data is completely stable when the clock is sampled, so as to avoid sampling errors caused by data changes. The hold time is the minimum time during which the data signal must be stable after the arrival of the active edge of the clock signal, which is used to prevent the data from changing rapidly after the clock is sampled, so as to prevent the sampling result from being unstable.

[0062] In the mini protocol, the minimum values of the setup time and the hold time are explicitly specified. When transmitting the data signal and the clock signal to the external device (such as a receiving chip, a bus, or other modules), the driving chip needs to ensure that the time difference between the actual transmitted data signal and the clock signal meets the minimum values of the setup time and the hold time. If the setup time is insufficient, the clock may sample unstable data in a transition state; if the hold time is insufficient, the data may change immediately after the sampling is completed, resulting in a latch error value at the receiving end.

[0063] In a possible implementation, the timing control chip includes an algorithm controller, which can be used to calculate the first phase difference between the data signal and the clock signal based on the first time point, the second time point, and the third time point, and the second phase difference between the data signal and the clock signal.

[0064] In S203, the signal output control of the driving module of the display is performed based on the first phase difference and the second phase difference.

[0065] The driving module of the display includes a timing control chip and a driving chip, and the timing control chip or the driving chip is controlled to output a signal based on the first phase difference and the second phase difference.

[0066] As shown in Figure 4 , Figure 4 a flowchart for controlling the timing control chip to output a signal is provided.

[0067] S401, the timing control chip sends a start signal to the driving chip. Correspondingly, the driving chip receives the start signal from the timing control chip.

[0068] The start signal is used to instruct the driving chip to drive the display to display a target picture.

[0069] In the embodiment of the present application, the driving chip is the first driving chip in Figure 1 .

[0070] It can be understood that the driving chip can also be any one of the driving chips other than the first driving chip in Figure 1 . At this time, the start signal is sent by the previous driving chip of the driving chip. For example, when the driving chip is the second driving chip as shown in Figure 1 , the start signal is sent from the first driving chip to the second driving chip, and the start signal is used to instruct the second driving chip to drive the display to display a target picture. When the driving chip is the Nth driving chip as shown in Figure 1 , the start signal is sent from the (N-1)th driving chip to the Nth driving chip, and the start signal is used to instruct the Nth driving chip to drive the display to display a target picture.

[0071] S402, the driving chip drives the display to display a target picture.

[0072] In the embodiment of the present application, after receiving the start signal, the driving chip immediately activates the driving stage circuit of the channel 1 to the channel 966. Each channel outputs a pulse width modulation (PWM) signal or an analog voltage in turn according to a preset row scanning timing (such as row-by-row lighting or partition refreshing), and drives the corresponding display unit to display a target picture. The target picture is a picture without content, such as a black picture, a blank picture, etc. This avoids the picture from being seen by the user due to other interference during the initial transmission of data.

[0073] S403, the driving chip sends an end signal to the timing control chip. Correspondingly, the timing control chip receives the end signal from the driving chip.

[0074] In the embodiment of the present application, the driving chip sends an end signal to the timing control chip after completing the output of the target picture. The end signal is used to indicate that the driving chip has completed the output of the target picture.

[0075] It can be understood that, when the driving chip is Figure 1 any one of the driving chips other than the first driving chip, the driving chip sends an end signal to the timing control chip after completing the output of the target picture.

[0076] For example, when the driving chip is Figure 1 the second driving chip as shown in FIG. 2, the second driving chip sends an end signal to the timing control chip after completing the output of the target picture. The end signal is used to indicate that the second driving chip has completed the output of the target picture. When the driving chip is Figure 1 the Nth driving chip as shown in FIG. 3, the Nth driving chip sends an end signal to the timing control chip after completing the output of the target picture. The end signal is used to indicate that the Nth driving chip has completed the output of the target picture.

[0077] In a possible implementation, the timing control chip comprises a signal controller configured to receive the end signal from the driving chip.

[0078] S404, the timing control chip generates the current eye diagram data of the display.

[0079] In a possible implementation, the timing control chip generates the current eye diagram data of the display upon receiving the end signal from the driving chip.

[0080] In a possible implementation, the timing control chip further receives a data signal and a clock signal from the driving chip. The timing control chip generates the current eye diagram data of the display based on the data signal and the clock signal upon receiving the end signal from the driving chip.

[0081] S405, the timing control chip obtains, based on the current eye diagram data of the display, a first time point of the data signal, a second time point of the data signal, and a third time point of the clock signal in a first period of the eye diagram.

[0082] S406, the timing control chip calculates, based on the first time point, the second time point, and the third time point, a first phase difference between the data signal and the clock signal, and a second phase difference between the data signal and the clock signal.

[0083] The specific implementation of steps S405-S406 can refer to steps S201-S202 in the above Figure 2 , and will not be described here again.

[0084] S407, the timing control chip determines the output time of the data signal based on the first phase difference and the second phase difference.

[0085] In the embodiments of the present application, in the case that the first phase difference is less than the first threshold, the output time of the data signal can be determined based on the first phase difference and the first threshold; or in the case that the second phase difference is less than the second threshold, the output time of the data signal can be determined based on the second phase difference and the second threshold.

[0086] The first threshold is the minimum value of the setup time of the data signal, and the second threshold is the minimum value of the hold time of the data signal. In the case that the first phase difference between the data signal and the clock signal satisfies the first threshold (i.e. the first phase difference is greater than or equal to the first threshold), and the second phase difference between the data signal and the clock signal satisfies the second threshold (i.e. the second phase difference is greater than or equal to the second threshold), the data signal can maintain a clear eye pattern, and there is no risk of display abnormality.

[0087] For example, the first threshold is set to 400 ps, and the second threshold is set to 400 ps. Taking the first phase difference of 300 ps and the second phase difference of 500 ps as an example. At this time, the first phase difference is less than the first threshold, and the second phase difference is greater than the second threshold. The output time of the data signal can be determined based on the first phase difference and the first threshold. That is, based on the first phase difference of 300 ps and the first threshold of 400 ps, the output time of the data signal is adjusted by 100 ps.

[0088] S408, the timing control chip outputs the data signal to the driving chip based on the output time of the data signal.

[0089] In the embodiments of the present application, the timing control chip can output the data signal to the driving chip based on the re-determined output time of the data signal when transmitting the data signal and the clock signal corresponding to the next frame of image, and output the clock signal to the driving chip based on the originally scheduled output time of the clock signal.

[0090] The timing control chip adjusts the first phase difference or the second phase difference between the data signal and the clock signal by controlling the output time of the data signal output to the driving chip, until the first phase difference between the data signal and the clock signal satisfies the first threshold, and the second phase between the data signal and the clock signal satisfies the second threshold. It is ensured that within the maximum allowed clock offset value range, the data signal and the clock signal can still maintain a clear eye pattern, thereby avoiding picture abnormalities such as display flicker, screen flashing, data disorder, etc.

[0091] S409, when the first phase difference is less than the first threshold, the timing control chip determines the delay time information of the data signal and performs delayed output processing on the data signal based on the delay time information; or when the second phase difference is less than the second threshold, it determines the advance time information of the data signal and performs advance output processing on the data signal based on the advance time information.

[0092] In this embodiment, the timing control chip can determine the delay time information of the data signal when the first phase difference is less than a first threshold, and perform delayed output processing on the data signal based on the delay time information when transmitting the data signal and clock signal corresponding to the next frame image. Simultaneously, the clock signal is output according to the originally planned clock signal output time. The delay time information includes the time that the data signal needs to be delayed for output, and the timing control chip performs delayed output processing on the data signal based on this required delay time.

[0093] The timing control chip can determine the advance time information of the data signal when the second phase difference is less than the second threshold. When transmitting the data signal and clock signal corresponding to the next frame of the image, it performs advance output processing on the data signal based on the advance time information. Simultaneously, the clock signal is output according to the originally planned clock signal output time. The advance time information includes the time by which the data signal needs to be output in advance, and the timing control chip performs advance output processing on the data signal based on this required advance output time.

[0094] The timing control chip adjusts the first phase difference or the second phase difference between the data signal and the clock signal by performing delayed output processing or advanced output processing on the data signal, until the first phase difference between the data signal and the clock signal meets the first threshold and the second phase difference between the data signal and the clock signal meets the second threshold.

[0095] It should be noted that steps S407 and S408 are one implementation method, while step S409 is another implementation method.

[0096] Through the embodiments of this application, the timing control chip can control the timing of the data signal output to the driver chip by detecting and analyzing the data signal and the clock signal, thereby ensuring that the first phase difference between the data signal and the clock signal meets the first threshold and the second phase between the data signal and the clock signal meets the second threshold, thus improving the quality of the eye diagram and improving the display effect of the display.

[0097] like Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a timing control chip provided in an embodiment of this application.

[0098] The timing control chip includes a data detection module 510, a data analysis module 520, and a differential signal output module 530.

[0099] The data detection module 510 can be used to obtain the first time point of the data signal and the second time point of the data signal in the first cycle of the eye diagram, as well as the third time point of the clock signal in the first cycle of the eye diagram, based on the current eye diagram data of the display.

[0100] The data analysis module 520 can be used to calculate the first phase difference between the data signal and the clock signal, and the second phase difference between the data signal and the clock signal, based on the first time point, the second time point, and the third time point.

[0101] In one possible implementation, the differential signal output module 530 can be used to determine the output time of the data signal based on the first phase difference and the second phase difference; and to output the data signal to the driver chip based on the output time of the data signal.

[0102] In one possible implementation, the differential signal output module 530 can be used to determine the output time of the data signal based on the first phase difference and the first threshold when the first phase difference is less than the first threshold; or to determine the output time of the data signal based on the second phase difference and the second threshold when the second phase difference is less than the second threshold.

[0103] In another possible implementation, the differential signal output module 530 can be used to determine the delay time information of the data signal when the first phase difference is less than a first threshold, and perform delayed output processing on the data signal based on the delay time information; or to determine the advance time information of the data signal when the second phase difference is less than a second threshold, and perform advance output processing on the data signal based on the advance time information.

[0104] like Figure 6 As shown, Figure 6 This is a schematic diagram of a signal output control process for a driver chip, provided as an embodiment of this application.

[0105] S601, the timing control chip sends a start signal to the driver chip. Correspondingly, the driver chip receives the start signal from the timing control chip.

[0106] S602, the driver chip drives the display to show the target image.

[0107] S603, the driver chip sends a stop signal to the timing control chip. Correspondingly, the timing control chip receives the stop signal from the driver chip.

[0108] S604, the timing control chip, generates the current eye diagram data of the display.

[0109] S605, the timing control chip obtains, based on current eye diagram data of the display, a first time point of the data signal, a second time point of the data signal, and a third time point of the clock signal in a first period of the eye diagram.

[0110] S606, the timing control chip calculates, based on the first time point, the second time point, and the third time point, a first phase difference between the data signal and the clock signal, and a second phase difference between the data signal and the clock signal.

[0111] The specific implementation of steps S601-S606 can refer to steps S401-S406 in the above Figure 4 , and will not be described here again.

[0112] S607, the timing control chip sends an output adjustment signal to the driving chip in a case where the first phase difference or the second phase difference satisfies a control condition. Correspondingly, the driving chip receives the output adjustment signal from the timing control chip.

[0113] The control condition is that the first phase difference is less than a first threshold value, and the second phase difference is less than a second threshold value. The first phase difference or the second phase difference satisfying the control condition means that the first phase difference is less than the first threshold value, or the second phase difference is less than the second threshold value. The output adjustment signal is used to control the driving chip to adjust the output time of the data signal according to a register parameter.

[0114] In the embodiment of the application, the timing control chip will send the output adjustment signal to the driving chip in a case where the first phase difference is less than the first threshold value, or the second phase difference is less than the second threshold value.

[0115] In a possible implementation, the timing control chip includes a control pin. The timing control chip sets the control pin to a high level in a case where the first phase difference is less than the first threshold value, or the second phase difference is less than the second threshold value. At this time, the timing control chip will send a high-level signal to the driving chip, and the high-level signal is the output adjustment signal.

[0116] S608, the driving chip adjusts the output time of the data signal according to the register parameter.

[0117] The register parameter is composed of 8 binary bits (Bit), each bit can represent 0 or 1, and the register parameter can include 256 levels (0-255).

[0118] In a possible implementation, each level can correspond to different adjustment time of the data signal, and different register parameters are used to realize high-precision output adjustment of the data signal.

[0119] In a possible implementation, when the first phase difference is less than the first threshold, the driving chip delays the output of the data signal according to the register parameter; and when the second phase difference is less than the second threshold, the driving chip advances the output of the data signal according to the register parameter.

[0120] For example, the adjustment time of the data signal corresponding to the register parameter with a level of 0 to the register parameter with a level of 255 is 1 ps to 256 ps.

[0121] When the first phase difference is less than the first threshold and the register parameter corresponds to a level of 0, the driving chip delays the output of the data signal to the display unit by 1 ps; when the second phase difference is less than the second threshold and the register parameter corresponds to a level of 0, the driving chip advances the output of the data signal to the display unit by 1 ps. When the first phase difference is less than the first threshold and the register parameter corresponds to a level of 20, the driving chip delays the output of the data signal to the display unit by 21 ps; when the second phase difference is less than the second threshold and the register parameter corresponds to a level of 20, the driving chip advances the output of the data signal to the display unit by 21 ps.

[0122] In another possible implementation, each level corresponds to a different output time of the data signal. The output time of the data signal is directly determined by the different register parameters.

[0123] For example, the output time of the data signal corresponding to the register parameter with a level of 0 to the register parameter with a level of 255 is increased by a level. The lower the level corresponding to the register parameter, the earlier the output time of the data signal by the driving chip. Correspondingly, the higher the level corresponding to the register parameter, the later the output time of the data signal by the driving chip.

[0124] The output time of the data signal by the timing control chip corresponds to the register parameter with a level of 125. When the first phase difference is less than the first threshold, the driving chip can adjust the register parameter to be decreased by a level starting from the register parameter with a level of 125, thereby delaying the output of the data signal; and when the second phase difference is less than the second threshold, the driving chip can adjust the register parameter to be increased by a level starting from the register parameter with a level of 125, thereby advancing the output of the data signal.

[0125] In one possible implementation, the driver chip can adjust the output time of the data signal to the display unit of the monitor according to register parameters while transmitting the data signal and clock signal corresponding to the current frame image. Optionally, the driver chip can also adjust the output time of the data signal to the display unit of the monitor according to register parameters while transmitting the data signal and clock signal corresponding to the next frame image.

[0126] S609, the timing control chip sets the control pin to a low level when the first phase difference and the second phase difference do not meet the control conditions.

[0127] In one possible implementation, when the timing control chip detects that the first phase difference and the second phase difference do not meet the control conditions, it sets the control pin to a low level. At this time, the timing control chip will send a low-level signal to the driver chip. This low-level signal is used to instruct the driver chip not to adjust the output time of the data signal according to the register parameters, but to output the data signal according to the original data signal output time.

[0128] Through the embodiments of this application, the timing control chip can detect and analyze data signals and clock signals, and when the first phase difference or the second phase difference meets the control conditions, send an output adjustment signal to the driver chip. The driver chip then controls the signal output of the display's driving module. This reduces the computing power required by the timing control chip, lowers its cost, and improves the quality of the eye diagram, thereby enhancing the display effect.

[0129] Simultaneously, a dynamic image quality optimization function interface can be opened to users. When the signal integrity of the user-end product deteriorates due to environmental factors such as component aging, temperature drift, or external power fluctuations during long-term use (e.g., eye diagram opening deterioration, increased jitter), users can enable the intelligent compensation mode by calling the open dynamic image quality optimization function interface. After activation, the system's built-in timing control chip will initiate real-time eye diagram detection and analysis. When the first phase difference or second phase difference of the eye diagram meets the control conditions, it sends an output adjustment signal to the driver chip, which then controls the signal output of the user-end product's drive module. This achieves dynamic recovery of eye diagram quality without manual intervention, ensuring that the displayed image always maintains the design standard signal-to-noise ratio and bit error rate performance.

[0130] like Figure 7 As shown, Figure 7 This is a schematic diagram of the structure of a timing control chip and a driver chip provided in an embodiment of this application.

[0131] The timing control chip comprises a data detection module 710 and a data analysis module 720. The drive chip comprises a signal receiving module 730, a register control module 740 and a differential signal output module 750.

[0132] The data detection module 710 is configured to obtain a first time point of the data signal, a second time point of the data signal and a third time point of the clock signal in a first period of the eye diagram based on current eye diagram data of the display.

[0133] The data analysis module 720 is configured to calculate a first phase difference between the data signal and the clock signal and a second phase difference between the data signal and the clock signal based on the first time point, the second time point and the third time point.

[0134] The signal receiving module 730 is configured to receive an output adjustment signal from the timing control chip.

[0135] The register control module 740 is configured to cache a register parameter.

[0136] The differential signal output module 750 is configured to adjust an output time of the data signal according to the register parameter.

[0137] The embodiments of the present application also provide an electronic device, please refer to Figure 8 , Figure 8 The electronic device provided by the embodiments of the present application is shown in a structural schematic diagram.

[0138] As Figure 8 shown, the electronic device can comprise one or more processors 810, one or more memories 830, one or more communication interfaces 820 and a bus 840, and the above-mentioned processor 810, memory 830 and communication interface 820 are connected through the bus 840.

[0139] The memory 830 is configured to store a program, and the processor 810 is configured to execute the above-mentioned program stored in the memory. When the above-mentioned program is executed, the processor 810 executes the method in any possible implementation manner of the above-mentioned display driving method.

[0140] It should be understood that, in the embodiments of the present application, the memory 830 includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read only memory (EPROM), or a compact disc read-only memory (CDROM), and an external memory other than a computer memory and a processor cache. Part of the memory 830 can also include a non-volatile random access memory, for example, the memory 830 can also store device type information.

[0141] The processor 810 can be one or more central processing units (CPUs). When the processor 810 is a CPU, the CPU can be a single-core CPU or a multi-core CPU. The processor 810 can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0142] The steps performed in the foregoing embodiments can be based on the above Figure 8 The processor 810 can implement the implementation manners described in any one of the optional embodiments of the display driving method provided in the embodiments of the present application, as shown in the structure of the electronic device. The memory 830 can provide a cache when the processor 810 performs the method in any one of the possible embodiments of the display driving method, and can also store the computer program required for the processor 810 to perform the method in any one of the possible embodiments of the display driving method.

[0143] In a possible implementation manner, the electronic device can be connected to a display device in a wired or wireless manner, and the display device includes a timing control chip and a driving chip. When the electronic device is connected to the display device, the timing control chip and the driving chip in the display device can implement the method shown in any one of the above Figure 2 、 Figure 4 or Figure 6 .

[0144] This application also provides a computer storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, enable the processor to implement the above-mentioned functions. Figure 2 , Figure 4 or Figure 6 The method shown.

[0145] This application also provides a computer program product, which includes: instructions or a computer program; when the instructions or the computer program are executed, the above-mentioned functions can be achieved. Figure 2 , Figure 4 or Figure 6 The method shown.

[0146] This application also provides a chip, which includes a processor. The processor executes instructions, enabling the chip to achieve the aforementioned... Figure 2 , Figure 4 or Figure 6 The method shown is described above. Optionally, the chip also includes a communication interface for receiving or transmitting signals.

[0147] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by hardware related to computer programs. The computer programs can be stored in computer storage media, and when executed, they can implement the processes of the above method embodiments. The aforementioned computer storage media include various media capable of storing computer program code, such as read-only memory (ROM) or random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A display driving method, characterized by, The method comprises: obtaining, based on current eye diagram data of a display, a first time point of a data signal in a first period of the eye diagram, a second time point of the data signal, and a third time point of a clock signal in the first period of the eye diagram; calculating, based on the first time point, the second time point, and the third time point, a first phase difference between the data signal and the clock signal, and a second phase difference between the data signal and the clock signal; controlling, based on the first phase difference and the second phase difference, signal output of a driving module of the display; wherein, in the eye diagram data, a negative intersection time point of the data signal with a horizontal axis in the first period is the first time point, a positive intersection time point of the data signal with the horizontal axis in the first period is the second time point, and an intersection time point of the clock signal with the horizontal axis in the first period is the third time point.

2. The method of claim 1, wherein, The driving module comprises a driving chip, and the controlling, based on the first phase difference and the second phase difference, signal output of the driving module of the display comprises: determining, based on the first phase difference and the second phase difference, an output time of the data signal; outputting, based on the output time of the data signal, the data signal to the driving chip.

3. The method of claim 2, wherein, The determining, based on the first phase difference and the second phase difference, the output time of the data signal comprises: in a case where the first phase difference is less than a first threshold, determining, based on the first phase difference and the first threshold, the output time of the data signal; or in a case where the second phase difference is less than a second threshold, determining, based on the second phase difference and the second threshold, the output time of the data signal.

4. The method of claim 1, wherein, The controlling, based on the first phase difference and the second phase difference, signal output of the driving module of the display comprises: in a case where the first phase difference is less than a first threshold, determining delay time information of the data signal, and performing delay output processing on the data signal based on the delay time information; or in a case where the second phase difference is less than a second threshold, determining advance time information of the data signal, and performing advance output processing on the data signal based on the advance time information.

5. The method according to any one of claims 2 to 4, wherein, Before the obtaining, based on current eye diagram data of a display, a first time point of a data signal in a first period of the eye diagram, a second time point of the data signal, and a third time point of a clock signal in the first period of the eye diagram, the method further comprises: sending a start signal to the driving chip, the start signal being used to instruct the driving chip to drive the display to display a target picture; generating the current eye diagram data of the display upon receiving an end signal from the driving chip.

6. The method according to any one of claims 1 to 4, wherein The driving module comprises a driving chip, and the controlling, based on the first phase difference and the second phase difference, signal output of the driving module of the display comprises: In a case where the first phase difference or the second phase difference meets a control condition, an output adjustment signal is sent to the driving chip, and the output adjustment signal is used to control the driving chip to adjust an output time of the data signal according to a register parameter.

7. The method of claim 6, wherein, The method further includes: In a case where the first phase difference and the second phase difference do not meet the control condition, a control pin is set to a low level.

8. A display device, characterized by The display device includes a driving module, and the driving module includes a timing control chip and a driving chip; the driving chip is configured to display an image picture through a display unit in response to control of the timing control chip. The timing control chip is configured to obtain, based on current eye diagram data of the display, a first time point of a data signal in a first period of the eye diagram, a second time point of the data signal, and a third time point of a clock signal in the first period of the eye diagram. The timing control chip is further configured to calculate, based on the first time point, the second time point, and the third time point, a first phase difference between the data signal and the clock signal, and a second phase difference between the data signal and the clock signal. The timing control chip is further configured to perform signal output control on a driving module of the display based on the first phase difference and the second phase difference. In the eye diagram data, a negative intersection time point of the data signal and a horizontal axis in the first period is the first time point, a positive intersection time point of the data signal and the horizontal axis in the first period is the second time point, and an intersection time point of the clock signal and the horizontal axis in the first period is the third time point.

9. The display device of claim 8, wherein, The timing control chip is further configured to, in a case where the first phase difference or the second phase difference meets a control condition, send an output adjustment signal to the driving chip, and the output adjustment signal is used to control the driving chip to adjust an output time of the data signal according to a register parameter.

10. The display device of claim 8, wherein, The timing control chip is further configured to, in a case where the first phase difference and the second phase difference do not meet the control condition, set a control pin to a low level.

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