Grid-friendly energy storage converter self-grid control protection method and device and medium

Abstract

The application provides a grid-connected friendly energy storage converter self-networking control protection method, device and medium. The method comprises the following steps: collecting electrical quantities of a grid-connected point and a direct current side, establishing a short-circuit capacity estimation value and a positive and negative zero sequence model, and generating a voltage phasor reference; generating a frequency given value and a voltage given value according to power and frequency droop and reactive power and voltage droop; performing generalized impedance shaping in a control loop, configuring virtual impedance and selective filtering according to frequency bands; completing grid connection or reconnection according to the order of frequency slope, phase angle alignment and voltage amplitude convergence based on the grid-connected point reference phasor; setting positive sequence, negative sequence and zero sequence fault current upper limits and time sequence templates in a symmetrical component domain; and outputting the frequency given value, the voltage given value, the sequence component limit value and the protection state instruction to a converter power bridge drive and a grid-connected switch control interface. The application can realize no-phase-lock grid connection synchronization, unified control protection switching, sequence component controlled fault current and weak grid stable operation.

Description

Technical Field

[0001] This application relates to the field of new energy technology, and in particular to a grid-connected grid-friendly energy storage converter self-networked control and protection method, device and medium. Background Technology

[0002] The high proportion of new energy sources connected to the grid causes fluctuations in the short-circuit capacity of the distribution network and increases the branch impedance. Energy storage converters undertake multiple tasks such as black start, islanded power supply, grid connection support and reconnection, and need to form controllable and limitable power behavior in terms of voltage, frequency and fault current.

[0003] Existing solutions mainly rely on grid-connected follower control, which depends on phase-locked loops to obtain phase, and power and reactive power are mostly measured by fixed droop parameters. Although some self-contained grid solutions can independently build voltage and frequency, control and protection are mostly designed separately, impedance shaping is concentrated in a single frequency band, grid-connected synchronization is mostly achieved by hard phase-locked loops, and fault current limiting is achieved by current inner loop saturation or simple derating.

[0004] However, existing technologies still have the following problems: negative damping and oscillations are prone to occur under weak grid and disturbance conditions; the switching between grid-connected, islanded, and current-limiting protection lacks a unified state machine and invariant constraints, leading to transient impacts; the reconnection process is insufficient in suppressing negative sequence and harmonics; fault currents are difficult to synthesize in a controlled manner in the positive, negative, and zero sequence dimensions; external commands lack feasible domains and rate constraints; droop and inertia settings do not adapt to short-circuit capacity and state of charge, making it difficult to balance self-contained grid capability and grid-friendly characteristics. Summary of the Invention

[0005] In view of this, embodiments of this application provide a grid-connected, grid-friendly energy storage converter self-contained control and protection method, device, and medium to solve the problems of existing technologies, such as grid-connected synchronization relying on phase-locked loops and unstable weak grids, lack of unified state switching constraints for control and protection, and uncontrollable synthesis of fault current in the sequence component domain.

[0006] A first aspect of this application provides a grid-connected, grid-friendly energy storage converter self-contained control and protection method, comprising: collecting electrical quantities at the grid connection point and the DC side, establishing short-circuit capacity estimates and positive and negative zero-sequence models, and generating a voltage phasor reference; enabling parallel control of the voltage inner loop and current inner loop without relying on a phase-locked loop, generating frequency and voltage setpoints based on power and frequency droop and reactive and voltage droop, and adaptively tuning the droop coefficient and inertia parameters based on the energy storage state of charge and short-circuit capacity estimates; performing generalized impedance shaping in the control loop, configuring virtual impedance and selective filtering according to the frequency band, and updating the impedance template through online identification; performing amplitude and rate constraints and compatibility checks on external power, reactive, voltage, or frequency commands, and verifying the results. The instructions are injected into the droop loop under the constraints of power change rate and frequency change rate; grid connection or reconnection is completed in the order of frequency ramp, phase angle gradual alignment and voltage amplitude convergence based on the grid connection point reference phasor; positive sequence, negative sequence and zero sequence fault current upper limits and timing templates are set in the symmetrical component domain, and a unified priority is established with current limiting and DC side protection to synthesize limited fault current; the system switches between self-grid, grid-connected operation and protection current limiting states in an event-triggered manner, and maintains voltage phasor continuity, phase angle and power change rate limitation and impedance template smooth migration during the switching process; the frequency setpoint, voltage setpoint, sequence component limit and protection status instructions are output to the converter power bridge drive and grid-connected switch control interface for control and protection execution of the self-grid and grid-connected operation of the energy storage converter.

[0007] A second aspect of this application provides a grid-connected, grid-friendly energy storage converter self-contained control and protection device, comprising: a data acquisition module for acquiring electrical quantities at the grid connection point and the DC side, establishing a short-circuit capacity estimate and a positive and negative zero-sequence model, and generating a voltage phasor reference; a control module for enabling parallel control of the voltage inner loop and the current inner loop without relying on a phase-locked loop, generating a frequency setpoint and a voltage setpoint based on power and frequency droop and reactive power and voltage droop, and adaptively tuning the droop coefficient and inertia parameter based on the energy storage state of charge and the short-circuit capacity estimate; a configuration module for performing generalized impedance shaping in the control loop, configuring virtual impedance and selective filtering according to the frequency band, and updating the impedance template through online identification; and a verification module for performing amplitude and rate constraints and compatibility verification on external power, reactive power, voltage, or frequency commands, and verifying the parameters that pass the verification. The instructions are injected into the droop loop under the constraints of power change rate and frequency change rate; the grid connection module is used to complete grid connection or reconnection based on the grid connection point reference phasor in the order of frequency ramp, phase angle gradual alignment and voltage amplitude gradual convergence; the synthesis module is used to set the upper limit of positive sequence, negative sequence and zero sequence fault current and the timing template in the symmetrical component domain, and establish a unified priority with current limiting and DC side protection to synthesize the limited fault current; the switching module is used to switch between self-grid, grid-connected operation and protection current limiting state in an event-triggered manner, and maintain voltage phasor continuity, phase angle and power change rate limitation and impedance template smooth migration during the switching process; the output module is used to output the frequency setpoint, voltage setpoint, sequence component limit and protection status instructions to the converter power bridge drive and grid connection switch control interface, and to control and protect the self-grid and grid-connected operation of the energy storage converter.

[0008] A third aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method.

[0009] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0010] By collecting electrical quantities at the grid connection point and the DC side, short-circuit capacity estimates and positive / negative zero-sequence models are established, generating a voltage phasor reference. Without relying on a phase-locked loop (PLL), parallel control of the voltage inner loop and current inner loop is enabled. Frequency and voltage setpoints are generated based on power and frequency droop, reactive power and voltage droop, and adaptive tuning of the droop coefficient and inertia parameters is performed based on the energy storage state of charge and short-circuit capacity estimates. Generalized impedance shaping is executed in the control loop, configuring virtual impedance and selective filtering according to frequency bands, and updating the impedance template through online identification. Amplitude and rate constraints and compatibility checks are performed on external power, reactive power, voltage, or frequency commands. Commands that pass the checks are then controlled under power change rate and frequency change rate constraints. The system injects a droop loop; based on the grid connection point reference phasor, it completes grid connection or reconnection in the order of frequency ramp, phase angle gradual alignment, and voltage amplitude gradual convergence; it sets positive sequence, negative sequence, and zero sequence fault current upper limits and timing templates in the symmetrical component domain, and establishes a unified priority with current limiting and DC side protection to synthesize limited fault currents; it switches between self-networked, grid-connected, and protection current-limited states in an event-triggered manner, maintaining voltage phasor continuity, phase angle and power change rate limitations, and smooth impedance template migration during the switching process; it outputs frequency setpoint, voltage setpoint, sequence component limit, and protection status commands to the converter power bridge drive and grid-connected switch control interface for controlling and protecting the self-networked and grid-connected operation of the energy storage converter. This application can achieve phase-locked grid connection synchronization, unified control and protection switching, sequence component controlled fault current, and stable operation in weak grids. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of the grid-connected grid-friendly energy storage converter self-grid control and protection method provided in the embodiments of this application;

[0013] Figure 2 This is a schematic diagram of the structure of the grid-connected grid-friendly energy storage converter self-grid control and protection device provided in the embodiments of this application;

[0014] Figure 3 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0015] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0016] Existing energy storage converters are mostly grid-following type, relying on phase-locked loops to obtain phase, and power and reactive power are mostly fixed droop parameters; although some self-contained grid schemes can build voltage and frequency, control and protection are independent of each other, impedance shaping is concentrated in a single frequency band, grid synchronization is mostly hard phase-locked, fault current limiting often relies on current inner loop saturation or simple derating, and external dispatch commands lack feasible domain and rate constraints.

[0017] Existing technical solutions still have the following problems: negative damping and oscillations are prone to occur under weak grid conditions; there is a lack of unified state switching and invariant constraints between self-contained grid, grid-connected and current-limiting protection, resulting in transient impacts and instability; fault current is difficult to synthesize in a controlled manner in the positive sequence, negative sequence and zero sequence dimensions; droop and inertia parameters cannot adapt to short-circuit capacity and state of charge.

[0018] In view of the problems existing in the prior art, this application proposes a grid-connected, grid-friendly energy storage converter self-contained control and protection method: It collects electrical quantities at the grid connection point and DC side, establishes short-circuit capacity estimates and positive / negative zero-sequence models, and generates a voltage phasor reference; without relying on a phase-locked loop, the voltage inner loop and current inner loop operate in parallel, generating frequency and voltage references based on power and frequency droop, reactive power and voltage droop, and adaptively adjusting them according to the state of charge and short-circuit capacity; generalized impedance shaping is performed in the control loop, configuring virtual impedance and selective filtering according to the frequency band, and smoothly updating them through online identification. Template; After implementing feasible domain convex projection, rate gating, and compatibility discrimination on external active, reactive, voltage, and frequency commands through the command sandbox, inject droop loop; Based on the grid connection point reference phasor, complete grid connection or reconnection by frequency ramp, phase angle gradual alignment, and voltage amplitude gradual convergence; Set the upper limit of fault current and timing template in the symmetrical component domain and establish a unified priority with current limiting and DC side protection to synthesize limited fault current; Execute the switching between self-networked, grid-connected operation and current limiting protection with event-triggered state machine, maintaining voltage phasor continuity, phase angle and power change rate limitation, and impedance template smooth migration.

[0019] Through the above-mentioned technical solution of this application, this application can achieve phase-locked grid synchronization, form a unified control and protection switching mechanism, controllably synthesize fault current in the sequence component domain, and maintain stable and limited operation in weak grids and during reconnection.

[0020] The technical solution of this application will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0021] Figure 1 This is a schematic flowchart of the grid-connected grid-friendly energy storage converter self-network control and protection method provided in the embodiments of this application. Figure 1 As shown, the grid-connected, grid-friendly energy storage converter self-contained control and protection method may specifically include:

[0022] S101 collects electrical quantities at the grid connection point and DC side, establishes short-circuit capacity estimates and positive and negative zero sequence models, and generates voltage phasor references;

[0023] S102 enables parallel control of the voltage inner loop and the current inner loop without relying on the phase-locked loop. It generates frequency and voltage setpoints based on power and frequency droop, reactive power and voltage droop, and adaptively tunes the droop coefficient and inertia parameters based on the energy storage state of charge and short-circuit capacity estimate.

[0024] S103 performs generalized impedance shaping in the control loop, configures virtual impedance and selective filtering according to frequency band, and updates the impedance template through online identification;

[0025] S104 performs amplitude and rate constraints and compatibility checks on external power, reactive power, voltage or frequency commands, and injects commands that pass the checks into the droop loop under the constraints of power change rate and frequency change rate.

[0026] S105, based on the grid connection point reference phasor, completes grid connection or reconnection in the order of frequency ramp, phase angle gradual alignment and voltage amplitude gradual convergence;

[0027] S106, set the upper limit of positive sequence, negative sequence and zero sequence fault current and timing template in the symmetrical component domain, and establish a unified priority with current limiting and DC side protection to synthesize limited fault current.

[0028] S107 switches between self-contained network, grid-connected operation and protection current limiting state in an event-triggered manner, and maintains continuous voltage phasor, limited phase angle and power change rate and smooth migration of impedance template during the switching process;

[0029] S108 outputs the frequency setpoint, voltage setpoint, sequence component limit, and protection status command to the converter power bridge drive and grid-connected switch control interface for controlling and protecting the self-grid-connected and grid-connected operation of the energy storage converter.

[0030] In some embodiments, establishing short-circuit capacity estimates and positive and negative zero-sequence models to generate voltage phasor references includes:

[0031] A sliding phasor estimator gated by the rate of change of frequency is used to output positive sequence voltage and current phasors;

[0032] Positive-sequence and zero-sequence equivalent impedances are obtained through frequency band switchable perturbation injection and recursive online identification with forgetting factor, and short-circuit capacity estimates are calculated accordingly.

[0033] A voltage phasor reference is formed by a phasor generator with positive and negative zero sequence weighting under the dual boundaries of phase angle integration and amplitude limiting;

[0034] Specifically, when the rate of change of frequency or the identification deviation exceeds the limit, phasor freezing and parameter self-update are performed.

[0035] Specifically, firstly, the system collects three-phase voltage and current signals at the grid connection point, and obtains positive, negative, and zero-sequence channels through symmetrical component transformation; when the frequency change rate gating condition is met, the sliding phasor estimator outputs positive-sequence voltage and current phasors; then, under controlled amplitude perturbation injection, the system uses recursive online identification with a forgetting factor to obtain the positive-sequence and zero-sequence equivalent impedances and converts them into short-circuit capacity estimates; finally, a voltage phasor reference is formed by a positive-negative-zero-sequence weighted phasor generator under the dual boundaries of phase angle integration and amplitude limiting; when the frequency change rate or identification deviation exceeds the limit, phasor freezing and parameter self-update are triggered.

[0036] Furthermore, frequency change rate gating is used to limit the effective window of phasor estimation, updating phasors only when the frequency change rate is below a threshold, thus improving estimation stability; band-switched perturbation injection refers to switching the injection frequency and duration as needed among several preset low-frequency, subsynchronous, and harmonic frequency bands, ensuring that identifiable impedance information can be obtained under different power grid conditions; recursive online identification with a forgetting factor achieves a balance between gradual and abrupt parameter changes by setting the forgetting factor to adaptively adjust according to the operating state; phasor freezing refers to keeping the phasor unchanged and suspending the phase angle integration during abnormal periods, resuming continuous evolution after the parameters are updated; double-boundary phasor generation refers to the phase angle being integrated from the estimated frequency and constrained by the upper limit of the phase angle change rate, with the amplitude constrained within the allowable range by a limiter, while applying suppression weights to negative-sequence and zero-sequence components.

[0037] In some specific scenario examples, this embodiment can be implemented as follows: The sampling module acquires three-phase voltage and current at a fixed sampling period, first performing DC bias removal and bandpass filtering to remove stray components other than the power frequency; after symmetrical component transformation, a frequency change rate threshold is set and the positive sequence voltage and current phasors are estimated using a sliding window. The window length is adaptively selected according to one to two fundamental frequency periods. When the frequency change rate approaches the threshold, the window is automatically shortened to reduce hysteresis.

[0038] To obtain the equivalent impedance, the controller injects a low-amplitude perturbation current into the positive-sequence channel, with the perturbation frequency switching between low-frequency and subsynchronous frequency bands as planned. Intermittent injection is used in the zero-sequence channel to avoid persistent imbalance. The identification module employs recursive online identification, with the forgetting factor adjusted between 0.95 and 0.995 according to the operating status. The forgetting factor is reduced to accelerate convergence when the frequency change rate increases or the harmonic content increases. The identification output includes the amplitude and phase of the positive-sequence and zero-sequence equivalent impedances, as well as resonance characteristic indicators. The short-circuit capacity estimate is calculated based on the positive-sequence impedance amplitude and the rated voltage at the grid connection point.

[0039] The phasor generator uses the estimated frequency as the phase angle integral input and sets an upper limit on the phase angle change rate to limit the phase angle advance speed. The amplitude limiter sets the amplitude boundary according to the upper and lower limits of the grid connection point voltage. Signal suppression weights are set for negative-sequence and zero-sequence components to make the output voltage phasor reference predominantly positive-sequence and suppress unbalanced components. The controller continuously monitors the frequency change rate and identification deviation. When either exceeds the limit, phasor freezing is immediately performed, retaining the previous valid phasor and pausing phase angle integration. At the same time, the perturbation injection priority is increased, the identification frequency band is switched, and the forgetting factor is reset to a smaller value to accelerate re-identification. After the identification error falls back to within the threshold, phase angle integration is resumed according to the preset ramp and the freeze is lifted.

[0040] In a typical operating example, the grid connection point has a rated frequency of 50 Hz and a voltage level of 10 kV. The system sets the frequency change rate threshold to 0.5 Hz per second, the phase angle change rate upper limit to 20 degrees per second, and the voltage amplitude limit range to ±10% of the rated value. The perturbation injection amplitude does not exceed 5% of the rated current, the low-frequency injection lasts for 200 milliseconds, and the sub-synchronization injection lasts for 100 milliseconds, with the two being executed alternately. The initial value of the forgetting factor is 0.99, which is reduced to 0.97 when the detected frequency change rate exceeds 0.3 Hz per second or the harmonic distortion rate increases to accelerate parameter updates. Based on the identified positive-sequence equivalent impedance amplitude and the rated voltage, the short-circuit capacity estimate is calculated, and the positive and negative zero-sequence models are updated in real time. Under the above dual-boundary and weighted suppression conditions, the phasor generator outputs a voltage phasor reference, providing a unified phasor reference for subsequent droop control and grid synchronization.

[0041] In some embodiments, parallel control of the voltage inner loop and the current inner loop is enabled, and frequency and voltage setpoints are generated based on power and frequency droop and reactive power and voltage droop, including:

[0042] Construct a droop and inertia coordinator, with active power, reactive power, energy storage state of charge, short-circuit capacity estimate and frequency change rate as inputs, and output frequency and voltage setpoints as outputs;

[0043] The active power droop coefficient, reactive power droop coefficient and inertia parameter are segmented and the hysteresis dead zone is set by the energy and short-circuit capacity joint mapper.

[0044] Configure dual-domain rate constraints for power change rate and phase angle change rate, and gated integral based on frequency change rate;

[0045] Sequence weighting and negative sequence gating are introduced for reactive power and voltage droop to limit the voltage given component;

[0046] The voltage inner loop generates the current reference without relying on the phase-locked loop, and the current inner loop follows and executes accordingly.

[0047] Specifically, firstly, the controller uses active power, reactive power, energy storage state of charge, short-circuit capacity estimates, and frequency change rate as inputs to construct the output frequency and voltage setpoints of the droop and inertia coordinator; the active power droop coefficient, reactive power droop coefficient, and inertia parameters are segmented and hysteresis dead zones are set by the energy and short-circuit capacity joint mapper; before the setpoint injection, the controller is limited by a dual-domain rate constraint composed of power change rate and phase angle change rate, and instantaneous changes are suppressed by a frequency change rate gated integrator; the reactive power and voltage droop are weighted by sequence components and negative sequence gated to limit the components of the voltage setpoint; the voltage inner loop generates a current reference without relying on the phase-locked loop, and the current inner loop follows the same sampling and modulation time base.

[0048] Furthermore, the droop and inertia coordinator simultaneously generates frequency and voltage inputs within a single interface, and binds the inertia parameter and droop coefficient to a two-dimensional mapping surface of the state of charge and short-circuit capacity estimates; the joint mapping tuning employs segmented intervals and hysteresis dead zones to avoid parameter jitter; dual-domain rate constraints simultaneously limit the rate of change of active power and the rate of change of phase angle, and use the rate of change of frequency as a gating signal to control the integral switching; sequence component weighting and negative sequence gating adjust the weights of positive sequence, negative sequence, and zero sequence to ensure that the voltage input is predominantly positive sequence and automatically suppresses negative sequence when it exceeds the limit.

[0049] In some specific scenario examples, this embodiment can be implemented as follows: The controller periodically reads the active and reactive power measurements, the energy storage state of charge, and the short-circuit capacity estimate, while simultaneously calculating the frequency change rate. The droop and inertia coordinator takes the active power deviation and reactive power deviation as inputs, generates initial frequency and initial voltage values ​​through active power-frequency droop and reactive power-voltage droop, and superimposes the inertia term output by the joint mapping.

[0050] The joint mapping divides the state of charge (SOC) and short-circuit capacity estimate into three segments, forming a nine-grid parameter table. Each grid corresponds to a set of active power droop coefficients, reactive power droop coefficients, and inertia parameters. A hysteresis band is set between adjacent grids, and the parameter set is switched only when the SOC or short-circuit capacity estimate crosses the hysteresis band. The initial frequency value enters the frequency change rate-gated integrator. When the frequency change rate is below a threshold, the integrator operates and outputs the frequency setpoint; when it is above the threshold, it retains the previous output. The initial voltage value is constrained by a dual-domain rate constraint composed of the power change rate and the phase angle change rate, and then used to form the voltage setpoint according to the limiting value.

[0051] To avoid the effects of imbalance, the controller calculates the negative-sequence and zero-sequence amplitudes in real time. When the negative-sequence amplitude is below a threshold, normal weighting is used; when it exceeds the threshold, the negative-sequence weight is reduced and the zero-sequence weight is set to zero. Ultimately, the voltage inner loop generates a current reference using the voltage setpoint and voltage phasor reference as inputs, while the current inner loop performs error regulation and modulation output using the same time base. The phase-locked loop is not used throughout the entire process.

[0052] In a typical example, the grid connection point has a rated frequency of 50 Hz, and the energy storage state of charge varies between 30% and 90%. The short-circuit capacity estimate is divided into three segments: low, medium, and high. The joint mapping selects a smaller active droop coefficient and a larger inertia parameter in the low state of charge and low short-circuit capacity estimate range, and a larger active droop coefficient and a moderate inertia parameter in the high state of charge and high short-circuit capacity estimate range. The hysteresis band is set to 5% of the boundary between adjacent intervals. The frequency change rate threshold is set to 0.5 Hz per second, the phase angle change rate upper limit is set to 20 degrees per second, and the active power change rate upper limit is limited to 10% of the rated power per second. The negative sequence amplitude threshold is set to 5% of the positive sequence amplitude; when the threshold is exceeded, the negative sequence weight is reduced to 50% of its original value, and the zero sequence weight is reset to zero. Under these parameters, the controller completes the parallel execution of the voltage inner loop and the current inner loop within the same sampling and modulation time base. The frequency and voltage setpoints are continuously injected after dual-domain rate constraints, and the current reference is generated by the voltage inner loop and stably followed by the current inner loop.

[0053] This embodiment achieves continuous output of frequency and voltage settings under different states of charge and short-circuit capacity conditions through the coordination of droop and inertia, joint mapping and setting of energy and short-circuit capacity, and the combination of dual-domain rate constraint and sequence component weighted gating. The voltage inner loop and the current inner loop work together without phase-locked loop to achieve dynamic and limited adjustment of active power, reactive power and phase angle, and stable tracking of the inner loop.

[0054] In some embodiments, generalized impedance shaping is performed in the control loop, virtual impedance and selective filtering are configured by frequency band, and the impedance template is updated by online identification, including:

[0055] Establish an impedance template library segmented by low frequency, subsynchronous, harmonic and high frequency bands, configure virtual resistance, virtual inductance and admittance limiting parameters for positive sequence, negative sequence and zero sequence respectively, and bind switchable selective filter indexes.

[0056] A dual-channel perturbation injection and recursive online identification with a forgetting factor are used to identify the equivalent impedance and resonance characteristics of each sequence component within the frequency change rate threshold, and output the template update amount.

[0057] The selective filter index switching is driven by the short-circuit capacity estimate and resonance characteristics, and the impedance template is smoothly updated by template versioning and continuous interpolation.

[0058] Under the conditions of grid connection handshake, weak network protection and current limiting protection, the parameters of the mid-to-high frequency band are frozen, and only the damping parameters of the low frequency band are allowed to be updated. The updated impedance template is then connected to the voltage inner loop and the current inner loop.

[0059] Specifically, firstly, an impedance template library is established, segmented into low-frequency, subsynchronous, harmonic, and high-frequency bands. The low-frequency band is used to set virtual damping and phase lead elements; the subsynchronous band sets switchable notch and lead / lag combinations; the harmonic band configures targeted notches and admittance limits; and the high-frequency band configures equivalent rise inductance and admittance limiters. Virtual resistance parameters, virtual inductance parameters, and admittance limiting parameters are set for positive-sequence, negative-sequence, and zero-sequence signals, respectively, and switchable selective filter indices are bound to each segment. Each index corresponds to a set of center frequency, bandwidth, and gain parameters, recorded with a template version number.

[0060] Secondly, a dual-channel perturbation injection and recursive online identification with a forgetting factor are employed to generate template update amounts. The positive-sequence channel injects small-amplitude current perturbations alternately in the low-frequency and subsynchronous frequency bands, while the zero-sequence channel injects intermittently within a permissible window to avoid long-term imbalance. Identification and parameter updates are enabled only when the frequency change rate is below a threshold. The identification output includes the amplitude and phase of the equivalent impedance of each sequence component, the suspected resonant center frequency, and its quality factor, which are used to calculate the template update amount. The forgetting factor is adaptively adjusted according to the operating state, decreasing as the frequency change rate increases or harmonic parameters rise to accelerate convergence. To avoid abrupt changes, template parameters are smoothly transitioned by weight through continuous interpolation, and the update sequence is recorded with a version number and timestamp.

[0061] Furthermore, the selective filter index switching is driven by the short-circuit capacity estimate and resonance characteristics, and a segmented freezing strategy is implemented. When the short-circuit capacity estimate is lower than the threshold or the resonance index exceeds the threshold, the filter automatically switches to a stronger suppression index combination. During grid handshake, weak grid protection, and current limiting protection states, mid-to-high frequency parameters are frozen, allowing only low-frequency damping parameters to be updated. The updated impedance templates are then connected to the voltage inner loop feedforward and current inner loop limiting channels, ensuring that both inner loops call consistent template parameters under the same time base.

[0062] For example, in a typical example, the grid connection point has a rated voltage of 10 kV and a rated frequency of 50 Hz. The frequency band division and initial configuration are as follows: for the low frequency band (0.1 to 5 Hz), a virtual damping coefficient with a value range of 0.05 to 0.2 per unit is set, with a slight phase lead superimposed; for the subsynchronous band (5 to 40 Hz), a switchable notch filter is configured, with initial center frequencies of 25 Hz and 35 Hz, each with a bandwidth of 2 Hz; for the harmonic band (40 to 600 Hz), narrowband notches are set for 150 Hz and 250 Hz, with an admittance upper limit of 0.6 per unit of the rated admittance; for the high frequency band (greater than 600 Hz), an equivalent rising inductance parameter and an admittance limiter are set to suppress high-frequency circulating current.

[0063] The perturbation injection amplitude does not exceed 2% of the rated current. Low-frequency injection lasts for 200 milliseconds, and subsynchronous injection lasts for 120 milliseconds, alternating between the two. The frequency change rate threshold is set to 0.5 Hz per second. The recursive online identification forgetting factor is initially set to 0.99, decreasing to 0.97 as the identification residual increases to improve tracking speed. If the subsynchronous resonance center frequency is identified to have shifted to 28 Hz and the quality factor exceeds the threshold, the subsynchronous segment index is switched to a stronger suppression setting, and parameter transition is completed within 100 milliseconds using continuous interpolation. When the system enters grid handshake or current limiting protection state, harmonic and high-frequency parameters are frozen, allowing only the low-frequency virtual damping coefficient to be updated in small steps. The updated template parameters are simultaneously connected to the voltage setpoint correction branch of the voltage inner loop and the current reference limiting branch of the current inner loop to ensure consistent invocation of the same impedance shaping strategy by both inner loops.

[0064] This embodiment utilizes a segmented impedance template library with switchable filter indexes, online identification with dual-channel perturbation and forgetting factor, adaptive index switching based on short-circuit capacity estimates and resonance characteristics, and a segmented freezing and smooth update mechanism to ensure that impedance shaping remains configurable and online correctable across the entire frequency band. It also ensures consistent template usage and stable transition between the voltage inner loop and the current inner loop, thereby maintaining the expected impedance boundary and control stability under different grid connection intensities and operating conditions.

[0065] In some embodiments, amplitude and rate constraints and compatibility checks are performed on external power, reactive power, voltage, or frequency commands, and commands that pass the checks are injected into the droop loop under power change rate and frequency change rate constraints, including:

[0066] The verification and injection of external active, reactive, voltage, or frequency commands are implemented by a command sandbox. The command sandbox includes: a safety domain projector that performs convex set projection on the feasible domains of active, reactive, and frequency based on the energy storage state of charge and short-circuit capacity estimates; a rate gate that applies rate constraints to active, reactive, and frequency commands and is linked to the phase angle change rate and voltage transition limit; and a scheduling unit that performs compatibility discrimination based on priority mutual exclusion rules and synchronously injects consistent command increments into the droop loop within the effective window.

[0067] Specifically, firstly, the controller receives human-machine commands from the dispatching side or locally, which sequentially enter the safety domain projector, rate gating unit, compatibility discrimination and scheduling unit. The safety domain projector constructs a feasible region based on the energy storage state of charge, short-circuit capacity estimate, and active and reactive power capacity boundaries, and performs convex set projection on external active, reactive, and frequency commands to obtain command vectors located within the feasible region; the rate gating unit implements dual-domain constraints on the active power change rate and frequency change rate, and links them with the phase angle change rate and voltage transition limiting; the compatibility discrimination solves for consistent solutions for active, reactive, voltage, and frequency commands based on priority mutual exclusion rules; the scheduling unit issues consistent command increments according to a unified time base within the effective window and injects them into the droop loop, and commands that fail to pass are entered into the waiting scheduling queue.

[0068] Furthermore, the feasible region adopts a convex set description, and the dynamic boundary is obtained by associating the active and reactive power capacity curves, the frequency offset allowable boundary, and the short-circuit capacity estimate. The safety domain projector uses a weighted distance metric to push outbound commands back into the boundary. The dual-domain rate constraint simultaneously constrains the active power change rate and the frequency change rate, and uses the phase angle change rate to gate the integral on / off of the frequency channel, thereby limiting the dual rate of change of "rapid quantity" and "phase advancement". The priority mutual exclusion rule is used to handle the conflict of multiple commands arriving at the same time. For example, when the frequency and voltage settings change at the same time, the frequency consistency is prioritized, and the voltage change is constrained by both the phase angle change rate and the voltage transition limit. The effective window is aligned with the control cycle to ensure that the command increment injected into the droop loop is consistent in timing between each loop.

[0069] For example, in a typical example, the energy storage converter has a rated power of 50 MW and a rated frequency of 50 Hz at the grid connection point. The capacity boundary is defined as active power upper and lower limits at ±100% of the rated power, and reactive power upper and lower limits are given according to the inverter and transformer parameters; the permissible frequency offset is set at ±0.2 Hz. Short-circuit capacity estimates are divided into three levels: low, medium, and high. The low level limits active power output to 60% of the rated value, the medium level to 80%, and the high level allows up to 100%.

[0070] When an external command requires an increase in active power from 30 MW to 45 MW within 1 second, the safety domain projector first determines the feasible upper limit based on the current short-circuit capacity estimate. If it is in the middle range, the target active power is projected as 40 MW. The rate gate sets an upper limit on the active power change rate of 10% per second of the rated power, i.e., a maximum of 5 MW per second, and sets an upper limit on the frequency change rate of 0.5 Hz per second, and links it to an upper limit on the phase angle change rate of 20 degrees per second. Therefore, in the first effective window, only an increase from 30 MW to 35 MW is allowed, and corresponding frequency increment and voltage constraint are given.

[0071] If both commands to set the frequency to 50.05 Hz and to increase the voltage by 2% are received simultaneously, the priority mutual exclusion rule prioritizes the frequency setting. While maintaining the phase angle change rate within the upper limit, the voltage change is limited by the voltage transition limit to no more than 0.5% per cycle. The scheduling unit uses a unified controller time base of 5 milliseconds as the effective window, synchronously injecting the projected and rate-limited active and reactive power increments along with the frequency command increments into the droop loop. Unadopted voltage increments enter the waiting-to-schedule queue and are gradually released in subsequent windows according to the remaining margin.

[0072] When the detected frequency change rate exceeds 0.5 Hz per second or the phase angle change rate approaches the upper limit, the rate gating controller automatically reduces the integral step of the frequency channel and temporarily tightens the upper limit of the active power change rate to 5% per second of the rated power. If the short-circuit capacity estimate drops from the middle to the low range, the safety domain projector immediately reconstructs the feasible domain and performs a secondary projection on the incremental instructions in transit. The scheduling unit reclaims the excess portion to the queue and marks it as derated execution. Under the above mechanism, continuous external instructions are decomposed into a series of restricted increments and gradually absorbed by the droop loop, with the voltage inner loop and current inner loop seamlessly following on the same time base.

[0073] This embodiment uses the safety domain constraint of convex set projection, dual-domain rate gating linked with phase angle change rate and voltage transition limit, and synchronous injection based on priority mutual exclusion rules and effective window to enable external multi-source instructions to be converted into executable consistent instruction increments under different short-circuit capacities and operating states. This avoids loop impacts caused by out-of-bounds and sudden changes, and ensures the timing consistency and controllability of instruction injection and droop loop.

[0074] In some embodiments, grid connection or reconnection is completed based on the grid connection point reference phasor in the order of frequency ramp, phase angle gradual alignment, and voltage amplitude convergence, including:

[0075] A phase angle-preserving synchronization unit is constructed, which takes the grid connection point reference phasor and voltage phasor reference as inputs and is executed in series by a frequency ramp generator, a phase angle soft aligner and an amplitude equalizer.

[0076] Among them, the frequency ramp generator outputs a monotonic ramp under the constraints of short-circuit capacity estimation and energy storage state of charge; the phase angle aligner implements monotonic phase angle increment and prohibits phase angle reversal under the phase angle change rate and alignment window gating; the amplitude acclimator performs segmented progressive synthesis on the positive sequence channel and applies gating attenuation to the negative sequence and zero sequence channels; the phase-locked loop is not used during the entire synchronization process, and the grid connection permission command is issued when the alignment window, frequency deviation and negative sequence amplitude threshold are simultaneously satisfied.

[0077] Specifically, first, after receiving the grid connection point reference phasor and voltage phasor reference, the controller starts the phase angle sequence-preserving synchronization unit, which sequentially executes the frequency ramp generator, phase angle easing aligner, and amplitude amplifier. The frequency ramp generator outputs a monotonic frequency ramp and limits the phase angle change rate under the constraints of the short-circuit capacity estimate and the energy storage state of charge. When the frequency deviation enters the alignment window, the phase angle easing aligner approximates the reference phase with a monotonic phase angle increment and prohibits phase angle reversal. Subsequently, the amplitude amplifier performs segmented asymptotic synthesis on the positive sequence channel while applying gated attenuation to the negative sequence and zero sequence components. The phase-locked loop is not used throughout the synchronization process. A grid connection permission command is issued when the alignment window, frequency deviation, and negative sequence amplitude threshold are simultaneously satisfied and maintained for a preset dwell time.

[0078] Furthermore, phase angle preservation means that the phase angle increment remains monotonically in the same direction to avoid oscillations caused by back-and-forth swings; the alignment window adopts a dual window of frequency and phase angle, and the phase angle alignment stage is only allowed to take effect after the frequency enters the narrow window; the piecewise asymptotic synthesis of amplitude convergence uses different slopes in different amplitude ranges to reduce the parallel error at high amplitudes; negative sequence gating is sensitive to imbalance, and when the negative sequence amplitude exceeds the threshold, amplitude convergence is suppressed and the system reverts to the phase angle alignment stage; the dwell time is used to prevent misjudgment caused by instantaneous fulfillment of conditions.

[0079] For example, in a typical example, the grid connection point has a rated frequency of 50 Hz and a voltage level of 10 kV. The short-circuit capacity estimate is divided into three segments: low, medium, and high. The low segment uses a frequency ramp of 0.1 Hz per second and a maximum phase angle change rate of 10 degrees per second; the medium segment uses a frequency ramp of 0.2 Hz per second and a maximum phase angle change rate of 15 degrees per second; and the high segment uses a frequency ramp of 0.3 Hz per second and a maximum phase angle change rate of 20 degrees per second. When the energy storage state of charge is below 30%, each ramp is reduced by 20%. The frequency alignment window is set to ±0.05 Hz, the phase angle alignment window is set to ±3 degrees, the negative sequence amplitude threshold is set to 5% of the positive sequence amplitude, and the dwell time is set to 200 milliseconds.

[0080] Frequency ramp phase: When the deviation between the islanded grid output frequency and the grid connection reference frequency is 0.4 Hz and the short-circuit capacity estimate is in the middle range, the frequency ramp generator increases the frequency at a slope of 0.2 Hz per second, while the hard constraint phase angle change rate does not exceed 15 degrees per second; if the energy storage state of charge is 25%, the slope drops to 0.16 Hz per second. After the frequency error enters ±0.05 Hz, it automatically switches to the phase angle gradual alignment phase.

[0081] Phase angle gradual alignment phase: Calculate the current phase angle difference. If the phase angle difference is -12 degrees, the phase angle gradual aligner approximates the reference phase with monotonically positive increments. The step size is constrained by both the upper limit of the phase angle change rate and the phase angle alignment window. If a momentary fluctuation in the grid connection point frequency is detected, causing the phase angle difference to swing back from -4 degrees to -6 degrees, the gradual aligner only reduces the step size and does not allow the phase angle to reverse, maintaining phase angle order. If the negative sequence amplitude is greater than the 5% threshold, the phase angle stepping is paused and the negative sequence gating timer is triggered. Stepping resumes after the timer ends and the negative sequence returns to normal.

[0082] Amplitude equalization phase: The amplitude equalizer is activated after the phase angle difference enters ±3 degrees and remains stable for 200 milliseconds. The positive sequence channel amplitude is equalized in two stages: when the difference with the positive sequence amplitude at the grid connection point is within 5%, a slope of 0.5% per cycle is used; when the difference is less than 2%, a slope of 0.2% per cycle is used until they are equal. The negative sequence and zero sequence channels are simultaneously attenuated by a preset exponential method to below the target threshold. If a frequency deviation exceeding ±0.05 Hz or the negative sequence amplitude exceeds the threshold again during the equalization process, the amplitude equalization is immediately frozen and the phase angle is rolled back to the phase angle soft alignment phase until the conditions are restored.

[0083] Grid connection authorization and execution: When the frequency deviation, phase angle difference and negative sequence amplitude remain continuously within their respective thresholds for no less than 200 milliseconds, the controller issues a grid connection authorization command and inserts an effective window between authorization and execution to ensure time base alignment with the voltage inner loop, current inner loop and grid connection switch control interface; after grid connection is completed, the phase angle sequence-preserving synchronization unit exits and enters grid connection operation state.

[0084] This embodiment achieves sequential alignment of frequency, phase angle, and amplitude of the grid connection point reference phasor without enabling the phase-locked loop by segmented constraints of frequency ramp, sequence-preserving gating of phase angle gradual alignment, and segmented progressive synthesis of amplitude gradual merging. It also uses negative sequence gating and dwell criteria as consistency conditions. This reduces paralleling errors and transient impacts, and improves synchronization reliability under weak grid conditions.

[0085] In some embodiments, upper limits and timing templates for positive-sequence, negative-sequence, and zero-sequence fault currents are set in the symmetrical component domain, and a unified priority is established with current limiting and DC-side protection to synthesize limited fault currents, including:

[0086] A sequence component fault current synthesis unit is set up, and the limit mapper determines the upper limits of positive sequence, negative sequence and zero sequence current based on the short-circuit capacity estimate and DC side voltage state, and applies gating weights to negative sequence and zero sequence current;

[0087] The timing generator generates references for each sequence component according to the rising, sustaining, and backoff templates, and uses the rate of change of frequency and the rate of change of phase angle as thresholds;

[0088] The priority arbiter outputs a composite current reference in the order of DC side protection first, bridge arm current limiting second, and sequence component upper limit last, and injects it into the current inner loop. When the fault exits, it is restored according to the backoff sequence and is consistent with the voltage inner loop boundary.

[0089] Specifically, the controller is equipped with a sequence component fault current synthesis unit, which includes a limit mapper, a timing generator, and a priority arbiter. The limit mapper takes the short-circuit capacity estimate and the DC-side voltage state as inputs, and outputs positive-sequence, negative-sequence, and zero-sequence current upper limits, and adds gating weights to the negative-sequence and zero-sequence currents. The timing generator generates reference trajectories for each sequence component based on the rising, sustaining, and backoff three-stage templates, and uses the frequency change rate and phase angle change rate as the effective thresholds. The priority arbiter decides the synthesized current reference and injects it into the current inner loop in the order of priority of DC-side protection, followed by bridge arm current limiting, and then the sequence component upper limit. When the fault exits, the backoff sequence is consistent with the voltage inner loop boundary.

[0090] Furthermore, the limit mapper binds the positive sequence upper limit to the short-circuit capacity estimate, and the negative sequence and zero sequence upper limits to the DC side voltage deviation and thermal margin. It also lowers the negative sequence and zero sequence reference ratios when the imbalance is severe by using gating weights. The timing generator describes the reference evolution of the fault process using a three-segment template: the rising segment limits the ramp-up speed, the holding segment limits the holding time, and the backoff segment limits the decay slope. The priority arbiter processes the energy side, device side, and sequence component side constraints in a unified order to avoid conflicts between multiple source current limits, and performs consistency constraints with the same boundary quantities as the voltage inner loop.

[0091] For example, in a typical example, the energy storage converter has a rated power of 50 MW and a rated voltage at the grid connection point of 10 kV. The short-circuit capacity estimate is divided into three segments: low, medium, and high. The low segment sets the upper limit of the positive sequence current to 1.0 per unit of the rated current, the medium segment to 1.2 per unit, and the high segment to 1.5 per unit, with a duration limited to no more than 200 milliseconds. The upper limits of the negative sequence current are set to 0.2, 0.3, and 0.4 per unit, respectively, and the upper limits of the zero sequence current are set to 0.05, 0.1, and 0.1 per unit, respectively. The upper and lower thresholds of the DC side voltage are set to 1.1 and 0.9 of the rated value of the bus, respectively. When the bus voltage exceeds the limit or the ripple exceeds the threshold, the limit mapper immediately lowers the positive sequence upper limit to 0.8 per unit and reduces the negative and zero sequence gating weights to zero.

[0092] The timing generator sets a rise time of 20 ms, a sustain time of 150 ms, and a backoff time of 300 ms for the positive sequence reference. For the negative and zero sequence references, it sets a slower rise time and a shorter sustain time to limit thermal load. The frequency change rate and phase angle change rate are set as thresholds of 0.7 Hz / s and 20 degrees / s, respectively; exceeding these limits freezes the rise phase and extends the backoff phase. In any given cycle, the priority arbiter first checks for DC-side protection triggering, then checks if the bridge arm current has reached its hard limit, then adjudicates the remaining channel references according to the upper limit of the sequence components, and finally injects the synthesized current reference into the inner current loop, where it performs consistency constraints together with the voltage setpoint boundary of the inner voltage loop.

[0093] In a single-phase ground fault example, an increase in negative sequence amplitude was detected, and the short-circuit capacity estimate was in the middle range. The system first raised the positive sequence current reference to 1.2 per unit within 20 milliseconds according to the rising phase, while simultaneously limiting the negative sequence reference to below 0.3 per unit and the zero sequence reference to below 0.1 per unit according to the gating weight. If the DC bus voltage briefly rises to the upper limit during the process, the priority arbiter immediately lowers the positive sequence reference back to 0.8 per unit according to the priority of DC side protection and freezes the negative sequence and zero sequence outputs. After the bus recovers, it enters the maintenance phase to maintain the arbitration value. When the fault is cleared, it enters the backoff phase, and the synthesized reference decays to the rated operating point within 300 milliseconds according to the preset slope, and the temporary constraints are released synchronously with the phase angle and amplitude boundary of the voltage inner loop.

[0094] This embodiment models the sequence component limit, DC side protection, and bridge arm current limiting as a unified priority sequence, and uses three-segment templates and threshold limits to coordinate constraints to complete the restricted synthesis of positive sequence, negative sequence, and zero sequence fault currents. During fault entry, maintenance, and exit, the current reference and voltage inner loop boundary remain consistent and recover smoothly according to the backoff sequence, which is beneficial for achieving controllable fault response and orderly recovery in unbalanced and weak network scenarios.

[0095] In some embodiments, switching between self-contained grid, grid-connected operation, and protection current-limiting states is triggered by events, while maintaining voltage phasor continuity, phase angle and power change rate limitation, and smooth impedance template migration during the switching process, including:

[0096] Configure the state machine controller, switch invariant constraint, and template migrater;

[0097] The state machine controller determines the switching conditions based on trigger quantities such as the frequency change rate, short-circuit capacity estimate, DC bus voltage and negative sequence amplitude, and issues a switching command within the synchronization window.

[0098] The switching invariant constraint applies upper limits to the voltage phasor, phase angle rate of change, and active power rate of change, while maintaining the continuity of the grid connection handshake steps and the current limiting protection steps.

[0099] The template migrater performs continuous interpolation migration on the impedance template of the generalized impedance shaping, and freezes the mid-to-high frequency parameters in the grid-connected handshake and current-limiting protection states, allowing only the low-frequency parameters to be updated.

[0100] Specifically, firstly, a state machine controller is established. The state set includes three basic states: self-contained network, grid-connected operation, and current-limiting protection, with reserved transitional sub-states for disconnection and grid handshaking. The state machine periodically reads trigger quantities, including frequency change rate, short-circuit capacity estimate, DC bus voltage, negative sequence amplitude, and device temperature, and determines switching conditions within the synchronized activation window. The activation window is aligned with the controller's main loop, using a fixed step size, such as 5 milliseconds per cycle, to ensure that switching commands are executed on the same time base as the voltage inner loop, current inner loop, and grid-connected switch control interface. Typical threshold settings are: a maximum frequency change rate of 0.5 Hz per second, a permissible DC bus voltage range of 0.9 to 1.1 Hz of the rated value, a negative sequence amplitude threshold of 5% of the positive sequence amplitude, and a device temperature threshold set according to the rated thermal design.

[0101] Secondly, a switching invariant constraint is set. Switching invariants refer to the constraints that must be met simultaneously during switching, including voltage phasor continuity, phase angle and active power rate limits, and the continuity of grid handshake and current limiting protection steps. The phase angle rate of change is capped at 20 degrees per second, and the active power rate of change is capped at 10% of the rated power per second. When entering current limiting protection or negative sequence over-limit, the above upper limits are temporarily tightened to 10 degrees per second and 5% of the rated power per second, respectively. The constraint employs a phase angle integral continuity maintenance strategy for the voltage phasor, i.e., locking the initial value of the phase angle integral at the switching edge and advancing with a limited slope to avoid phase angle reversal and sudden jumps. For grid handshake and current limiting protection, the constraint requires execution in a predetermined order, disallowing jumps across steps. For example, in grid handshake, amplitude convergence can only begin after the frequency and phase angle enter the window and the dwell time is satisfied.

[0102] Next, the template migrater is configured. The impedance template for generalized impedance shaping is maintained in a versioned manner, segmented by low-frequency, subsynchronous, harmonic, and high-frequency bands. Template migration uses continuous interpolation across old and new versions, with an interpolation time constant ranging from 100 to 200 milliseconds. Under grid-connected handshake and current-limiting protection conditions, the template migrater freezes the mid-to-high-frequency parameters, allowing only small-step updates of the low-frequency virtual damping; under grid-connected operation conditions, smooth updates across the entire frequency band are allowed according to priority. Template switching triggers are jointly determined by the short-circuit capacity estimate and resonance characteristics. When the short-circuit capacity estimate decreases or the resonance index increases, a switch to a stronger suppression index combination is prioritized.

[0103] For example, Example 1: Switching from self-contained grid to grid-connected operation. Upon detecting that the grid-connection permitting conditions are met—namely, frequency deviation within the ±0.05 Hz window, phase angle difference within the ±3 degree window, and negative sequence amplitude below 5% and residing for 200 milliseconds—the state machine issues a handshake command to switch from self-contained grid to grid-connected operation in the next effective window. The switching invariant constraint limits the phase angle change rate to 15 degrees per second and the active power change rate to 8% of rated power per second. The voltage phasor is aligned with the grid-connection point reference phasor with a limited slope. The template migrater freezes harmonic and high-frequency parameters, allowing only low-frequency damping coefficients to be fine-tuned according to a set step size. After the handshake is completed and stability is confirmed, the state machine enters grid-connected operation.

[0104] Example 2: Grid-connected operation enters current-limiting protection and then returns. During operation, if the DC bus voltage exceeds the permissible upper limit or the bridge arm current approaches the limit, the state machine triggers current-limiting protection. The switching invariant constraint immediately tightens the phase angle and active power change rate upper limit, and issues current-limiting reference and derating commands to the inner current loop; the voltage phasor continues to advance to avoid phasor jumps. The template migrater maintains small-step updates in the low-frequency band and freezes parameters in the mid-to-high-frequency band to prevent the introduction of additional high-frequency adjustments during current limiting. After the fault or overload is cleared, the state machine cancels the current limiting using a backoff sequence, gradually releases the active power change rate to 10% of the rated power per second, and restores the impedance template to the grid-connected operation version within 200 milliseconds according to the interpolation strategy.

[0105] Example 3: Grid-connected operation reverts to self-contained grid. If the short-circuit capacity estimate drops sharply and a persistent imbalance occurs at the grid connection point, the state machine determines that the disconnection condition is met, issues a disconnection command, and transitions to the disconnection holding sub-state. The switching invariant constraint maintains voltage phasor continuity at the disconnection edge and limits the phase angle change rate to 10 degrees per second for a smooth transition; the template migrater switches to the self-contained grid template and completes low-frequency damping enhancement through continuous interpolation. After the grid connection point recovers and meets the reconnection condition, the grid handshake is initiated again in the order of Example 1.

[0106] This embodiment ensures that voltage phasors remain continuous, phase angle and active power change rate are limited, and generalized impedance templates migrate smoothly according to a controlled rhythm by using event-triggered state machine determination, switching invariant constraints and template migration in coordination. In the three states of self-contained network, grid-connected operation and current limiting protection and their transition processes, the above mechanism reduces transient impact and parameter mutation caused by switching, and achieves consistency and reversibility of control and protection.

[0107] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0108] Figure 2 This is a schematic diagram of the grid-connected, grid-friendly energy storage converter self-contained control and protection device provided in an embodiment of this application. (See attached diagram.) Figure 2 As shown, the grid-connected grid-friendly energy storage converter's self-contained grid control and protection device includes:

[0109] The acquisition module 201 is used to acquire electrical quantities at the grid connection point and the DC side, establish short-circuit capacity estimates and positive and negative zero sequence models, and generate voltage phasor references.

[0110] The control module 202 is used to enable parallel control of the voltage inner loop and the current inner loop without relying on the phase-locked loop. It generates frequency and voltage setpoints based on power and frequency droop and reactive power and voltage droop, and adaptively tunes the droop coefficient and inertia parameters based on the energy storage state of charge and short-circuit capacity estimate.

[0111] Configuration module 203 is used to perform generalized impedance shaping in the control loop, configure virtual impedance and selective filtering by frequency band, and update the impedance template by online identification;

[0112] The verification module 204 is used to perform amplitude and rate constraints and compatibility verification on external power, reactive power, voltage or frequency commands, and inject commands that pass the verification into the droop loop under the constraints of power change rate and frequency change rate.

[0113] The grid connection module 205 is used to complete grid connection or reconnection based on the grid connection point reference phasor in the order of frequency ramp, phase angle gradual alignment and voltage amplitude gradual convergence.

[0114] Synthesis module 206 is used to set the upper limit of positive sequence, negative sequence and zero sequence fault current and timing template in the symmetrical component domain, and to establish a unified priority with current limiting and DC side protection to synthesize limited fault current.

[0115] The switching module 207 is used to switch between self-contained network, grid-connected operation and protection current limiting state in an event-triggered manner, and maintain voltage phasor continuity, phase angle and power change rate limitation and impedance template smooth migration during the switching process;

[0116] The output module 208 is used to output frequency setpoint, voltage setpoint, sequence component limit and protection status command to the converter power bridge drive and grid-connected switch control interface, and to control and protect the self-grid and grid-connected operation of the energy storage converter.

[0117] In some embodiments, Figure 2 The acquisition module 201 uses a frequency-change rate-gated sliding phasor estimator to output positive-sequence voltage and current phasors; it obtains positive-sequence and zero-sequence equivalent impedances through frequency band-switched perturbation injection and recursive online identification with forgetting factor, and calculates short-circuit capacity estimates accordingly; a voltage phasor reference is formed by a positive-negative-zero-sequence weighted phasor generator under the dual boundaries of phase angle integration and amplitude limiting; when the frequency change rate or identification deviation exceeds the limit, phasor freezing and parameter self-updating are performed.

[0118] In some embodiments, Figure 2 The control module 202 constructs a droop and inertia coordinator, taking active power, reactive power, energy storage state of charge, short-circuit capacity estimate, and frequency change rate as inputs, and outputting frequency and voltage setpoints. The active droop coefficient, reactive droop coefficient, and inertia parameters are segmented and hysteresis dead zones are set by the energy and short-circuit capacity joint mapper. Dual-domain rate constraints for power change rate and phase angle change rate are configured, as well as gated integrals based on frequency change rate. Sequence component weighting and negative sequence gating are introduced for reactive power and voltage droop to limit the voltage setpoint component. The voltage inner loop generates a current reference without relying on the phase-locked loop, and the current inner loop follows the execution.

[0119] In some embodiments, Figure 2 The configuration module 203 establishes an impedance template library segmented by low frequency, subsynchronous, harmonic, and high frequency bands. It configures virtual resistance, virtual inductance, and admittance limiting parameters for positive sequence, negative sequence, and zero sequence, respectively, and binds them to switchable selective filter indices. It adopts dual-channel perturbation injection and recursive online identification with forgetting factor to identify the equivalent impedance and resonance characteristics of each sequence component within the frequency change rate threshold, and outputs the template update amount. It drives the switching of selective filter indices with short-circuit capacity estimates and resonance characteristics, and achieves smooth updates of impedance templates through template versioning and continuous interpolation. It freezes the mid-to-high frequency band parameters under grid handshake, weak grid protection, and current limiting protection states, allowing only the low-frequency band damping parameters to be updated, and attaches the updated impedance template to the voltage inner loop and current inner loop.

[0120] In some embodiments, Figure 2 The verification module 204 verifies and injects external active, reactive, voltage, or frequency commands through a command sandbox. The command sandbox includes: a safety domain projector that performs convex set projection on the feasible domains of active, reactive, and frequency based on the energy storage state of charge and short-circuit capacity estimates; a rate gate that applies rate constraints to active, reactive, and frequency commands and is linked to the phase angle change rate and voltage transition limit; and a scheduling unit that performs compatibility discrimination based on priority mutual exclusion rules and synchronously injects consistent command increments into the droop loop within the effective window.

[0121] In some embodiments, Figure 2The grid-connected module 205 constructs a phase angle-preserving synchronization unit, which takes the grid connection point reference phasor and voltage phasor as inputs and is executed in series by a frequency ramp generator, a phase angle easing aligner, and an amplitude easing aligner. The frequency ramp generator outputs a monotonic ramp under the constraints of the short-circuit capacity estimate and the energy storage state of charge. The phase angle easing aligner implements a monotonic phase angle increment and prohibits phase angle reversal under the phase angle change rate and alignment window gating. The amplitude easing aligner performs segmented progressive synthesis of the positive sequence channel and applies gating attenuation to the negative sequence and zero sequence channels. The phase-locked loop is not used during the entire synchronization process. When the alignment window, frequency deviation, and negative sequence amplitude threshold are simultaneously satisfied, a grid connection permission command is issued.

[0122] In some embodiments, Figure 2 The synthesis module 206 is equipped with a sequence component fault current synthesis unit. The limit mapper determines the upper limits of positive sequence, negative sequence and zero sequence current based on the short-circuit capacity estimate and DC side voltage state, and applies gating weights to the negative sequence and zero sequence. The timing generator generates references for each sequence component according to the rising, sustaining and backoff templates, and uses the frequency change rate and phase angle change rate as thresholds. The priority arbiter outputs the synthesized current reference in the order of DC side protection first, bridge arm current limiting second, and sequence component upper limit last, and injects it into the current inner loop. When the fault exits, it is restored according to the backoff sequence and is consistent with the voltage inner loop boundary.

[0123] In some embodiments, Figure 2 The switching module 207 is configured with a state machine controller, a switching invariant constraint, and a template migrater. The state machine controller determines the switching conditions based on trigger quantities such as the frequency change rate, short-circuit capacity estimate, DC bus voltage, and negative sequence amplitude, and issues a switching command within the synchronization window. The switching invariant constraint applies upper limits to the voltage phasor, phase angle change rate, and active power change rate, and maintains the continuity of the grid connection handshake and current limiting protection steps. The template migrater performs continuous interpolation migration on the impedance template of the generalized impedance shaping, and freezes the mid-to-high frequency parameters under the grid connection handshake and current limiting protection states, allowing only the low-frequency parameters to be updated.

[0124] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0125] Figure 3 This is a schematic diagram of the structure of the electronic device 3 provided in an embodiment of this application. Figure 3As shown, the electronic device 3 of this embodiment includes a processor 301, a memory 302, and a computer program 303 stored in the memory 302 and executable on the processor 301. When the processor 301 executes the computer program 303, it implements the steps in the various method embodiments described above. Alternatively, when the processor 301 executes the computer program 303, it implements the functions of each module / unit in the various device embodiments described above.

[0126] For example, computer program 303 may be divided into one or more modules / units, which are stored in memory 302 and executed by processor 301 to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 303 in electronic device 3.

[0127] Electronic device 3 can be a desktop computer, laptop, handheld computer, cloud server, or other electronic device. Electronic device 3 may include, but is not limited to, processor 301 and memory 302. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 3 and does not constitute a limitation on electronic device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device may also include input / output devices, network access devices, buses, etc.

[0128] Processor 301 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0129] The memory 302 can be an internal storage unit of the electronic device 3, such as a hard disk or RAM. The memory 302 can also be an external storage device of the electronic device 3, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 302 can include both internal and external storage units of the electronic device 3. The memory 302 is used to store computer programs and other programs and data required by the electronic device. The memory 302 can also be used to temporarily store data that has been output or will be output.

[0130] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0131] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0132] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0133] In the embodiments provided in this application, it should be understood that the disclosed apparatus / computer devices and methods can be implemented in other ways. For example, the apparatus / computer device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. Multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of apparatus or units may be electrical, mechanical, or other forms.

[0134] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0135] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0136] If integrated modules / units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program may include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0137] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although the technical solutions of this application are described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A grid-connected, grid-friendly energy storage converter self-contained control and protection method, characterized in that, include: Collect electrical quantities at the grid connection point and DC side, establish short-circuit capacity estimates and positive and negative zero sequence models, and generate voltage phasor references; Without relying on a phase-locked loop, the voltage inner loop and the current inner loop are enabled for parallel control. Based on the power and frequency droop, as well as the reactive power and voltage droop, the frequency and voltage setpoints are generated, and the droop coefficient and inertia parameters are adaptively tuned based on the energy storage state of charge and the short-circuit capacity estimate. Generalized impedance shaping is performed in the control loop, virtual impedance and selective filtering are configured according to frequency band, and the impedance template is updated through online identification. External power, reactive power, voltage, or frequency commands are subjected to amplitude and rate constraints and compatibility checks. Commands that pass the checks are then injected into the droop loop under the constraints of power change rate and frequency change rate. Grid connection or reconnection is completed in the order of frequency ramp, phase angle gradual alignment and voltage amplitude convergence based on the grid connection point reference phasor; In the symmetrical component domain, upper limits and timing templates for positive sequence, negative sequence and zero sequence fault currents are set, and a unified priority is established with current limiting and DC side protection to synthesize limited fault currents. It switches between self-contained network, grid-connected operation and protection current limiting state in an event-triggered manner, and maintains voltage phasor continuity, phase angle and power change rate limitation and impedance template smooth migration during the switching process; The frequency setpoint, voltage setpoint, sequence component limit, and protection status command are output to the converter power bridge drive and grid-connected switch control interface for controlling and protecting the self-grid and grid-connected operation of the energy storage converter.

2. The method according to claim 1, characterized in that, The process of establishing short-circuit capacity estimates and positive / negative zero-sequence models to generate voltage phasor references includes: A sliding phasor estimator gated by the rate of change of frequency is used to output positive sequence voltage and current phasors; Positive-sequence and zero-sequence equivalent impedances are obtained through frequency band switchable perturbation injection and recursive online identification with forgetting factor, and short-circuit capacity estimates are calculated accordingly. A voltage phasor reference is formed by a phasor generator with positive and negative zero sequence weighting under the dual boundaries of phase angle integration and amplitude limiting; Specifically, when the rate of change of frequency or the identification deviation exceeds the limit, phasor freezing and parameter self-update are performed.

3. The method according to claim 1, characterized in that, The activation of parallel control of the voltage inner loop and current inner loop generates frequency and voltage setpoints based on power and frequency droop, reactive power and voltage droop, including: Construct a droop and inertia coordinator, with active power, reactive power, energy storage state of charge, short-circuit capacity estimate and frequency change rate as inputs, and output frequency and voltage setpoints as outputs; The active power droop coefficient, reactive power droop coefficient and inertia parameter are segmented and the hysteresis dead zone is set by the energy and short-circuit capacity joint mapper. Configure dual-domain rate constraints for power change rate and phase angle change rate, and gated integral based on frequency change rate; Sequence weighting and negative sequence gating are introduced for reactive power and voltage droop to limit the voltage given component; The voltage inner loop generates the current reference without relying on the phase-locked loop, and the current inner loop follows and executes accordingly.

4. The method according to claim 1, characterized in that, The process of performing generalized impedance shaping in the control loop, configuring virtual impedance and selective filtering according to frequency bands, and updating the impedance template through online identification includes: Establish an impedance template library segmented by low frequency, subsynchronous, harmonic and high frequency bands, configure virtual resistance, virtual inductance and admittance limiting parameters for positive sequence, negative sequence and zero sequence respectively, and bind switchable selective filter indexes. A dual-channel perturbation injection and recursive online identification with a forgetting factor are used to identify the equivalent impedance and resonance characteristics of each sequence component within the frequency change rate threshold, and output the template update amount. The selective filter index switching is driven by the short-circuit capacity estimate and the resonance characteristics, and the impedance template is smoothly updated by template versioning and continuous interpolation. Under the conditions of grid connection handshake, weak network protection and current limiting protection, the parameters of the mid-to-high frequency band are frozen, and only the damping parameters of the low frequency band are allowed to be updated. The updated impedance template is then connected to the voltage inner loop and the current inner loop.

5. The method according to claim 1, characterized in that, The process of performing amplitude and rate constraints and compatibility checks on external power, reactive power, voltage, or frequency commands, and injecting commands that pass the checks into the droop loop under power change rate and frequency change rate constraints, includes: The verification and injection of external active, reactive, voltage, or frequency commands are implemented by a command sandbox, which includes: a safety domain projector that performs convex set projection on the feasible domains of active, reactive, and frequency based on the energy storage state of charge and short-circuit capacity estimates; a rate gate that applies rate constraints to active, reactive, and frequency and is linked to the phase angle change rate and voltage transition limit; and a scheduling unit that performs compatibility discrimination based on priority mutual exclusion rules and synchronously injects consistent command increments into the droop loop within the effective window.

6. The method according to claim 1, characterized in that, The process of completing grid connection or reconnection based on the grid connection point reference phasor in the order of frequency ramp, phase angle gradual alignment, and voltage amplitude convergence includes: A phase angle-preserving synchronization unit is constructed, which takes the grid connection point reference phasor and voltage phasor reference as inputs and is executed in series by a frequency ramp generator, a phase angle soft aligner and an amplitude equalizer. Among them, the frequency ramp generator outputs a monotonic ramp under the constraints of short-circuit capacity estimation and energy storage state of charge; the phase angle aligner implements monotonic phase angle increment and prohibits phase angle reversal under the phase angle change rate and alignment window gating; the amplitude acclimator performs segmented progressive synthesis on the positive sequence channel and applies gating attenuation to the negative sequence and zero sequence channels; the phase-locked loop is not used during the entire synchronization process, and the grid connection permission command is issued when the alignment window, frequency deviation and negative sequence amplitude threshold are simultaneously satisfied.

7. The method according to claim 1, characterized in that, The step of setting upper limits and timing templates for positive-sequence, negative-sequence, and zero-sequence fault currents in the symmetrical component domain, and establishing a unified priority with current limiting and DC-side protection to synthesize restricted fault currents includes: A sequence component fault current synthesis unit is set up, and the limit mapper determines the upper limits of positive sequence, negative sequence and zero sequence current based on the short-circuit capacity estimate and DC side voltage state, and applies gating weights to negative sequence and zero sequence current; The timing generator generates references for each sequence component according to the rising, sustaining, and backoff templates, and uses the rate of change of frequency and the rate of change of phase angle as thresholds; The priority arbiter outputs a composite current reference in the order of DC side protection first, bridge arm current limiting second, and sequence component upper limit last, and injects it into the current inner loop. When the fault exits, it is restored according to the backoff sequence and is consistent with the voltage inner loop boundary.

8. The method according to claim 1, characterized in that, The switching between self-contained network, grid-connected operation, and protection current-limiting states via event triggering, while maintaining voltage phasor continuity, limited phase angle and power change rate, and smooth impedance template migration during the switching process, includes: Configure the state machine controller, switch invariant constraint, and template migrater; The state machine controller determines the switching conditions based on the frequency change rate, short-circuit capacity estimate, DC bus voltage and negative sequence amplitude trigger value, and issues a switching command within the synchronization window. The switching invariant constraint applies upper limits to the voltage phasor, phase angle rate of change, and active power rate of change, while maintaining the continuity of the grid handshake step and the current limiting protection step. The template migrater performs continuous interpolation migration on the impedance template of the generalized impedance shaping, and freezes the mid-to-high frequency parameters in the grid-connected handshake and current-limiting protection states, allowing only the low-frequency parameters to be updated.

9. A grid-connected, grid-friendly energy storage converter self-contained control and protection device, characterized in that, include: The acquisition module is used to collect electrical quantities at the grid connection point and the DC side, establish short-circuit capacity estimates and positive and negative zero sequence models, and generate voltage phasor references. The control module is used to enable parallel control of the voltage inner loop and the current inner loop without relying on the phase-locked loop. It generates frequency and voltage setpoints based on power and frequency droop and reactive power and voltage droop, and adaptively tunes the droop coefficient and inertia parameters based on the energy storage state of charge and the short-circuit capacity estimate. The configuration module is used to perform generalized impedance shaping in the control loop, configure virtual impedance and selective filtering by frequency band, and update the impedance template through online identification; The verification module is used to perform amplitude and rate constraints and compatibility verification on external power, reactive power, voltage or frequency commands, and inject commands that pass the verification into the droop loop under the constraints of power change rate and frequency change rate. The grid connection module is used to complete grid connection or reconnection based on the grid connection point reference phasor in the order of frequency ramp, phase angle gradual alignment and voltage amplitude gradual convergence. The synthesis module is used to set the upper limit of positive sequence, negative sequence and zero sequence fault current and timing template in the symmetrical component domain, and to establish a unified priority with current limiting and DC side protection to synthesize limited fault current. The switching module is used to switch between self-contained network, grid-connected operation and protection current limiting state in an event-triggered manner, and maintain voltage phasor continuity, phase angle and power change rate limitation and impedance template smooth migration during the switching process; The output module is used to output the frequency setpoint, voltage setpoint, sequence component limit value and protection status command to the converter power bridge drive and grid-connected switch control interface, and to control and protect the self-grid and grid-connected operation of the energy storage converter.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 8.

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