A chip configuration circuit

Abstract

This application provides a chip configuration circuit, including: a configuration control interface; and a configuration control function module. The configuration control module includes a main control module and an AXI module. The AXI module is connected to the configuration control interface and the configuration control function module via the AXI interface. During the configuration phase, the main control module determines the configuration mode based on configuration instructions, and the AXI module calls the corresponding configuration control interface based on the configuration mode, obtains the data transmitted by the configuration control interface, and determines the data flow direction to execute the corresponding configuration process. The controlled unit is connected to the AXI module via the AXI interface. During the user mode phase, the controlled unit sends user instructions to the AXI module based on the AXI interface, and the AXI module calls the corresponding configuration control function module as the user circuit based on the user instructions. This application can avoid the problem of the configuration control function module being idle after configuration in traditional designs, improve hardware resource utilization, and reduce hardware costs.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to a chip configuration circuit. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) are large-scale programmable devices. In FPGA design, software architecture and hardware architecture are two core concepts. The PGA software architecture typically includes Hardware Description Languages ​​(HDLs), synthesis tools, place-and-route tools, and configuration management tools. These tools are used to transform the design into a circuit that can run on the FPGA. The FPGA hardware architecture consists of three parts: programmable logic blocks, programmable I / O modules, and interconnect resources. These parts work together to realize the circuit functions of the design. FPGAs overcome the shortcomings of custom circuits. Users can describe the required functions using a hardware description language, then compile the description language into a code stream file using software, and finally configure the FPGA. The advantages of programmability, reconfigurability, and ease of use have led to the widespread application of FPGAs in various fields.

[0003] With advancements in manufacturing processes and improved yields, high-precision FPGA chips are becoming increasingly larger, more functional, and more diverse in configuration modes. This necessitates larger configuration scale and capacity, as well as higher demands for configuration speed and security. These characteristics dictate that configuration circuits are becoming increasingly complex and larger. Furthermore, for normal FPGA devices, configuration circuits only operate for a short period after power-on, and may not even function during power-on. Once the programmable logic is configured, the system enters user mode. In user mode, these configuration circuits are typically only reused when restarting the configuration process or reloading the configuration file, and are not available for user access, resulting in significant resource waste.

[0004] Therefore, for FPGA configuration circuits, it is extremely important to optimize the future development of programmable logic and hardware design if they can meet both complex configuration functions and provide flexible user circuits. Summary of the Invention

[0005] This application discloses a chip configuration circuit that enables users to flexibly call the configuration circuit after configuration is completed. This avoids the problem of the configuration control function module being idle after configuration in traditional designs. It can balance configuration efficiency and user mode flexibility, improve hardware resource utilization and reduce hardware costs.

[0006] Other objectives and advantages of this application can be further understood from the technical features disclosed herein.

[0007] To achieve one or more of the above objectives or other objectives, in a first aspect, this application provides a chip configuration circuit, comprising:

[0008] Configure control interfaces for receiving data from external storage units, including JTAG control interface, SPI control interface, Slave control interface, and BPI control interface;

[0009] Configure control function modules, including decryption circuit, authentication circuit, and decompression circuit;

[0010] The configuration control module includes a main control module and an AXI module. The main control module is connected to the AXI module via an AXI interface. The AXI module is connected to the configuration control interface and the configuration control function module via AXI interfaces. During the configuration phase, the main control module determines the configuration mode based on configuration instructions. The AXI module calls the corresponding configuration control interface based on the configuration mode, obtains the data transmitted by the configuration control interface, and determines the data flow direction to execute the corresponding configuration process, thereby realizing the configuration of the controlled unit.

[0011] The controlled unit is connected to the AXI module via an AXI interface. In the user mode phase, the controlled unit sends user commands to the AXI module based on the AXI interface. The AXI module then calls the corresponding configuration control function module as the user circuit based on the user commands.

[0012] During the user mode phase, the controlled unit sends user commands to the AXI module through the AXI interface. The AXI module determines the configuration control interface to be accessed based on the access address and calls the corresponding configuration control interface.

[0013] The AXI interface includes a host interface and a slave interface. The host interface is located in the SPI control interface, the BPI control interface, the configuration control module, and the controlled unit. The slave interface is located in the configuration control interface, the configuration control module, and the configuration control function module.

[0014] The controlled unit connects to the AXI module through the host interface, and the controlled unit directly accesses the configuration control function module or the configuration control interface through the host interface.

[0015] The AXI module and the configuration control function module communicate with each other through the slave interface.

[0016] The AXI module and the JTAG control interface are connected via the slave interface.

[0017] The controlled unit and the main control module are connected via a link configuration interface. During the configuration phase, the main control module configures the controlled unit through the link configuration interface.

[0018] The decryption circuit performs data decryption processing based on the configuration instructions or user instructions distributed by the AXI module; the authentication circuit performs data authentication processing based on the configuration instructions or user instructions distributed by the AXI module; and the decompression circuit performs data decompression processing based on the configuration instructions or user instructions distributed by the AXI module.

[0019] The configuration control module obtains the data processed by the configuration control function module, and writes the processed data into the controlled unit through a data chain and an address chain to configure the controlled unit.

[0020] The decryption circuit includes AES128 or AES256, the authentication circuit includes SHA256 or SHA1024, and the decompression circuit includes LZR or LZ77.

[0021] The aforementioned chip configuration circuit reuses the configuration circuit from the configuration stage to the user mode, solving the problem of resource waste caused by limitations after configuration in traditional circuits. Furthermore, it achieves unified interaction across all modules through the AXI module, simplifying circuit design and enabling seamless switching between the two stages. This balances configuration efficiency with user mode flexibility, improving hardware resource utilization and reducing hardware costs.

[0022] To make the above and other objects, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram illustrating an FPGA configuration loading process as an example.

[0025] Figure 2 This is a schematic diagram of the structure of an FPGA configuration circuit as an example of a related technology.

[0026] Figure 3 This is a block diagram illustrating the structure of a chip configuration circuit according to this application.

[0027] Figure 4This is a schematic diagram of the architecture of a chip configuration circuit according to this application, as an example. Detailed Implementation

[0028] The foregoing and other technical contents, features, and effects of this application will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a method of distinguishing objects with the same attributes in the embodiments of this application.

[0029] like Figure 1 The diagram illustrates the FPGA configuration loading process in the prior art. From left to right, different configuration modes are controlled, followed by authentication, encryption, and compression algorithms, ultimately completing the FPGA configuration. To ensure compatibility with different FPGA configuration modes, the configuration circuit requires both active and passive loading. Furthermore, different circuits are designed for active and passive loading depending on the external storage medium. The diagram shows JTAG, SPI, Slave, and BPI configuration modes. To improve configuration speed, the bitstream needs to be compressed during configuration loading. Multiple compression algorithms are available to adapt to different configuration bitstreams; the diagram shows LZR and LZ77 decompression algorithms. To address FPGA device privatization, authentication of the FPGA device and its corresponding bitstream is required, ensuring the device can only load a specific bitstream. There are many authentication algorithms and complex authentication circuits; the diagram shows SHA256 and SHA1024 authentication algorithms. To address the security of FPGA devices, decryption processing is required using the loading circuit. The encryption and decryption algorithms are divided into symmetric encryption and asymmetric encryption. Furthermore, there are various methods for storing the key. The above diagram shows the decryption algorithms for AES128 and AES256.

[0030] For a normal FPGA device, the above configuration circuit will only work for a period of time after power-on, and may not work during the power-on process. Once the programmable logic controller is configured, it enters user mode, and these configuration circuits will almost never be used again.

[0031] Traditional FPGA configuration circuit architecture, such as Figure 2As shown, a traditional FPGA configuration system consists of a configuration control interface, a configuration control module, a configuration control function module, and a controlled unit. The configuration control interface includes JTAG, SPI, Slave, and BPI control interfaces; the configuration control module is the Configuration controller; the configuration control function module includes AES128 / 256 decryption circuits, SHA256 / 1024 authentication circuits, and LZR / LZ77 decompression circuits; and the controlled unit is the Programmable Logic. The configuration control interface primarily receives data from external storage units actively or passively; the configuration control module controls the data flow and processes it; the configuration control function module primarily processes the data flow, including decryption, decompression, and authentication; and the controlled unit is mainly the user circuit, programmed by the user using languages ​​such as Verilog, VHDL, and System Verilog, and then compiled and synthesized by software to ultimately implement the desired circuit. In traditional FPGA configuration circuit architecture, the configuration control module directly configures the controlled unit through a linked list. At the same time, the communication between the configuration circuit and the user circuit is unidirectional. That is, once the user circuit is working, the function of the configuration circuit becomes invalid and will not be used again until the next power cycle.

[0032] Therefore, in order to improve the resource utilization of the configuration circuit, such as Figure 3 As shown in the illustration, this application provides a chip configuration circuit, including a configuration control interface, a configuration control module, a configuration control function module, and a controlled unit. The configuration control interface receives data from external storage units and includes a JTAG control interface, an SPI control interface, a Slave control interface, and a BPI control interface. The configuration control function module includes a decryption circuit, an authentication circuit, and a decompression circuit. The configuration control module includes a master control module and an AXI module. The master control module is connected to the AXI module via an AXI interface, and the AXI module is connected to both the configuration control interface and the configuration control function module via AXI interfaces. During the configuration phase, the master control module determines the configuration mode based on configuration instructions, and the AXI module calls the corresponding configuration control interface based on the configuration mode to obtain the data transmitted by the configuration control interface and determine the data flow direction to execute the corresponding configuration process, thereby configuring the controlled unit. The controlled unit is connected to the AXI module via an AXI interface. During the user mode phase, the controlled unit sends user instructions to the AXI module via the AXI interface, and the AXI module calls the corresponding configuration control function module as the user circuit based on the user instructions.

[0033] In the chip configuration circuit of this embodiment, during the power-on configuration phase, after external triggering of configuration, the main control module receives and parses the configuration instruction, determines the configuration module to be used, and sends the instruction to the AXI module through the AXI interface. The AXI module calls the corresponding configuration interface based on the configuration mode. The external storage unit transmits the configuration data to the AXI module through the called configuration control interface. The AXI module calls the configuration control function module to process the data according to the data type. The valid configuration data processed between the AXI modules is sent to the controlled unit through the AXI interface to complete the hardware parameter configuration of the controlled unit. In the user mode phase, after configuration is completed, the user mode is entered. At this time, the controlled unit begins to execute user tasks. If functions such as decryption and authentication are required, user instructions are generated and sent to the AXI module through the AXI interface. The AXI module parses the user instructions, identifies the required function, and calls the corresponding configuration control function module. At this time, the configuration control function module is activated as a user circuit. The controlled unit transmits the user data to be processed to the called function module through the AXI module. The processed data is then sent back to the controlled unit through the AXI module to support the execution of user tasks. This allows the configuration circuitry from the configuration phase to be reused in user mode, solving the problem of resource waste caused by limitations after configuration in traditional circuits. Furthermore, the AXI module enables unified interaction across all modules, simplifying circuit design and achieving seamless switching between the two phases. This balances configuration efficiency with user mode flexibility, improving hardware resource utilization and reducing hardware costs.

[0034] Furthermore, in the user mode phase, the controlled unit sends user commands to the AXI module via the AXI interface. The AXI module determines the configuration control interface to be accessed based on the access address and invokes the corresponding configuration control interface. This allows the configuration control interface to be activated and utilized even in user mode, and precise scheduling of interface access is achieved through address mapping. This expands the functional flexibility of user mode and further reduces hardware resource redundancy. For example, during the design phase, a dedicated AXI address space, i.e., an access address, is allocated to each configuration control interface to avoid access conflicts. When the controlled unit needs to access an external storage unit in user mode, it generates a user instruction containing the target interface address. The instruction format may include an opcode, access address, data length, and data content. After receiving the user instruction, the AXI module first parses the access address and determines the corresponding configuration control interface by comparing it with a pre-allocated address range table. After determining the target interface, the AXI module activates the configuration control interface through internal logic and establishes a data transmission channel. If the opcode indicates a read operation, such as when the controlled unit needs to read user data from an external SPI Flash, the AXI module controls the SPI control interface to send a read command to the external storage unit. After receiving the returned data, it sends it back to the controlled unit through the AXI interface. If the opcode indicates a write operation, such as when the controlled unit needs to write a configuration log to an external ROM through the BPI interface, the user data of the controlled unit between the AXI modules is transmitted to the external storage unit through the BPI control interface. After completion, an operation completion signal is returned to the controlled unit. In this process, the hardware logic of the configuration control interface, such as the timing control of SPI and the scan chain drive of JTAG, is reused in user mode, eliminating the need to design separate interface circuits for user scenarios. This simplifies the drive design of the controlled unit, and this high flexibility can adapt to more complex application scenarios, such as real-time data interaction in industrial control and remote configuration updates of IoT devices.

[0035] Furthermore, such as Figure 4 As shown, compared to traditional configuration circuit architectures, the chip configuration circuit architecture of this application includes a configuration control module and an AXI module. The configuration control interface, configuration control function module, and controlled unit all interact through the AXI interface. The AXI interface is divided into a master interface (simply labeled M in the figure) and a slave interface (simply labeled S in the figure). The master interface is used to actively initiate read / write requests, and the slave interface is used to receive requests and return data / acknowledgment signals. Specifically, the master interface is located at the SPI control interface, the BPI control interface, the configuration control module, and the controlled unit; the slave interface is located at the configuration control interface, the configuration control module, and the configuration control function module.

[0036] Specifically, the host interface is located at the SPI control interface, the BPI control interface, the configuration control module, and the controlled unit; the slave interface is located at the configuration control interface, the configuration control module, and the configuration control function module. The controlled unit connects to the AXI module through the host interface, and directly accesses the configuration control function module or the configuration control interface through the host interface. The AXI module and the configuration control function module communicate through the slave interface. The AXI module and the JTAG control interface communicate through the slave interface.

[0037] More specifically, the SPI control interface and BPI control interface need to actively interact with the external storage unit and initiate transactions with other modules, such as transmitting external data to the decryption circuit and sending processed data to the controlled unit; therefore, a host interface is configured. The configuration control module, as the scheduling hub, needs to actively initiate transactions with the configuration control interface and configuration control function module during the configuration phase; therefore, a host interface is configured. The controlled unit, in user mode, needs to actively initiate transactions with the configuration control function module and configuration control interface; therefore, a host interface is configured. In addition to the SPI / BPI control interface, the JTAG / Slave control interface is used to passively receive external commands or respond to calls from the AXI module or the controlled unit in some scenarios; therefore, a slave interface is configured. The configuration control function module only passively responds to external calls and does not actively initiate requests; therefore, a slave interface is configured.

[0038] The master-slave interface division method described above supports the orderly configuration process in the configuration phase and enables flexible resource reuse in user mode. At the same time, by simplifying arbitration and strengthening isolation, the utilization and stability of circuit resources are further improved, and the latency caused by disordered master contention is avoided, the resource overhead of dynamic negotiation is reduced, and the reliability of configuration and the stability of user mode are improved.

[0039] In one optional implementation, the controlled unit and the main control module are connected via a link configuration interface. During the configuration phase, the main control module configures the controlled unit through the link configuration interface. The link configuration interface is used to implement initialization control, low-level parameter configuration, and initialization status feedback, and to achieve layered processing of configuration tasks with the AXI interface. Specifically, the link configuration interface is used in the initial startup phase of the configuration phase when the controlled unit is in an uninitialized state, such as registers not being reset, clock not being stable, or AXI interface logic not being activated. At this time, complex interactions cannot be performed through the AXI interface. The link configuration interface can then be used to write core parameters such as startup enable and clock configuration to the startup register of the controlled unit using a fixed timing sequence, causing it to enter a configurable state from a dormant state. Thus, the link configuration interface ensures the reliability and efficiency of the configuration phase.

[0040] Furthermore, the main control module of the configuration control module is used to acquire and distribute data streams, and then configure them to the controlled unit. Specifically, the timing signals at different stages are as follows: During the configuration stage, Done is 0, INIT_B is high, GWE is 0, GTS is 1, EOS is 0, and POR is 1. During this stage, the configuration control interface and configuration control function module are controlled by the configuration control module until the data stream ends. During the startup stage, POR and INIT_B are both high, the Done, GWE, and EOS signals change from 0 to 1, and the GTS signal changes from 1 to 0, entering user mode. When entering user mode, the configuration control interface and configuration control function module are no longer controlled by the configuration control module, but instead by the programmable logic of the controlled unit.

[0041] As an optional implementation, the decryption circuit decrypts the data based on configuration instructions or user instructions distributed by the AXI module; the authentication circuit authenticates the data based on configuration instructions or user instructions distributed by the AXI module; and the decompression circuit decompresses the data based on configuration instructions or user instructions distributed by the AXI module. Furthermore, the configuration control module obtains the data processed by the configuration control function module and writes the processed data into the controlled unit via a data chain and address chain to configure the controlled unit.

[0042] During the configuration phase, configuration instructions are generated by the master control module and distributed to the configuration control function module via the AXI module. The goal is to ensure the legitimacy, integrity, and efficient transmission of external configuration data. For example, for encrypted configuration data, the configuration instructions distributed by the AXI module include the decryption algorithm type and key index. The decryption circuit loads the algorithm parameters according to the configuration instructions, decrypts the encrypted configuration data transmitted through the slave interface, and outputs plaintext configuration data back to the AXI module.

[0043] In the user mode phase, user commands are generated by the controlled unit and distributed to the configuration control function module via the AXI module. The goal is to reuse hardware resources to process user business data, which includes user application data such as encrypted sensor data and compressed log files. For example, user commands include data to be authenticated, such as control commands sent by external devices, and authentication strategies, such as MAC address-based device legitimacy verification. The authentication circuit verifies the data source or integrity and outputs a pass or reject signal to support the controlled unit's security decisions, such as rejecting commands from unauthorized devices.

[0044] Furthermore, when the configuration control module writes the processed valid data to the controlled unit, it uses a separate transmission method combining data chain and address chain, i.e., a structured method of address-first positioning and data-following-writing. Specifically: the AXI module receives the valid configuration data processed by the configuration control function module and divides it into blocks according to the controlled unit's storage structure (such as register groups or RAM blocks); for each block of data, the AXI module generates corresponding address information (base address, step size, length) and sends it to the controlled unit via the address chain; after the controlled unit confirms the address information is valid, it returns an address-ready signal; the AXI module continuously transmits the block of configuration data via the data chain, and the controlled unit automatically writes it to the corresponding position according to the address counter, while verifying data integrity through data check bits; after a single block of data is written, the controlled unit returns a data reception completion signal, and the AXI module continues to process the next block of data until all configuration data is written. This solves the problem of efficient and accurate mapping of large-scale data, improving configuration efficiency and user task execution efficiency.

[0045] By changing the chip configuration circuit architecture in this application, the configuration circuit and the user circuit become bidirectionally linked. That is, once the user circuit is working, the configuration control function module of the chip configuration circuit can still be called by the user. When the user wants to use the relevant configuration control interface and configuration control function module, the user can directly access the relevant configuration control interface and configuration control function module through the AXI interface. Since the configuration control interface and configuration control function module are very general-purpose circuits with great application prospects in practical applications, the user does not need to program them separately, achieving a good practical effect.

[0046] The chip configuration circuit in this application, in addition to using FPGA chips, also provides guidance for other chips, especially SOC chips such as MCU, DSP, and CPLD, and can be extended to other types of chips.

[0047] It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles thereof, and such improvements and modifications also fall within the scope of protection of the claims of this application. It should be understood that certain features of this disclosure described in the context of individual embodiments for clarity may also be provided in combination in a single embodiment. Conversely, various features of this disclosure described in the context of individual embodiments for clarity may also be provided individually or in any suitable combination or as part of any other described embodiment of this disclosure.

Claims

1. A chip configuration circuit, characterized by comprising: The application relates to a configuration control system of a programmable logic device, comprising: a configuration control interface for receiving data of an external storage unit, including a JTAG control interface, an SPI control interface, a Slave control interface and a BPI control interface; a configuration control function module including a decryption circuit, an authentication circuit and a decompression circuit; a configuration control module including a master control module and an AXI module, wherein the master control module is connected with the AXI module through an AXI interface, the AXI module is connected with the configuration control interface and the configuration control function module through AXI interfaces, in a configuration stage, the master control module determines a configuration mode based on a configuration instruction, the AXI module calls a corresponding configuration control interface based on the configuration mode, obtains data transmitted by the configuration control interface and determines a data flow direction to execute a corresponding configuration process, thereby realizing configuration of a controlled unit; the controlled unit is connected with the AXI module through an AXI interface, in a user mode stage, the controlled unit sends a user instruction to the AXI module based on the AXI interface, and the AXI module calls a corresponding configuration control function module as a user circuit based on the user instruction.

2. The chip configuration circuit of claim 1, wherein In the user mode stage, the controlled unit sends a user instruction to the AXI module through the AXI interface, and the AXI module determines a configuration control interface to be accessed according to an access address to call a corresponding configuration control interface.

3. The chip configuration circuit of claim 2, wherein, The AXI interface includes a host interface and a slave interface, the host interface is arranged in the SPI control interface, the BPI control interface, the configuration control module and the controlled unit, and the slave interface is arranged in the configuration control interface, the configuration control module and the configuration control function module.

4. The chip configuration circuit of claim 3, wherein The controlled unit is connected with the AXI module through the host interface, and the controlled unit directly accesses the configuration control function module or the configuration control interface through the host interface.

5. The chip configuration circuit of claim 3, wherein, The AXI module and the configuration control function module are connected through the slave interface.

6. The chip configuration circuit of claim 3, wherein, The AXI module and the JTAG control interface are connected through the slave interface.

7. The chip configuration circuit of claim 1, wherein The controlled unit and the master control module are connected through a link configuration interface, and the master control module configures the controlled unit through the link configuration interface in the configuration stage.

8. The chip configuration circuit of claim 1, wherein, The decryption circuit performs decryption processing of data based on a configuration instruction or a user instruction distributed by the AXI module, the authentication circuit performs authentication processing of data based on the configuration instruction or the user instruction distributed by the AXI module, and the decompression circuit performs decompression processing of data based on the configuration instruction or the user instruction distributed by the AXI module.

9. The chip configuration circuit of claim 8, wherein, The configuration control module obtains processed data of the configuration control function module, and writes the processed data into the controlled unit through a data chain and an address chain to configure the controlled unit.

10. The chip configuration circuit of claim 8, wherein, The decryption circuit includes AES128 or AES256, the authentication circuit includes SHA256 or SHA1024, and the decompression circuit includes LZR or LZ77.

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