Three-dimensional chip thermal sensing optimization method based on tensor data flow

Abstract

The invention discloses a three-dimensional chip thermal perception optimization method based on tensor data flow, and relates to the field of integrated circuits, and the method comprises the steps: firstly, starting from the angle of tensor data flow, providing a collaborative thermal optimization process combining a network, an architecture, physics and packaging; then, based on a quantitative modeling tensor data flow energy optimization method, automatically identifying the most energy-saving tensor data flow under given three-dimensional chip constraints by using a heuristic optimization method; and finally, providing a thermal sensing three-dimensional architecture spatial layout method, simplifying the spatial layout problem of the SRAM macro block into an affine mapping optimization problem, and optimizing an affine mapping relationship through a heuristic optimization method to obtain the spatial layout with optimal thermal performance. According to the method, the tensor calculation characteristics are optimized in a targeted manner, so that the three-dimensional stacked SRAM chip meets the thermal reliability requirement in a high-density integration scene.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a three-dimensional chip thermal sensing optimization method based on tensor data flow. Background Technology

[0002] In recent years, the rapid development of computationally intensive applications such as deep neural networks (DNN) and large language models (LLM) has led to an exponential increase in demand for chip tensor computing power. With traditional two-dimensional integrated circuits approaching their physical limits, three-dimensional integrated circuits (3DICs) technology, through vertical device stacking, has achieved increased transistor density, reduced interconnect latency, and breakthroughs in memory bandwidth, becoming a key path to extending Moore's Law and significantly optimizing chip power consumption, performance, and area (PPA) metrics.

[0003] In 3D IC architecture, the three-dimensional stacked SRAM architecture has been widely used in various computing scenarios due to its advantages such as high bandwidth, low latency, and large-capacity buffer. A typical example is AMD's 3D V-Cache technology, which vertically stacks a large-capacity L3 cache on the logic chip, significantly improving bandwidth and performance. This technology has been successfully commercialized in Ryzen and EPYC processors, verifying the feasibility of three-dimensional stacked SRAM. However, the vertical stacking characteristics of three-dimensional stacked SRAM lead to increased chip power density, causing serious thermal problems and becoming a major bottleneck restricting its further development.

[0004] Existing heat dissipation measures for 3D chips mainly focus on dynamic thermal management (DTM), microfluidic cooling, and task scheduling optimization. However, in-depth research on the impact of the characteristics of tensor data streams on thermal effects is still lacking. In fact, the data stream characteristics of tensor computation directly affect the energy efficiency and power consumption distribution of 3D stacked SRAM chips, thereby indirectly affecting the heat generation and heat propagation of the 3D chip. Therefore, without targeted optimization of tensor computation characteristics, 3D stacked SRAM chips cannot meet the thermal reliability requirements of high-density integration scenarios.

[0005] Therefore, those skilled in the art are dedicated to developing a method optimized for tensor computation characteristics. Summary of the Invention

[0006] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by the present invention is how to optimize the tensor computation characteristics in a targeted manner so that the three-dimensional stacked SRAM chip can meet the thermal reliability requirements of high-density integration scenarios.

[0007] To achieve the above objectives, this invention provides a three-dimensional chip thermal sensing optimization method based on tensor data flow. The method is characterized by: firstly, proposing a collaborative thermal optimization process combining network, architecture, physics, and packaging from the perspective of tensor data flow; secondly, using a quantitatively modeled tensor data flow energy optimization method, automatically identifying the most energy-efficient tensor data flow under given three-dimensional chip constraints using heuristic optimization methods; and finally, proposing a thermally sensing three-dimensional architecture spatial layout method, simplifying the SRAM macroblock spatial layout problem into an affine mapping optimization problem, and optimizing the affine mapping relationship through heuristic optimization methods to obtain the thermally optimal spatial layout.

[0008] Furthermore, the three-dimensional chip architecture adopts a LoM (Logic-on-Memory) stack configuration, placing the high-power logic chip closest to the heat sink to maximize its heat dissipation efficiency. The logic chip and the top SRAM layer are interconnected via face-to-face (F2F) hybrid bonding, effectively avoiding interference from through-silicon vias (TSVs) on the logic layout, while ensuring high computing density and excellent signal integrity. For multi-layer SRAM stacks, face-to-back and F2B hybrid bonding combined with TSV communication are used to maximize silicon utilization and maintain signal transmission efficiency. The SRAM layer requires silicon thinning to ensure TSV penetration.

[0009] Furthermore, the three-dimensional chip architecture constructs a dual-path heat dissipation mechanism, wherein the primary path includes: silicon chip → thermally conductive interface material → thermal diffuser → heat sink, and the secondary path includes: silicon chip → packaging substrate → printed circuit board.

[0010] Furthermore, based on a three-dimensional chip architecture, this method proposes a thermal sensing collaborative optimization framework. The framework takes network structure, architecture configuration, stacking method and thermal parameters as inputs, and outputs multi-dimensional indicators including optimal data flow, spatial layout, performance density, power density, energy efficiency and thermal performance.

[0011] Furthermore, the tensor data stream energy optimization method identifies the energy-optimized tensor data stream by conducting Tensor Cube Engine (TCE) organization exploration, and simultaneously generates the power and area characteristics of each functional unit.

[0012] Furthermore, the thermal sensing collaborative optimization framework adopts a genetic algorithm based on the open-source DEAP framework, with overall energy consumption as the optimization objective. The key parameters QM, QN, and QK of the Tensor Cubic Engine are encoded as chromosome genes. The optimization process continuously evolves the candidate solution population through crossover and mutation operations. Through multiple iterations, the optimal TCE organization structure that balances performance density and thermal efficiency can be obtained under the constraints of limited area and power consumption, thereby effectively reducing overall heat generation.

[0013] Furthermore, the thermal sensing three-dimensional architecture spatial layout method achieves dynamic balanced distribution of power consumption in the vertical and horizontal dimensions through global and local layout collaborative optimization, thereby effectively reducing the peak temperature of the three-dimensional chip, improving the heat conduction path, and enhancing overall reliability and energy efficiency.

[0014] Furthermore, the global layout and local layout are optimized at the physical layout and data layout levels, respectively.

[0015] Furthermore, the global layout implementation method includes the following steps: Step 1: Define the key parameters GFpara for the global layout, including aspect ratio, rotation direction, and connectivity, to determine the feasible geometry and interconnect complexity of the logic layer. Step 2: Construct the evaluation function EvalCost, which is a linear combination of area, peak temperature Tmax and wiring length, to achieve a balance between area utilization, thermal performance and wiring overhead. Step 3: Call the HotSpot v7.0 thermal simulation tool to perform thermally-aware layout optimization of the logic layer, and expand the thermal performance term in the evaluation function to the peak temperature of the entire three-dimensional chip, so as to simultaneously introduce the thermal constraint conditions of the SRAM layer. Step 4: Convert the iteratively optimized Normalized Polish Notation (NPE) into a global layout representation to obtain the physical layout result of the logical layer. This optimization can obtain the optimal three-dimensional physical layout.

[0016] Furthermore, the local layout implementation method includes the following steps: Step 1: Divide each SRAM layer into Rnum equal-area sub-regions, and each sub-region can only be occupied by one SRAM macroblock; Step 2: Based on the capacity ratio of matrices A, B and C, deduce the number of SRAM macroblocks required for each matrix, and distribute their power consumption evenly to the corresponding SRAM macroblocks. Step 3: Initialize the 3D spatial layout using the global layout results and affine mapping relationship to generate an initial solution for local layout optimization; Step 4: Introduce a heuristic algorithm to iteratively optimize the spatial location of SRAM macroblocks; specifically, evolve candidate layouts through a genetic algorithm; call the thermal simulation module to calculate the thermal performance indicators of the new and old layouts; update the optimal solution based on the peak temperature results; this process terminates when the set iteration time limit is reached, and finally outputs the optimized layout and the corresponding thermal distribution heatmap.

[0017] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description

[0018] Figure 1 This is a preferred embodiment of the three-dimensional stacked SRAM chip architecture and packaging design of the present invention; Figure 2 This is a preferred embodiment of the three-dimensional stacked SRAM chip thermal sensing collaborative optimization framework of the present invention; Figure 3 This is the basic structure of a Tensor Cube Engine (TCE) according to a preferred embodiment of the present invention; Figure 4 This is a comparison of bandwidth requirements and power consumption of different tensor data stream organization methods in a preferred embodiment of the present invention. Figure 5 This is a preferred embodiment of the GEMM multi-level loop and on-chip data stream execution method of the present invention; Figure 6 This is a preferred embodiment of the three-dimensional chip array-level architecture of the present invention; Figure 7 This is a simplified local floorplan problem of a preferred embodiment of the present invention, which is an affine mapping problem. Detailed Implementation

[0019] The following description, with reference to the accompanying drawings, illustrates several preferred embodiments of the present invention to make its technical content clearer and easier to understand. The present invention can be embodied in many different forms, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0020] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of some components has been appropriately exaggerated in the drawings.

[0021] Example 1: Three-dimensional stacked SRAM chip architecture and thermal sensing co-optimization framework

[0022] This embodiment proposes a thermal sensing collaborative optimization method for three-dimensional stacked SRAM chips oriented towards tensor computing. It aims to effectively alleviate the problems of excessive power density and local hot spots caused by vertical stacking by integrating architecture design and thermal management.

[0023] In the design of the three-dimensional stacked SRAM chip architecture, this embodiment adopts the following... Figure 1 The illustrated Logic-on-Memory (LoM) stack configuration (using a two-layer SRAM chip as an example) places the high-power logic chip closest to the heatsink to maximize its heat dissipation efficiency. The logic layer and the top SRAM layer are interconnected via face-to-face (F2F) hybrid bonding, effectively avoiding interference from through-silicon vias (TSVs) on the logic layout while ensuring high computational density and excellent signal integrity. For multi-layer SRAM stacks, face-to-back (F2B) hybrid bonding combined with TSV communication is used to maximize silicon utilization and maintain signal transmission efficiency. The SRAM layer requires silicon thinning to ensure TSV penetration. The hybrid bonding bump spacing is 5.5 μm, the TSV spacing is 11 μm, and the aspect ratio is 10:1. Signals are redistributed across layers via a redistribution layer (RDL) to optimize interconnect paths and enhance three-dimensional signal integrity. This structure establishes a dual-path heat dissipation mechanism: a primary path (silicon chip → thermal interface material → thermal diffuser → heatsink) and a secondary path (silicon chip → packaging substrate → printed circuit board). Table 1 shows the physical and packaging parameters of the three-dimensional stacked SRAM chip in this embodiment. Among them, L chip It is the side length of the chip.

[0024] Table 1 Physical and Packaging Parameters of 3D Stacked SRAM Chips

[0025] Based on the chip structure and parameters constructed in this embodiment, this invention proposes a thermal sensing collaborative optimization framework to quickly determine the optimal energy consumption / power consumption distribution and three-dimensional chip space layout, achieving rapid quantitative evaluation of key design indicators and providing complete quantitative basis and optimization decision support for the architecture design and system implementation of three-dimensional stacked SRAM chips. This framework is as follows: Figure 2As shown, taking network structure, architecture configuration, stacking method, and thermal parameters as inputs, and multi-dimensional indicators including optimal data flow, spatial layout, performance density, power density, energy efficiency, and thermal performance as outputs, this framework includes two core technical processes: heat generation optimization based on tensor energy consumption quantitative modeling (Example 2) and heat dissipation optimization based on spatial layout affine optimization (Example 3). The former conducts tensor cube engine (TCE) organization exploration to identify the energy-efficient tensor data flow and simultaneously generate the power and area characteristics of each functional unit; the latter combines thermal parameters to perform thermally-sensory spatial layout optimization to improve heat diffusion efficiency. This provides complete quantitative basis and optimization decision support for the architecture design and system implementation of three-dimensional stacked SRAM chips.

[0026] Example 2: Heat generation optimization based on tensor energy consumption quantitative modeling

[0027] This embodiment proposes a tensor data stream energy optimization method based on quantitative modeling for tensor data streams in a three-dimensional stacked SRAM architecture. Using a heuristic optimization algorithm, the most energy-efficient tensor data stream can be automatically identified under given three-dimensional chip constraints, thereby reducing heat generation.

[0028] 1. Basic Structure of Tensor Cube Engine (TCE)

[0029] like Figure 3 As shown, the Tensor Cube Engine (TCE) consists of a large number of multiply-accumulate units, organized in a three-dimensional array of size QM×QN×QK. Each computation cycle can perform the multiplication of two matrices (matrix A of size QM×QK and matrix B of size QN×QK), and the spatial reduction of the multiplication result and its temporal reduction with the previous result are achieved through a spatiotemporal accumulator. To reduce the number of data transfers, this embodiment adopts a fixed output data scheduling method, writing back the result only after the computation is completed; intermediate results are temporarily stored in the spatiotemporal accumulator buffer.

[0030] 2. Main problems

[0031] Traditional solutions often rely on a single and rigid tensor data stream organization method, resulting in high energy consumption, high power density, and severe heat generation problems. This embodiment analyzes, through a case study, how different tensor data stream organization methods can lead to significant differences in energy consumption / power consumption with the same number of multiply-accumulate units, specifically as follows: Figure 4As shown. For example, while increasing QK can reduce the use of the accumulation buffer and thus lower the power consumption of the logic layer, it significantly increases the memory bandwidth requirement, leading to increased SRAM access power consumption. At the same time, the increased bandwidth requires more through-silicon vias (TSVs), which not only incurs area overhead but also alters the chip's heat dissipation path, potentially impacting thermal performance. Therefore, achieving a power / energy balance while maintaining performance without incurring significant area overhead is one of the key challenges in 3D stacked SRAM architectures.

[0032] 3. Quantitative Modeling and Optimization Methods

[0033] 3.1 The calculation cycle and partial access cycle of a block

[0034] Figure 5 This demonstrates the GEMM multi-level loop and on-chip data stream execution method. The outer loop is responsible for storing tiled data into the on-chip SRAM buffer in a ping-pong manner. The middle loop is responsible for feeding the data in the on-chip SRAM buffer into multiple blocks for TCE execution. The inner loop is responsible for executing the calculation result of a block, and each block requires at least tK / QK calculation cycles to obtain the accumulated result. On-chip execution calculates the parts and results of different blocks sequentially according to a fixed output method. Figure 6 The three-dimensional chip array-level architecture was demonstrated, which includes a Tensor Cube Engine (TCE), a Task Scheduling Unit (TSU), and a Data Management Unit (DMU). The QM×QN×QK 3D array is organized into QM×QN processing elements (PEs), each PE containing QK MACs and a spatiotemporal accumulator. To ensure seamless connection and pipelined operation between different blocks, a ping-pong buffering mechanism is used in the spatiotemporal accumulator buffer, allowing accumulation, write-back, and read operations to alternate. That is, while Block m,n is being accumulated in one buffer, another buffer simultaneously completes the write-back of Block m,n-1 and the initial load of Block m,n+1. Furthermore, when the SRAM bandwidth meets the requirements, the TCE utilization rate can reach 100%. Therefore, the computation cycle and partial access cycle of a block can be expressed as formula (1). Wherein, and These are the bandwidth requirements for matrix A and matrix B, respectively. This represents the total bandwidth of the on-chip SRAM.

[0035]

[0036] 3.2 Three-dimensional physical constraints

[0037] This embodiment employs a multi-attach strategy to improve signal integrity and power supply capability during vertical interconnection in a three-dimensional stack. For vertical transmission signals between the logic chip and the SRAM chip, and between the three-dimensional chip and external I / O signals, at least 2 and 8 hybrid bonding bumps (HBs) are allocated, respectively, ensuring that the number of HBs allocated to power and ground is no less than the number of HBs for the signals. The physical constraint relationship of the hybrid bonding bumps is shown in formula (2). For external I / O bandwidth, The side length of the three-dimensional chip. The spacing of the hybrid bonding bumps is 5.5 μm.

[0038]

[0039] For TSVs, a multi-point interconnect strategy is also adopted. For vertical transmission signals between logic chips and SRAM chips, and between 3D chips and external I / O signals, at least 1 and 2 TSVs are allocated, respectively, and the number of TSVs allocated to power and ground is not less than the number of TSVs for the signals. For the interconnect communication between the SRAM stack layer (n layers in total) and the logic chip, except for the top SRAM layer, the remaining (n-1) layers rely on TSV interconnects, and it is necessary to ensure that the area of ​​the logic chip is consistent with that of all SRAM chips. The physical constraint relationship and area constraint relationship of TSVs are shown in formula (3). TSV area in each SRAM die This represents the total area of ​​the circuitry within all SRAM chips. This represents the area of ​​the logic layer.

[0040]

[0041] 3.3 Architectural Performance Constraints

[0042] In this embodiment, performance must be maintained without loss when optimizing energy consumption. Performance density is used as the metric, and its expression is shown in formula (4). For different TCE configurations, we can obtain the optimal SRAM bandwidth allocation for matrices A, B, and C by solving the optimal performance density problem. The number of operands required for a single-layer GEMM ( Here, each MAC contains two operations. For single-layer GEMM calculation cycles, For the chip's execution frequency, Indicates the number of tiles. Indicates the number of blocks.

[0043]

[0044] 3.4 Quantitative Analysis of Energy Consumption

[0045] Based on the above parameters such as tensor data flow and bandwidth allocation, the energy consumption of the logic layer and storage layer can be quantitatively modeled according to formula (5) to take the heat generation of the side inverse matrix multiply-accumulate (GEMM) layer under the three-dimensional stacked SRAM structure. For a single-layer GEMM, in order to ensure the integrity of the model, this embodiment takes into account both dynamic energy consumption and static energy consumption in the energy consumption calculation. The static energy consumption of the logic layer is obtained through the RTL-level synthesis process (28nm@1GHz), while the static energy consumption of the SRAM storage layer is estimated based on the Cacti 7.0 tool. Dynamic energy consumption includes the dynamic energy consumption of the logic chip and the memory access power consumption of the SRAM chip. The energy consumption of the logic layer is composed of the Tensor Cube Engine (TCE), the Task Scheduling Unit (TSU), and the Data Management Unit (DMU). Among them, the TCE part further includes the energy consumption of the multiply-accumulate unit (MAC) and the space-time accumulator (STA) buffer. The energy consumption of the SRAM storage layer mainly comes from the read and write operations of the on-chip SRAM, while also considering the energy consumption overhead caused by the interaction with external storage. This indicates the number of multiply-accumulate units contained in the TCE; This represents the energy consumption of one calculation using an 8-bit multiply-accumulate unit. This indicates the number of spacetime accumulator buffers included in the TCE (multiplying by 2 is to make...). ); This represents the energy consumption of one toggle of the spacetime accumulator buffer; and This indicates the energy consumption for reading and writing 8-bit data from SRAM.

[0046]

[0047] Based on the energy consumption quantification calculation of a single-layer GEMM in formula (5), it is further extended to the total tensor energy consumption of the entire deep neural network (DNN) or large-scale language model (LLM), as shown in formula (6).

[0048]

[0049] 3.5 Heuristic Optimization

[0050] Based on the established energy consumption model, this embodiment introduces a heuristic optimization algorithm to optimize energy consumption. Specifically, a genetic algorithm based on the open-source DEAP framework is used, with the overall energy consumption in formula (6) as the optimization objective. The key parameters QM, QN, and QK of the Tensor Cubic Engine are encoded as chromosome genes. The optimization process continuously evolves the candidate solution population through crossover and mutation operations. Through multiple iterations, the optimal TCE organization structure that balances performance density and thermal efficiency can be obtained under the constraints of limited area and power consumption, thereby effectively reducing overall heat generation.

[0051] 4. Conclusion of this embodiment

[0052] Through the above modeling and optimization process, the following conclusions can be drawn from this embodiment: (1) From formula (1), we can obtain that when Only when the total bandwidth is sufficient can the TCE resource utilization reach 100%. A sufficiently large tK is key to ensuring this condition. That is, the size of the on-chip tile block must ensure that enough data can be stored in the tK direction to guarantee the full pipelined non-blocking execution of the TCE.

[0053] (2) As can be seen from the energy consumption formula (5), under the same MAC resources, the energy consumption of the space-time accumulator buffer is inversely proportional to QK, while the energy consumption of SRAM access is directly proportional to it. QM=QN is more energy efficient than QM≠QN. By reasonably balancing QM, QN, and QK, power consumption can be balanced between the logic layer and the SRAM layer, reducing the risk of hotspots.

[0054] (3) This embodiment provides a configuration that is optimal in terms of performance density, energy efficiency, thermal performance and manufacturability. The TCE in the three-dimensional stacked SRAM architecture contains 2048 MAC units, QM×QN×QK=16×16×8; the SRAM capacity is 2048KB, the SRAM bandwidth is 1024B / cycle; 4-tier SRAM is used, and each layer of SRAM chip is allocated 512KB capacity.

[0055] Example 3: Heat dissipation optimization based on spatial layout affine optimization

[0056] This embodiment addresses the heat dissipation problem caused by uneven power distribution in SRAM macroblocks. propose A heat dissipation optimization method based on spatial layout affine optimization is proposed. By co-optimizing the global and local two-layer layout, a dynamic and balanced distribution of power consumption in the vertical and horizontal dimensions is achieved, thereby effectively reducing the peak temperature of the three-dimensional chip, improving the heat conduction path, and enhancing overall reliability and energy efficiency.

[0057] 1. Main problems

[0058] In a three-dimensional stacked SRAM architecture, when performing GEMM operations using a Tensor Cube Engine (TCE), the following methods are typically employed: Figure 5 The block partitioning method shown is adapted to the limited capacity of the on-chip SRAM, and output fixed (OS) scheduling is used in the inner loop computation to maximize data reuse. At this time, the partial sum (psum) of each computation block needs to be temporarily stored in the space-time accumulator (STA) until all computations in the corresponding tK dimension are completed before being uniformly written back to the SRAM buffer. Therefore, the following phenomenon is observed: matrices A and B are in a highly active state in each computation cycle, while matrix C is only active once in tK / QK cycles, resulting in significantly higher SRAM access power consumption for matrices A and B than for matrix C. Furthermore, when QM≠QN, the access power consumption of matrices A and B also exhibits a different distribution. More complexly, matrix C typically occupies a larger capacity in SRAM than matrices A and B, further amplifying the power consumption difference. Given the uneven SRAM macroblock power caused by the difference in memory access frequencies of matrices A, B, and C, their spatial layout in the three-dimensional stacked SRAM structure becomes one of the key factors affecting heat dissipation performance.

[0059] 2. Optimization of hierarchical spatial layout

[0060] This implementation, based on HotSpot v7.0, proposes a hierarchical spatial layout optimization algorithm that combines global and local layout. It optimizes both the physical and data layout levels to achieve a balanced power consumption distribution in the vertical and horizontal dimensions, thereby optimizing heat propagation. The optimization process is shown in Algorithm 1.

[0061]

[0062] The algorithm input includes information such as the area and power consumption of each computing module obtained after optimization in Example 2, as well as information such as physical packaging.

[0063] 2.1 Global floorplan (Algorithm 1, lines 1-5)

[0064] The global layout is primarily achieved at the module level using the HotSpot v7.0 tool, completing the 3D physical layout. The SRAM layer is divided into regions according to typical process practices to ensure manufacturing friendliness; the physical division method is as follows: Figure 7 As shown on the right, it includes two through-silicon via (TSV) regions for vertical interconnects and a centrally located SRAM data storage region. The logic layer is thermally optimized using the HotSpot v7.0 tool, assuming a uniform power distribution across the SRAM layer without considering non-uniform differences between macroblocks.

[0065] (1) First, define the key parameter GFpara for the global layout, including aspect ratio, rotation direction, and connectivity, to determine the feasible geometry and interconnection complexity of the logic layer. (Algorithm 1, line 2)

[0066] (2) Next, construct the evaluation function EvalCost, which is a linear combination of area, peak temperature (Tmax), and wiring length, to achieve a balance between area utilization, thermal performance, and wiring overhead. (Line 3 of Algorithm 1)

[0067] (3) Use HotSpot v7.0 thermal simulation tool to perform thermally-aware layout optimization of the logic layer, and expand the thermal performance term in the evaluation function to the peak temperature of the entire three-dimensional chip, so as to simultaneously introduce the thermal constraint condition of the SRAM layer. (Algorithm 1, line 4)

[0068] (4) Finally, the iteratively optimized Normalized Polish Notation (NPE) is converted into a global layout representation to obtain the physical layout result of the logical layer. This optimization can obtain the optimal 3D physical layout. (Algorithm 1, line 5)

[0069] 2.2 Local Layout (Global floorplan, Algorithm 1, lines 6-15)

[0070] Local layout optimization addresses the differences in memory access frequencies among matrices A, B, and C by performing thermally sensitive optimization on the spatial distribution of SRAM macroblocks. This embodiment simplifies this optimization into an affine mapping problem, such as... Figure 7 As shown, by allocating sub-regions exclusively and strategically, the local heat accumulation caused by power consumption differences is reduced.

[0071] (1) First, each SRAM layer is divided into Rnum equal-area sub-regions, and each sub-region can only be occupied by one SRAM macroblock. In this embodiment, Rnum is set to 8 to balance search efficiency and optimization quality. (Algorithm 1, line 7)

[0072] (2) Next, based on the capacity ratio of matrices A, B and C, deduce the number of SRAM macroblocks required for each matrix, and evenly distribute their power consumption to the corresponding SRAM macroblocks. (Algorithm 1, line 8)

[0073] (3) Furthermore, the three-dimensional spatial layout is initialized using the global layout results and affine mapping relationship to generate an initial solution for local layout optimization. (Algorithm 1, line 9)

[0074] (4) Finally, a heuristic algorithm (genetic algorithm) is introduced to iteratively optimize the spatial location of the SRAM macroblock. Specifically, the candidate layout is evolved through a genetic algorithm (line 11 of Algorithm 1); the thermal simulation module is called to calculate the thermal performance indicators of the old and new layouts (line 12 of Algorithm 1); and the optimal solution is updated based on the peak temperature results (line 13 of Algorithm 1). This process terminates when the set iteration time limit is reached (line 10 of Algorithm 1), and finally the optimized layout and the corresponding thermal distribution heatmap are output (line 15 of Algorithm 1).

[0075] 3. Conclusion of this embodiment

[0076] Through the above optimization process, the following technical effects and regularities can be obtained in this embodiment: (1) Vertical power consumption distribution of three-dimensional stacked SRAM chips: It presents a gradient that gradually decreases from the top SRAM to the bottom SRAM, forming a structure similar to an "inverted power tower". High-power SRAM macroblocks are concentrated near the logic layer to achieve efficient heat dissipation with the help of heat sinks; however, not all high-power SRAM macroblocks can be concentrated near the logic layer. A small number of high-power macroblocks need to be distributed in the SRAM layer near the PCB to avoid overheating of the logic layer, and heat dissipation is achieved by relying on silicon-based materials and packaging paths.

[0077] (2) Horizontal power consumption distribution of three-dimensional stacked SRAM chips: The three-dimensional stacked SRAM chips are divided into 64 small blocks according to grid. During the local layout optimization process, it was observed that the power density difference between grids gradually decreased, indicating that high power SRAM macroblocks should be avoided from being stacked in the same horizontal area of ​​different layers of SRAM chips. Instead, a cross-layer staggered arrangement should be adopted to weaken vertical thermal coupling and thus improve the overall thermal uniformity.

[0078] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A three-dimensional chip thermal sensing optimization method based on tensor data flow, characterized in that, This method first proposes a collaborative thermal optimization process that combines network, architecture, physics, and encapsulation from the perspective of tensor data flow; Then, based on the energy optimization method of tensor data streams using quantitative modeling, the most energy-efficient tensor data streams are automatically identified under given three-dimensional chip constraints using heuristic optimization methods. Finally, a thermally sensing three-dimensional architecture spatial layout method is proposed, which simplifies the spatial layout problem of SRAM macroblocks into an affine mapping optimization problem. The affine mapping relationship is optimized through heuristic optimization methods to obtain the spatial layout with optimal thermal performance.

2. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 1, characterized in that, The three-dimensional chip architecture adopts LoM, or Logic-on-Memory stacked configuration, which places high-power logic chips closest to the heat sink to maximize their heat dissipation efficiency.

3. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 2, characterized in that, The logic chip and the top SRAM layer are interconnected via face-to-face (F2F) hybrid bonding, which effectively avoids interference from through-silicon vias (TSVs) on the logic layout, while ensuring high computing density and excellent signal integrity. For multi-layer SRAM stacks, face-to-back and F2B hybrid bonding combined with TSV communication are used to maximize silicon utilization and maintain signal transmission efficiency. The SRAM layer needs to be thinned to ensure that the TSVs can penetrate through it.

4. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 3, characterized in that, Based on a three-dimensional chip architecture, this method proposes a thermal sensing collaborative optimization framework. The framework takes network structure, architecture configuration, stacking method and thermal parameters as inputs, and outputs multi-dimensional indicators including optimal data flow, spatial layout, performance density, power consumption density, energy efficiency and thermal performance.

5. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 4, characterized in that, The tensor data stream energy optimization method identifies the energy-optimal tensor data stream by conducting Tensor Cube Engine (TCE) organization exploration, and simultaneously generates the power and area characteristics of each functional unit.

6. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 5, characterized in that, The thermal sensing collaborative optimization framework adopts a genetic algorithm based on the open-source DEAP framework. With overall energy consumption as the optimization objective, the key parameters QM, QN, and QK of the Tensor Cubic Engine are encoded as chromosome genes. The optimization process continuously evolves the candidate solution population through crossover and mutation operations. Through multiple iterations, the optimal TCE organization structure that balances performance density and thermal efficiency can be obtained under the constraints of limited area and power consumption, thereby effectively reducing overall heat generation.

7. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 6, characterized in that, The thermal sensing 3D architecture spatial layout method achieves dynamic and balanced power consumption distribution in the vertical and horizontal dimensions through global and local layout collaborative optimization, thereby effectively reducing the peak temperature of the 3D chip, improving the heat conduction path, and enhancing overall reliability and energy efficiency.

8. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 7, characterized in that, The global layout and local layout are optimized from the perspectives of physical layout and data layout, respectively.

9. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 8, characterized in that, The global layout implementation method includes the following steps: Step 1: Define the key parameters GFpara for the global layout, including aspect ratio, rotation direction, and connectivity, to determine the feasible geometry and interconnect complexity of the logic layer. Step 2: Construct the evaluation function EvalCost, which is a linear combination of area, peak temperature Tmax and wiring length, to achieve a balance between area utilization, thermal performance and wiring overhead. Step 3: Call the HotSpot v7.0 thermal simulation tool to perform thermally-aware layout optimization of the logic layer, and expand the thermal performance term in the evaluation function to the peak temperature of the entire three-dimensional chip, so as to simultaneously introduce the thermal constraint conditions of the SRAM layer. Step 4: Convert the iteratively optimized Normalized Polish Notation (NPE) into a global layout representation to obtain the physical layout result of the logical layer. This optimization can obtain the optimal three-dimensional physical layout.

10. The three-dimensional chip thermal sensing optimization method based on tensor data flow as described in claim 9, characterized in that, The method for implementing the local layout includes the following steps: Step 1: Divide each SRAM layer into Rnum equal-area sub-regions, and each sub-region can only be occupied by one SRAM macroblock; Step 2: Based on the capacity ratio of matrices A, B and C, deduce the number of SRAM macroblocks required for each matrix, and distribute their power consumption evenly to the corresponding SRAM macroblocks. Step 3: Initialize the 3D spatial layout using the global layout results and affine mapping relationship to generate an initial solution for local layout optimization; Step 4: Introduce a heuristic algorithm to iteratively optimize the spatial location of SRAM macroblocks; specifically, evolve candidate layouts through a genetic algorithm; call the thermal simulation module to calculate the thermal performance indicators of the new and old layouts; update the optimal solution based on the peak temperature results; this process terminates when the set iteration time limit is reached, and finally outputs the optimized layout and the corresponding thermal distribution heatmap.

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