Gamma voltage generating circuit, display device and driving method of display device

Abstract

The invention discloses a gamma voltage generation circuit, a display device and a driving method of the display device. The gamma voltage generation circuit comprises a voltage output module, the input end of the voltage output module is connected with a first voltage, and the voltage output module is used for controlling whether to output the first voltage or not according to a signal connected with the control end of the voltage output module; and the gamma voltage generation module is connected with the output end of the voltage output module and is used for generating at least two gamma voltages according to the first voltage when the output end of the voltage output module outputs the first voltage. The voltage output module is also used for controlling the disconnection between the output end and the input end of the voltage output module according to the potential of the control end of the voltage output module so that the first voltage cannot be output, the output end of the voltage output module is in a high-resistance state, the first voltage is not output any more at the stage of not influencing normal display of the display device, and the power consumption of the display device is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gamma voltage generation circuit, a display device, and a driving method for the display device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is considered the most promising next-generation display technology. Compared with liquid crystal display technology, OLED display technology has advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed.

[0003] In the traditional OLED display panel manufacturing process, a fine metal mask (FMM) is typically used to pattern the light-emitting pixels. FMM technology is mature and has extensive mass production experience. However, FMM technology also suffers from limitations in precision and high cost. Fine metal mask-less technology eliminates the limitations of traditional OLED processes on display size, resolution, and other screen performance characteristics, offering advantages such as high performance, full-size display, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, and CN118781966A describe relevant content regarding fine metal mask-less technology and are provided for reference.

[0004] However, OLED products consume a relatively large amount of power in practical applications. Summary of the Invention

[0005] This invention provides a gamma voltage generation circuit, a display device, and a driving method for the display device to solve the problem of high power consumption in display devices.

[0006] According to a first aspect of the present invention, a gamma voltage generating circuit is provided, comprising:

[0007] A voltage output module, wherein the input terminal of the voltage output module is connected to a first voltage, and the voltage output module is used to control whether to output the first voltage according to the signal connected to the control terminal of the voltage output module;

[0008] A gamma voltage generation module is connected to the output terminal of the voltage output module and is used to generate at least two gamma voltages based on the first voltage when the first voltage is output at the output terminal of the voltage output module.

[0009] Optionally, the voltage output module includes a first output unit, the input terminal of which is connected to the first voltage, and the output terminal of which is connected to the gamma voltage generation module. The first output unit is used to turn on in response to a signal connected to its own control terminal in a first stage to output the first voltage, and is also used to turn off in response to a signal connected to its own control terminal in a second stage to stop outputting the first voltage.

[0010] Optionally, the first output unit includes a transistor connected between the input terminal and the output terminal of the first output unit. The gate of the transistor is connected to a control signal. The transistor is used to turn on in response to the control signal in a first stage and to turn off in response to the control signal in a second stage.

[0011] Alternatively, the first output unit includes at least two transistors connected in series between the input terminal and the output terminal of the first output unit. The gate of each transistor is connected to its corresponding control signal. Each transistor is turned on in response to the control signal connected to its gate in the first stage. At least one transistor connected between the input terminal and the output terminal of the first output unit is turned off in response to the control signal connected to its gate in the second stage.

[0012] Optionally, the voltage output module further includes a second output unit, the output terminal of which is connected to the output terminal of the first output unit, and the input terminal of the second output unit is connected to a second voltage. The second output unit is used to shut down in response to the signal connected to its own control terminal in both the first stage and the second stage.

[0013] Optionally, the first output unit includes: a first switching unit and a second switching unit;

[0014] The first terminal of the first switching unit is connected to the first voltage, and the second terminal of the first switching unit is connected to the first terminal of the second switching unit. The first switching unit is used to turn on in response to a first control signal in the first stage, and the second switching unit is used to turn on in response to a second control signal in the first stage. The first switching unit is also used to turn off in response to the first control signal in the second stage, and / or the second switching unit is also used to turn off in response to the second control signal in the second stage.

[0015] The second output unit includes a third switch unit and a fourth switch unit. The first terminal of the third switch unit is connected to the second terminal of the second switch unit, and the second terminal of the third switch unit is connected to the first terminal of the fourth switch unit. The second terminal of the fourth switch unit is connected to the second voltage. The third switch unit is used to turn off in response to a third control signal in the first stage, and / or the fourth switch unit is used to turn off in response to a fourth control signal in the first stage; the third switch unit is used to turn off in response to the third control signal in the second stage; and / or the fourth switch unit is used to turn off in response to the fourth control signal in the second stage.

[0016] Optionally, the first switching unit includes a first transistor, the second switching unit includes a second transistor, and the third switching unit includes a third transistor;

[0017] The first terminal of the first transistor is connected to the first voltage, the gate of the first transistor is connected to the first control signal, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the second transistor is connected to the second control signal, the second terminal of the second transistor is connected to the first terminal of the third transistor, and the gate of the third transistor is connected to the third control signal.

[0018] The fourth switching unit includes a fourth transistor, the first terminal of the fourth transistor is connected to the second terminal of the third transistor, the second terminal of the fourth transistor is connected to the second voltage, and the gate of the fourth transistor is connected to the fourth control signal;

[0019] Optionally, the first control signal is multiplexed into the fourth control signal, the second control signal is multiplexed into the third control signal, the first transistor and the second transistor have the same channel type, the third transistor and the fourth transistor have different channel types, and the first transistor and the third transistor have different channel types.

[0020] Optionally, the first switching unit includes a first transistor, the second switching unit includes a second transistor, the third switching unit includes a third transistor, and the fourth switching unit includes a fourth transistor and an inverter;

[0021] The first terminal of the first transistor is connected to the first voltage, the gate of the first transistor is connected to the first control signal, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the second transistor is connected to the second control signal, the second terminal of the second transistor is connected to the first terminal of the third transistor, and the gate of the third transistor is connected to the third control signal.

[0022] The first terminal of the fourth transistor is connected to the second terminal of the third switching transistor, the second terminal of the fourth transistor is connected to the second voltage, the gate of the fourth transistor is connected to the output terminal of the inverter, and the input terminal of the inverter is connected to the fourth control signal.

[0023] Optionally, the first control signal is multiplexed into the fourth control signal, the second control signal is multiplexed into the third control signal, the fourth switching unit includes the fourth transistor and the inverter, the first transistor and the second transistor have the same channel type, the third transistor and the fourth transistor have the same channel type, and the first transistor and the third transistor have different channel types.

[0024] Optionally, the first output unit includes a fifth transistor, and the second output unit includes a sixth transistor;

[0025] The first terminal of the fifth transistor is connected to the first voltage, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor, the gate of the fifth transistor is connected to the fifth control signal, the second terminal of the sixth transistor is connected to the second voltage, and the gate of the sixth transistor is connected to the sixth control signal.

[0026] Optionally, the gamma voltage generation module includes multiple resistors connected in series between the output terminal and the fixed potential terminal of the voltage output module. The fixed potential terminal is connected to a third voltage. Both ends of each resistor are used to output the gamma voltage, and the gamma voltage output from the common terminal of two adjacent resistors is the same.

[0027] The third voltage is different from the first voltage;

[0028] Optionally, the first voltage is the gamma voltage corresponding to the maximum gray level of the display device where the gamma voltage generation circuit is located, and the third voltage is the gamma voltage corresponding to the minimum gray level of the display device where the gamma voltage generation circuit is located.

[0029] According to a second aspect of the present invention, a display device is also provided, including a display panel and a driving chip, wherein the driving chip includes a data voltage generation module and the gamma voltage generation circuit described in the first aspect, the data voltage generation module being connected to the gamma voltage generation module and used to generate a corresponding data voltage based on the gamma voltage.

[0030] Optionally, the display panel includes a plurality of pixel circuits arranged in an array;

[0031] The voltage output module is used to respond to a signal received by the control terminal of the voltage output module in the first stage and output a first voltage, and is also used to respond to a signal received by the control terminal of the voltage output module in the second stage and stop outputting the first voltage.

[0032] The first stage is the time period within a display frame from scanning the first row of pixel circuits to scanning the last row of pixel circuits, and the second stage is the time period within a display frame from scanning the last row of pixel circuits to starting scanning the first row of pixel circuits in the next display frame.

[0033] Optionally, the display panel includes: a light-emitting device;

[0034] The display panel also includes:

[0035] Array substrate;

[0036] An isolation structure located on one side of the array substrate, the isolation structure enclosing a plurality of isolation openings, the light-emitting device being at least partially located within the isolation openings.

[0037] Optionally, the isolation structure includes a first isolation portion and a second isolation portion sequentially stacked along a direction away from the array substrate;

[0038] The orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate;

[0039] Optionally, the isolation structure further includes a base located on the side of the first isolation portion near the array substrate, the base being disposed protruding relative to the first isolation portion in a direction toward the isolation opening, and the orthographic projection of the first isolation portion on the array substrate being located within the orthographic projection of the base on the array substrate.

[0040] Optionally, the display panel further includes:

[0041] A pixel defining layer is disposed between the isolation structure and the array substrate. The pixel defining layer is provided with a plurality of pixel openings that are respectively connected to each of the isolation openings. Each light-emitting device is disposed corresponding to each of the pixel openings.

[0042] Optionally, the pixel defining layer includes a plurality of sub-layers, the plurality of sub-layers including a first sub-layer and a second sub-layer sequentially stacked along a direction away from the array substrate.

[0043] Optionally, each of the light-emitting devices includes a first electrode, a light-emitting structure, and a second electrode stacked together. The first electrode is disposed on the side of the light-emitting structure close to the array substrate. The pixel defining layer exposes the first electrode through the pixel opening. Each of the light-emitting structures covers the pixel opening sidewall of the pixel defining layer and the side of the pixel defining layer away from the array substrate. Each of the light-emitting structures is located in the pixel opening and in contact with the first electrode. The second electrode is electrically connected to the isolation structure.

[0044] The display panel further includes a first encapsulation layer, which includes a plurality of encapsulation portions. The encapsulation portions are located on the side of the second electrode away from the array substrate and extend through the sidewall of the isolation structure to the side of the isolation structure away from the array substrate.

[0045] The encapsulation portion includes a first segment and a second segment connected to each other. The first segment is located inside the isolation opening and disposed on the side of the light-emitting device away from the substrate. The second segment is located on the side of the isolation structure facing the isolation opening. The surface of the first segment away from the array substrate and the surface of the second segment away from the isolation structure are at least partially connected to each other to enclose and form a gap space.

[0046] According to a third aspect of the present invention, a method for driving a display device is also provided for driving the display device described in the second aspect;

[0047] The driving method for the display device includes:

[0048] In the first stage, the voltage output module responds to the signal input to its own control terminal and outputs a first voltage. The gamma voltage generation module generates at least two gamma voltages based on the first voltage. The data voltage generation module generates a data voltage based on the gamma voltage and transmits it to the pixel circuit through a data line.

[0049] In the second stage, the voltage output module shuts down in response to the signal input to its own control terminal.

[0050] Optionally, the voltage output module includes a first output unit and a second output unit, wherein the input terminal of the first output unit is connected to the first voltage, the output terminal of the first output unit is connected to the gamma voltage generating module, the output terminal of the second output unit is connected to the output terminal of the first output unit, and the input terminal of the second output unit is connected to the second voltage.

[0051] In the first stage, the voltage output module responds to the signal input to its own control terminal and conducts a first voltage output, including:

[0052] In the first stage, the first output unit turns on in response to the signal input to its own control terminal and outputs the first voltage, while the second output unit turns off in response to the signal input to its own control terminal.

[0053] In the second stage, the voltage output module shuts down in response to a signal input to its control terminal, including:

[0054] In the second stage, the first output unit shuts down in response to the signal received by its own control terminal, and the second output unit shuts down in response to the signal received by its own control terminal.

[0055] Optionally, the display panel includes an array of pixel circuits. The first stage is the time period within a display frame from scanning the first row of pixel circuits to scanning the last row of pixel circuits. The second stage is the time period within a display frame from scanning the last row of pixel circuits to starting scanning the first row of pixel circuits in the next display frame.

[0056] The gamma voltage generation circuit in this embodiment of the invention includes a voltage output module and a gamma voltage generation module. The voltage output module controls the output of a first voltage to the output terminal based on the potential of its own control terminal, so that the gamma voltage generation module generates a gamma voltage based on the first voltage. This allows the display device where the gamma voltage generation circuit is located to generate a data voltage based on the gamma voltage to drive the sub-pixel display. The voltage output module is also used to control the connection between its output terminal and input terminal to be disconnected based on the potential of its own control terminal, so that the first voltage cannot be output. This makes the output terminal of the voltage output module a high-impedance state, so that the first voltage is no longer output during the stage that does not affect the normal display of the display device, thereby reducing the power consumption of the display device.

[0057] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a schematic diagram of a gamma voltage generation circuit provided in an embodiment of the present invention;

[0060] Figure 2 This is a schematic diagram of a gamma voltage generation circuit provided in an embodiment of the present invention;

[0061] Figure 3 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention;

[0062] Figure 4 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention;

[0063] Figure 5 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention;

[0064] Figure 6 A driving timing diagram for a voltage output module provided in an embodiment of the present invention;

[0065] Figure 7 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention;

[0066] Figure 8 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention;

[0067] Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0068] Figure 10 This is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present invention;

[0069] Figure 11 A schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention;

[0070] Figure 12 This is a schematic diagram of the pixel circuit in a display panel provided by an embodiment of the present invention;

[0071] Figure 13 This is a schematic diagram of an isolation structure in a display panel provided by an embodiment of the present invention;

[0072] Figure 14 A schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention;

[0073] Figure 15 A schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention;

[0074] Figure 16 A schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention;

[0075] Figure 17 A schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention;

[0076] Figure 18 This is a schematic diagram of a light-emitting structure provided in an embodiment of the present invention;

[0077] Figure 19 A schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention;

[0078] Figure 20 A schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention;

[0079] Figure 21 A flowchart of a driving method for a display device provided in an embodiment of the present invention. Detailed Implementation

[0080] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0081] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0082] As described in the background section, existing display devices consume a significant amount of power. The inventors have discovered that this is because the first voltage of the driver chip accounts for a large proportion of the logic power consumption. The first voltage generates gamma voltages at different gray levels, and these gamma voltages serve as the output reference voltage for the driver chip's data output terminal (the port connected to the data line). Currently, the first voltage is constantly in output mode during the display panel's operation, resulting in high power consumption.

[0083] To address the aforementioned technical problems, embodiments of the present invention provide a gamma voltage generation circuit that can be applied in a display device to reduce power consumption by not outputting a first voltage at certain stages.

[0084] Figure 1This is a schematic diagram of a gamma voltage generation circuit provided in an embodiment of the present invention, with reference to... Figure 1 The circuit includes:

[0085] The voltage output module 10 has an input terminal connected to a first voltage GM1. The voltage output module 10 is used to control whether to output the first voltage GM1 according to the signal connected to the control terminal of the voltage output module 10.

[0086] The gamma voltage generation module 11 is connected to the output terminal Y of the voltage output module 10 and is used to generate at least two gamma voltages based on the first voltage GM1 when the output terminal Y of the voltage output module 10 outputs the first voltage GM1.

[0087] The voltage output module 10 can be a switching module. When it is turned on in response to a signal input to its control terminal, it transmits the first voltage GM1 to its output terminal Y. When it is turned off in response to a signal input to its control terminal, it disconnects the connection between the first voltage GM1 and its output terminal Y, and the first voltage GM1 can no longer be output to its output terminal Y. That is, the output terminal Y is in a high-impedance state and no longer outputs voltage. In an optional embodiment, the voltage output module 10 may include only one transistor. When the transistor is turned on, it outputs the first voltage GM1, and when the transistor is turned off, it stops outputting the first voltage GM1.

[0088] The gamma voltage generation module 11 is used to generate multiple gamma voltages based on the first voltage GM1 when the voltage output module 10 outputs a first voltage GM1 at its output terminal Y. Specifically, the gamma voltage generation module 11 includes multiple output terminals, each outputting a gamma voltage, and different output terminals output different gamma voltages. Figure 1 The example illustrates a gamma voltage generation module comprising n-1 output terminals, sequentially outputting a first gamma voltage GM2, a second gamma voltage GM3, a third gamma voltage GM4, ..., the (n-1)th gamma voltage GMn, where n is an integer greater than or equal to 2. When the voltage output module 1 ceases to output the first voltage GM1, the gamma voltage generation module 11 also ceases to output gamma voltages.

[0089] Since the voltage output module 10 can control whether to output the first voltage GM1, in certain stages that do not affect the normal display of the screen on the display panel in the display device, the voltage output module 10 may stop outputting the first voltage, such as controlling its own output terminal Y to be in a high impedance state and stop outputting the first voltage GM1, thereby reducing the power consumption of the first voltage GM1 and thus reducing the logic power consumption of the display device where the gamma voltage generation circuit is located.

[0090] The gamma voltage generation circuit in this embodiment of the invention includes a voltage output module and a gamma voltage generation module. The voltage output module controls the output of a first voltage to the output terminal based on the potential of its own control terminal, so that the gamma voltage generation module generates a gamma voltage based on the first voltage. This allows the display device where the gamma voltage generation circuit is located to generate a data voltage based on the gamma voltage to drive the sub-pixel display. The voltage output module is also used to control the connection between its output terminal and input terminal to be disconnected based on the potential of its own control terminal, so that the first voltage cannot be output. This makes the output terminal of the voltage output module a high-impedance state, so that the first voltage is no longer output during the stage that does not affect the normal display of the display device, that is, the gamma voltage is output, thereby reducing the power consumption of the display device.

[0091] Figure 2 This is a schematic diagram of a gamma voltage generation circuit provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 2 The voltage output module 10 includes a first output unit 101. The input terminal of the first output unit 101 is connected to a first voltage GM1, and the output terminal of the first output unit 101 is connected to the gamma voltage generation module 11. The first output unit 101 is used to turn on the signal connected to its own control terminal in the first stage to output the first voltage GM1, and is also used to turn off the signal connected to its own control terminal in the second stage to stop outputting the first voltage GM1.

[0092] The voltage output module 10 may include only one output unit, denoted as the first output unit 101. The first output unit may be a switching unit, which connects its input terminal and output terminal when turned on, and disconnects the connection between the input terminal and output terminal when turned off. The first output unit 101 may be a switching device such as a relay, etc., and there is no specific limitation on this.

[0093] Continue to refer to Figure 2Optionally, the first output unit 101 includes a transistor T0, which is connected between the input and output terminals of the first output unit 101. The gate of transistor T0 is connected to a control signal G0. The transistor is used to turn on in response to the control signal G0 in a first stage and to turn off in response to the control signal G0 in a second stage. The first output unit 101 may include only one transistor T0, which can be an NMOS transistor or a PMOS transistor. The NMOS transistor turns off when the gate is low and turns on when the gate is high, while the PMOS transistor turns off when the gate is high and turns on when the gate is low. The first output unit 101 includes only one transistor T0, resulting in a simple structure and low cost. In other embodiments, the first output unit 101 includes at least two transistors connected in series between the input and output terminals of the first output unit 101. Each transistor's gate is connected to its corresponding control signal. Each transistor is turned on in response to the control signal connected to its gate in a first stage. At least one transistor connected between the input and output terminals of the first output unit 101 is turned off in response to the control signal connected to its gate in a second stage. When the first output unit 101 includes two or more transistors, each transistor is connected in series between the input and output terminals of the first output unit 101. All transistors in the first output unit 101 can be of the same type, such as all NMOS transistors or all PMOS transistors. In this case, all transistors can share a single control signal at their gates, and all transistors are turned off in response to the connected control signal in the second stage. The first output unit 101 may include a portion of NMOS transistors and a portion of PMOS transistors. All NMOS transistors share a common control signal, and all PMOS transistors share a common control signal. The control signals connected to the NMOS transistors and the control signals connected to the PMOS transistors may be the same or different. There is no specific limitation on this. It is only necessary to ensure that in the first stage, all transistors turn on in response to the signal connected to their respective gates, and in the second stage, at least one transistor turns off in response to the signal connected to its gate.

[0094] Figure 3 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention. Based on the above embodiments, refer to... Figure 3 Optionally, the voltage output module 10 includes: a first output unit 101 and a second output unit 102;

[0095] The output terminal of the second output unit 102 is connected to the output terminal of the first output unit 101. The second output unit 102 is used to shut down in response to the signal input to its own control terminal in both the first and second stages.

[0096] The input terminal of the second output unit 102 is connected to a second voltage. In this embodiment, the input terminal of the second output unit 102 is grounded (GND), meaning the second voltage is ground potential. The second output unit 102 can be a switching unit. After responding to the signal of its own control terminal, it connects its own input terminal and its own output terminal, thereby outputting the second voltage. It is also used to disconnect the connection between its own input terminal and its own output terminal after responding to the signal of its own control terminal. In this embodiment, in the first stage, the first output unit 101 responds to the signal of its own control terminal and turns on, while the second output unit 102 responds to the signal of its own control terminal and turns off, thereby causing the first voltage GM1 to be transmitted to the output terminal Y of the voltage output module 10 through the turned-on first output unit 101. In the second stage, the first output unit 101 responds to the signal of its own control terminal and turns off, while the second output unit 102 responds to the signal of its own control terminal and turns off, thereby causing the output terminal Y to be in a high-impedance state and no longer outputting voltage. When the gamma voltage generation circuit is applied to a display device, the display device includes a display panel, which includes an array of pixel circuits. The pixel circuits are used to drive light-emitting devices to emit light. The pixel circuits arranged in an array form multiple rows and columns of pixel circuits. Optionally, the voltage output module is used to output a first voltage in response to a signal input to the control terminal of the voltage output module in the first stage, and to stop outputting the first voltage in response to a signal input to the control terminal of the voltage output module in the second stage. The first stage is the period from scanning the first row of pixel circuits to the last row of pixel circuits within a display frame, i.e., the effective display stage. The second stage is the period from scanning the last row of pixel circuits to starting scanning the first row of pixel circuits in the next display frame, i.e., the blank stage. In the effective display stage, the voltage output module 10 normally outputs the first voltage GM1 so that the display panel can display normally. In the blank stage, the voltage output module 10 is in a high-impedance state and no longer outputs the first voltage GM1, reducing power consumption without affecting the normal display of the screen.

[0097] Figure 4 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention, referred to... Figure 3 and Figure 4 Optionally, the first output unit 101 includes: a first switch unit 1011 and a second switch unit 1012;

[0098] The first terminal of the first switching unit 1011 is connected to the first voltage GM1. The second terminal of the first switching unit 1011 is connected to the first terminal of the second switching unit 1012. The control terminal of the first switching unit 1011 is connected to the first control signal G1, and the control terminal of the second switching unit 1012 is connected to the second control signal G2. The first switching unit 1011 is used to turn on in response to the first control signal G1 in the first stage, and the second switching unit 1012 is used to turn on in response to the second control signal G2 in the first stage. The first switching unit 1011 is also used to turn off in response to the first control signal G1 in the second stage, and / or the second switching unit 1012 is also used to turn off in response to the second control signal G2 in the second stage.

[0099] The first switching unit 1011 and the second switching unit 1022 are connected in series between the first voltage GM1 and the output terminal Y of the voltage output module 10. In the first stage, both the first switching unit 1011 and the second switching unit 1012 are turned on in response to the signal input to their respective control terminals to transmit the first voltage GM1 to the output terminal Y of the voltage output module 10. In the second stage, if at least one of the first switching unit 1011 and the second switching unit 1012 is turned off, the transmission path between the first voltage GM1 and the output terminal Y of the voltage output module 10 is broken, so that the output terminal Y of the voltage output module 10 no longer outputs the first voltage GM1. The first control signal G1 and the second control signal G2 can be the same or different; this embodiment does not specifically limit this.

[0100] The second output unit 102 includes a third switch unit 1021 and a fourth switch unit 1022. The first end of the third switch unit 1021 is connected to the second end of the second switch unit 1012, and the second end of the second switch unit 1012 is used as the output end of the first output unit 101, and then as the output end Y of the voltage output module 10. The second end of the third switch unit 1021 is connected to the first end of the fourth switch unit 1022. The control end of the third switch unit 1021 is connected to a third control signal G3, and the second end of the fourth switch unit 1022 is connected to a second voltage. The control end of the fourth switch unit 1022 is connected to a fourth control signal G4. The third switch unit 1021 is used to turn off in response to the third control signal G3 in the first stage, and / or the fourth switch unit 1022 is used to turn off in response to the fourth control signal G4 in the first stage. The third switch unit 1021 is used to turn off in response to the third control signal G3 in the second stage, and / or the fourth switch unit 1022 is used to turn off in response to the fourth control signal G4 in the second stage.

[0101] The third switching unit 1021 and the fourth switching unit 1022 are connected in series between the output terminal Y of the voltage output module 10 and the second voltage. In the first stage, at least one of the third switching unit 1021 and the fourth switching unit 1022 is turned off to prevent the second voltage from being transmitted to the output terminal Y of the voltage output module 10 and affecting the potential of the first voltage GM1 output from the output terminal Y of the voltage output module 10. In the second stage, at least one of the third switching unit 1021 and the fourth switching unit 1022 is turned off so that the output terminal Y of the voltage output module 10 does not output the second voltage. Combined with the fact that at least one of the first switching unit 1021 and the second switching unit 1022 is turned off, the output terminal Y of the voltage output module 10 no longer outputs voltage, and the output terminal Y of the voltage output module 10 is in a high-impedance state in the second stage.

[0102] Optionally, the first switching unit 1011 is turned off in response to the first control signal G1 in the second stage, the second switching unit 1012 is turned off in response to the second control signal G2 in the second stage, the third switching unit 1021 is turned off in response to the third control signal G3 in the second stage, and the fourth switching unit 1022 is turned off in response to the fourth control signal G4 in the second stage. In the second stage, both the first switching unit 1011 and the second switching unit 1012 are turned off, reducing the leakage current between the first voltage GM1 and the output terminal Y of the voltage output module 10. The third switching unit 1021 and the fourth switching unit 1022 are both turned off, reducing the leakage current between the second voltage and the output terminal Y of the voltage output module 10, further reducing power consumption.

[0103] Continue to refer to Figure 4 Optionally, the first switching unit 1011 includes a first transistor T1, the second switching unit 1012 includes a second transistor T2, and the third switching unit 1021 includes a third transistor T3;

[0104] The first terminal of the first transistor T1 is connected to the first voltage GM1, the gate of the first transistor T1 is connected to the first control signal G1, the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2, the gate of the second transistor T2 is connected to the second control signal G2, the second terminal of the second transistor T2 is connected to the first terminal of the third transistor T3, and the gate of the third transistor T3 is connected to the third control signal G3.

[0105] The fourth switching unit 1022 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3. The second terminal of the fourth transistor T4 is connected to a second voltage. The gate of the fourth transistor T4 is connected to a fourth control signal G4.

[0106] Each switching unit includes only one transistor, resulting in a simple structure that is easy to implement. The first terminal of each transistor can be the source and the second terminal the drain, or vice versa. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be either NMOS or PMOS transistors; no specific limitation is made. Taking the first transistor T1 as an example, when the first transistor T1 is an NMOS transistor, it turns on in response to a high potential of the first control signal G1 and turns off in response to a low potential of the first control signal G1. When the first transistor T1 is a PMOS transistor, it turns on in response to a low potential of the first control signal G1 and turns off in response to a high potential of the first control signal G1. In one optional embodiment, a first transistor T1 is turned on in response to a first control signal G1 in the first stage, a second transistor T2 is turned on in response to a second control signal G2 in the first stage, a third transistor T3 is turned off in response to a third control signal G3 in the first stage, and a fourth transistor T4 is turned off in response to a fourth control signal G4 in the first stage. In the second stage, the first transistor T1 is turned off in response to the first control signal G1, the second transistor T2 is turned off in response to the second control signal G2 in the second stage, the third transistor T3 is turned off in response to the third control signal G3 in the second stage, and the fourth transistor T4 is turned off in response to the fourth control signal G4 in the second stage. The third transistor T3 and the fourth transistor T4 are both turned off in both the first and second stages to reduce the leakage current between the output terminal Y of the voltage output module and the second voltage.

[0107] Continue to refer to Figure 4 Optionally, the first control signal G1 is multiplexed into the fourth control signal G4, the second control signal G2 is multiplexed into the third control signal G3, the first transistor T1 and the second transistor T2 have the same channel type, the third transistor T3 and the fourth transistor T4 have different channel types, and the first transistor T1 and the third transistor T3 have different channel types.

[0108] In this embodiment, the first switch T1, the second switch T2, and the fourth switch T4 are all PMOS transistors, and the third switch T3 is an NMOS transistor. In the first stage, the first transistor T1 turns on in response to a low potential of the first control signal G1, the second transistor T2 turns on in response to a low potential of the second control signal G2, the third transistor T3 turns off in response to a low potential of the third control signal G3, and the fourth transistor T4 turns on in response to a low potential of the fourth control signal G4. Because the third transistor T3 is off, the second voltage cannot be transmitted to the output terminal Y of the voltage output module 10. The first voltage GM1 is transmitted to the output terminal Y of the voltage output module 10 through the turned-on first transistor T1 and the second transistor T2, so that a gamma voltage can be generated based on the first voltage, and then a data voltage can be generated based on the gamma voltage to drive the light-emitting device in the sub-pixel for display. In the second stage, the first transistor T1 turns off in response to the high potential of the first control signal G1, and the fourth transistor T4 turns off in response to the high potential of the fourth control signal G4. At this time, regardless of whether the second control signal G2 or the third control signal G3 is at a high potential or a low potential, neither the first voltage GM1 nor the second voltage can be transmitted to the output terminal Y of the voltage output module 10, and the output terminal Y of the voltage output module 10 is in a high-impedance state. In other embodiments, the first transistor T1, the second transistor T2, and the fourth transistor T4 can all be NMOS transistors, and the third transistor T3 can be a PMOS transistor. The working process is similar to that described above and will not be repeated here. The first control signal G1 is multiplexed into the fourth control signal G4, and the second control signal G2 is multiplexed into the third control signal G3, which can save the number of signal sources and simplify the circuit structure.

[0109] Figure 5 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention. Figure 6 This invention provides a driving timing diagram for a voltage output module according to an embodiment of the present invention. Figure 6 Applicable to drivers Figure 5 The voltage output module in the middle, Figure 5 The first switch unit 1011, the second switch unit 1012, and the third switch unit 1022 have the same structure, and will not be described again here. Figure 5 In the middle, the fourth switching unit 1022 includes a fourth transistor T4 and an inverter 10221. The first terminal of the fourth transistor T4 is connected to the second terminal of the third switching transistor T3. The second terminal of the fourth transistor T4 is connected to a second voltage. The gate of the fourth transistor T4 is connected to the output terminal of the inverter 10221. The input terminal of the inverter 10221 is connected to the fourth control signal G4.

[0110] In this embodiment, the first control signal G1 is multiplexed into the fourth control signal G4, and the second control signal G2 is multiplexed into the third control signal G3. The first transistor T1 and the second transistor T2 have the same channel type, the third transistor T3 and the fourth transistor T4 have the same channel type, and the first transistor T1 and the third transistor T3 have different channel types. This embodiment uses the example where the first transistor T1 and the second transistor T2 are both PMOS transistors, and the third transistor T3 and the fourth transistor T4 are both NMOS transistors. In the first stage t1, the first transistor T1 turns on in response to the low potential of the first control signal G1, the second transistor T2 turns on in response to the low potential of the second control signal G2, and the third transistor T3 turns off in response to the low potential of the third control signal G3. The fourth control signal G4, which is low in the first stage, becomes high after passing through the inverter 10221 and is transmitted to the gate of the fourth transistor T4. The fourth transistor T4 turns on in response to the high potential of its own gate. Because the third transistor T3 is off, the second voltage cannot be transmitted to the output terminal Y of the voltage output module 10. The first voltage GM1 is transmitted to the output terminal Y of the voltage output module 10 through the turned-on first transistor T1 and the second transistor T2, so that a gamma voltage can be generated according to the first voltage, and then a data voltage can be generated according to the gamma voltage to drive the light-emitting device in the sub-pixel to display. In the second stage t2, the first transistor T1 turns off in response to the high potential of the first control signal G1, and the high potential of the fourth control signal G4 is inverted by the inverter 10221 and becomes a low potential, which is then transmitted to the gate of the fourth transistor T4. The fourth transistor T4 turns off in response to the low potential of its own gate. At this time, regardless of whether the second control signal G2 or the third control signal G3 is high or low, neither the first voltage GM1 nor the second voltage can be transmitted to the output terminal Y of the voltage output module 10. The output terminal Y of the voltage output module 10 is in a high-impedance state. In this embodiment, taking the second control signal G2 as a low potential in the second stage as an example, the corresponding second transistor T2 turns on in response to the low potential of the second control signal G2, and the third transistor T3 turns off in response to the low potential of the third control signal G3. In other embodiments, the first transistor T1 and the second transistor T2 can both be PMOS transistors, and the third transistor T3 and the fourth transistor T4 can all be NMOS transistors. The working process is similar to the above, and will not be repeated here. Figure 4 Compared to the structure shown, the structure in this embodiment not only saves the number of signal sources, but also uses two NMOS transistors connected in series between the first voltage GM1 and the output terminal Y of the voltage output module 10, or between the output terminal Y of the voltage output module 10 and the second voltage. This reduces the leakage current and makes the high-impedance state of the output terminal Y of the voltage output module 10 more stable.

[0111] Whether Figure 4 still Figure 5The medium-voltage output modules 10 all adopt a tri-state gate structure. A tri-state gate adds an enable terminal (the ports connected to the first control signal G1 and the fourth control signal G4 are collectively called the enable terminal) to the basic logic gate (such as an AND gate or an OR gate). When the enable terminal is invalid, the output stage transistors are simultaneously turned off, forming a high-impedance state (equivalent to being disconnected). At this time, the output terminal Y has no effect on other parts of the circuit. This design avoids the leakage current or signal conflict problems that may exist when traditional logic gates are turned off. In the high-impedance state, the output impedance of the tri-state gate is extremely high (typically reaching the megaohm level), consuming almost no static power, and having a minimal load effect on external signals, thus improving the system's anti-interference capability and energy efficiency ratio.

[0112] In addition to the above Figure 2 , Figure 4 , Figure 5 In addition to the structure of the voltage output module shown, this embodiment of the invention also provides a structure for a voltage output module. Figure 7 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention, referred to... Figure 7 The first output unit 101 includes a fifth transistor T5, and the second output unit 102 includes a sixth transistor T6;

[0113] The first terminal of the fifth transistor T5 is connected to the first voltage GM1, the second terminal of the fifth transistor T5 is connected to the first terminal of the sixth transistor T6, the gate of the fifth transistor T5 is connected to the fifth control signal G5, the second terminal of the sixth transistor G6 is connected to the second voltage, and the gate of the sixth transistor T6 is connected to the sixth control signal G6.

[0114] Compared to Figure 4 or Figure 5 The voltage output module shown includes four transistors. In this embodiment, the voltage output module includes only two transistors, resulting in a simpler structure. The first terminal of both the fifth transistor T5 and the sixth transistor T6 can be the source, and the second terminal can be the drain; alternatively, the first terminal can be the drain, and the second terminal can be the source. The fifth transistor T5 can be an NMOS transistor or a PMOS transistor, and the sixth transistor T6 can be an NMOS transistor or a PMOS transistor; no specific limitation is made. Figure 7Taking PMOS transistors as an example, both transistor T5 and transistor T6 are used. In the first stage, transistor T5 turns on in response to the low potential of the fifth control signal G5 to transmit the first voltage GM1 to the output terminal Y of the voltage output module 10. Transistor T6 turns off in response to the high potential of the sixth control signal G6 to prevent the second voltage from affecting the potential of the first voltage at the output terminal Y. In the second stage, transistor T5 turns off in response to the high potential of the fifth control signal G5, and transistor T6 turns off in response to the high potential of the sixth control signal G6. The output terminal Y of the voltage output module 10 is in a high-impedance state, with no voltage output, thereby reducing the power consumption of the first voltage. Although Figure 7 medium structure compared to Figure 4 or Figure 5 It has fewer components and a simpler structure, but the leakage current of a single transistor may be relatively large. Therefore, the specific structure of the voltage output module can be selected according to the requirements.

[0115] Figure 8 This is a schematic diagram of another gamma voltage generation circuit provided in an embodiment of the present invention, referred to... Figure 8 The gamma voltage generation module 11 includes multiple resistors that are connected in series between the output terminal Y and the fixed potential terminal of the voltage output module 10. The fixed potential terminal is connected to a third voltage VI. Both ends of each resistor are used to output gamma voltage, and the gamma voltage output from the common terminal of two adjacent resistors is the same.

[0116] The third voltage VI is different from the first voltage GM1;

[0117] The first voltage GM1 is the gamma voltage corresponding to the maximum gray level of the display device where the gamma voltage generation circuit is located, and the third voltage VI is the gamma voltage corresponding to the minimum gray level of the display device where the gamma voltage generation circuit is located. In other words, the first voltage is the gamma voltage corresponding to the bright state voltage of the display device where the gamma voltage generation circuit is located, and the third voltage is the gamma voltage corresponding to the black state voltage of the display device where the gamma voltage generation circuit is located.

[0118] The last resistor in the series-connected resistors of the gamma voltage generation module 11 is connected to the third voltage VI. A voltage divider circuit is formed by the multiple resistors to generate multiple gamma voltages based on the first voltage GM1 and the third voltage VI. The first voltage GM1 can also be used as a gamma voltage after being output by the voltage output module 10, i.e., the first gamma voltage GM2 in this embodiment. The (n-1)th gamma voltage GMn can be the third voltage VI.

[0119] This invention also provides a display device, including a display panel and a driver chip. The driver chip includes a data voltage generation module and a gamma voltage generation circuit in any of the above embodiments. The data voltage generation module is connected to the gamma voltage generation module and is used to generate a corresponding data voltage based on the gamma voltage.

[0120] After the gamma voltage generation circuit outputs a gamma voltage, the data voltage generation module converts the gamma voltage into a data voltage for transmission to the pixel circuit via a data line. This data voltage generation module can be an analog-to-digital converter (DAC). The beneficial effects of the display device are the same as those of the gamma voltage generation circuit, and will not be elaborated further here.

[0121] Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, with reference to... Figure 9 The display panel 100 can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. The display panel 100 includes a display area AA with display function and a non-display area NA.

[0122] The display area AA of the display panel 100 can be rectangular, square, circular, oval, or other shapes.

[0123] The display area AA includes a plurality of pixels PX arranged in the X and Y directions. Each pixel PX includes a plurality of sub-pixels that display different colors. In some embodiments, a pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is a blue sub-pixel, the second sub-pixel SPX2 is a green sub-pixel SPX2, and the third sub-pixel SPX3 is a red sub-pixel SPX3. In some embodiments, in addition to sub-pixels SPX1, SPX2, and SPX3, a pixel PX also includes sub-pixels SPX that emit white or other colors of light.

[0124] A sub-pixel (SPX) includes a pixel circuit and a light-emitting device driven by the pixel circuit to emit light of the corresponding color. The first sub-pixel (SPX1) includes a first light-emitting device, the second sub-pixel (SPX2) includes a second light-emitting device, and the third sub-pixel (SPX3) includes a third light-emitting device. One pixel circuit drives at least one light-emitting device to emit light. For example, the display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is a display area set according to a corresponding sensor and has light-transmitting properties, while the normal display area is a display area not set according to a corresponding sensor. In the normal display area, one pixel circuit drives one light-emitting device to emit light, and in the light-transmitting display area, one pixel circuit drives one or more light-emitting devices to emit light.

[0125] Figure 10 This is a schematic cross-sectional view of a display panel provided in an embodiment of the present invention. Figure 10 It shows Figure 9 A schematic diagram of a partial cross-sectional structure of the film layer in the BB direction of a local area of ​​the display panel, for reference. Figure 10 The display panel includes: sub-pixels, and each sub-pixel includes a light-emitting device 23;

[0126] The display panel also includes:

[0127] Array substrate 20;

[0128] An isolation structure 21 is located on one side of the array substrate 20. The isolation structure 21 encloses and forms a plurality of isolation openings 21a. The light-emitting device 23 is at least partially located within the isolation openings 21a.

[0129] Figure 11 This is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention, with reference to... Figure 10 and Figure 11 The array substrate 20 includes a pixel circuit layer and a planarization layer 19. The pixel circuit layer includes pixel circuits for driving the light-emitting device 23 to emit light. Figure 11 The diagram shows a transistor 18 in a pixel circuit. A via is provided in the planarization layer 19, through which the first electrode 231 is electrically connected to the preset transistor 18 in the pixel circuit layer. Furthermore, the pixel circuit layer includes at least one insulating layer, which may include at least one of inorganic and organic layers. Additionally, the array substrate 20 includes scan lines providing the scan signal Scan and data lines providing the data signal Data to the pixel circuit. The preset transistor is a transistor in the pixel circuit layer connected to the first electrode of the light-emitting device.

[0130] Figure 12 This is a schematic diagram of the pixel circuit in a display panel according to an embodiment of the present invention, with reference to... Figure 12The pixel circuit includes a driving transistor M1 and a data transistor M2. The source of the data transistor M2 is connected to the data line that provides the data signal Data, the gate of the data transistor M2 is connected to the scan line that provides the scan signal Scan, and the drain of the data transistor M2 is connected to the gate of the driving transistor M1. The two ends of the storage capacitor C1 are respectively connected to the gate and the source of the driving transistor M1, and the drain of the driving transistor M1 is connected to the light-emitting device 23. Figure 12 This is one implementation of a pixel circuit; the pixel circuit described in this application is not limited to... Figure 12 The 2T1C pixel circuit shown can also be other pixel circuits, such as 7T1C, 8T1C pixel circuits, etc.

[0131] Figure 13 This is a schematic diagram of an isolation structure in a display panel provided by an embodiment of the present invention, with reference to... Figure 10 and Figure 13 An isolation structure 21 is located on one side of the array substrate 20 and encloses multiple isolation openings 21a, including multiple first isolation openings 21a1, multiple second isolation openings 21a2, and multiple third isolation openings 21a3. Multiple light-emitting devices 23 are located on one side of the array substrate 20 and include multiple first light-emitting devices 23a, multiple second light-emitting devices 23b, and multiple third light-emitting devices 23c. First light-emitting devices 23a are disposed corresponding to first isolation openings 21a1, second light-emitting devices 23b are disposed corresponding to second isolation openings 21a2, and third light-emitting devices 23c are disposed corresponding to third isolation openings 21a3. In one embodiment, one light-emitting device 23 is disposed corresponding to one isolation opening 21a. For example, one-to-one correspondence between first light-emitting devices 23a and first isolation openings 21a1, one-to-one correspondence between second light-emitting devices 23b and second isolation openings 21a2, and one-to-one correspondence between third light-emitting devices 23c and third isolation openings 21a3. At least a portion of the first light-emitting device 23a is disposed within a corresponding first isolation opening 21a1, at least a portion of the second light-emitting device 23b is disposed within a corresponding second isolation opening 21a2, and at least a portion of the third light-emitting device 23c is disposed within a corresponding third isolation opening 21a3. In another embodiment, multiple light-emitting devices 23 are correspondingly disposed with one isolation opening 21a; for example, multiple light-emitting devices with the same emission color are corresponding to one isolation opening 21a.

[0132] In one example, the isolation structure 21 includes a first isolation portion 212 and a second isolation portion 211 sequentially stacked along a direction away from the array substrate 20 (i.e., the Z direction). The orthographic projection of the first isolation portion 212 on the array substrate 20 lies within the orthographic projection of the second isolation portion 211 on the array substrate 20, and the width of the second isolation portion 211 is greater than the width of the first isolation portion 212. Therefore, the two ends of the second isolation portion 211 protrude compared to the sides of the first isolation portion 212; this shape of the isolation structure 21 is also referred to as a pendant shape. The first isolation portion 212 and the second isolation portion 211 are made of different materials, and the etching rate of the second isolation portion 211 is lower than that of the first isolation portion 212. The material of the first isolation portion 212 includes a conductive material, specifically including at least one of aluminum (Al), aluminum alloys, and aluminum alloys including at least one of aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The second isolation portion 211 can be a single-layer structure or a multi-layer structure. If the second isolation portion 211 is a single-layer structure, its material can include at least one of titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. If the second isolation portion 211 is a multi-layer structure, one layer of the second isolation portion 211 is made of at least one of titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy, and the other layer of the second isolation portion 211 can be made of a conductive oxide or an inorganic insulating material. The conductive oxide may be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0133] Figure 14 This is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention. In some embodiments, reference is made to... Figure 14 The isolation structure 21 may further include a base 213 located on the side of the first isolation portion 212 near the array substrate 20. The base 213 protrudes relative to the first isolation portion 212 in the direction toward the isolation opening 21a, and the orthographic projection of the first isolation portion 212 on the array substrate 20 lies within the orthographic projection of the base 213 on the array substrate 20. The material of the base 213 may include at least one of molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb).

[0134] Figure 15 This is a schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention. Figure 15 and Figure 14 The difference is that, Figure 15 The second isolation section 211 has a multi-layer structure, including a third sub-layer and a fourth sub-layer. The fourth sub-layer is located on the side of the third sub-layer away from the first isolation section 212. The material of the fourth sub-layer is indium tin oxide (ITO). Figure 14 The second isolation section 211 is a single-layer structure.

[0135] refer to Figure 10 In one embodiment, the display panel 100 may further include a pixel defining layer 17 disposed between the isolation structure 21 and the array substrate 20. The isolation structure 21 is disposed on the pixel defining layer 17. The pixel defining layer 17 is provided with a plurality of pixel openings respectively communicating with each isolation opening 21a, and each light-emitting device 23 is disposed corresponding to each pixel opening. Specifically, the pixel defining layer 17 is provided with a first pixel opening communicating with a first isolation opening 21a1, a second pixel opening communicating with a second isolation opening 21a2, and a third pixel opening communicating with a third isolation opening 21a3. The areas of the orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening on the array substrate 20 may be the same or different. The shapes of the orthographic projections of the pixel openings and the corresponding isolation openings 21a on the array substrate 20 may be the same or different. Generally speaking, the area of ​​the orthographic projection of the isolation opening 21a on the array substrate 20 is larger than the area of ​​the orthographic projection of the pixel opening communicating with the isolation opening 21a on the array substrate 20. The orthographic projection of the pixel opening of the light-emitting device 23 onto the array substrate 20 overlaps with the orthographic projection of the isolation opening 21a onto the array substrate 20. The pixel defining layer 17 is made of an inorganic material, such as an inorganic insulating material formed by using at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON).

[0136] In one embodiment, the pixel defining layer 17 includes multiple sub-layers. Figure 16 This is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention, with reference to... Figure 16 Multiple sub-layers include a first sub-layer 171 and a second sub-layer 172 stacked sequentially along a direction away from the array substrate 20, meaning that the pixel limiting layer 17 can adopt a double-layer design.

[0137] For example, the first sublayer 171 exhibits better film-forming properties than the second sublayer 172. That is, under the same thickness conditions, the first sublayer 171 can better cover the stepped structure formed by the first electrode compared to the second sublayer, without generating cracks. Conversely, to achieve the same stepped coverage effect, the thickness of the first sublayer 171 needs to be thinner than that of the second sublayer, meaning the thickness requirement for the first sublayer 171 is relatively low, which is beneficial for product thinning. Furthermore, better film-forming properties are reflected in the better coverage of the formed film, making it denser and more effective at isolating moisture.

[0138] For example, the second sublayer 172 has better etching resistance than the first sublayer 171. Since the side of the pixel defining layer 17 facing away from the array substrate 20 will be etched during the display panel manufacturing process, by selecting a material with stronger etching resistance as the second sublayer 172, the etching resistance of the pixel defining layer 17 can be improved, and the reliability of the display panel can be further improved.

[0139] For example, the first sublayer 171 and the second sublayer 172 are made of different materials. For instance, the first sublayer 171 is made of silicon nitride, and the second sublayer 172 is made of silicon oxide.

[0140] For example, the thickness of the first sublayer 171 is greater than or equal to 1000 micrometers and less than or equal to 5000 micrometers. For example, the thickness of the first sublayer 171 is 1000 micrometers, 2000 micrometers, 3000 micrometers, 4000 micrometers, 5000 micrometers, etc.

[0141] For example, the thickness of the second sublayer 172 is greater than or equal to 500 micrometers and less than or equal to 3000 micrometers. For instance, the thickness of the second sublayer 172 is 500 micrometers, 1000 micrometers, 2000 micrometers, 3000 micrometers, etc.

[0142] In another embodiment, the isolation structure 21 is disposed within the groove of the pixel limiting layer 17. Alternatively, the pixel limiting layer 17 may not be provided in the display panel 100, and the isolation structure 21 may be disposed on one side of the array substrate 20, with the isolation structure 21 in contact with one side of the array substrate 20.

[0143] The first light-emitting device 23a, the second light-emitting device 23b, and the third light-emitting device 23c emit light of different colors. Each of the three devices includes a first electrode 231, a light-emitting structure 232, and a second electrode 233 stacked together. The first electrode 231 is disposed on the array substrate 20, and a pixel defining layer 17 covers the end of the first electrode 231. A pixel opening is provided on the pixel defining layer 17, through which the first electrode 231 is exposed. The light-emitting structure 232 of the first light-emitting device 23a, the second light-emitting device 23b, and the third light-emitting device 23c covers the sidewall of the pixel opening of the pixel defining layer 17 and the side of the pixel defining layer 17 facing away from the array substrate 20. Each light-emitting structure 232 is located within the pixel opening and is in contact with the first electrode 231, and the second electrode 233 is electrically connected to the isolation structure 21.

[0144] The second electrodes 233 of the first light-emitting device 23a, the second light-emitting device 23b, and the third light-emitting device 23c respectively cover the corresponding light-emitting structure 232. The second electrodes 233 are electrically connected to the isolation structure 21. For example, the second electrodes 233 are connected to the first isolation portion 212 of the isolation structure 21, and / or the second electrodes 233 are connected to the base portion 213 of the isolation structure 21. Specifically, when the isolation structure 21 includes a three-layer structure of the first isolation portion 212, the second isolation portion 211, and the base portion 213, the second electrodes 233 can extend to the side surface of the base portion 213 facing away from the array substrate 20 to connect with the base portion 213. In this case, the second electrodes 233 may or may not be connected to the first isolation portion 212. Figures 14-16 The example in which the second electrode 233 is connected to the first isolation part 212 is taken. Figure 17 This is a schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present invention. Figure 17 In this configuration, the second electrode 233 is not connected to the first isolation section 212.

[0145] The first electrode 231 can be an anode, and the second electrode 233 can be a cathode. The first electrode 231 of each light-emitting device 23 can be connected to the pixel circuit through a via, so that the pixel circuit drives the light-emitting device 23 to emit light.

[0146] The first electrode 231 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 233 is formed, for example, from a metallic material such as an alloy of magnesium and silver (MgAg).

[0147] Figure 18 This is a schematic diagram of a light-emitting structure provided in an embodiment of the present invention. The light-emitting structure 232 of at least one of the first light-emitting device 23a, the second light-emitting device 23b, and the third light-emitting device 23c includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the array substrate 20 (i.e., the Z direction). The light-emitting structure 232 may include one light-emitting material layer EML, or a stacked light-emitting structure including multiple light-emitting material layers EML.

[0148] In order for the light-emitting structure 232 to emit light, a pixel voltage is provided to the first electrode 231 and a common voltage is provided to the second electrode 233, respectively, forming a potential difference between the first electrode 231 and the second electrode 233, so that the light-emitting structure 232 disposed between the first electrode 231 and the second electrode 233 emits light. In one embodiment, if a potential difference is formed between the first electrode 231 and the second electrode 233 of the first light-emitting device 23a, the light-emitting material layer EML of the light-emitting structure 232 emits blue light; if a potential difference is formed between the first electrode 231 and the second electrode 233 of the second light-emitting device 23b, the light-emitting material layer EML of the light-emitting structure 232 emits green light; and if a potential difference is formed between the first electrode 231 and the second electrode 233 of the third light-emitting device 23c, the light-emitting material layer EML of the light-emitting structure 232 emits red light.

[0149] In this configuration, the pixel voltage of the first electrode 231 is provided by the pixel circuit, and the common voltage of the second electrode 233 is provided by the isolation structure 21. Specifically, the second electrode 233 is electrically connected to the isolation structure 21, and the common voltage is supplied to the second electrode 233 by providing the isolation structure 21. That is, the isolation structure 21 has the function of supplying a common voltage to the second electrode 233.

[0150] Figure 19 This is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention, with reference to... Figure 10 and Figure 19 The display panel 100 further includes a first encapsulation layer, which includes a plurality of encapsulation portions 14. The encapsulation portions 14 are located on the side of the second electrode 233 away from the array substrate 20, and extend through the sidewall of the isolation structure 21 to the side of the isolation structure 21 away from the array substrate 20. The plurality of encapsulation portions 14 include a plurality of first encapsulation portions 14a corresponding to a plurality of first light-emitting devices 23a, a plurality of second encapsulation portions 14b corresponding to a plurality of second light-emitting devices 23b, and a plurality of third encapsulation portions 24c corresponding to a plurality of third light-emitting devices 23c. The first encapsulation portions 14a are disposed on the side of the corresponding first light-emitting device 23a away from the array substrate 11, the second encapsulation portions 14b are disposed on the side of the corresponding second light-emitting device 23b away from the array substrate 11, and the third encapsulation portions 14c are disposed on the side of the corresponding third light-emitting device 23c away from the array substrate 20.

[0151] For example, the encapsulation portion 14 includes a first segment 51 and a second segment 52 that are interconnected. The first segment 51 is located within the isolation opening 21a and disposed on the side of the light-emitting device 23 facing away from the array substrate 20. The second segment 52 is located on the side of the isolation structure 21 facing the isolation opening 21a. The surface of the first segment 51 facing away from the array substrate 20 and the surface of the second segment 52 facing away from the isolation structure 21 are at least partially interconnected to enclose and form a gap space 500.

[0152] The first segment 51 includes a first sub-segment 511 and a second sub-segment 512 connected in sequence, and the second segment 52 includes a third sub-segment 521 and a fourth sub-segment 522 connected in sequence, with the fourth sub-segment 522 connected to the second sub-segment 512. That is, in the encapsulation part 14, the first sub-segment 511, the second sub-segment 512, the fourth sub-segment 522 and the third sub-segment 521 are connected in sequence.

[0153] For example, such as Figure 10 As shown, the surface of the first segment 51 facing away from the array substrate 20 and the surface of the second segment 52 facing away from the isolation structure 21 may not be connected.

[0154] Figure 20 This is a schematic cross-sectional view of another display panel provided in an embodiment of the present invention, as shown below. Figure 20 As shown, the display panel 100 further includes a second encapsulation layer 15 and a third encapsulation layer 16. The second encapsulation layer 15 covers the isolation structure 21 and the encapsulation portion 14, and the third encapsulation layer 16 covers the second encapsulation layer 15. Both the first encapsulation layer and the third encapsulation layer 16 are inorganic materials, and the materials of the first encapsulation layer and the third encapsulation layer 16 include at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The second encapsulation layer 15 is an organic insulating material, such as epoxy resin, acrylic resin, or other resin materials. The second encapsulation layer 15 and the third encapsulation layer 16 are continuously disposed at least over the entire display area AA, with a portion of them also disposed in the bezel area NA.

[0155] The display panel 100 may also include at least one film layer such as a touch layer, a polarizer, a color filter substrate, and a protective cover. This film layer may also be bonded to the display panel via an adhesive layer such as OCA (Optical Clear Adhesive).

[0156] This invention also provides a driving method for a display device. Figure 21 A flowchart of a driving method for a display device provided in an embodiment of the present invention is shown below. Figure 1 and Figure 21 The method includes:

[0157] S110: In the first stage, the voltage output module responds to the signal input to its own control terminal and outputs the first voltage. The gamma voltage generation module generates at least two gamma voltages based on the first voltage, and the data voltage generation module generates a data voltage based on the gamma voltage and transmits it to the pixel circuit through the data line.

[0158] By controlling the potential of the control terminal of the voltage output module 10, the voltage output module 10 is turned on in the first stage. The first voltage GM1 is transmitted to the output terminal Y of the voltage output module 10 through the turned-on voltage output module 10, which facilitates the subsequent gamma voltage generation module to generate at least two gamma voltages based on the first voltage and the data voltage generation module to generate data voltage based on the gamma voltage. The data voltage is transmitted to the pixel circuit through the data line connected to the pixel circuit to drive the light-emitting device for display.

[0159] S120: In the second stage, the voltage output module responds to the signal input to its own control terminal and shuts down, stopping the output of the first voltage.

[0160] By controlling the potential of the control terminal of the voltage output module 10, the voltage output module 10 is turned off in the second stage, thereby making the voltage output module 10 a high-impedance state and no longer outputting the first voltage GM1. Consequently, the data voltage generation module also stops generating data voltage to the pixel circuit.

[0161] In this embodiment of the invention, in the first stage, the voltage output module is turned on to output a first voltage, so that the gamma voltage generation module generates a gamma voltage based on the first voltage, thereby enabling the data voltage generation module to generate a data voltage based on the gamma voltage to drive the light-emitting device in the sub-pixel to display. In the second stage, the voltage output module is turned off to prevent the first voltage from being output, so that the output terminal of the voltage output module is in a high-impedance state, so that the first voltage is no longer output in the stage that does not affect the normal display of the display device, thereby reducing the power consumption of the display device.

[0162] S110 can be further refined as follows: In the first stage, the first output unit responds to the signal input to its own control terminal to turn on and output the first voltage, the second output unit responds to the signal input to its own control terminal to turn off, the gamma voltage generation module generates at least two gamma voltages based on the first voltage, the data voltage generation module generates data voltage based on the gamma voltage and transmits it to the pixel circuit through the data line.

[0163] S120 can be further refined as follows: In the second stage, the first output unit shuts down in response to the signal input to its own control terminal, and the second output unit shuts down in response to the signal input to its own control terminal.

[0164] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0165] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gamma voltage generation circuit, characterized in that, include: A voltage output module, wherein the input terminal of the voltage output module is connected to a first voltage, and the voltage output module is used to control whether to output the first voltage according to the signal connected to the control terminal of the voltage output module; A gamma voltage generation module is connected to the output terminal of the voltage output module and is used to generate at least two gamma voltages based on the first voltage when the first voltage is output at the output terminal of the voltage output module.

2. The gamma voltage generating circuit according to claim 1, characterized in that, The voltage output module includes a first output unit, the input terminal of which is connected to the first voltage, and the output terminal of which is connected to the gamma voltage generation module. The first output unit is used to turn on in response to a signal connected to its own control terminal in a first stage to output the first voltage, and is also used to turn off in response to a signal connected to its own control terminal in a second stage to stop outputting the first voltage.

3. The gamma voltage generating circuit according to claim 2, characterized in that, The first output unit includes a transistor connected between the input terminal and the output terminal of the first output unit. The gate of the transistor is connected to a control signal. The transistor is used to turn on in response to the control signal in a first stage and to turn off in response to the control signal in a second stage. Alternatively, the first output unit includes at least two transistors connected in series between the input terminal and the output terminal of the first output unit. The gate of each transistor is connected to its corresponding control signal. Each transistor is turned on in response to the control signal connected to its gate in the first stage. At least one transistor connected between the input terminal and the output terminal of the first output unit is turned off in response to the control signal connected to its gate in the second stage.

4. The gamma voltage generating circuit according to claim 2, characterized in that, The voltage output module further includes a second output unit, the output terminal of which is connected to the output terminal of the first output unit, and the input terminal of the second output unit is connected to a second voltage. The second output unit is used to shut down in response to the signal connected to its own control terminal in both the first stage and the second stage.

5. The gamma voltage generating circuit according to claim 4, characterized in that, The first output unit includes: a first switching unit and a second switching unit; a first terminal of the first switching unit is connected to the first voltage, and a second terminal of the first switching unit is connected to the first terminal of the second switching unit; the first switching unit is configured to turn on in response to a first control signal in the first stage, and the second switching unit is configured to turn on in response to a second control signal in the first stage; the first switching unit is further configured to turn off in response to the first control signal in the second stage, and / or the second switching unit is further configured to turn off in response to the second control signal in the second stage; The second output unit includes a third switch unit and a fourth switch unit. A first terminal of the third switch unit is connected to a second terminal of the second switch unit, and a second terminal of the third switch unit is connected to a first terminal of the fourth switch unit. The second terminal of the fourth switch unit is connected to the second voltage. The third switch unit is used to turn off in response to a third control signal in the first stage, and / or the fourth switch unit is used to turn off in response to a fourth control signal in the first stage; the third switch unit is used to turn off in response to the third control signal in the second stage; and / or the fourth switch unit is used to turn off in response to the fourth control signal in the second stage.

6. The gamma voltage generating circuit according to claim 5, characterized in that, The first switching unit includes a first transistor, the second switching unit includes a second transistor, and the third switching unit includes a third transistor; The first terminal of the first transistor is connected to the first voltage, the gate of the first transistor is connected to the first control signal, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the second transistor is connected to the second control signal, the second terminal of the second transistor is connected to the first terminal of the third transistor, and the gate of the third transistor is connected to the third control signal. The fourth switching unit includes a fourth transistor, the first terminal of the fourth transistor is connected to the second terminal of the third transistor, the second terminal of the fourth transistor is connected to the second voltage, and the gate of the fourth transistor is connected to the fourth control signal; Preferably, the first control signal is multiplexed into the fourth control signal, the second control signal is multiplexed into the third control signal, the first transistor and the second transistor have the same channel type, the third transistor and the fourth transistor have different channel types, and the first transistor and the third transistor have different channel types.

7. The gamma voltage generating circuit according to claim 5, characterized in that, The first switching unit includes a first transistor, the second switching unit includes a second transistor, the third switching unit includes a third transistor, and the fourth switching unit includes a fourth transistor and an inverter; The first terminal of the first transistor is connected to the first voltage, the gate of the first transistor is connected to the first control signal, the second terminal of the first transistor is connected to the first terminal of the second transistor, the gate of the second transistor is connected to the second control signal, the second terminal of the second transistor is connected to the first terminal of the third transistor, and the gate of the third transistor is connected to the third control signal. The first terminal of the fourth transistor is connected to the second terminal of the third switching transistor, the second terminal of the fourth transistor is connected to the second voltage, the gate of the fourth transistor is connected to the output terminal of the inverter, and the input terminal of the inverter is connected to the fourth control signal. Preferably, the first control signal is multiplexed into the fourth control signal, the second control signal is multiplexed into the third control signal, the fourth switching unit includes the fourth transistor and the inverter, the first transistor and the second transistor have the same channel type, the third transistor and the fourth transistor have the same channel type, and the first transistor and the third transistor have different channel types.

8. The gamma voltage generating circuit according to claim 4, characterized in that, The first output unit includes a fifth transistor, and the second output unit includes a sixth transistor; The first terminal of the fifth transistor is connected to the first voltage, the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor, the gate of the fifth transistor is connected to the fifth control signal, the second terminal of the sixth transistor is connected to the second voltage, and the gate of the sixth transistor is connected to the sixth control signal.

9. The gamma voltage generating circuit according to claim 1, characterized in that, The gamma voltage generation module includes multiple resistors connected in series between the output terminal and the fixed potential terminal of the voltage output module. The fixed potential terminal is connected to a third voltage. Both ends of each resistor are used to output the gamma voltage, and the gamma voltage output from the common terminal of two adjacent resistors is the same. The third voltage is different from the first voltage; Preferably, the first voltage is the gamma voltage corresponding to the maximum gray level of the display device where the gamma voltage generation circuit is located, and the third voltage is the gamma voltage corresponding to the minimum gray level of the display device where the gamma voltage generation circuit is located.

10. A display device, characterized in that, The device includes a display panel and a driver chip. The driver chip includes a data voltage generation module and a gamma voltage generation circuit as described in any one of claims 1-9. The data voltage generation module is connected to the gamma voltage generation module and is used to generate a corresponding data voltage based on the gamma voltage.

11. The display device according to claim 10, characterized in that, The display panel includes multiple pixel circuits arranged in an array; The voltage output module is used to respond to a signal received by the control terminal of the voltage output module in the first stage and output a first voltage, and is also used to respond to a signal received by the control terminal of the voltage output module in the second stage and stop outputting the first voltage. The first stage is the time period within a display frame from scanning the first row of pixel circuits to scanning the last row of pixel circuits, and the second stage is the time period within a display frame from scanning the last row of pixel circuits to starting scanning the first row of pixel circuits in the next display frame.

12. The display device according to claim 10, characterized in that, The display panel includes: a light-emitting device; The display panel also includes: Array substrate; An isolation structure located on one side of the array substrate, the isolation structure enclosing a plurality of isolation openings, the light-emitting device being at least partially located within the isolation openings.

13. The display device according to claim 12, characterized in that, The isolation structure includes a first isolation portion and a second isolation portion that are sequentially stacked along a direction away from the array substrate; The orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate; Preferably, the isolation structure further includes a base located on the side of the first isolation portion near the array substrate, the base being disposed protruding relative to the first isolation portion in a direction toward the isolation opening, and the orthographic projection of the first isolation portion on the array substrate being located within the orthographic projection of the base on the array substrate.

14. The display device according to claim 13, characterized in that, The display panel also includes: A pixel defining layer is disposed between the isolation structure and the array substrate. The pixel defining layer is provided with a plurality of pixel openings that are respectively connected to each of the isolation openings. Each light-emitting device is disposed corresponding to each of the pixel openings. Preferably, the pixel defining layer includes a plurality of sub-layers, the plurality of sub-layers including a first sub-layer and a second sub-layer stacked sequentially along a direction away from the array substrate.

15. The display device according to claim 14, characterized in that, Each of the light-emitting devices includes a first electrode, a light-emitting structure, and a second electrode stacked together. The first electrode is disposed on the side of the light-emitting structure close to the array substrate. The pixel limiting layer exposes the first electrode through the pixel opening. Each of the light-emitting structures covers the pixel opening sidewall of the pixel limiting layer and the side of the pixel limiting layer away from the array substrate. Each of the light-emitting structures is located in the pixel opening and in contact with the first electrode. The second electrode is electrically connected to the isolation structure. The display panel further includes a first encapsulation layer, which includes a plurality of encapsulation portions. The encapsulation portions are located on the side of the second electrode away from the array substrate and extend through the sidewall of the isolation structure to the side of the isolation structure away from the array substrate. The encapsulation portion includes a first segment and a second segment connected to each other. The first segment is located inside the isolation opening and disposed on the side of the light-emitting device away from the substrate. The second segment is located on the side of the isolation structure facing the isolation opening. The surface of the first segment away from the array substrate and the surface of the second segment away from the isolation structure are at least partially connected to each other to enclose and form a gap space.

16. A driving method for a display device, characterized in that, For driving the display device according to any one of claims 10-15; The driving method for the display device includes: In the first stage, the voltage output module responds to the signal input to its own control terminal and outputs a first voltage. The gamma voltage generation module generates at least two gamma voltages based on the first voltage. The data voltage generation module generates a data voltage based on the gamma voltage and transmits it to the pixel circuit through a data line. In the second stage, the voltage output module shuts down in response to the signal input to its own control terminal.

17. The driving method for a display device according to claim 16, characterized in that, The voltage output module includes a first output unit and a second output unit. The input terminal of the first output unit is connected to the first voltage, and the output terminal of the first output unit is connected to the gamma voltage generation module. The output terminal of the second output unit is connected to the output terminal of the first output unit, and the input terminal of the second output unit is connected to the second voltage. In the first stage, the voltage output module responds to the signal input to its own control terminal and conducts a first voltage output, including: In the first stage, the first output unit turns on in response to the signal input to its own control terminal and outputs the first voltage, while the second output unit turns off in response to the signal input to its own control terminal. In the second stage, the voltage output module shuts down in response to a signal input to its control terminal, including: In the second stage, the first output unit shuts down in response to the signal received by its own control terminal, and the second output unit shuts down in response to the signal received by its own control terminal.

18. The driving method for a display device according to claim 17, characterized in that, The display panel includes an array of pixel circuits. The first stage is the time period from scanning the first row of pixel circuits to scanning the last row of pixel circuits within a display frame. The second stage is the time period from scanning the last row of pixel circuits to starting scanning the first row of pixel circuits in the next display frame within a display frame.

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