Duty cycle based receiver with reduced listening power consumption

Abstract

The invention relates to a duty cycle based receiver with reduced listening power consumption. A direct sequence spread spectrum (DSSS) receiver operates in a duty cycle mode to reduce power consumption of the DSSS receiver. The DSSS receiver uses fast DSSS preamble detection to determine whether the input signal is a desired channel DSSS preamble symbol, and uses one preamble symbol to determine whether the input signal is the desired channel DSSS preamble symbol. When operating in a duty cycle mode, the DSSS receiver selectively disables at least one power domain of a plurality of power domains of the DSSS receiver during an ON time of the duty cycle and when a desired signal is not detected, and selectively disables at least one power domain of the DSSS receiver during an OFF time of the duty cycle, and the power consumption is further reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to wireless communications, and in particular to reducing power consumption of a wireless receiver. BACKGROUND

[0002] A typical Internet of Things (IoT) based wireless communication device product can operate using multiple wireless protocols, such as IEEE 802.15.4 based protocols (Zigbee® and Thread) and Bluetooth® Low Energy / Bluetooth (BLE / BT). According to the requirements of the IEEE 802.15.4 Standard 2.4 GHz Physical Interface Specification, Direct Sequence Spread Spectrum (DSSS) technique is used to reduce the impact of interference by spreading 4 bits into a 32-chip PN sequence. The IEEE 802.15.4 Standard is specifically designed to meet the needs of low power, cost-effective, standards-compliant solutions. In typical applications conforming to this standard, the wireless communication devices are usually powered by batteries, and frequent battery replacement or battery charging is not practical, which makes power consumption a concern. Therefore, techniques are needed to reduce the power consumption of a DSSS receiver. SUMMARY

[0003] In at least one embodiment, a duty cycle based DSSS receiver utilizes fast DSSS preamble detection to operate the receiver in a power duty cycle mode in a receiver search state to achieve lower average power consumption, where the SSS preamble detection uses only one preamble symbol to determine whether an input signal is a desired channel DSSS preamble symbol. The power duty cycle mode is compatible with multiple wireless protocols, such as IEEE 802.15.4 based protocols Zigbee and OpenThread.

[0004] In an embodiment, a method for operating a wireless communication device includes periodically enabling a radio frequency receiver circuit. The radio frequency receiver circuit is divided into a plurality of power domains. The method includes controlling power consumption of the radio frequency receiver circuit by selectively disabling at least one of the plurality of power domains during an on-time of the radio frequency receiver circuit. The power consumption is controlled based on a signal arrival detection and an average received signal power. The method can include determining the average received signal power based on a comparison of a predetermined threshold to a moving average of an estimated instantaneous power of a received signal. Controlling the power consumption can include configuring the radio frequency receiver circuit to a data packet reception state. The power consumption can also be controlled based on a detection of a synchronization word in a received data packet. Controlling the power consumption can include disabling at least one of the plurality of power domains in response to detecting an end of a data packet.

[0005] In at least one embodiment, a wireless communication device includes a radio frequency receiver circuit configured to generate a signal arrival detection signal and an average received signal power signal. The radio frequency receiver circuit is divided into a plurality of power domains. The wireless communication device includes a controller configured to periodically enable the radio frequency receiver circuit and configured to generate a power domain control signal for at least one of the plurality of power domains of the radio frequency receiver circuit based on the signal arrival detection signal and the average received signal power signal. A demodulator circuit can also be configured to determine the average received signal power based on a comparison of a predetermined threshold to a running average of an estimated instantaneous power of a received signal. The demodulator circuit can also be configured to detect a synchronization word in a received data packet, and the power domain control signal can also be based on an indication of the detection of the synchronization word. The controller can also be configured to disable a power domain of the plurality of power domains prior to detection of the synchronization word, and enable the power domain in response to detection of the synchronization word. The controller can also be configured to disable at least one of the plurality of power domains in response to a timeout of a synchronization word detection window. BRIEF DESCRIPTION OF DRAWINGS

[0006] The application can be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0007] Figure 1 is a table illustrating exemplary symbol-to-chip mapping for the 2450 MHz and 2380 MHz bands of an exemplary offset-quadrature phase shift keying (O-QPSK) physical interface of a wireless communication network.

[0008] Figure 2 illustrates a data packet structure for transmission using an exemplary O-QPSK physical interface of a wireless communication network.

[0009] Figure 3 illustrates an offset between I-phase chip modulation and Q-phase chip modulation.

[0010] Figure 4 illustrates an example of a sample baseband chip sequence (zero sequence) with half-sine pulse shaping.

[0011] Figure 5 illustrates a functional block diagram of an embodiment of a duty cycle based receiver of a wireless communication device, including an exemplary non-coherent DSSS demodulator consistent with at least one embodiment of the application.

[0012] Figure 6 illustrates an exemplary O-QPSK data packet, and in particular, a preamble portion and a start of frame delimiter (SFD) portion of a data packet for signal detection and timing by a duty cycle based receiver of Figure 5 ​

[0013] Figure 7A A functional block diagram of an embodiment of a power detector of a duty cycle based receiver of Figure 5

[0014] Figure 7B A functional block diagram of an embodiment of a power detector of a duty cycle based receiver of Figure 5

[0015] Figure 8 An exemplary waveform of a power detector in Figure 7A and Figure 7B

[0016] Figure 9 A timing diagram of a duty cycle timing for a single channel scan by a duty cycle based receiver in Figure 5

[0017] Figure 10 A high level flow chart consistent with at least one embodiment of a duty cycle based receiver of Figure 5

[0018] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0019] Since a direct sequence spread spectrum (DSSS) receiver typically spends more time waiting and searching for a desired channel DSSS signal (referred to as a "receiver search state") than the time of an actual received signal, a DSSS receiver operates in a duty cycle mode to reduce the power consumption of the DSSS receiver. The DSSS receiver uses a fast DSSS preamble detection to determine if an input signal is a desired channel DSSS preamble symbol, and uses one preamble symbol to determine if the input signal is a desired channel DSSS preamble symbol. In a duty cycle mode of operation, the DSSS receiver further reduces power consumption by selectively disabling at least one power domain of a plurality of power domains of the DSSS receiver during an on-time of a duty cycle and when a preamble is not detected, and selectively disabling at least one power domain of the DSSS receiver during an off-time of the duty cycle.

[0020] ​​​​​Before describing details of embodiments of a DSSS receiver and its use, some background knowledge about the signal being demodulated is provided. The IEEE 802.15.4 standard offset-quadrature phase shift keying (O-QPSK) employs semi-sine O-QPSK, which is equivalent to minimum shift keying (MSK) modulation. The use of DSSS increases the signal bandwidth to obtain a lower bit error rate for the same received signal-to-noise ratio (SNR). DSSS reduces the impact of interference by spreading four bits into a thirty-two chip pseudo-random noise (PN) sequence. The IEEE 802.15.4 standard O-QPSK uses 16 symbols. Each symbol includes 32 chips. Each symbol represents 4 bits. Each symbol is mapped into an approximately orthogonal 32-chip sequence as specified by the table shown in Figure 1 The baud rate is 250 kbps, the chip rate is 2 Mchips per second, and the symbol rate is 62.5 k symbols per second.

[0021] The IEEE 802.15.4 standard O-QPSK transmits data in the data packet shown in Figure 2 The data packet includes a preamble field consisting of eight symbol zeros and a start-of-frame delimiter (SFD) field (i.e., a sync word) consisting of predefined bits (e.g., "11100101") that indicate the end of the preamble and the start of the packet data. The eight-symbol preamble and two-symbol sync word can be used for initial timing / frequency acquisition.

[0022] For DSSS, the chip sequence representing each data symbol is modulated onto a carrier using O-QPSK modulation with semi-sine pulse shaping. Even-indexed chips are modulated onto an in-phase (I) carrier, and odd-indexed chips are modulated onto a quadrature-phase (Q) carrier. In the 2450 MHz and 2380 MHz bands, the chip rate is 32 times the symbol rate because each data symbol is represented by a 32-chip sequence.

[0023] Referring to Figure 3 To form the offset between the I-phase chip modulation and the Q-phase chip modulation, the Q-phase chips are delayed in time T c , where T c is the inverse of the chip rate. In the 2450 MHz, 915 MHz, 868 MHz, and 2380 MHz bands, each baseband chip is represented using a semi-sine pulse shape as follows:

[0024] .

[0025] Figure 4 A sample baseband chip sequence (zero sequence) with semi-sine pulse shaping is shown. The baseband O-QPSK signal is:

[0026] .

[0027] Baseband signal to RF signal: S RF (t) where f ctx is the carrier frequency at the transmitter. The chip duration is T c = 0.5 μs, from which the symbol rate (1 / T c ) / 32 = 62.5 kilo-symbols / s (kilo-symbols / s) can be derived, and the data rate of the O-QPSK PHY is 62.5 x 4 = 250 kb / s.

[0028] The chip sequence is modulated onto the carrier using O-QPSK with half-sine pulse shaping, which is equivalent to MSK modulation with index h = 0.5. But in order to make MSK strictly equivalent to the specified O-QPSK format, the data is encoded, and the MSK / O-QPSK chip encoder is as follows. Figure 1 The binary chips in the table of

[0029]

[0030] The signed MSK chip data c_msk_signed[k] can be calculated as follows:

[0031] c_msk_signed[2 x n] = c_oqpsk[2 x n + 1] x c_oqpsk[2 x n];

[0032] c_msk_signed[2 x n + 1] = -c_oqpsk[2 x n + 2] x c_oqpsk[2 x n + 1],

[0033] where n = 0, 1, 2, 3, 4,...

[0034] If k is even, then k = 2 x n; if k is odd, then k = 2 x n + 1.

[0035] The binary MSK chip c_msk[k] can be converted by:

[0036]

[0037] Figure 5A high-level block diagram of an embodiment of a duty cycle-based receiver 500 included in a wireless communication device is shown. The duty cycle-based receiver 500 has the ability for fast signal arrival detection. The duty cycle-based receiver 500 uses a heterodyne (intermediate frequency (IF) sampling) receive architecture. A series of passive and active devices downconvert the carrier radio frequency (RF) to a lower or higher intermediate frequency (IF) for sampling while maintaining signal integrity. An antenna 501 provides an RF signal to a passive network 503, which provides impedance matching, filtering, and electrostatic discharge protection. A low noise amplifier 505 amplifies the signal from the passive network 503 without significantly degrading the signal-to-noise ratio and provides the amplified RF signal to a mixer 507. The mixer 507 frequency converts or shifts the RF signal using a signal generated by an RF clock synthesizer 552. The RF clock synthesizer 552 uses a fractional-N phase-locked loop (PLL) 508 and an I / Q generation block 510 to convert a local oscillation signal from the fractional-N PLL 508 to I LO and Q LO signals for use by the mixer 507.

[0038] The mixer 507 provides the converted output signal as a set of two signals, namely, an in-phase (Im) signal and a quadrature (Qm) signal, to a programmable gain amplifier (PGA) 509. The Im and Qm signals are analog time domain signals. In at least one embodiment of the duty cycle-based receiver 500, the PGA amplifier 509 and a filter (not shown separately) provide amplified and filtered versions of the Im and Qm signals to an intermediate frequency analog-to-digital converter 514, which converts these versions of the Im and Qm signals to digital signals. The intermediate frequency analog-to-digital converter 514 provides digital I and Q signals to a receiver digital filter chain. The receiver digital filter chain includes a decimator 516 that supplies signals to a digital mixer 518. The digital mixer 518 mixes the signals from the intermediate frequency to baseband, and a channel filter 520 provides filtering to reduce the effects of channel interferers. The bandwidth of the channel filter 520 is configurable to combine a large frequency offset tracking range with optimized sensitivity. The embodiment selects an IF frequency of 1.369977 Mhz. In an embodiment, the initial bandwidth of the channel filter 520 is 2.2 MHz, and upon detection of a trigger signal, the bandwidth of the channel filter 520 switches to 1.8 Mhz. In other embodiments, other bandwidths can be selected for the channel filter 520. A sample rate converter (SRC) 522 scales the output sample rate of the channel filter to an integer value with respect to the expected chip rate. This reduces or eliminates sample phase jitter, but does not guarantee that the chip sample phase is correct. A timing loop is needed to provide chip timing information. A coordinate rotation digital computer (CORDIC) 524 converts the I and Q signals to phase and amplitude. Typically, the CORDIC implements known techniques to perform calculations, including trigonometric functions and complex multiplication, without using multipliers. The CORDIC implements an arctangent function using only addition, subtraction, shift, and lookup table operations. In other embodiments, a digital signal processor using executing firmware or custom circuitry is used. In an embodiment, the duty cycle-based receiver 500 provides amplitude information to a received signal strength indicator (RSSI) block (not shown in the figure). The CORDIC 524 also provides phase information to a function transformation block 532.

[0039] In embodiments, the function transform module 532 converts the phase signal to single chip and multi-chip (2 to 6 chips) differential detection, averages the single chip phase difference between two adjacent samples (interpretation), and provides a second order difference. The DSSS demodulator 556 also includes a correlator bank 534 that computes the correlation of the transform received from the function transform block 532 with a corresponding template signal c(k) over the duration of an entire symbol sequence. The correlator bank also serves as an “averaging filter” to estimate the frequency offset. The DSSS processor 536 generates the template signal c[k] based on a predefined DSSS symbol-to-chip table. The DSSS processor 536 determines which symbol the received signal is most likely based on the output of the correlator bank 534 (maximum likelihood). This soft decision detection of the DSSS code achieves more than 2 dB improvement over other methods. The DSSS processor 536 determines whether a first preamble symbol is detected within an observation period of one symbol. Upon detection of the first symbol, a coarse frequency offset error (FOE) is fed back to the digital mixer 518 or fractional-N PLL 508. In addition, upon detection of the first preamble symbol, the bandwidth of the channel filter 520 is narrowed to improve sensitivity for detection of the second preamble symbol. The DSSS demodulator 556 is also used for timing / frequency acquisition and tracking.

[0040] In some embodiments, the DSSS processor 536 performs various functions (e.g., logic, arithmetic, etc.) needed for demodulation and other signal processing tasks. The DSSS processor 536 can also use the demodulated data in programs, routines, or algorithms (whether software, firmware, hardware, or a combination thereof) to perform the required control or data processing tasks. In embodiments, the DSSS processor 536 includes one or more processors (such as a microcontroller) and software and / or firmware to perform the required demodulation functions described herein. The memory 542 stores software and firmware used by the DSSS processor 536 to perform various tasks and stores data provided to or generated by the DSSS processor 536. The memory 542 can include various types of memory in various embodiments, including dynamic random access memory (DRAM), static random access memory (SRAM), and / or non-volatile memory (NVM) depending on system requirements. Moreover, while the DSSS processor 536 has access to the memory 542, in embodiments, other system components (such as the function transform block 532, the correlator bank, and the microcontroller unit 550) can have access to the memory 542.

[0041] In an environment requiring monitoring of multiple communication systems, such as an IoT environment using multiple physical interfaces, slow signal arrival detection can make it difficult to achieve fast frequency hopping. In a traditional non-coherent DSSS demodulator, data packet error rate sensitivity is limited by the synchronization word error rate (SER). Poor SER performance often results from variations in initial frequency error estimation and initial timing detection. The detection signal DSA is used to indicate whether a DSSS preamble signal is being received. In a multiple physical interface environment, the system needs fast signal detection to avoid missing transmissions. Fast detection requires a short correlation observation period. However, in a low signal-to-noise ratio (SNR) environment, the signal to be detected is very weak compared to the noise. Embodiments described herein provide fast DSSS signal arrival detection for channel scanning / handoff and antenna diversity applications. Embodiments also provide more accurate initial timing and frequency offset estimation, and more robust DSSS de-spreading, making the demodulator more sensitive. Embodiments such as the DSSS demodulator shown in FIG. 1 provide a low cost, low power, and configurable correlator bank for DSSS demodulation. Figure 5 Embodiments such as the DSSS demodulator shown in FIG. 1 provide a low cost, low power, and configurable correlator bank for DSSS demodulation.

[0042] The duty cycle-based receiver 500 completes signal arrival detection within one preamble symbol. After one symbol detection, the correlator bank 534 is dynamically reconfigured to determine the coarse frequency offset. A second preamble signal is then used to confirm signal arrival detection. An early exit mechanism allows for fast processing of false detections. After confirming signal arrival detection, the duty cycle-based receiver 500 extends the correlation length for robust initial timing detection. During the initial timing detection phase, the duty cycle-based receiver 500 configures the correlator bank 534 as a matched finite impulse response (FIR) filter to process two function transforms for each of four symbols. This step improves the reliability of initial timing detection and eliminates unnecessary false detections. Additionally, after frequency offset estimation and timing detection, the duty cycle-based receiver 500 dynamically reconfigures the correlator bank 534 as a matched FIR filter to decode (e.g., de-spread) received DSSS symbols and track timing drift.

[0043] Reference is made to Figure 5 and Figure 6In embodiments, the duty cycle-based receiver 500 uses the received preamble symbol 602 (e.g., “0”) for signal arrival detection and required channel power detection. The duty cycle-based receiver 500 uses the received preamble symbol 604 following the received preamble symbol 602 for qualifying signal arrival detection and rejecting false signal arrival detection. The coarse timing estimate and the fine residual frequency offset estimate use the last two zero symbols and two SFD symbols (e.g., “7A”) of the preamble symbol, which together have a value of “007A”. In at least one embodiment, the synchronization detector 546 correlates the received data RXD provided by the DSSS processor 536 with a predetermined symbol value (e.g., “7A”) of the SFD field to generate a control signal SFD_DET. The synchronization detector 546 asserts the control signal SFD_DET in response to the correlation exceeding a predetermined threshold, indicating detection of an IEEE. 802.15.4 standard signal; otherwise, the control signal SFD_DET is de-asserted. Further details of the DSSS demodulator 556, including the function transformer 532, the correlator bank 534, the DSSS processor 536, and the generation of the control signal DSA, are further described in U.S. Patent Application No. 18 / 217,015, filed June 30, 2023, entitled “Non-Coherent DSSS Demodulator with Fast Signal Arrival Detection and Improved Timing and Frequency Offset Estimation,” and U.S. Patent Application No. 18 / 217,019, filed June 30, 2023, entitled “Configurable Correlator Bank for Non-Coherent DSSS Demodulator,” which are incorporated by reference herein.

[0044] In at least one embodiment, duty cycle based receiver 500 is divided into multiple power domains that can be selectively disabled by microcontroller unit 550 to reduce power consumption. In embodiments, microcontroller unit 550 executes software and / or firmware to perform the required functions described herein. In at least one embodiment, each of the five main modules of duty cycle based receiver 500 is associated with a corresponding power domain and a corresponding power domain control signal. Microcontroller unit 550 is in power domain 0, which is enabled in response to a control signal PWR_D0 received from an external control circuit. When operating in duty cycle mode, power domain 0 is always on for the on-time and off-time of the receiver duty cycle. RF synthesizer 552 operates in power domain 1, and microcontroller unit 550 enables or disables the power domain by setting control signal PWR_D1. RF receiver circuit 554 operates in power domain 2, and microcontroller unit 550 enables or disables power domain 2 by setting control signal PWR_D2. DSSS demodulator 556 and automatic gain controller 558 operate in power domain 3, and microcontroller unit 550 enables or disables power domain 3 by setting control signal PWR_D3. Frame controller 548 operates in power domain 4, and microcontroller unit 550 enables or disables power domain 4 by setting control signal PWR_D4. In embodiments, duty cycle based receiver 500 operates in duty cycle mode to reduce the power consumption of power domains 1, 2, 3, and 4. Since microcontroller unit 550 is required to control the on-time and off-time of the portions of duty cycle based receiver 500, power consumption of power domain 0 is not saved in duty cycle mode. For example embodiments, the operation of each power domain is summarized as follows:

[0045]

[0046] In embodiments, power domains 1-4 have a combined power consumption of 5 mW in the receiver search state where all power domains are enabled without running duty cycle mode. In other embodiments, the receiver circuit is divided differently into different domains. The power consumption, power-up time, and power savings of the operation of duty cycle mode will vary depending on the embodiment. In at least one embodiment, a single power domain is controlled by gating the clock signal provided to the power domain. In other embodiments, a single power domain is controlled by selectively disabling the power supply to the circuitry provided to the power domain.

[0047] Referring to Figures 5 to 8In at least one embodiment, the power detector block 544 receives the I and Q signals from the sample rate converter 522 of the receiver digital filter chain and generates a signal PWR_TOO_LOW that is set in response to PWR_PASS being deasserted. Channel power is defined as the sum of all power in the channel within a defined bandwidth (e.g., 2.2 MHz as defined in the IEEE 802.15.4 standard). The power detector module 544 detects the instantaneous power of the received signal and averages it over a predetermined period to obtain an average of the received signal power. The squaring function circuit 702, the squaring function circuit 704, and the summing circuit 706 compute the instantaneous power of the received signal samples at a sample rate of f s In at least one embodiment, the squaring function circuit 702 and the squaring function circuit 704 can be replaced with an absolute value function or the amplitude operation of CORDIC. The integrate-and-dump filter 708 accumulates the sum of the discrete-time input signal, and the control signal RESET clears the sum according to a predetermined schedule. The integrate-and-dump filter 708 updates the signal x(k) at the chip rate (i.e., once every four samples, for example). The moving average filter 710 provides the average received power in the channel CHPWR(k):

[0048]

[0049] The comparator 712 asserts the PWR_PASS signal in response to the average received signal power CHPWR(k) exceeding a predetermined value PWR THD, and deasserts the PWR_PASS signal otherwise.

[0050] In at least one embodiment, the noise figure (NF) refers to the amount of noise power added to the thermal noise power 724 at the input of the receiver by the electronic circuitry in the receiver. The thermal noise 724 at the input of the receiver is passed to the DSSS demodulator 556. The thermal noise 724 is present in the receiver channel and cannot be eliminated. The NF of the circuitry in the receiver, such as amplifiers and mixers, adds additional noise to the received channel and boosts the noise at the demodulator to a noise floor 722. In order to achieve a demodulated signal of a desired quality (e.g., the desired channel signal 720), the average received power CHPWR(k) must be PWR THD higher than the noise floor.

[0051] Referring to Figure 5 and Figure 9In an embodiment, the microcontroller unit 550 periodically enables and disables the duty cycle based receiver 500 according to a duty cycle. During the on time of the duty cycle, the RF receiver circuit 554 needs an interval A to power up. In an embodiment, the interval A is the maximum of the time it takes for the duty cycle based receiver 500 to lock the local oscillator frequency after powering up the RF receiver circuit 554 from a powered down state and the time it takes for all the RF receive chain circuits to power up and fully stabilize. The interval Y includes the automatic gain control stabilization time and the propagation delay of the receiver digital filter chain before the signal becomes available for the demodulator to process. This delay is picked up mainly in the automatic gain control and channel filter. The interval W is the power detection interval. If only noise is detected (e.g., PWR_TOO_LOW = "1"), the microcontroller unit 550 powers down the duty cycle based receiver 500. If, during the on time of the duty cycle, the duty cycle based receiver 500 receives only a few chips of the preamble and these chips are not enough to detect a signal (e.g., PWR_TOO_LOW = "1"), the duty cycle based receiver 500 powers down and the preamble chips within the interval t_WASTED will not be used. If, during the on time of the duty cycle, the duty cycle based receiver 500 receives enough preamble chips that are enough to detect a signal (e.g., PWR_TOO_LOW = "0"), the duty cycle based receiver 500 sets the control signal PWR_PASS and suspends the duty cycle. The duty cycle based receiver 500 performs a fast DSSS preamble arrival detection and frequency offset estimation within the interval R. If a signal arrival is detected, the DSSS processor 536 sets the control signal DSA.

[0052] In an exemplary embodiment, the on time (i.e., ON) is equal to A + Y + W and t_WASTED + OFF time + A + Y + W + R is less than 128 μs - (t_WASTED + A + Y + W + R). The duty cycle based power savings of this embodiment can be calculated as a percentage as follows: OFF time / (on time + OFF time), and the duty cycle based power savings is approximately total power consumption x the percentage of power savings. In an exemplary embodiment, t_WASTED = 8 μs, the scan window is 40 μs (A = 20 μs, Y = 4 μs, W = 16 μs), R = 32 μs, the on time = 40 μs, and the OFF time = 48 μs. Thus, the duty cycle based operation power savings in this embodiment is 2.7 mW.

[0053] Referring to Figure 5 and Figure 10The exemplary duty cycle-based DSSS demodulator operation includes a microcontroller unit 550 (or other state machine) that is initialized in response to the duty cycle-based receiver 500 asserting the control signal PWR DO to enable power domain 0. The microcontroller unit 550 and any other necessary circuitry (i.e., circuitry that cannot be powered down for proper operation) are located in power domain 0. The other power domains are disabled (802) by the corresponding control signals (e.g., PWR D1 = 0, PWR D2 = 0, PWR D3 = 0, and PWR D4 = 0). The microcontroller unit 550 enables the duty cycle on-time (804), e.g., by asserting the control signals PWR D1, PWR D2, and PWR D3 to enable power domains 1, 2, and 3; enables the duty cycle timer and sets the predetermined on-time timeout threshold, e.g., ON = A + Y + W (806). The microcontroller unit 550 polls the duty cycle timer to determine whether the predetermined on-time has expired (808). If the predetermined on-time has not expired, the microcontroller unit 550 waits until the predetermined on-time expires. When the predetermined on-time expires, the state machine initializes the variable L (e.g., L = 0) (810). If a power deficiency is detected (e.g., PWR_TOO_LOW = 1 or PWR_PASS = 0) (812), the state machine enters the duty cycle off-time and powers down domains 1, 2, and 3 (826) (e.g., by deasserting the control signals PWR D1, PWR D2, and PWR D3). The microcontroller unit then starts the duty cycle timer and sets the predetermined off-time timeout threshold (824), e.g., OFF = 128 - (t WASTED + A + Y + W + R), and waits for the off-time to expire (822). In response to the off-time expiring, the microcontroller unit 550 again starts the duty cycle timer for the duty cycle on-time (804).

[0054] If sufficient power is detected (i.e., PWR_PASS = 1) (812), the microcontroller unit 550 waits for a predetermined interval T1 (e.g., 4 μβ) (814) and increments the variable L (816). If the control signal DSA is set to indicate that a signal arrival is detected (818), the microcontroller unit 550 causes the duty cycle-based receiver 500 to activate a frame start delimiter search timeout timer (832). The microcontroller unit 550 determines whether the synchronization detector 546 detects a frame start delimiter (834). If the synchronization detector 546 does not detect a frame start delimiter, the microcontroller unit 550 continues to wait for detection of a frame start delimiter until a frame start delimiter search timeout (840). If the frame start delimiter search timeout, the microcontroller unit 550 starts a duty cycle off time and powers down domains 1, 2, and 3 (e.g., PWR_D1 = 0, PWR_D2 = 0, and PWR_D3 = 0) (826), starts a duty cycle timer and sets an off time timeout threshold (824), e.g., OFF = 128 - (t_WASTED + A + Y + W + R), and waits until the off time expires (822). In response to the off time expiring, the microcontroller unit 550 again starts a duty cycle on time (804).

[0055] If a frame start delimiter is detected (834), the microcontroller unit 550 enables power domain 4 by setting the corresponding control signal (e.g., PWR_D4 = 1) (836), to enter a data packet reception state (837), and the microcontroller unit 550 waits until the duty cycle-based receiver 500 detects an end of a data packet (838). When the duty cycle-based receiver 500 detects an end of a data packet, the microcontroller unit 550 closes the duty cycle on time, starts a duty cycle off time, powers down power domains 1, 2, 3, and 4 using the corresponding control signals (e.g., PWR_D1 = 0, PWR_D2 = 0, PWR_D3 = 0, and PWR_D4 = 0) (826), enables the duty cycle timer for the off time, sets the off time timeout threshold, e.g., OFF = 128 - (t_WASTED + A + Y + W + R) (824), and waits until the off time expires (822). In response to the off time expiring, the microcontroller unit 550 again starts a duty cycle on time (804).

[0056] If the control signal DSA is unset (818), the microcontroller unit 550 determines whether the wait time L MAXthe maximum number of iterations (e.g., L = 4) (820). If the maximum number of iterations is not reached, the microcontroller unit 550 continues to wait for sufficient power to be detected (812). If the maximum number of iterations is reached without sufficient power being detected (812), the microcontroller unit 550 turns off the on-time of the duty cycle and powers down domains 1, 2, and 3 (e.g., PWR_D1 = 0, PWR_D2 = 0, and PWR_D3 = 0) (826), enables the off-time of the duty cycle timer, sets the off-time timeout threshold, e.g., OFF = 128 - (t_WASTED + A + Y + W + R) (824), and waits until the off-time expires (822). In response to the off-time expiring, the microcontroller unit 550 again starts the on-time of the duty cycle (804).

[0057] Accordingly, techniques have been described for reducing the power consumption of a DSSS receiver by using duty cycle based operation and selectively disabling power domains of the DSSS receiver. The description of the application set forth herein is illustrative, and is not intended to limit the scope of the application as set forth in the following claims. For example, although the application has been described in embodiments using a heterodyne DSSS receiver, those skilled in the art will appreciate that the teachings herein can be used in conjunction with other receiver architectures. The use of the terms "first," "second," "third," etc. in the claims, unless otherwise specified, are used for identification purposes only and do not connote or imply any order, sequence or position in time, location, or level of importance. For example, "a first receive signal" and "a second receive signal" do not connote or imply that the first receive signal occurs in time before the second receive signal. Changes and modifications can be made to the embodiments disclosed herein without departing from the scope of the application as set forth in the following claims.

Claims

1. A method for operating a wireless communication device, the method comprising: The radio frequency receiver circuit is periodically activated, and the radio frequency receiver circuit is divided into multiple power domains; as well as The power consumption of the radio frequency receiver circuit is controlled by selectively disabling at least one of the plurality of power domains during the on-time of the radio frequency receiver circuit. The power consumption is controlled based on signal arrival detection and average received signal power.

2. The method according to claim 1, further comprising: The average received signal power is determined by comparing a predetermined threshold with a moving average of the estimated instantaneous power of the received signal.

3. The method according to claim 1, wherein, Controlling the power consumption includes: Configure the radio frequency receiver circuit in data packet receiving mode. The power consumption is further controlled based on the detection of synchronization words in the received data packets.

4. The method according to claim 3, wherein, Controlling the power consumption includes: Disable the power domains in the plurality of power domains before the synchronization word is detected; and In response to the detection of the synchronization word, the power domain is enabled.

5. The method according to claim 1, 2, 3 or 4, wherein, Controlling the power consumption includes: In response to a timeout in the synchronization word detection window, at least one of the power domains is disabled.

6. The method according to claim 1, 2, 3 or 4, wherein, Controlling the power consumption includes: In response to the detection of the end of a data packet, at least one of the plurality of power domains is disabled.

7. The method according to claim 1, 2, 3 or 4, wherein, The multiple power domains include the local oscillator power domain, the RF front-end circuit power domain, the automatic gain control and demodulator power domain, and the frame controller power domain.

8. The method according to claim 1, 2, 3 or 4, further comprising: Based on the configuration of the correlator group and in response to the correlation between the first plurality of transformations corresponding to the first received symbol and the corresponding first template signal, the arrival of the signal is detected.

9. A wireless communication device, comprising: The radio frequency receiver circuit is configured to generate a signal arrival detection signal and an average received signal power signal, and the radio frequency receiver circuit is divided into multiple power domains. as well as The controller is configured to periodically enable the radio frequency receiver circuit and generate a power domain control signal for at least one of the plurality of power domains of the radio frequency receiver circuit based on the signal arrival detection signal and the average received signal power signal.

10. The wireless communication device according to claim 9, wherein, The radio frequency receiver circuit includes: The demodulator circuit is configured to detect signal arrival based on the configuration of the correlator group and in response to the correlation between the first plurality of transformations corresponding to the first received symbol and the corresponding first template signal.

11. The wireless communication device according to claim 10, wherein, The demodulator circuit is further configured to determine the average received signal power based on a comparison of a predetermined threshold with a moving average of the estimated instantaneous power of the received signal.

12. The wireless communication device according to claim 11, wherein, The demodulator circuit is further configured to detect a synchronization word in a received data packet, and the power domain control signal is also based on an indication of the detection of the synchronization word.

13. The wireless communication device according to claim 12, wherein, The controller is also configured to disable a power domain among the plurality of power domains before the synchronization word is detected, and to enable the power domain in response to the detection of the synchronization word.

14. The wireless communication device according to claim 12, wherein, The controller is also configured to disable at least one of the plurality of power domains in response to a timeout of the synchronization word detection window.

15. The wireless communication device according to claim 12, wherein, The controller is also configured to disable at least one of the plurality of power domains in response to detecting the end of a data packet.

16. The wireless communication device according to claim 9, 10, 11, 12, 13 or 14, wherein, The multiple power domains include the local oscillator power domain, the RF front-end circuit power domain, the automatic gain control and demodulator power domain, and the frame controller power domain.

17. The wireless communication device according to claim 16, wherein, The radio frequency receiver circuit includes: The radio frequency receiver front-end circuit is associated with a first power domain among the plurality of power domains; A local oscillator circuit is coupled to the radio frequency receiver circuit and associated with a second power domain of the plurality of power domains; An automatic gain control circuit is associated with a third power domain among the plurality of power domains; Demodulator, associated with the third power domain of the plurality of power domains; and The frame controller circuit is associated with the fourth power domain among the plurality of power domains.

18. The wireless communication device according to claim 17, in, The controller is associated with an additional power domain, which is a constant power domain, and The controller is further configured to selectively enable the first power domain, the second power domain, the third power domain, and the fourth power domain during the on-time of the radio frequency receiver circuit.

19. An apparatus comprising: Device for receiving and demodulating radio frequency signals; as well as A means for periodically enabling and controlling the power consumption of the device used for receiving and demodulating radio frequency signals based on signal arrival detection and average received signal power.

20. The apparatus according to claim 19, wherein, The power consumption of the device used for receiving and demodulating radio frequency signals is further controlled based on the detection of synchronization words in the received data packets.

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