Communication method and communication device

Abstract

According to the communication method, a receiving end device generates a bit sequence based on A information bits and the number nPC of PC bits, the bit sequence comprises N bits, the information bits and the PC bits are located at A + nPC positions with the highest sequence reliability in the bit sequence, and the PC positions where the PC bits are placed meet a first condition and a second condition, the first condition is that the minimum row weight of A positions where A information bits are located is not less than the minimum row weight of A positions with the highest sequence reliability in the bit sequence, and the second condition is that the kth high position number in nPC position numbers in the bit sequence is not less than the kth high position number in the set S3, the set S3 comprises nPC positions with the lowest reliability in A + nPC positions with the highest sequence reliability; and performing polarization coding on the bit sequence to obtain a code word sequence. According to the method, a PC bit placement mode for determining the requirement of a correct decoding path based on PC bits is provided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of coding, and more particularly, to a communication method and a communication apparatus. BACKGROUND

[0002] At present, a parity check (PC) polar code (PC-Polar code) is proposed, and PC bits in the PC-Polar code can correct path metric (PM) values of a Successive Cancellation List (SCL) decoding to improve the probability that a correct decoding path is ranked first. The main principle of the PC-Polar code is that, if n PC PC bits are needed, n PC positions of frozen bits at N positions of to-be-encoded bits are selected as PC positions, values at the PC positions are different from values at other frozen bits and are not fixed as 0, and the values at the PC positions are determined based on a PC check relationship and values at to-be-encoded bits before the PC positions. For example, the PC check relationship indicates that the value at a current PC position is an exclusive-OR result of a bit at an i-th position before the current PC position and a bit at a j-th position.

[0003] In an SCL decoding process, if a current decoding bit is a PC bit, a value at the current PC position needs to be calculated based on a previous decoding result and a PC check relationship, and if the value is different from a hard decision result of a log-likelihood ratio (LLR) corresponding to the current PC position, a penalty needs to be added to a current decoding path, and a PM value of the current decoding path will be increased and the current decoding path will be ranked later. Therefore, the addition of the PC bit can make a correct decoding path be ranked earlier, and the probability that a first decoding path output is a correct codeword is improved. However, a placement manner of the PC bit does not consider the requirement of determining a correct decoding path based on the PC bit, and therefore the decoding performance based on the PC bit needs to be improved. SUMMARY

[0004] Embodiments of the present application provide a communication method and a communication apparatus, and a PC bit placement manner considering the requirement of determining a correct decoding path based on a PC bit.

[0005] In a first aspect, a communication method is provided, which can be executed by a sending-end device. In the case where no special description is given, the sending-end device in the present application can refer to the sending-end device itself (for example, a network device or a terminal device), a component (for example, a processor, a chip, or a chip system) in the sending-end device, or a logic module or software capable of realizing all or part of the functions of the sending-end device.

[0006] The method comprises: obtaining A information bits and a number n of parity check PC bits PC , the A information bits comprising K payload bits and L cyclic redundancy check CRC bits, K, L and n PC are positive integers; generating a first bit sequence, the first bit sequence comprising N bits, the N bits comprising the A information bits and n PC PC bits, the A information bits and n PC PC bits being located at (A+n PC ) positions with the highest sequence reliability in the first bit sequence, wherein N is a power of 2, n is a positive integer, n PC PC positions satisfying a first condition and a second condition, the first condition being that minimum row weights corresponding to A positions where the A information bits are located are not less than minimum row weights corresponding to (A+n PC ) positions with the highest sequence reliability in the first bit sequence, wherein each position corresponds to a row weight, and the second condition being that a kth highest position number in n PC position numbers corresponding to the n PC PC positions is greater than or equal to a kth highest position number in n PC position numbers corresponding to a third position set S3, the third position set S3 comprising n PC positions with the lowest sequence reliability in the (A+n PC ) positions with the highest sequence reliability, and 1≤k≤n PC ; performing polar encoding on the first bit sequence to obtain a codeword sequence; and outputting the codeword sequence.

[0007] It can be understood that how the A information bits and the n PC PC bits are placed, the A information bits and the n PC PC bits are always located at (A+n PC ) positions with the highest sequence reliability in the first bit sequence, and remaining N-(A+n PC ) positions are used to place frozen bits.

[0008] It can also be understood that the row weight is an engineering index reflecting the quality of a code spectrum, but is not equivalent to the code spectrum (the better the code spectrum, the stronger the error correction capability of the code), since the process of calculating the code spectrum is very complex and cannot be directly used as an index for engineering construction. Therefore, the first condition can also be understood as the code spectrum corresponding to the positions where the A information bits in the first bit sequence are located being not worse than a native code spectrum, the native code spectrum being a code spectrum corresponding to the A information bits being located at (A) positions with the highest sequence reliability in the first bit sequence when there are no PC bits. In the present application, n PCThe placement of the PC bits is determined by the following condition: as long as the minimum row weight corresponding to the positions of the A information bits does not change or increase compared to the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence, then the n bits of the first bit sequence are considered to be... PC The PC positions satisfy the first condition.

[0009] It can also be understood that the larger the position number of the PC bit, the wider the check range of the PC bit. In this application, regardless of n PC How to place the PC bits, as long as n in the first bit sequence PC The test range corresponding to each PC bit is no worse than that of n when the first PC bit is placed. PC The test range corresponding to each PC bit, the first PC placement method refers to placing n bits... PC The PC bits are placed in the first bit sequence, where the sequence reliability is highest (A+n). PC The nth position with the lowest sequence reliability among ) positions PC At position n, it is considered that the first bit sequence is n PC The PC positions satisfy the second condition.

[0010] Secondly, a communication method is provided, which can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the receiving device.

[0011] The method includes: acquiring a symbol sequence; determining, based on the symbol sequence, to place A information bits and n at N positions in a first bit sequence. PC The log-likelihood ratio (LLR) corresponding to the position of each check bit (PC bit), wherein the A information bits include K payload bits and L cyclic redundancy check (CRC) bits, and the A information bits and the n PC The PC bits are located in the first bit sequence with the highest sequence reliability (A+n). PC At positions ), where N is 2 to the power of n, and K, L, and n PC All are positive integers, where n is placed. PC n PC bits PC The PC positions satisfy the first and second conditions. The first condition is that the minimum row weight corresponding to the A positions where the A information bits are located is not less than the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence. Each position corresponds to one row weight. The second condition is that the n... PC n corresponding to each PC position PCthe kth highest position number in the n PC position number, the second position set S3 indicates the n PC positions with the lowest sequence reliability in the n PC positions with the highest sequence reliability, 1≤k≤n PC ; obtaining S decoding paths with the minimum path metric value PM corresponding to the positions before the ith PC position, wherein the ith PC position is any position in the n PC PC positions, the PM of the S decoding paths is determined based on the LLRs corresponding to the positions before the ith PC position; if a first value of the ith PC position corresponding to a first decoding path is different from a second value of the ith PC position, increasing the PM of the first decoding path, wherein the first decoding path is any path in the S paths, the first value is determined based on the decoding result corresponding to the first decoding path and the PC check relation corresponding to the ith PC position, and the second value is the hard decision result of the LLR corresponding to the ith PC position; if the first value of the ith PC position corresponding to the first decoding path is the same as the second value of the ith PC position, keeping the PM value of the first decoding path unchanged; continuing decoding based on the symbol sequence and the S decoding paths until the final S decoding paths with the minimum PM are obtained by completing the decoding of the symbol sequence; obtaining the first bit sequence, the first bit sequence being determined based on the decoding result of the decoding path with the minimum PM in the final S decoding paths with the minimum PM.

[0012] The beneficial effects of the second aspect are described in the description of the first aspect, which will not be repeated here.

[0013] In some implementations of the first aspect or the second aspect, n PCThe first PC position of the three PC positions is determined based on the minimum row weight corresponding to the second position set S2 and the row weight corresponding to the first candidate position, the first PC position being the first determined PC position of the three PC positions, wherein the first candidate position is the position with the highest sequence reliability in the third set S3, the second position set S2 includes A positions with the highest sequence reliability in the first bit sequence, if the row weight corresponding to the first candidate position is smaller than the minimum row weight corresponding to the second position set S2, the first candidate position is taken as the first PC position, if the row weight corresponding to the first candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, the position with the largest position number or the highest sequence reliability in the fourth position set S4 is taken as the first PC position, the fourth position set S4 includes positions in the first position set S1 with the minimum row weight equal to the minimum row weight of the second position set S2, and the first position set S1 includes the second position set S2 and the first candidate position.

[0014] It can be understood that blindly expanding the checking range of the PC bit may cause the native code spectrum to deteriorate. Therefore, in order to improve the native code spectrum as much as possible when there is no PC bit, and to make the PC bit checking range as wide as possible, a compromise between the checking range and the row weight is needed to determine the PC position. The above technical solution takes n PC As an example, the implementation of the compromise determination of the first PC position is given when n

[0015] In some implementations of the first aspect or the second aspect, the second PC position of the three PC positions is determined based on the minimum row weight corresponding to the second position set S2 after the first update and the row weight corresponding to the second candidate position, the second PC position being the second determined PC position of the three PC positions, wherein the second candidate position is the position with the second highest sequence reliability in the third set S3, the second position set S2 after the first update is the position set corresponding to the first position set S1 after the first PC position is deleted, if the row weight corresponding to the second candidate position is smaller than the minimum row weight corresponding to the second position set S2 after the first update, the second candidate position is taken as the second PC position, if the row weight corresponding to the second candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 after the first update, the position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as the second PC position, the fifth position set S5 includes positions in the first position set S1 after the first update with the minimum row weight equal to the minimum row weight of the second position set S2 after the first update, and the first position set S1 after the first update includes the second position set S2 after the first update and the second candidate position.

[0016] The above technical solution takes n PCFor example, when n

[0017] In some implementations of the first aspect or the second aspect, the third PC position is determined based on the minimum row weight corresponding to the second position set S2 after the second update and a row weight corresponding to a third candidate position, the third PC position being the third determined PC position among the n

[0018] The above technical solutions are based on n PC For example, when n

[0019] In some implementations of the first aspect or the second aspect, the i-th PC position among the n PC PC positions is determined based on the minimum row weight corresponding to the second position set S2 after the i-th round and a row weight corresponding to an i-th candidate position in the third position set, the i-th candidate position being an i-th highest sequence reliability position in the third position set S3, the n PC PC positions being determined in turn as a PC position based on the sequence reliability from high to low, the n PC The first PC position among the n PC-1; If the row weight corresponding to the i-th candidate position is less than the minimum row weight corresponding to the second position set S2 in the i-th round, the i-th candidate position is taken as the i-th PC position. If the row weight corresponding to the i-th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 in the i-th round, the position with the largest position number or the highest sequence reliability in the fourth position set S4 is taken as the i-th PC position. The fourth position set S4 includes the position in the first position set S1 in the i-th round whose row weight is equal to the minimum row weight of the second position set S2 in the i-th round. The first position set S1 in the i-th round includes the second position set S2 in the i-th round and the i-th candidate position; n PC The (i+1)th PC position is determined based on the row weight of the second position set S2 in the (i+1)th round and the row weight of the (i+1)th candidate position. The second position set S2 in the (i+1)th round includes all positions remaining in the first position set in the i-th round except for the ith PC position. The (i+1)th candidate position is the position with the (i+1)th highest sequence reliability in the third position set S3. If the row weight corresponding to the (i+1)th candidate position is less than the minimum row weight corresponding to the second position set S2 in the (i+1)th round, the (i+1)th candidate position is selected as the... For the (i+1)th PC position, if the row weight corresponding to the (i+1)th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the (i+1)th round, the position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as the (i+1)th PC position. The fifth position set S5 includes the position in the first position set S1 of the (i+1)th round with the minimum row weight equal to the minimum row weight of the second position set S2 of the (i+1)th round. The first position set S1 of the (i+1)th round includes the second position set S2 of the (i+1)th round and the (i+1)th candidate position.

[0020] The above technical solution provides a method for determining the PC position by compromising between the check range and line weight. It can maximize the original code spectrum when PC bits are absent while simultaneously expanding the PC bit check range. In this solution, n needs to be determined sequentially. PC There are n PC positions, and the previous PC position affects the determination of the next PC position. This implementation can be viewed as determining n positions serially. PC The method of PC location.

[0021] In some implementations of the first or second aspect, n PC The PC positions are based on the minimum row weight corresponding to the second position set S2 and n in the third position set S3. PC The row weight corresponding to each position is determined. The second position set S2 includes the A positions with the highest sequence reliability in the first bit sequence. If the row weight corresponding to m1 positions in the third position set S3 is less than the minimum row weight corresponding to the second position set S2, then m1 positions are used as PC positions, where 1 ≤ m1 ≤ n.PC If the row weight corresponding to the m2 positions in the third position set S3 is greater than or equal to the minimum row weight corresponding to the second position set S2, the m2 positions with the largest position number or the m2 positions with the highest sequence reliability in the fourth position set S4 are PC positions, the fourth position set S4 includes positions in the first position set S1 with the minimum row weight equal to the second position set S2, the first position set S1 includes the second position set S2 and the third position set S3, and m1+m2=n PC .

[0022] The technical solution above gives another implementation mode of determining PC positions between the check range and the row weight, which can make the PC bit check range as wide as possible while improving the native code spectrum as much as possible when there is no PC bit. In this technical solution, n PC PC positions are determined at the same time, and this implementation mode can be regarded as a mode of determining n PC PC positions in parallel.

[0023] In some implementation modes of the first aspect or the second aspect, the n PC PC positions are determined based on the minimum row weight corresponding to the second position set S2 and the row weight corresponding to the n PC positions in the third position set S3, wherein the second position set S2 includes A positions with the highest sequence reliability in the first bit sequence, if the row weight corresponding to the i-th position in the third position set S3 is less than the minimum row weight corresponding to the second position set S2, the i-th position is a PC position, 1≤i≤n PC If the row weight corresponding to the i-th position in the third position set S3 is greater than or equal to the minimum row weight corresponding to the second position set S2, the position with the largest position number or the position with the highest sequence reliability in the fifth position set S5 is a PC position, wherein the fifth position set S5 is the remaining positions in the fourth position set S4 except the PC positions that have been determined, and the fourth position set includes positions in the first position set S1 with the minimum row weight equal to the second position set S2, and the first position set S1 includes the second position set S2 and the third position set S3.

[0024] The technical solution above gives another implementation mode of determining PC positions between the check range and the row weight, which can make the PC bit check range as wide as possible while improving the native code spectrum as much as possible when there is no PC bit. This implementation mode can be regarded as another mode of determining n PC PC positions in parallel.

[0025] In some implementation modes of the first aspect or the second aspect, the n PC PC positions are the n PCOne position, or n PC The PC position is n, which has the highest sequence reliability or the largest position number in the first bit sequence. PC One position.

[0026] In some implementations of the first or second aspect, A information bits are located in the sequence with the highest sequence reliability (A+n) of the first bit sequence. PC ) positions excluding n PC The remaining A positions are outside of the PC positions.

[0027] In some implementations of the first or second aspect, the method further includes: based on n PC The PC check relationship corresponding to each PC position is determined. PC The value of each PC bit.

[0028] Thirdly, a communication method is provided, which can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0029] The method includes: obtaining A information bits and the number n of parity check (PC) bits. PC A information bits include K payload bits and L cyclic redundancy check (CRC) bits, where K, L, and n are... PC All are positive integers; generate the first bit sequence, which consists of N bits, including A information bits and n. PC One PC bits, A information bits, and n PC The PC bits are located in the first bit sequence with the highest sequence reliability (A+n). PC In ) positions, where N is 2 to the power of n, and n is a positive integer.

[0030] n PC The i-th PC position is determined based on the minimum row weight corresponding to the second position set S2 in the i-th round and the row weight of the i-th candidate position in the third position set. The i-th candidate position is the position with the highest sequence reliability in the third position set S3, and the n-th candidate position in the third position set S3... PC Each position is selected as a candidate position based on its sequence reliability, from highest to lowest, to determine a PC position. PCThe first PC position in the PC positions is determined based on a row weight of a second position set S2 of the first round and a row weight of a first candidate position, the second position set S2 of the first round including A positions with the highest sequence reliability in the first bit sequence, and the first candidate position being a position with the highest sequence reliability in the third position set S3, 1≤i≤n PC -1,

[0031] If the row weight corresponding to the ith candidate position is less than the minimum row weight corresponding to the second position set S2 of the ith round, the ith candidate position is taken as the ith PC position,

[0032] If the row weight corresponding to the ith candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the ith round, a position with the largest position number or the highest sequence reliability in the fourth position set S4 is taken as the ith PC position, the fourth position set S4 including positions with the row weight equal to the minimum row weight of the second position set S2 of the ith round in the first position set S1 of the ith round, and the first position set S1 of the ith round including the second position set S2 of the ith round and the ith candidate position;

[0033] n PC The ith+1 PC position in the PC positions is determined based on a row weight of a second position set S2 of the ith+1 round and a row weight of an ith+1 candidate position, the second position set S2 of the ith+1 round including positions other than the ith PC position in the first position set S1 of the ith round, and the ith+1 candidate position being a position with the ith+1 highest sequence reliability in the third position set S3,

[0034] If the row weight corresponding to the ith+1 candidate position is less than the minimum row weight corresponding to the second position set S2 of the ith+1 round, the ith+1 candidate position is taken as the ith+1 PC position,

[0035] If the row weight corresponding to the ith+1 candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the ith+1 round, a position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as the ith+1 PC position, the fifth position set S5 including positions with the row weight equal to the minimum row weight of the second position set S2 of the ith+1 round in the first position set S1 of the ith+1 round, and the first position set S1 of the ith+1 round including the second position set S2 of the ith+1 round and the ith+1 candidate position;

[0036] The first bit sequence is polarized to obtain a code word sequence; and the code word sequence is output.

[0037] In a fourth aspect, a communication method is provided, which can be performed by a transmitting device. In the present application, the "transmitting device" can refer to the transmitting device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system) in the transmitting device, or a logic module or software capable of realizing all or part of the functions of the transmitting device.

[0038] The method comprises: obtaining A information bits and a number n of parity check PC bits PC , the A information bits comprising K payload bits and L cyclic redundancy check CRC bits, K, L, and n PC are positive integers; generating a first bit sequence, the first bit sequence comprising N bits, the N bits comprising the A information bits and the n PC PC bits, the A information bits and the n PC PC bits being located at (A+n PC ) positions with the highest sequence reliability in the first bit sequence, wherein N is a power of 2, n is a positive integer,

[0039] n PC PC positions are determined based on a minimum row weight corresponding to a second position set S2 and row weights corresponding to n PC positions in a third position set S3, wherein the second position set S2 comprises A positions with the highest sequence reliability in the first bit sequence,

[0040] If m1 positions in the third position set S3 correspond to row weights smaller than the minimum row weight corresponding to the second position set S2, the m1 positions are taken as the PC positions, 1≤m1≤n PC ,

[0041] If m2 positions in the third position set S3 correspond to row weights greater than or equal to the minimum row weight corresponding to the second position set S2, m2 positions with the largest position number or the highest sequence reliability in a fourth position set S4 are taken as the PC positions, the fourth position set S4 comprising positions in the first position set S1 with row weights equal to the minimum row weight of the second position set S2, the first position set S1 comprising the second position set S2 and the third position set S3, wherein m1+m2=n PC ;

[0042] Polar encoding the first bit sequence to obtain a codeword sequence; and outputting the codeword sequence.

[0043] In a fifth aspect, a communication method is provided, which can be performed by a transmitting device. In the present application, the "transmitting device" can refer to the transmitting device itself (e.g., a network device, a terminal device), a component (e.g., a processor, a chip, or a chip system) in the transmitting device, or a logic module or software capable of realizing all or part of the functions of the transmitting device.

[0044] The method comprises: obtaining A information bits and a number n of parity check PC bits PC , the A information bits comprising K payload bits and L cyclic redundancy check CRC bits, K, L and n PC being positive integers; generating a first bit sequence, the first bit sequence comprising N bits, the N bits comprising the A information bits and the n PC PC bits, the A information bits and the n PC PC bits being located at (A+n PC ) positions with the highest sequence reliability in the first bit sequence, wherein N is a power of 2, n is a positive integer,

[0045] n PC PC positions being determined based on a minimum row weight corresponding to a second position set S2 and row weights corresponding to n PC positions in a third position set S3, wherein the second position set S2 comprises A positions with the highest sequence reliability in the first bit sequence,

[0046] if an i-th position in the third position set S3 corresponds to a row weight smaller than the minimum row weight corresponding to the second position set S2, the i-th position is taken as a PC position, 1≤i≤n PC ,

[0047] if an i-th position in the third position set S3 corresponds to a row weight greater than or equal to the minimum row weight corresponding to the second position set S2, a position with the largest position number or the highest sequence reliability in a fifth position set S5 is taken as a PC position, wherein the fifth position set S5 is a set of positions remaining in a fourth position set S4 except the PC positions already determined, the fourth position set S4 comprising positions in a first position set S1 with a row weight equal to the minimum row weight of the second position set S2, the first position set S1 comprising the second position set S2 and the third position set S3;

[0048] polar encoding the first bit sequence to obtain a codeword sequence; and outputting the codeword sequence.

[0049] In a sixth aspect, a communication apparatus is provided. The apparatus is configured to perform the method in any one of the preceding aspects or implementation manners. Specifically, the apparatus can include units and / or modules for performing the method in any one of the preceding aspects or implementation manners, such as a processing unit and / or a transceiving unit.

[0050] In an implementation manner, the apparatus is a sending device or a receiving device. When the apparatus is the sending device or the receiving device, the transceiving unit can be a transceiver, or an input / output interface, or a communication interface; and the processing unit can be at least one processor. Optionally, the transceiver is a transceiving circuit. Optionally, the input / output interface is an input / output circuit.

[0051] In another implementation manner, the apparatus is a chip, a chip system or a circuit for the sending device or the receiving device. When the apparatus is the chip, the chip system or the circuit for the sending device or the receiving device, the transceiving unit can be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or related circuit, etc. on the chip, the chip system or the circuit; and the processing unit can be at least one processor, a processing circuit or a logic circuit, etc.

[0052] In a seventh aspect, a communication apparatus is provided. The apparatus includes a memory configured to store a program; and at least one processor configured to execute the computer program or instructions stored in the memory to perform the method in any one of the preceding aspects or implementation manners.

[0053] In an implementation manner, the apparatus is a sending device or a receiving device.

[0054] In another implementation manner, the apparatus is a chip, a chip system or a circuit for the sending device or the receiving device.

[0055] In an eighth aspect, a communication apparatus is provided. The apparatus includes at least one processor and a communication interface. The at least one processor is configured to acquire, through the communication interface, a computer program or instructions stored in a memory, to perform the method in any one of the preceding aspects or implementation manners. The communication interface can be implemented by hardware or software.

[0056] In an implementation manner, the apparatus further includes the memory.

[0057] In a ninth aspect, a processor is provided. The processor is configured to perform the method in the preceding aspects.

[0058] For the sending and obtaining / receiving operations involved by the processor, if no special description is made, or if it does not conflict with the actual role or internal logic in the related description, it can be understood as the processor output and receive, input and other operations, and can also be understood as the sending and receiving operations performed by the radio frequency circuit and the antenna, and the present application does not limit this.

[0059] In a tenth aspect, a computer readable storage medium is provided, which stores program codes for execution by a device, and the program codes comprise codes for executing the method provided in any one of the above aspects or implementation manners thereof.

[0060] In an eleventh aspect, a computer program product containing instructions is provided, which, when executed on a computer, causes the computer to execute the method provided in any one of the above aspects or implementation manners thereof.

[0061] In a twelfth aspect, a chip is provided, which comprises a processor and a communication interface, and the processor reads instructions stored on a memory through the communication interface and executes the method provided in any one of the above aspects or implementation manners thereof. The communication interface can be implemented by hardware or software.

[0062] Optionally, as an implementation manner, the chip further comprises a memory, and the memory stores a computer program or instructions, and the processor is configured to execute the computer program or instructions stored on the memory, and when the computer program or instructions are executed, the processor is configured to execute the method provided in any one of the above aspects or implementation manners thereof.

[0063] When the method provided in the present application is executed by a chip, the present application does not limit the number of chips for specifically implementing the method of the present application, for example, the method can be executed by one chip, or two or more chips. Moreover, when the number of chips for implementing the method of the present application is two or more, the chips are not limited to the same manufacturer, and can be different manufacturers.

[0064] In a thirteenth aspect, a communication system is provided, which comprises at least one of the above-mentioned sending device or receiving device. BRIEF DESCRIPTION OF DRAWINGS

[0065] Figure 1 is a schematic diagram of a network architecture applicable to embodiments of the present application.

[0066] Figure 2 is a schematic diagram of an information transmission process.

[0067] Figure 3 is a schematic diagram of 8*8 Polar code encoding.

[0068] Figure 4 is a schematic diagram of SC decoding.

[0069] Figure 5 Binary tree diagram for Polar code SC decoding.

[0070] Figure 6 Binary tree diagram for Polar code SCL-2 decoding.

[0071] Figure 7 Fig. 7 is a schematic flow chart of a communication method 700 provided by the present application.

[0072] Figures 8 to 10 Fig. 8 is a schematic diagram of the code spectrum corresponding to Table 3 to Table 5, respectively.

[0073] Figure 11 Fig. 9 is a schematic block diagram of a communication apparatus 1000 provided by an embodiment of the present application.

[0074] Figure 12 Fig. 10 is a schematic block diagram of a communication apparatus 1100 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0075] In order to understand the embodiments of the present application, the following points are explained before the embodiments of the present application are introduced.

[0076] "Indicative of" or "indicate" can include both direct and indirect indication, or "indicative of" or "indicate" can explicitly and / or implicitly indicate. The first, second, etc. various numerical designations are only for the convenience of description and do not limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc. "Predefined" can be implemented by pre-storing corresponding codes, tables or other means for indicating relevant information in the device, and the specific implementation manner is not limited in the present application. The "protocol" referred to can refer to a standard protocol in the communication field, for example, can include a long term evolution (LTE) protocol, a new radio (NR) protocol, and a protocol applied in a future communication system, and the present application is not limited thereto. The words "example", "for example", "exemplary", "as an example", etc. are used to indicate an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. The terms "include", "contain", "have" and their variants mean "including but not limited to", unless otherwise specifically emphasized. "At least one" refers to one or more, and "multiple" refers to two or more. "At most one" refers to one or 0. "And / or", which describes the association relationship of the associated objects, means that there can be three kinds of relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can mean a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple. The description related to the network element A sending a message, information or data to the network element B, and the network element B receiving the message, information or data from the network element A, is intended to indicate which network element the message, information or data is intended to send to, and does not limit whether they are directly sent or indirectly sent via other network elements. "When", "in the case of", "if" and "if" and other descriptions all refer to the objective situation in which the device will make corresponding processing, and are not limited by time, and do not require the device to have a judgment action when implemented, nor does it mean that there are other limitations.

[0077] In addition, the network architecture and service scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0078] The communication system to which the embodiments of the present application can be applied will be described below.

[0079] The embodiments of the present application can be applied to various communication systems, including but not limited to: a 5th generation (5G) system, an LTE system, a long term evolution-advanced (LTE-A) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as a 6th generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), an internet of things (IoT) communication system, a narrow band-internet of things (NB-IoT) system, or other communication systems. In addition, it can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and 3rd generation partnership project (3GPP) related communication systems, etc., without limitation.

[0080] The communication system to which the embodiments of the present application can be applied can include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device can be a terminal device, and the other can be a network device. Optionally, the transmitting end device and the receiving end device can both be terminal devices. Optionally, the transmitting end device and the receiving end device can both be network devices.

[0081] Figure 1 is a schematic diagram of a network architecture to which embodiments of the present application are applicable. As shown in Figure 1 embodiments of the present application are applicable to both uplink data transmission and downlink data transmission. Figure 1 In the following, only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting terminal device is the terminal device and the receiving terminal device is the network device; conversely, in downlink data transmission, the transmitting terminal device is the network device and the receiving terminal device is the terminal device. In addition, the applicability of embodiments of the present application in other communication scenarios is not limited, for example, it can also be applied to sidelink communication.

[0082] The terminal device of the present application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, unmanned aerial vehicle, wireless communication device, user agent or user equipment, etc. The terminal device in the embodiments of the present application can refer to a device that provides voice and / or data connectivity to users, and can be used to connect people, things and machines, such as handheld devices with wireless connection function, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc.

[0083] The network device of the present application can be a device with wireless transceiving function, which can be a device providing wireless communication function service, usually located at the network side, including but not limited to next generation base station (gNodeB, gNB) in 5G system, base station in sixth generation mobile communication system, base station in future mobile communication system, or access node in wireless fidelity (WiFi) system, evolved node B (eNB) in long term evolution (LTE) system, radio network controller (RNC), node B (NB), base station controller (BSC), home base station (such as home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellite, unmanned aerial vehicle, etc. In one network structure, the network device can include a centralized unit (CU) node, or include a distributed unit (DU) node, or be a RAN device including CU node and DU node, or be a RAN device including control plane CU node and user plane CU node, and DU node, or the network device can also be a wireless controller in cloud radio access network (CRAN) scenario, relay station, vehicle-mounted device, wearable device, etc. In addition, the base station can be a macro base station, micro base station, relay node, donor node or combination thereof. The base station can also refer to a communication module, modem or chip for setting in the foregoing device or apparatus. The base station can also be a mobile switching center and a device assuming base station function in D2D, V2X, M2M communication, network side device in 6G network, device assuming base station function in future communication system, etc. The base station can support networks of the same or different access technologies, without limitation.

[0084] Unless otherwise specified, the apparatuses used to implement the functions of the terminal device or the network device in the present application can refer to the terminal device or the network device itself, or can refer to an apparatus capable of supporting the terminal device or the network device to implement the functions, such as a chip system or a chip, specifically, a system on a chip (SoC), a Modem. The apparatus can be installed in the terminal device or the network device. In the embodiments of the present application, the chip system can be composed of a chip, or can include a chip and other discrete devices.

[0085] It should also be noted that some embodiments in the present application take the 5G system as an example to introduce specific scheme details. It can be understood that when the scheme is used in other communication systems, for example, an LTE system, or a future communication system, the messages, channels or information in the scheme can be replaced by messages, channels or information capable of realizing corresponding functions in other communication systems, and the present application does not limit this.

[0086] In addition, the embodiments of the present application can be applied to various application scenarios, such as a high throughput scenario, a high reliability scenario, a low latency scenario, a high reliability low latency scenario, or a low power consumption scenario. Among them, the high throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, and the high reliability low latency scenario can be, for example, an ultra reliable low latency communication (URLLC) scenario, and the low power consumption scenario can be, for example, an M2M scenario, an MTC scenario, or an IoT scenario.

[0087] Figure 2 is a schematic diagram of an information transmission process. As shown in Figure 2 , information is sent by a signal source, processed by signal source encoding, channel encoding, modulation, air interface transmission, demodulation, channel decoding, signal recovery, and reaches a signal sink, completing the transmission of information from the signal source to the signal sink. Among them, Figure 2 The processing shown in the upper layer (including signal source encoding, channel encoding and modulation, etc.) is performed at the sending end device, and the processing shown in the lower layer (including demodulation, channel decoding, signal recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly involve Figure 2 signal source encoding, channel encoding, channel decoding and signal recovery shown in

[0088] At present, Polar code is the first channel coding scheme that can be strictly proved to "reach" the Shannon channel capacity, and has the characteristics of good error correction performance and low decoding complexity. At present, Polar code has been determined by 3GPP to be the coding scheme of the control channel in the 5G eMBB scenario (uplink / downlink). The encoding, construction and decoding process of Polar code are briefly introduced below.

[0089] Figure 3 is a schematic diagram of Polar code encoding with length 8. The encoding process includes several polar kernel operations (the polar kernel is filled with gray color in the schematic), and the polar kernel multiplies two input bits with two output bits. It can be seen that the Polar code is recursively constructed, in which the Polar code with length 8 can be obtained by coupling 2 Polar codes with length 4 (corresponding to the two dashed boxes in the figure), and the Polar code with length 4 can be obtained by coupling 2 Polar codes with length 2.

[0090] It can be understood that the N positions corresponding to the N to-be-encoded bits before Polar code encoding have different reliabilities. Among the N positions, the A positions with the highest reliability are used to place A data bits in the to-be-encoded bits, and the remaining N-A positions are used to place frozen bits. The bits on the frozen bit positions are usually 0, and the frozen bits are known at both ends of the actual transmission. In this application, the positions carrying the A data bits can be referred to as data bit positions, and the positions carrying the frozen bits can be referred to as frozen bit positions. For example, as shown in Figure 3 , N = 8, 8 positions are used to carry 8 to-be-encoded bits, and the 8 to-be-encoded bits are u0-u7 on the leftmost side. Among the to-be-encoded bits, there are 4 data bits (i.e., u7, u6, u5, and u3), and the data bit positions for placing the 4 data bits are the four bit positions with the highest reliability. The remaining 4 positions place frozen bits (u4, u2, u1, and u0), and the frozen bit positions for placing the 4 frozen bits are the four bit positions with the lowest reliability. As shown in Figure 3 , after encoding, the 8 codeword bits on the rightmost side 01010101 are obtained, which are denoted as c0-c7. The sending end device sends c0-c7 to the channel W.

[0091] For Polar code decoding, a serial cancellation decoding (SC) algorithm can be used. In SC, the decoding result is directly determined by hard decision. Specifically, the log-likelihood ratio (LLR) of the data bits is calculated step by step. For a data bit, if the LLR > 0, the bit is determined to be 0, and if the LLR < 0, the bit is determined to be 1. For a frozen bit, the bit is set to 0 regardless of the LLR. Figure 4is a simplest SC decoding diagram. There are 8 computing nodes in the diagram, including 4 f nodes and 4 g nodes. The calculation of the f node requires 2 LLR inputs on the right side, and the calculation of the g node requires 2 LLR inputs on the right side and 1 "partial sum" input on the top. It can be understood that the output item can only be calculated after the input item is calculated. According to the above rules, Figure 4 the SC decoding process is to calculate the 8 nodes in order from the right side of the received signal, and the order of the obtained decoding bits is ①→②→③→④. From another point of view, since each information bit only has two values of 0 and 1, the SC decoding of the Polar code can be abstracted as a binary tree search problem, Figure 5 the binary tree diagram of the SC decoding of the Polar code is shown in FIG. 2. Each layer of the binary tree represents the judgment result of an information bit. The binary tree can represent 0 to the left and 1 to the right. The 4 decoding bits correspond to 2 4 paths in total. The paths with darker colors in the figure are the decoding paths obtained by hard decision.

[0092] It is proved that the Polar code can reach the infinite-length capacity based on the SC algorithm. However, the performance of SC is not satisfactory in the finite length. In view of this problem, the industry proposes a serial cancellation list (SCL) decoding algorithm and a cyclic redundancy check (CRC) aided successive cancellation list (CA-SCL) decoding algorithm to improve the performance of the Polar code. The two algorithms are introduced below.

[0093] The SCL algorithm is an extension of the SC algorithm. Figure 6 The binary tree diagram of the SCL-2 decoding of the Polar code is shown in FIG. 3. As shown in Figure 6 the SCL algorithm does not directly determine the decoding result by hard decision in the middle process, but saves the decoding results corresponding to 0 and 1 into 2 branch decoding paths. Through the above method, if the SCL algorithm saves List decoding paths in total, and finally selects the correct path through the path metric (PM), the List paths can be sorted in order of PM from small to large. The decoding path that is closer to the front in the order is more likely to be the correct codeword. This way of selecting the path without CRC is the way that the traditional SCL decoding outputs the final codeword, that is, the path with the optimal PM (i.e., the first path with the smallest PM) is output as the final codeword. The CA-SCL will use CRC to select the correct path from the first path, thereby obtaining better error correction performance than the SCL. Figure 6The two paths with darker color are the two paths of SCL2 output. The SCL decoder outputs the path with smaller PM (more like the correct codeword) as the final decoding result. The CA-SCL first tests the path with the smallest PM with CRC. If the path does not pass the CRC test, the CA-SCL continues to test the second path with the second smallest PM until a path that passes the CRC test is found as the final decoding result. If all paths do not pass the CRC test, the decoding fails. However, the CA-SCL decoding algorithm using CRC to select the path loses the error detection capability of CRC. The error detection probability of a CRC polynomial with length L crc is about 1 / 2 Lcrc , and L crc is the length of the CRC. However, the CA-SCL decoding uses List CRC tests to select the path, and thus the error detection probability of the CRC is multiplied by List and becomes List / 2 Lcrc . Therefore, the CRC path selection in the CA-SCL decoding loses the error detection performance.

[0094] At present, as shown in the background art, a PC-Polar code is proposed. The PC bits in the PC-Polar code can correct the PM of the SCL decoding and improve the probability that the correct decoding path is ranked first. In this application, the PC bits can also be referred to as dynamic frozen bits (the position is from the frozen bit, but the value is not fixed as 0). In this application, the position where the PC bits are placed can be referred to as the dynamic frozen bit position, or the PC position. The application does not make any limitation. The addition of the PC bits can make the correct decoding path more forward, and thus the probability that the first output path is the correct codeword is improved. Therefore, the decoding path does not need to be checked by CRC, thereby saving the number of CRC uses and not losing the error detection capability of CRC. However, the existing placement method of the PC bits does not consider the requirement of determining the correct decoding path based on the PC bits, and thus the decoding performance based on the PC bits needs to be improved.

[0095] Therefore, the present application provides a communication method which can effectively solve the above technical problems. The method embodiments provided in the present application are described below.

[0096] Figure 7 is a schematic flowchart of a communication method 700 provided by the present application. The method includes the following steps.

[0097] It can be understood that the method 700 can be executed by a sending terminal device and a receiving terminal device, and the "sending terminal device" or the "receiving terminal device" can refer to the sending terminal device or the receiving terminal device itself, or can refer to an apparatus capable of supporting the sending terminal device or the receiving terminal device to implement the function, and for the convenience of description, the sending terminal device and the receiving terminal device are used for description below. The sending terminal device can be a terminal device or a network device, and the receiving terminal device can be a terminal device or a network device.

[0098] S710, the sending terminal device acquires A information bits and the number n of PC bits PC , wherein the A information bits include K payload bits and L CRC bits, K, L and n PC are positive integers.

[0099] It can be understood that the value of the n PC PC bits is determined based on the PC position where each PC bit is located and the corresponding PC check relationship. Therefore, the placement position of the n PC PC bits (that is, the n PC PC positions) needs to be determined first, and then the value of the PC bit at each PC position is determined.

[0100] S720, the sending terminal device generates a first bit sequence, the first bit sequence includes N bits, the N bits include A information bits and n PC PC bits, the A information bits and the n PC PC bits are located at (A+n PC ) positions with the highest sequence reliability in the first bit sequence, N is the mother code length of a Polar code word, N is 2 raised to the power of n, and n is a positive integer.

[0101] It can be understood that no matter how the A information bits and the n Pc PC bits are placed, the A information bits and the n PC PC bits are always located at (A+n PC ) positions with the highest sequence reliability in the first bit sequence, and the remaining N-(A+n PC ) positions are used to place frozen bits, and the sending terminal device and the receiving terminal device both know the value at the frozen position, and the value of the frozen bit can be fixed as 0.

[0102] Optionally, in this application, the sequence reliability can also be replaced by a Gaussian approximate (GA) reliability, and the GA reliability is a reliability calculated based on Gaussian approximation.

[0103] , wherein n PCThe A PC positions satisfy the first condition and the second condition. The first condition and the second condition are as follows:

[0104] (1) The first condition is that the minimum row weight corresponding to the A positions where the A information bits are located is not less than the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence, where each position corresponds to a row weight.

[0105] The row weight corresponding to a position can be calculated as follows: the current position number is i, and the binary representation corresponding to the current position is (b0, b1, b2,.., b m-1 , then the row weight corresponding to the current position i is For example, the current position is 3, and the binary representation corresponding to the current position is (0, 1, 1), then the row weight of position 0 is 2 2 = 4; the current position is 7, and the binary representation corresponding to the current position is (1, 1, 1), then the row weight of position 7 is 2 3 = 8.

[0106] It can be understood that the row weight is an engineering index reflecting the quality of the code spectrum, and is not equivalent to the code spectrum (the better the code spectrum, the stronger the error correction capability of the code). Since the process of calculating the code spectrum is very complex, it cannot be directly used as an index for engineering construction. Therefore, the first condition can also be understood as the code spectrum corresponding to the positions where the A information bits are located in the first bit sequence is not worse than the original code spectrum, and the original code spectrum refers to the code spectrum corresponding to the case where the A information bits are placed in the A positions with the highest sequence reliability in the first bit sequence when there are no PC bits.

[0107] In the present application, due to the existence of PC bits, the A information bits and the n PC PC bits are placed in the (A+n PC ) positions with the highest sequence reliability in the first bit sequence. If the n PC PC bits are placed in the n PC positions with the lowest sequence reliability among the (A+n PC ) positions with the highest sequence reliability (hereinafter referred to as the first PC placement mode), the sequence reliability of the positions where the A information bits are located does not change, and the minimum row weight corresponding to the positions where the A information bits are located does not change compared with the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence. If the n PC PC bits are placed in other positions of the (A+n PC ) positions with the highest sequence reliability among the N positions (different from the first PC placement mode), the sequence reliability of the positions where the A information bits are located will be lost, and the minimum row weight corresponding to the positions where the A information bits are located may be larger or smaller or unchanged compared with the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence. Regardless of the n PCThe PC bits are placed only if the minimum row weight corresponding to the positions of the A information bits does not change or become larger than the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence. PC The n PC positions of the first bit sequence satisfy the first condition.

[0108] (2) The second condition is that the n PC PC positions correspond to the kth highest position number in the n PC position numbers, and the third position set indicates the n PC positions with the lowest sequence reliability in the (A+n PC ) positions with the highest sequence reliability. PC

[0109] It can be understood that the larger the position number of the PC bit is, the wider the checking range of the PC bit is. Therefore, the second condition can be understood as the checking range corresponding to the n PC PC bits in the first bit sequence is not worse than the checking range corresponding to the n PC PC bits in the first PC placement mode.

[0110] To illustrate the second condition, n PC = 3, and the position numbers of the 3 PC bits from small to large are {190, 216, 220} in the first PC placement mode. Then, the position numbers of the 3 PC positions corresponding to the first bit sequence are sorted from small to large, only if the 1st position number (the smallest position number) is not less than 190, the 2nd position number is not less than 216, and the 3rd position number (the largest position number) is not less than 220, it is considered that the n PC PC positions of the first bit sequence satisfy the second condition.

[0111] It can be understood that for the first bit sequence with different K values and N values, there can be multiple PC placement modes that satisfy the above first condition and second condition. The following gives the PC placement modes that satisfy the first condition and the second condition based on the first PC placement mode and in combination with different examples.

[0112] Example one, the number of payload bits K = 17, the number of CRC bits L = 6 (then A = 23), the number of PC bits n PC = 3, and the length of the first bit sequence N = 256. Then, the first PC bit placement mode corresponding to this example is shown in Table 1. Table 1 includes 26 (i.e. A+n PCThe 26 position numbers indicate 26 positions with the highest sequence reliability in the first bit sequence, and the sequence reliability decreases from right to left, i.e., the position numbered 256 has the highest sequence reliability, and the position numbered 190 has the lowest sequence reliability. The PC bits are placed in the three positions with the lowest sequence reliability in Table 1, and the CRC bits are placed in the positions with the largest position numbers in the remaining positions.

[0113] Table 1

[0114]

[0115] To further improve the probability that the first decoding path in SCL decoding is a correct codeword, the three PC bits can check as many payload bits as possible. In this embodiment, the PC bits are placed in the three positions with the largest position numbers in the first bit sequence, and all payload bits and CRC bits can be checked. The PC bit placement mode corresponding to this example is shown in Table 2.

[0116] Table 2

[0117]

[0118]

[0119] It can be seen that when the PC bits are placed in the positions with the largest position numbers, the payload bits and the CRC bits are moved forward in turn, the sequence reliability of the positions where the A information bits are located is lost, but the minimum row weight corresponding to the position set composed of the positions where the payload bits and the CRC bits are located does not change compared with the minimum row weight corresponding to the position set composed of the positions where the payload bits and the CRC bits are located in Table 1, and the minimum row weight is still 32 (the row weight corresponding to the position numbered 249). Moreover, the position numbers corresponding to the three PC bits in Table 2 are greater than the position numbers corresponding to the three PC bits in Table 1. In summary, the three PC positions in Table 2 satisfy the first condition and the second condition, i.e., the PC placement mode shown in Table 2 is acceptable.

[0120] It can be understood that the PC bits in Table 1 are placed in the positions with the lowest sequence reliability in Table 1, although the sequence reliability of the payload bits and the CRC bits is not lost, when errors occur in the payload bits and the CRC bits, it is difficult to detect and check the errors through the PC bits, and thus the errors cannot be reflected in the PM, the error decoding path cannot be moved backward, and the probability that the first decoding path is an error path is relatively larger. However, in Table 2, the three PC bits are placed at the end of the first bit sequence, when errors occur in the 17 payload bits and the 6 CRC bits, the three PC bits at the end can detect the errors, so that a penalty value is added to the PM value of the error decoding path, and the ranking of the error decoding path in the List paths is moved backward, so that the probability that the first path is a correct codeword is improved.

[0121] Based on Example 1, in a possible implementation, if n PC PC bits are placed in the position with the largest position number in the position set #1 formed by the A+n PC positions with the highest sequence reliability in the first bit sequence, the minimum row weight corresponding to the position set #2 formed by the positions of the payload bits and the CRC bits (that is, A information bits) is not reduced relative to the minimum row weight corresponding to the position set #3 formed by the positions of the A information bits when the first PC is placed, and then the n PC PC bits can be placed in the position with the largest position number in the position set #1, so that the checking range of the PC bits is the widest (that is, all the payload and CRC bits before the PC bit checking).

[0122] Example 2, the number of payload bits K = 19, the number of CRC bits L = 6 (then A = 25), the number of PC bits n Pc = 3, and the length of the first bit sequence N = 256. The first PC bit placement mode corresponding to this example is shown in Table 3. Table 3 includes 28 (that is, A+n PC ) position numbers and the row weight corresponding to each position. The 28 position numbers indicate the 28 positions with the highest sequence reliability in the first bit sequence, and the sequence reliability decreases from right to left, that is, the position number 256 is the position with the highest sequence reliability, and the position number 243 is the position with the lowest sequence reliability. The PC bits are placed in the three positions with the lowest sequence reliability in Table 3, and the CRC bits are placed in the position with the largest position number in the remaining positions.

[0123] Table 3

[0124]

[0125] In order to further improve the probability that the first decoding path in SCL decoding is the correct codeword, the 3 PC bits need to check as many payload bits as possible. In this embodiment, placing the PC bits in the 3 positions with the largest position numbers in the first bit sequence can check all the payload bits and CRC bits, and the PC bit placement mode corresponding to this example is shown in Table 4.

[0126] Table 4

[0127]

[0128]

[0129] It can be seen that placing the PC bits in the positions with the largest position numbers, the payload bits and CRC bits are moved forward accordingly, the sequence reliability of the positions where the payload bits and CRC bits are located is lost, but the minimum row weight corresponding to the position set constituted by the positions where the payload bits and CRC bits are located does not change compared with the minimum row weight corresponding to the position set constituted by the positions where the payload bits and CRC bits are located in Table 3, and the minimum row weight is still 32, and the position numbers corresponding to the 3 PC bits in Table 4 are greater than the position numbers corresponding to the 3 PC bits in Table 3, respectively. In summary, the 3 PC positions in Table 4 satisfy the first condition and the second condition, that is, the PC placement mode shown in Table 4 is acceptable.

[0130] Based on this example, another possible PC placement mode is given. The sequence reliability of the positions where the payload bits and CRC bits are located in the PC placement mode shown in Table 3 is the highest (i.e. completely no loss of sequence reliability), and at this time the minimum row weight corresponding to the positions where the payload bits and CRC bits are located is 32, and there is only one position with a row weight of 32. If the PC bits are placed in this position with the minimum row weight, the payload bits and CRC bits are moved forward in turn, the minimum row weight corresponding to the payload bits and CRC bits will be improved from 32 to 64, and the PC bit placement mode corresponding to this example is shown in Table 5.

[0131] Table 5

[0132]

[0133] It can be seen that the sequence reliability of the positions where the payload bits and CRC bits are located in Table 5 is lost, but the minimum row weight corresponding to the position set constituted by the positions where the payload bits and CRC bits are located is larger, and the position numbers corresponding to the 3 PC bits in Table 4 are greater than the position numbers corresponding to the 3 PC bits in Table 3, respectively. In summary, the 3 PC positions in Table 5 satisfy the first condition and the second condition, that is, the PC placement mode shown in Table 4 is also acceptable.

[0134] From the above, the PC placement manners shown in Table 4 and Table 5 are both acceptable, but the PC placement manner shown in Table 5 improves the minimum row weight of the position set constituted by the positions of the payload bits and the CRC bits, and the code spectrum becomes better compared with the original code spectrum, improving the error correction capability of the code.

[0135] Figure 8 , Figure 9 and Figure 10 are schematic diagrams of the code spectrums corresponding to Table 3, Table 4 and Table 5 respectively. Among them, Figure 8 , Figure 9 and Figure 10 , the horizontal axis is the code weight, and the vertical axis is the number of codewords with the corresponding code weight. In this example, the PC placement manner shown in Table 4 has a minimum row weight of 32 at the positions of the A information bits, but Figure 9 the code spectrum shown in Table 4 is improved compared with Figure 8 the code spectrum shown in Table 3. In addition, the PC placement manner shown in Table 5 eliminates the positions with a row weight equal to 32 in the position set where the A information bits are located, which is reflected in the code spectrum that Figure 10 the code spectrum shown in Table 5 is better than Figure 8 and Figure 9 the code spectrums shown in Table 3 and Table 4.

[0136] Example Three, the number of payload bits K = 13, the number of CRC bits L = 6 (then A = 19), the number of PC bits n PC = 3, and the length of the first bit sequence N = 128. Then the first PC bit placement manner corresponding to this example is shown in Table 6. Table 6 includes 22 (i.e. A + n PC ) position numbers and the row weight corresponding to each position. The 22 position numbers indicate the 22 positions with the highest sequence reliability in the first bit sequence, where the sequence reliability decreases from right to left, i.e. the position numbered 128 has the highest sequence reliability, and the position numbered 121 has the lowest sequence reliability. The PC bits are placed in the three positions with the lowest sequence reliability in Table 6, and the CRC bits are placed in the position with the largest position number among the remaining positions.

[0137] Table 6

[0138]

[0139] Similarly, in order to further improve the probability that the first decoding path in SCL decoding is the correct codeword, it is necessary to let the 3 PC bits check as many payload bits as possible. In this embodiment, the PC bits are placed in the three positions with the largest position numbers in the first bit sequence, which can check all the payload bits and the CRC bits. Therefore, the PC bit placement manner corresponding to this example is shown in Table 7.

[0140] Table 7

[0141]

[0142] As can be seen, the minimum row weight corresponding to the set of positions formed by the locations of the payload bits and CRC bits (i.e., A information bits) in Table 6 is 32, while the minimum row weight corresponding to the set of positions formed by the locations of the payload bits and CRC bits in Table 7 is 16. The minimum row weight has decreased, which does not meet the first condition. Therefore, the PC placement method shown in Table 7 is unacceptable.

[0143] Based on Example 3, in one possible implementation, if n PC The PC bits are placed in the first bit sequence, with the highest sequence reliability being A+n. PC When the position with the largest position number in position set #1, which consists of positions of A information bits, is in the position, the minimum row weight corresponding to position set #2, which consists of positions of A information bits, is smaller than the minimum row weight corresponding to position set #3, which consists of positions of A information bits, when the first PC placement method is used. Therefore, when n are placed based on the first PC placement method... PC PC bits (i.e., the placement shown in Table 6).

[0144] Based on Example 2, we know that there may be multiple ways to place the PC (Program Counter) bits to satisfy both the first and second conditions. Based on Example 3, we know that simply expanding the check range of the PC bits may degrade the original code spectrum. Therefore, to improve the original code spectrum when PC bits are absent, and to maximize the PC bit check range, a trade-off needs to be made between the check range and line weight to determine the PC position. Several specific methods for determining the PC position through this trade-off are given below.

[0145] Implementation method one, which may include the following steps.

[0146] a) Determine the first position set, which includes the i-th candidate position from the second and third position sets in the i-th round, where 1 ≤ i ≤ n. PC -1.

[0147] Among them, n in the third position set PC Each position is selected as a candidate position based on its sequence reliability, from highest to lowest, to determine a PC position.

[0148] It is understandable that the i-th candidate position is n. PC The position with the highest sequence reliability among the positions. Specifically, the first candidate position is the position with the highest sequence reliability in the third position set, the second candidate position is the position with the second highest sequence reliability in the third position set, and so on, which will not be elaborated here.

[0149] It's understandable; a total of n needs to be determined.PC The first PC position is determined based on the first candidate position and the minimum row weight corresponding to the second position set of the first round.

[0150] b) determining the ith PC position based on the row weight corresponding to the ith candidate position and the minimum row weight corresponding to the second position set of the ith round.

[0151] If the row weight corresponding to the ith candidate position is less than the minimum row weight corresponding to the second position set, the ith candidate position is taken as the ith PC position.

[0152] If the row weight corresponding to the ith candidate position is greater than or equal to the minimum row weight corresponding to the second position set, the position with the maximum position number or the highest sequence reliability in the fourth position set S4 is taken as the ith PC position, wherein the fourth position set S4 includes all positions in the first position set of the ith round with the row weight equal to the minimum row weight of the second position set S2 of the ith round.

[0153] It can be understood that one PC position (i.e., the ith PC position) can be determined in the first position set based on step b). Thereafter, the first position set and the second position set of the ith round need to be updated to obtain the first position set and the second position set required for the (i+1)th round, so as to determine the next PC position (i.e., the (i+1)th PC position). The following continues to be described.

[0154] c) updating the second position set of the ith round to obtain the second position set of the (i+1)th round. The second position set of the (i+1)th round is the position set corresponding to the first position set of the ith round after the ith PC position is deleted.

[0155] It can be understood that the number of positions corresponding to the second position set used in each round of iteration is A.

[0156] d) updating the first position set of the ith round to obtain the first position set of the (i+1)th round. The first position set of the (i+1)th round includes the (i+1)th candidate position in the second position set of the (i+1)th round and the third position set.

[0157] It can be understood that the number of positions corresponding to the first position set used in each round of iteration is A+1.

[0158] e) determining the (i+1)th PC position based on the row weight corresponding to the (i+1)th candidate position and the minimum row weight corresponding to the second position set of the (i+1)th round.

[0159] If the row weight corresponding to the (i+1)th candidate position is less than the minimum row weight corresponding to the second position set of the (i+1)th round, the (i+1)th candidate position is taken as the (i+1)th PC position.

[0160] If the row weight corresponding to the i+1th candidate position is greater than or equal to the minimum row weight corresponding to the second position set of the i+1th round, the position with the largest position number or the highest sequence reliability in the fifth position set is taken as the i+1th PC position, and the fifth position set includes all positions in the first position set of the i+1th round with a row weight equal to the minimum row weight of the second position set S2 of the i+1th round.

[0161] f) repeating the operations in c) to e) to update the first position set and the second position set to be used in the next round until n PC PC positions are determined.

[0162] For the sake of understanding, the following describes the first implementation with n PC = 3.

[0163] (1) The first PC position among the three PC positions is determined based on the minimum row weight corresponding to the second position set of the first round and the row weight corresponding to the first candidate position, and the first PC position is the first determined PC position among the three PC positions.

[0164] The first candidate position is the position with the highest sequence reliability in the third set, and the second position set of the first round includes A positions with the highest sequence reliability in the first bit sequence.

[0165] If the row weight corresponding to the first candidate position is less than the minimum row weight corresponding to the second position set of the first round, the first candidate position is taken as the first PC position; if the row weight corresponding to the first candidate position is greater than or equal to the minimum row weight corresponding to the second position set of the first round, the position with the largest position number or the highest sequence reliability in the fourth position set is taken as the first PC position, and the fourth position set includes all positions in the first position set of the first round with a row weight equal to the minimum row weight of the second position set of the first round, and the first position set of the first round includes the second position set of the first round and the first candidate position.

[0166] (2) The second PC position among the three PC positions is determined based on the minimum row weight corresponding to the second position set of the second round and the row weight corresponding to the second candidate position, and the second PC position is the second determined PC position among the three PC positions.

[0167] The second candidate position is the position with the second highest sequence reliability in the third set, and the second position set of the second round is the position set corresponding to the first position set of the first round after the first PC position is deleted.

[0168] If the row weight corresponding to the second candidate position is less than the minimum row weight corresponding to the second position set of the second round, the second candidate position is taken as the second PC position; if the row weight corresponding to the second candidate position is greater than or equal to the minimum row weight corresponding to the second position set of the second round, the position with the largest position number or the highest sequence reliability in the fifth position set is taken as the second PC position, the fifth position set including all positions in the first position set of the second round with the row weight equal to the minimum row weight of the second position set of the second round, the first position set of the second round including the second position set of the second round and the second candidate position.

[0169] (3) The third PC position in the three PC positions is determined based on the minimum row weight corresponding to the second position set of the third round and the row weight corresponding to the third candidate position, and the third PC position is the third determined PC position in the three PC positions.

[0170] The third candidate position is the position with the lowest sequence reliability in the third set, and the second position set of the third round is the position set corresponding to the first position set of the second round after the second PC position is deleted.

[0171] If the row weight corresponding to the third candidate position is less than the minimum row weight corresponding to the second position set of the third round, the third candidate position is taken as the third PC position; if the row weight corresponding to the third candidate position is greater than or equal to the minimum row weight corresponding to the second position set of the third round, the position with the largest position number or the highest sequence reliability in the sixth position set is taken as the third PC position, the sixth position set including all positions in the first position set of the third round with the row weight equal to the minimum row weight of the second position set of the third round, the first position set of the third round including the second position set of the third round and the third candidate position.

[0172] The pseudo code corresponding to the implementation mode one when n PC = 3 is given below.

[0173] / / used to indicate an added position (i.e. used to indicate a candidate PC position in the third set), initialize the value, which is equivalent to i in the implementation mode one

[0174] n PC = 3; / / initialize the total number of target PC bits

[0175] S = []; / / initialize the PC position set S

[0176] According to the NR sequence reliability sequence and the rate matching puncturing mode, the sequence reliability of each position is determined, the sequence B is a sequence with a length of N, N elements in the sequence B are N position numbers, each position number indicates a position, and the positions indicated by the N elements are sorted in descending order of sequence reliability, that is, the sequence reliability of the position corresponding to the first element is the lowest, and the sequence reliability of the position corresponding to the last element is the highest.

[0177] weights is a sequence with a length of N, recording the corresponding row weight of each position in the N positions.

[0178] while length(S)<n PC / / If the number of elements in the PC position set is less than 3

[0179] / / Get the set S1 (i.e., the first position set) composed of the current set S2 (i.e., the second position set) and the newly added position (i.e., a candidate PC position in the third set), end indicates the number of the last position of the sequence B, the last position of the sequence B is the position with the highest reliability, end is equal to N, and A is the number of information bits

[0180] S1_weights=weights(S1); / / Get the row weight of all positions in S1

[0181] w_min_new=S1_weights(1); / / Get the row weight corresponding to the newly added position

[0182] S2_weights=weights(S2); / / Get the row weight of set S2

[0183] w_min=min(S2_weights); / / Get the minimum row weight corresponding to set S2

[0184] ifw_min_new<w_min / / If the row weight of the newly added position is less than the minimum row weight corresponding to the current set S2

[0185] newPC=S1(1); / / Take the newly added position as the PC position

[0186] S=[S newPC]; / / Put the newly added position into set S

[0187] else / / If the row weight of the newly added position is greater than or equal to the minimum row weight corresponding to the current set S2

[0188] temp=S1(S1_weights==w_min); / / Select the positions with the minimum row weight in set S1 to form set temp

[0189] newPC = max(temp) ; / / select the largest number position in the set temp as PC position

[0190] S = [S newPC] ; / / put the selected largest number position into the set S

[0191] end

[0192] %

[0193] / / used to indicate the updated new position

[0194] / / update the set S2

[0195] S2 = S1 ; / / copy all elements in S1 to S2

[0196] S2 (S2 == newPC (1) ) = [] ; / / delete the determined PC position from the set S2

[0197] End

[0198] Implementation mode two

[0199] Implementation mode two can be regarded as replacing the largest number criterion in implementation mode one into the highest sequence reliability criterion. Specifically, the difference between implementation mode two and implementation mode one is in steps b) and e). In step b) of implementation mode two, if the row weight corresponding to the i th candidate position is greater than or equal to the minimum row weight corresponding to the second position set, the first position in the second position set is taken as the i th PC position, and the first position is the position with the highest sequence reliability in the position with the minimum row weight in the second position set. Similarly, in step e), if the row weight corresponding to the i + 1 th candidate position is greater than or equal to the minimum row weight corresponding to the updated second position set, the first position in the updated second position set is taken as the i + 1 th PC position, and the first position is the position with the highest sequence reliability in the position with the minimum row weight in the updated second position set.

[0200] The pseudo code corresponding to implementation mode two is given below.

[0201] / / used to indicate a new position (i.e. used to indicate a candidate PC position in the third set), initialize the value, which is equivalent to i in implementation mode one

[0202] n PC = 3 ; / / initialize the total number of target PC bits

[0203] S = [] ; / / initialize the PC position set S

[0204] while length(S) < n PC / / If the number of elements in the PC position set is less than 3

[0205] / / Get the set S1 (i.e. the first position set) composed of the current set S2 (i.e. the second position set) and the new position (i.e. a candidate PC position in the third set), end indicates the number of the last position of the sequence B, the last position of the sequence B is the position with the highest reliability, end is equal to N, and A is the number of information bits

[0206] S1_weights = weights(S1); / / Get the row weight of all positions in S1

[0207] w_min_new = S1_weights(1); / / Get the row weight of the new position

[0208] S2_weights = weights(S2); / / Get the row weight of set S2

[0209] w_min = min(S2_weights); / / Get the minimum row weight corresponding to set S2

[0210] if w_min_new < w_min / / If the row weight of the new position is less than the minimum row weight corresponding to the current set S2

[0211] newPC = S1(1); / / Take the new position as the PC position

[0212] S = [S newPC]; / / Put the new position into set S

[0213] else / / If the row weight of the new position is greater than or equal to the minimum row weight corresponding to the current set S2

[0214] temp = S1(S1_weights == w_min); / / Select the positions with the minimum row weight in set S1 to form set temp

[0215] newPC = temp(end); / / Select the position with the highest sequence reliability in set temp as the PC position

[0216] S = [S newPC]; / / Put the position with the highest sequence reliability into set S

[0217] end

[0218] %

[0219] / / Used to indicate the updated new position

[0220] / / update set S2

[0221] S2 = S1; / / copy all elements in S1 to S2

[0222] S2(S2 == newPC(1)) = []; / / delete the determined PC position from set S2

[0223] End

[0224] Implementation three

[0225] The difference between implementation three and implementation one is in steps b) and e). As can be seen, in steps b) and e), implementation one corresponds to the same operation when the row weight corresponding to the candidate position is greater than or equal to the minimum row weight corresponding to the second position set, that is, the position with the largest position number in the second position set is taken as the PC position. Therefore, implementation three can be further subdivided. If equal, the first position is the position with the largest position number in the second position set. If greater, the first position is the position with the highest sequence reliability in the second position set.

[0226] The pseudo code corresponding to implementation three is given below.

[0227] / / used to indicate an added position (i.e., to indicate a candidate PC position in the third set), initialize the value, which is equivalent to i in implementation one

[0228] n PC = 3; / / initialize the total number of target PC bits

[0229] S = []; / / initialize the PC position set S

[0230] while length(S) < n PC / / if the number of elements in the PC position set is less than 3

[0231] / / get the set S1 (i.e., the first position set) composed of the current set S2 (i.e., the second position set) and the added position (i.e., a candidate PC position in the third set), end indicates the number of the last position of the sequence B, which is the position with the highest reliability, end is equal to N, and A is the number of information bits

[0232] S1_weights = weights(S1); / / get the row weight of all positions in S1

[0233] w_min_new = S1_weights(1); / / Get the row weight of the new position

[0234] S2_weights = weights(S2); / / Get the row weight of set S2

[0235] w_min = min(S2_weights); / / Get the minimum row weight of set S2

[0236] if w_min_new < w_min / / If the row weight of the new position is less than the minimum row weight of set S2

[0237] newPC = S1(1); / / Set the new position as the PC position

[0238] S = [S newPC]; / / Add the new position to set S

[0239] elseif w_min_new == w_min / / If the row weight of the new position is equal to the minimum row weight of set S2

[0240] temp = S1(S1_weights == w_min); / / Select positions with the same row weight as the minimum row weight from set S1 to form set temp

[0241] newPC = max(temp); / / Select the position with the highest sequence reliability from set temp as the PC position

[0242] S = [S newPC]; / / Add the position with the highest sequence reliability to set S

[0243] else

[0244] temp = S1(S1_weights == w_min); / / Select positions with the same row weight as the minimum row weight from set S1 to form set temp

[0245] newPC = temp(end); / / Select the position with the highest sequence reliability from set temp as the PC position

[0246] S = [S newPC]; / / Add the position with the highest sequence reliability to set S

[0247] end

[0248] %

[0249] / / Used to indicate the updated new position

[0250] / / Update set S2

[0251] S2 = S1; / / Copy all elements in S1 to S2

[0252] S2(S2 == newPC(1)) = [] ; / / Remove the determined PC position from the set S2

[0253] End

[0254] Implementation four

[0255] The difference between implementation four and implementation one is in steps b) and e). As can be seen, in steps b) and e), implementation one corresponds to the same operation when the row weight corresponding to the candidate position is greater than or equal to the minimum row weight corresponding to the second position set, that is, the position with the largest position number in the second position set is taken as the PC position. Therefore, implementation four can be further subdivided. If greater than, the first position is the position with the largest position number in the second position set. If equal to, the first position is the position with the highest sequence reliability in the second position set.

[0256] The pseudo code corresponding to implementation four is given below.

[0257] / / Used to indicate an added position (i.e., to indicate a candidate PC position in the third set), initialize the value, which is equivalent to i in implementation one

[0258] n PC = 3; / / Initialize the total number of target PC bits

[0259] S = [] ; / / Initialize the PC position set S

[0260] while length(S) < n PC / / If the number of elements in the PC position set is less than 3

[0261] / / Get the set S1 (i.e., the first position set) composed of the current set S2 (i.e., the second position set) and the added position (i.e., a candidate PC position in the third set), end indicates the number of the last position of the sequence B, which is the position with the highest reliability, end is equal to N, and A is the number of information bits

[0262] S1_weights = weights(S1) ; / / Get the row weight of all positions in S1

[0263] w_min_new = S1_weights(1) ; / / Get the row weight corresponding to the added position

[0264] S2_weights = weights (S2) ; / / get the row weights of set S2

[0265] w_min = min (S2_weights) ; / / get the minimum row weight of set S2

[0266] if w_min_new < w_min / / if the row weight of the new position is less than the minimum row weight of set S2

[0267] newPC = S1 (1) ; / / take the new position as the PC position

[0268] S = [S newPC] ; / / put the new position into set S

[0269] elseif w_min_new == w_min / / if the row weight of the new position is equal to the minimum row weight of set S2

[0270] temp = S1 (S1_weights == w_min) ; / / select the positions with the same row weight as the minimum row weight from set S1 to form set temp

[0271] newPC = temp (end) ; / / select the position with the highest sequence reliability from set temp as the PC position

[0272] S = [S newPC] ; / / put the position with the highest sequence reliability into set S

[0273] else

[0274] temp = S1 (S1_weights == w_min) ; / / select the positions with the same row weight as the minimum row weight from set S1 to form set temp

[0275] newPC = max (temp) ; / / select the position with the largest position number from set temp as the PC position

[0276] S = [S newPC] ; / / put the position with the largest position number into set S

[0277] end

[0278] %

[0279] / / used to indicate the updated new position

[0280] / / update set S2

[0281] S2 = S1 ; / / copy all elements in S1 to S2

[0282] S2(S2==newPC(1))=[]; / / Remove the determined PC position from set S2

[0283] End

[0284] The above implementation methods one through four can be seen as serial methods for determining the PC position. Below are two parallel methods for determining the PC position.

[0285] Implementation method five includes the following steps.

[0286] a) Determine the first set of positions, which includes the second set of positions and the third set of positions.

[0287] The second set of positions indicates the A positions with the highest sequence reliability in the first bit sequence, and the third set of positions indicates the (A+n) positions with the highest sequence reliability. PC The n positions with the lowest sequence reliability PC The first set of positions can also be understood as indicating the (A+n) positions with the highest reliability in the first bit sequence. PC ) positions.

[0288] b) Determine n based on the row weight corresponding to each position in the third position set and the minimum row weight corresponding to the second position set. PC PC locations.

[0289] If m1 positions in the third position set correspond to row weights less than the minimum row weight in the second position set, then these m1 positions are designated as PC positions, where 1 ≤ m1 ≤ n. PC .

[0290] If m2 positions in the third position set have a row weight greater than or equal to the minimum row weight corresponding to the second position set, then the m2 positions with the largest position numbers or the m2 positions with the highest sequence reliability in the fourth position set are taken as PC positions. The fourth position set includes all positions in the first position set whose row weight is equal to the minimum row weight of the second position set, where m1 + m2 = n. PC .

[0291] Implementation method six includes the following steps.

[0292] a) Determine the first set of positions, which includes the second set of positions and the third set of positions.

[0293] The second and third position sets are described in Implementation Method 5, and will not be repeated here.

[0294] b) Determine n based on the row weight corresponding to each position in the third position set and the minimum row weight corresponding to the second position set.PC PC locations.

[0295] If the row weight corresponding to the i-th position in the third position set is less than the minimum row weight corresponding to the second position set, then the i-th position is taken as a PC position, 1≤i≤n. PC .

[0296] If the row weight corresponding to the i-th position in the third position set is greater than or equal to the minimum row weight corresponding to the second position set, then the position with the largest position number or the highest sequence reliability in the fifth position set is taken as a PC position. The fifth position set is the remaining positions in the fourth position set excluding the determined PC positions. The fourth position set includes all positions in the first position set whose row weight is equal to the minimum row weight of the second position set.

[0297] The placement of the PC bits has been described in detail above. When n is determined... PC After each PC position, place A information bits into the sequence with the highest reliability (A+n) in the first bit sequence. PC ) positions excluding n PC The remaining A positions are excluding the PC positions. Additionally, based on n... PC The PC check relationship corresponding to each PC position is determined. PC The values ​​of the PC bits at each PC position are used to obtain the first bit sequence to be encoded.

[0298] S730: The transmitting device performs Polar encoding on the first bit sequence and outputs a codeword sequence.

[0299] For information on the Polar encoding process, please refer to... Figure 3 The description in the text will not be repeated here.

[0300] S740, the transmitting device determines the symbol sequence based on the codeword sequence.

[0301] It is understandable that a symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the transmitting device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0302] For example, the modulation mode can be QPSK (quaternary phase shift keying), and the obtained QPSK symbol (i.e., the code word sequence #2) after modulation is mapped to a physical resource for transmission. For example, the sending end modulates the code word sequence after rate matching, modulates bit 0 in the code word sequence after rate matching as 1, and modulates bit 1 as -1 to obtain a symbol sequence to be sent. For example, the sequence before modulation is {1, 0, 0, 1, 1, 0}, and the sequence after modulation is the symbol sequence #1 {-1, 1, 1, -1, -1, 1}.

[0303] S750, the sending end device sends the symbol sequence to the receiving end device. Correspondingly, the receiving end device receives the symbol sequence from the sending end device.

[0304] It can be understood that, due to the introduction of channel noise signals in the transmission process of the symbol sequence, the symbol sequence #1 output or sent by the sending end device and the symbol sequence #2 received by the receiving end device can be different.

[0305] S760, the receiving end device performs PC-SCL decoding on the symbol sequence to obtain a first bit sequence.

[0306] It can be understood that the PC position obtained by the receiving end device is the same as the PC position obtained by the sending end device, and the application does not specifically limit how the receiving end device and the sending end device obtain the PC position. For example, the receiving end device and the sending end device can determine the PC position based on the same criterion. The receiving end device knows A information bit positions, n PC PC positions, and the position range corresponding to the frozen bit position. The A information bit positions and the n PC PC positions are (A+n PC ) positions with the highest sequence reliability in the first bit sequence. In addition, the frozen bit position is the remaining N-A-n PC position in the first bit sequence.

[0307] It can also be understood that the PC-SCL decoding algorithm does not use CRC test decoding paths, and the path criterion PM of the SCL decoding is corrected by the PC bit, so as to improve the probability that the correct decoding path is ranked first.

[0308] It can also be understood that in the PC-SCL decoding algorithm, only the 8 decoding paths with the smallest current PM are saved as candidate decoding paths for each decoding (i.e., decoding a bit). Then, the current decoding process for the bit at the i-th PC position includes the following steps.

[0309] a) Based on the symbol sequence #2, obtain the LLR corresponding to the N positions of the first bit sequence.

[0310] For example, the symbol sequence #1 sent by the sending end is {-1, 1, 1, -1, -1, 1}, the receiving end demodulates the symbol sequence #2 to obtain the LLR corresponding to the position where A information bits and n PC PC bits in the first bit sequence, for example, {-0.8, 1.1, 0.9, -0.9, -1.2, 0.6}.

[0311] b) Obtain S decoding paths with the minimum PM corresponding to the positions before the ith PC position (hereinafter, S = 8 is taken as an example for illustration), and the ith PC position is any position in the n PC PC positions in the first bit sequence.

[0312] It can be understood that the positions before the ith PC position in the first bit sequence where the payload bits and the CRC bits are placed correspond to two decoding results. For example, if the number of positions before the ith PC position in the first bit sequence where the payload bits and the CRC bits are placed is 4, there will be 2 4 = 16 decoding paths, and the 8 decoding paths here are the 8 paths with the minimum PM in the 16 decoding paths.

[0313] It can also be understood that the PM of each decoding path is determined based on the LLR corresponding to all (i-1) positions before the ith PC position.

[0314] c) Determine whether to increase the penalty of the current path based on the first value of the ith PC position corresponding to the decoding path #1 and the second value of the ith PC position. The decoding path #1 is any one of the current 8 decoding paths, the first value is determined based on the decoding result corresponding to the decoding path #1 and the PC check relationship corresponding to the ith PC position, and the second value is the hard decision result of the LLR corresponding to the ith PC position.

[0315] If the first value of the ith PC position corresponding to the decoding path #1 is different from the second value of the ith PC position, the PM value of the decoding path #1 is increased, that is, a value is added to the current PM to obtain a new PM.

[0316] If the first value of the ith PC position corresponding to the decoding path #1 is the same as the second value of the ith PC position, the PM value of the decoding path #1 is kept unchanged, that is, the PM value of the decoding path #1 is kept unchanged.

[0317] It can be understood that in the present application, when calculating the PM value of the decoding path, the decoding path with the smaller PM is more likely to be the correct code word, and therefore, increasing the penalty of the decoding path can be realized by increasing the PM value of the decoding path.

[0318] In another implementation, if the PM of a decoding path is made to be larger, the decoding path is more likely to be the correct codeword, the S decoding paths with the largest PM are selected in each round of decoding, and the penalty added to the decoding path can also be realized by reducing the PM of the decoding path, i.e., a value can be subtracted from the PM of the current decoding path.

[0319] d) Based on the LLRs corresponding to the positions after the i-th PC position in the first bit sequence and the above-mentioned 8 decoding paths, decoding is continued until the final 8 decoding paths with the smallest PM are obtained.

[0320] e) The first bit sequence is determined, and the first bit sequence is the decoding result corresponding to the decoding path with the smallest PM in the above-mentioned final 8 decoding paths with the smallest PM.

[0321] It can be understood that the above-mentioned steps in the above-mentioned drawings are only exemplary and are not strictly limited. In addition, the size of the serial number of the above-mentioned processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0322] It can also be understood that some optional features in the embodiments of the present application can not depend on other features in some scenarios, or can be combined with other features in some scenarios, without limitation.

[0323] It can also be understood that the methods and operations implemented by the device (the sending end device or the receiving end device) in the above-mentioned various method embodiments can also be implemented by the components (such as chips or circuits) of the device, without limitation.

[0324] The above describes the method embodiments provided by the present application in detail in combination with Figures 1 to 10 , and the device embodiments of the present application will be described in combination with Figure 11 and Figure 12 . It can be understood that, in order to realize the functions in the above-mentioned embodiments, Figure 11 and Figure 12 , the devices include the corresponding hardware structures and / or software modules for executing various functions. Those skilled in the art should easily realize that, in combination with the embodiments disclosed in the present application, the units and method steps of each example described in the present application can be realized in the form of hardware or a combination of hardware and computer software. It can be understood that the technical features described in the above-mentioned method embodiments are also applicable to the following device embodiments.

[0325] Figure 11 and Figure 12A possible apparatus structure diagram is provided for the embodiments of the present application. The apparatus can be used to implement the functions of the sending end device or the receiving end device in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0326] Figure 11 FIG. 1 is a schematic block diagram of a communication apparatus 1000 provided by the embodiments of the present application. As shown in FIG. 1, the apparatus 1000 can include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside, and the processing unit 1020 can process data. The communication unit 1010 can also be referred to as a communication interface or a transceiver unit. Figure 11

[0327] In a possible design, the apparatus 1000 can implement the steps or processes performed by the sending end device in the above method embodiments, where the processing unit 1020 is configured to perform processing-related operations of the sending end device in the above method embodiments, and the communication unit 1010 is configured to perform sending-related operations of the sending end device in the above method embodiments.

[0328] In another possible design, the apparatus 1000 can implement the steps or processes performed by the receiving end device in the above method embodiments, where the communication unit 1010 is configured to perform receiving-related operations of the receiving end device in the above method embodiments, and the processing unit 1020 is configured to perform processing-related operations of the receiving end device in the above method embodiments.

[0329] It can be understood that the apparatus 1000 is embodied in the form of functional units. The term “unit” can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (shared, dedicated or group) and memory for executing one or more software or firmware programs, a baseband processor or a combination thereof, and support the described functions. In an optional example, those skilled in the art can understand that the apparatus 1000 can be embodied as the sending end device in the above embodiments, and can be used to perform the processes and / or steps corresponding to the sending end device in the above method embodiments. Alternatively, the apparatus 1000 can be embodied as the receiving end device in the above embodiments, and can be used to perform the processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, details are not described here.

[0330] ​The apparatus 1000 of each of the above-mentioned solutions has a function of implementing the corresponding steps performed by the sending-end device in the above-mentioned methods, or the apparatus 1000 of each of the above-mentioned solutions has a function of implementing the corresponding steps performed by the receiving-end device in the above-mentioned methods. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions; for example, the communication unit can be replaced by a transceiver (for example, the sending unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units such as the processing unit can be replaced by a processor, which respectively performs the transceiving operations and related processing operations in each method embodiment.

[0331] In addition, the communication unit can also be a transceiving circuit (for example, can include a receiving circuit and a sending circuit), and the processing unit can be a processing circuit. In the embodiments of the present application, Figure 11 The apparatus in the above-mentioned embodiments can be a receiving-end device or a sending-end device, or can be a chip or a chip system, for example, a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface, and the processing unit can be a processor or a microprocessor integrated on the chip or an integrated circuit. In this regard, no limitation is made.

[0332] Figure 12 A schematic block diagram of a communication apparatus 1100 provided in the embodiments of the present application is shown in FIG. 11. The apparatus 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is configured to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0333] Optionally, the apparatus 1100 can further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 through an internal connection path. The memory 1130 is configured to store instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the apparatus 1100 is configured to implement the corresponding procedures and steps of the sending-end device in the above-mentioned method embodiments. In another possible implementation, the apparatus 1100 is configured to implement the corresponding procedures and steps of the receiving-end device in the above-mentioned method embodiments.

[0334] Optionally, the memory 1130 can be integrated in the processor 1110.

[0335] In one possible scenario, the apparatus 1100 includes at least one processor integrated with a memory, and other memories in addition to the memory integrated on the processor.

[0336] It can be understood that the apparatus 1100 can be specifically a sending device or a receiving device in the above-described embodiments, or can be a chip or a chip system. Correspondingly, the transceiver 1120 can be a transceiver circuit of the chip, which is not limited here. Specifically, the apparatus 1100 can be configured to perform various steps and / or processes in the above-described method embodiments corresponding to the sending device or the receiving device.

[0337] Optionally, the memory 1130 can include read-only memory and random access memory, and provide instructions and data for the processor. The memory can include non-volatile random access memory. For example, the memory can also store device type information. The processor 1110 can be configured to execute instructions stored in the memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to perform various steps and / or processes of the above-described method embodiments corresponding to the sending device or the receiving device.

[0338] In the implementation process, the steps of the above method can be completed by integrated logic circuits of hardware in the processor or instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as hardware processor execution completion, or executed by a combination of hardware and software modules in the processor. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0339] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with a signal processing capability. In the implementation process, the steps of the above method embodiments can be completed by the integrated logic circuit or the instruction in the form of software in the processor. The processor mentioned above can be a general processor, a digital signal processing (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic devices, a discrete gate or transistor logic device, a discrete hardware component. The processor in the embodiments of the present application can realize or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor and the like. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware code processor for execution, or be executed by a combination of hardware and software modules in the code processor. The software module can be located in a random memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register or other mature storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0340] It is to be appreciated that the memory in the embodiments of the application can be a volatile memory or a nonvolatile memory, or can include both volatile and nonvolatile memory. Where the nonvolatile memory is, for example, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory. The volatile memory, which can be used as external cache, can be, for example, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), or direct RAM bus RAM (DRAM). It is to be appreciated that the memory described herein is intended to include, among other things, these and any other memory suitable for storing or providing program code or instructions to a processor or other system.

[0341] Optionally, the memory (e.g., 1130) in the embodiments of the application can be integrated in the processor (e.g., 1110).

[0342] In addition, the application also provides a computer readable storage medium, the computer readable storage medium stores computer instructions, when the computer instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0343] The application also provides a computer program product, the computer program product includes computer program code or instructions, when the computer program code or instructions run on the computer, the operations and / or processes performed by the sending end device or the receiving end device in the method embodiments of the application are executed.

[0344] Further, the application provides a chip including a processor. A memory for storing a computer program is arranged independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processes performed by the sending device or the receiving device in any one of the method embodiments are performed.

[0345] Further, the chip can further include a communication interface. The communication interface can be an input / output interface, an interface circuit, or the like. Further, the chip can further include a memory.

[0346] Further, the application provides a communication system including the sending device and the receiving device in the embodiments of the application.

[0347] It should be further noted that the memory described herein is intended to include, but not limited to, these and any other suitable type of memory.

[0348] Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the application. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. In several embodiments provided in the application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form. The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the functional units in each embodiment of the application can be integrated in one processing unit, or each unit can be physically present, or two or more units can be integrated in one unit.

[0349] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0350] It can be understood that the "embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0351] It can also be understood that in the present application, "when", "if" and "when" all refer to the case that the network element will make corresponding processing under certain objective circumstances, not the time limit, and it is not required that the network element must have a judgment action when it is implemented, nor does it mean that there are other limitations.

[0352] It can also be understood that in the embodiments of the present application, "A corresponding B" means that B is associated with A, and B can be determined according to A. However, it can also be understood that determining B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

Claims

1. A communication method, characterized in that, include: Obtain the number n of A information bits and the parity check (PC) bits. PC The A information bits include K payload bits and L cyclic redundancy check (CRC) bits, wherein K, L, and n PC All are positive integers; Generate a first bit sequence, which comprises N bits, wherein the N bits include the A information bits and the n bits. PC PC bits, the A information bits and the n PC The PC bits are located in the first bit sequence with the highest sequence reliability (A+n). PC At positions N, where N is a power of 2 and n is a positive integer, the n positions are placed. PC n PC bits PC The PC locations satisfy both the first and second conditions. The first condition is that the minimum row weight corresponding to the A positions where the A information bits are located is not less than the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence, wherein each position corresponds to one row weight. The second condition is n PC n corresponding to each PC position PC Among the position numbers, the k-th highest position number is greater than or equal to the n corresponding to the third position set S3. PC The k-th highest position number among the position numbers, the third position set S3 includes the (A+n) sequence with the highest reliability. PC The n positions with the lowest sequence reliability PC There are n positions, 1≤k≤n PC ; The first bit sequence is polar-coded to obtain a codeword sequence; Output the codeword sequence.

2. A communication method, characterized in that, include: Obtain the symbol sequence; Based on the symbol sequence, determine the log-likelihood ratio (LLR) corresponding to N positions of the first bit sequence, where the first bit sequence includes A information bits and n... PC The A information bits include K payload bits and L cyclic redundancy check (CRC) bits. The A information bits and the n... PC The PC bits are located in the first bit sequence with the highest sequence reliability (A+n). PC At positions ), where N is 2 to the power of n, and K, L, and n CC All are positive integers, where n is placed. Pc n PC bits PC The PC locations satisfy both the first and second conditions. The first condition is that the minimum row weight corresponding to the A positions where the A information bits are located is not less than the minimum row weight corresponding to the A positions with the highest sequence reliability in the first bit sequence, wherein each position corresponds to one row weight. The second condition is n PC n corresponding to each PC position PC Among the position numbers, the k-th highest position number is greater than or equal to the n corresponding to the second position set S3. PC The k-th highest position number among the position numbers, the second position set S3 indicates the (A+n) sequence with the highest reliability. PC The n positions with the lowest sequence reliability PC There are n positions, 1≤k≤n PC ; Find the S decoding paths with the smallest path metric PM corresponding to the positions preceding the i-th PC position, where the i-th PC position is n. PC For any of the PC positions, the PM of the S decoding paths is determined based on the LLR corresponding to the position preceding the i-th PC position; If the first value of the i-th PC position corresponding to the first decoding path is different from the second value of the i-th PC position, the PM of the first decoding path is increased. Here, the first decoding path is any one of the S paths, the first value is determined based on the decoding result corresponding to the first decoding path and the PC check relationship corresponding to the i-th PC position, and the second value is the hard decision result of the LLR corresponding to the i-th PC position. If the first value of the i-th PC position corresponding to the first decoding path is the same as the second value of the i-th PC position, the PM value of the first decoding path remains unchanged; Based on the position after the i-th PC position, the S decoding paths corresponding to the LLR are continued to be decoded until the final PM is obtained with the minimum S decoding paths. Obtain the first bit sequence, which is the decoding result corresponding to the decoding path with the smallest PM among the S decoding paths with the smallest PM in the final result.

3. The method according to claim 1 or 2, characterized in that, The n PC =3, The n PC The first PC position among the n PC positions is determined based on the minimum row weight corresponding to the second position set S2 and the row weight corresponding to the first candidate position. PC The first PC location determined out of the PC locations. Wherein, the first candidate position is the position with the highest sequence reliability in the third set S3, and the second position set S2 includes the A positions with the highest sequence reliability in the first bit sequence. If the row weight corresponding to the first candidate position is less than the minimum row weight corresponding to the second position set S2, then the first candidate position is taken as the first PC position. If the row weight corresponding to the first candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2, the position with the largest position number or the highest sequence reliability in the fourth position set S4 is taken as the first PC position. The fourth position set S4 includes the position in the first position set S1 with the minimum row weight equal to the second position set S2. The first position set S1 includes the second position set S2 and the first candidate position.

4. The method according to claim 3, characterized in that, The n PC The second PC position among the n PC positions is determined based on the minimum row weight corresponding to the second position set S2 after the first update and the row weight corresponding to the second candidate position. PC The second determined PC position out of the total number of PC positions. The second candidate position is the position with the second highest sequence reliability in the third set S3, and the second position set S2 after the first update is the position set corresponding to the deletion of the first PC position in the first position set S1. If the row weight corresponding to the second candidate position is less than the minimum row weight corresponding to the second position set S2 after the first update, the second candidate position is taken as the second PC position. If the row weight corresponding to the second candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 after the first update, the position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as the second PC position. The fifth position set S5 includes the position in the first position set S1 after the first update whose row weight is equal to the minimum row weight of the second position set S2 after the first update. The first position set S1 after the first update includes the second position set S2 after the first update and the second candidate position.

5. The method according to claim 4, characterized in that, The n PC The third PC position among the n PC positions is determined based on the minimum row weight corresponding to the second position set S2 after the second update and the row weight corresponding to the third candidate position. PC The third PC location identified out of the total number of PC locations. The third candidate position is the position with the lowest sequence reliability in the third set S3, and the second position set S2 after the second update is the set of positions corresponding to the deletion of the second PC position in the first position set S1 after the first update. If the row weight corresponding to the third candidate position is less than the minimum row weight corresponding to the second position set S2 after the second update, the third candidate position is taken as the third PC position. If the row weight corresponding to the third candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 after the second update, the position with the largest position number or the highest sequence reliability in the sixth position set S6 is taken as the third PC position. The sixth position set S6 includes the position in the first position set S1 after the second update whose row weight is equal to the minimum row weight of the second position set S2 after the second update. The position set after the second update includes the second position set S2 after the second update and the third candidate position.

6. The method according to claim 1 or 2, characterized in that, The n pc The i-th PC position in the set of PC positions is determined based on the minimum row weight corresponding to the second position set S2 in the i-th round and the row weight of the i-th candidate position in the third position set, where, The i-th candidate position is the position with the highest sequence reliability in the third position set S3, and the n-th candidate position in the third position set S3 is... PC Each of the n positions is selected as a candidate position based on its sequence reliability from high to low, thus determining a PC position. PC The first PC position in the set of positions is determined based on the row weight of the second position set S2 in the first round and the row weight of the first candidate position. The second position set S2 in the first round includes the A positions with the highest sequence reliability in the first bit sequence, and the first candidate position is the position with the highest sequence reliability in the third position set S3, where 1 ≤ i ≤ n. PC -1; If the row weight corresponding to the i-th candidate position is less than the minimum row weight corresponding to the second position set S2 in the i-th round, then the i-th candidate position is taken as the i-th PC position. If the row weight corresponding to the i-th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 in the i-th round, the position with the largest position number or the highest sequence reliability in the fourth position set S4 is taken as the i-th PC position. The fourth position set S4 includes the position in the first position set S1 in the i-th round whose row weight is equal to the minimum row weight of the second position set S2 in the i-th round. The first position set S1 in the i-th round includes the second position set S2 in the i-th round and the i-th candidate position. The n PC The (i+1)th PC position is determined based on the row weight of the second position set S2 in the (i+1)th round and the row weight of the (i+1)th candidate position. The second position set S2 in the (i+1)th round includes the remaining positions in the first position set in the ith round, excluding the ith PC position. The (i+1)th candidate position is the position with the (i+1)th highest sequence reliability in the third position set S3. If the row weight corresponding to the (i+1)th candidate position is less than the minimum row weight corresponding to the second position set S2 in the (i+1)th round, then the (i+1)th candidate position is taken as the (i+1)th PC position. If the row weight corresponding to the (i+1)th candidate position is greater than or equal to the minimum row weight corresponding to the second position set S2 of the (i+1)th round, the position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as the (i+1)th PC position. The fifth position set S5 includes the position in the first position set S1 of the (i+1)th round with the minimum row weight equal to the minimum row weight of the second position set S2 of the (i+1)th round. The first position set S1 of the (i+1)th round includes the second position set S2 of the (i+1)th round and the (i+1)th candidate position.

7. The method according to claim 1 or 2, characterized in that, The n PC The PC position is based on the minimum row weight corresponding to the second position set S2 and n in the third position set S3. PC The row reordering corresponding to each position is determined, wherein the second position set S2 includes the A positions with the highest sequence reliability in the first bit sequence. If the row weight corresponding to m1 positions in the third position set S3 is less than the minimum row weight corresponding to the second position set S2, then the m1 positions are taken as PC positions, where 1 ≤ m1 ≤ n. PC , If m2 positions in the third position set S3 have a row weight greater than or equal to the minimum row weight corresponding to the second position set S2, then the m2 positions with the largest position numbers or the m2 positions with the highest sequence reliability in the fourth position set S4 are taken as PC positions. The fourth position set S4 includes the positions in the first position set S1 whose row weight is equal to the minimum row weight of the second position set S2. The first position set S1 includes the second position set S2 and the third position set S3, where m1 + m2 = n. PC .

8. The method according to claim 1 or 2, characterized in that, The n pC The PC position is based on the minimum row weight corresponding to the second position set S2 and n in the third position set S3. PC The row reordering corresponding to each position is determined, wherein the second position set S2 includes the A positions with the highest sequence reliability in the first bit sequence. If the row weight corresponding to the i-th position in the third position set S3 is less than the minimum row weight corresponding to the second position set S2, then the i-th position is taken as a PC position, 1≤i≤n. PC , If the row weight corresponding to the i-th position in the third position set S3 is greater than or equal to the minimum row weight corresponding to the second position set S2, then the position with the largest position number or the highest sequence reliability in the fifth position set S5 is taken as a PC position. The fifth position set S5 consists of the remaining positions in the fourth position set S4 excluding the determined PC positions. The fourth position set includes the position in the first position set S1 with the minimum row weight equal to the second position set S2. The first position set S1 includes the second position set S2 and the third position set S3.

9. The method according to any one of claims 1 to 8, characterized in that, The n PC The PC position is the nth position in the first bit sequence with the lowest sequence reliability. PC One location, or, The n PC The PC position is n, which is the position with the highest sequence reliability or the largest position number in the first bit sequence. PC One position.

10. The method according to any one of claims 1 to 9, characterized in that, The A information bits are located in the first bit sequence with the highest sequence reliability (A+n). PC ) positions excluding the n pc The remaining A positions are outside of the PC positions.

11. The method according to any one of claims 1 to 10, characterized in that, The method further includes: Based on the n pc The PC verification relationship corresponding to each PC position determines the n PC The value of each PC bit.

12. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 11 to be implemented via logic circuits or executing code instructions.

13. The communication device according to claim 12, characterized in that, The communication device is a chip or chip system.

14. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 11 to be implemented.

15. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 11 to be implemented.

16. A communication system, characterized in that, include: A transmitting device for performing the method as described in any one of claims 1, 3 to 11; A receiving device for performing the method as described in any one of claims 2 to 11.

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