A communication system and method for applying an Ethernet device to a GLink network

Abstract

The application provides a communication system for applying an Ethernet device to a GLink network, and relates to the technical field of information transmission, which comprises a GLink bridge device, an Ethernet switch connected with the GLink bridge device through a network cable, and a GLink switch connected with the GLink bridge device through an optical fiber; a PL end of the GLink bridge device establishes a UDP communication link with a Glink simulation terminal through the Ethernet switch; the Glink simulation terminal comprises a CtrlNC sub-terminal, a CtrlNT sub-terminal, a SmartNC sub-terminal and a SmartNT sub-terminal; a PS end of the GLink bridge device establishes an optical fiber communication link with a Glink node device through the GLink switch; the number of sub-devices in the Glink node device is the same as the number of sub-terminals in the Glink simulation terminal; the GLink bridge device comprises a JLK1263 chip; when a control message is transmitted, the JLK1263 chip informs the PS end to transmit a UDP message to the Glink simulation terminal in the form of an interruption; when a data message is transmitted, a long data message is transmitted to the JLK1263 chip through a FIFO interface after being stored in a DDR cache, and a short data message is directly transmitted to the JLK1263 chip through the FIFO interface.

Description

Technical Field

[0001] This invention relates to the field of information transmission technology, and in particular to a communication system and method for applying Ethernet devices to a GLink network. Background Technology

[0002] Ethernet is a computer local area network (LAN) technology and a type of random access technology. It defines the physical layer connections, electronic signals, and media access layer protocols, and is a widely used LAN technology. With the rapid development of automation technology, enterprises are increasingly demanding higher levels of automation in their production lines. Against this backdrop, automated control systems have become a core component of industrial production. However, with increasing system complexity, signal transmission and compatibility issues between different devices are becoming increasingly prominent. Especially in scenarios where multiple controllers need to share encoder signals, traditional methods often face numerous challenges. Different brands and models of encoders use their own unique communication protocols, making direct signal interoperability difficult. Alternatively, to achieve signal distribution and transmission, dedicated encoder protocol converters must be used. These converters are not only expensive but also often lack universality. Changing the encoder brand or model requires purchasing a new, compatible converter, undoubtedly increasing the company's operating and time costs. Therefore, how to ensure the efficient operation of automated control systems while solving the compatibility and cost issues of encoder signals has become a critical problem that the industry urgently needs to address. Summary of the Invention

[0003] In view of this, the present invention proposes a communication system and method for applying Ethernet devices to GLink networks.

[0004] The technical solution of the present invention is implemented as follows: The first aspect of the present invention provides a communication system for applying Ethernet devices to a GLink network, comprising:

[0005] A GLink bridge device, an Ethernet switch connected to the GLink bridge device via a network cable, and a GLink switch connected to the GLink bridge device via an optical fiber;

[0006] The PL end of the GLink bridge device establishes a UDP communication link with the Glink emulation terminal through the Ethernet switch; the Glink emulation terminal includes a CtrlNC sub-terminal, a CtrlNT sub-terminal, a SmartNC sub-terminal, and a SmartNT sub-terminal; the PS end of the GLink bridge device establishes an optical fiber communication link with the Glink node device through the GLink switch; the number of sub-devices in the Glink node device is the same as the number of sub-terminals in the Glink emulation terminal.

[0007] The GLink bridge device includes a JLK1263 chip. When transmitting control messages, the JLK1263 chip notifies the PS terminal to transmit UDP messages to the GLink emulation terminal via an interrupt. When transmitting data messages, long data messages are buffered by DDR and then transmitted to the JLK1263 chip through the FIFO interface, while short data messages are transmitted directly to the JLK1263 chip through the FIFO interface.

[0008] Based on the above technical solutions, preferably, the PS terminal performs initialization operations and dynamic register configuration on the JLK1263 chip through the EMIF interface, including: communicating with the PL terminal through the AXI-Lite interface, and the PL terminal maps the signal passing through the AXI-Lite interface into an EMIF signal form after data parsing to communicate with the JLK1263 chip.

[0009] Based on the above technical solutions, preferably, the Glink simulation terminal includes 2 CtrlNC sub-terminals, 1 CtrlNT sub-terminal, 4 SmartNC sub-terminals and 4 SmartNT sub-terminals, and the Glink node device includes 2 CtrlNT sub-devices, 1 CtrlNC sub-device, 4 SmartNC sub-devices and 4 SmartNT sub-devices.

[0010] Based on the above technical solution, preferably, when the JLK1263 chip is used as CtrlNC, the GLink emulation terminal encapsulates the GLink message into a UDP message and sends it to the PS end of the GLink bridge device. The PS end receives and parses the UDP message and initiates Ctrl message transmission through the EMIF interface. After receiving the command sequence from the JLK1263 chip, the GLink node device responds with a status sequence. The JLK1263 chip notifies the PS end via an interrupt, and the PS end sends a UDP message to the GLink emulation terminal after receiving the notification.

[0011] Based on the above technical solution, preferably, when the JLK1263 chip is used as CtrlNT, the GLink node device is used as CtrlNC and sends a command sequence to the JLK1263 chip; the JLK1263 chip responds with the command sequence and notifies the PS end through an interrupt; after receiving the interrupt notification, the PS end obtains the GLink message through the EMIF interface, packages it into a UDP message and sends it to the GLink emulation terminal.

[0012] Based on the above technical solution, preferably, when the JLK1263 chip is used as SmartNC and set to long message mode, the GLink emulation terminal packages the SmartNC long message into several UDP packets and sends them to the PL end one by one; while receiving the UDP packets, the PL end writes the UDP packets into DDR and reads the UDP packets from DDR and sends them to the JLK1263 chip; the JLK1263 chip sends the command sequence and the UDP packets to the GLink node device; after receiving the data, the GLink node device returns a status sequence to the JLK1263 chip; after the PL end has sent all GLink message data to the JLK1263 chip, it sends the UDP packets to the GLink emulation terminal.

[0013] Based on the above technical solutions, preferably, when the JLK1263 chip is used as SmartNT and set to long message mode, the GLink node device, in SmartNC long message mode, sends Smart long messages to the JLK1263 chip through command sequence and data sequence; the JLK1263 chip sends GLink messages to the PL end through the high-speed FIFO interface; after the JLK1263 chip finishes sending, it responds to the GLink node device through a status sequence; the PL end receives long message messages from the high-speed FIFO interface and writes them into the DDR buffer, and at the same time, the PL end reads GLink messages from the DDR and splits the GLink messages into multiple UDP packets and sends them to the GLink emulation terminal.

[0014] More preferably, a second aspect of the present invention provides a communication method for applying an Ethernet device to a GLink network, applied to the communication system for applying an Ethernet device to a GLink network as described in the first aspect, comprising:

[0015] Acquire the transmitted message and detect the message type of the transmitted message;

[0016] If the message type is a control message, the PS terminal is notified to transmit a UDP message to the GLink emulation terminal via an interrupt; if the message type is a data message, and it is long data, the transmission message is buffered in DDR and then transmitted to the JLK1263 chip through the FIFO interface; if the message type is a short message, and it is short data, the transmission message is transmitted to the JLK1263 chip through the FIFO interface.

[0017] More preferably, a third aspect of the present invention provides an electronic device including a processor and a memory; the memory has a computer program stored thereon, wherein the computer program, when executed by the processor, implements the communication method of applying an Ethernet device to a GLink network as described in the second aspect.

[0018] More preferably, a fourth aspect of the present invention provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the communication method for applying an Ethernet device to a GLink network as described in the second aspect.

[0019] The communication system and method for applying Ethernet devices to GLink networks according to the present invention have the following advantages over the prior art:

[0020] 1. By connecting Ethernet switches and GLink switches through a GLink bridge device, a communication bridge was successfully established between Ethernet devices and the GLink network, enabling networks based on different technologies to work together. At the protocol conversion level, based on the PS+PL heterogeneous architecture collaborative processing mechanism, the Ethernet-side UDP protocol and the GLink-side FC protocol are deeply coupled: the PL end parses the Ethernet frame structure through hardware, accurately separates control messages and data messages, uses an internal pass-through channel for short Ctrl-type messages to achieve fast transparent transmission, and uses the DDR cache management module to fragment and reassemble long Smart-type messages, effectively avoiding data blocking caused by protocol stack processing bottlenecks; the core conversion module of the GLink bridge realizes intelligent mapping of protocol fields through the JLK1263 chip.

[0021] 2. When transmitting control messages, the JLK1263 chip notifies the PS end to transmit UDP packets to the GLink emulation terminal via an interrupt. This interrupt mechanism ensures timely processing of control messages, avoiding delays caused by polling and ensuring that control commands are quickly and accurately transmitted to the GLink emulation terminal, improving system response speed and control precision. Different transmission strategies are employed for data packets of varying lengths. For long data packets, they are first buffered in DDR mode before being transmitted to the JLK1263 chip via the FIFO interface. This effectively alleviates the pressure during data transmission, avoiding congestion caused by transmitting long data packets all at once, and ensuring the stability and smoothness of data transmission. For short data packets, they are directly transmitted to the JLK1263 chip via the FIFO interface, reducing unnecessary buffering, lowering transmission latency, and improving the transmission efficiency of short data packets. This flexible data transmission strategy optimizes processing based on the characteristics of the data packets, thereby improving the overall data transmission performance of the system.

[0022] 3. Dynamic management of end-to-end resources. The PS end dynamically configures the registers of the JLK1263 chip through the EMIF interface. System reliability is enhanced through a multi-layered protection mechanism: at the physical layer, the GT interface is used to achieve anti-interference transmission of the fiber optic link, and at the PL end, UDP receive checksum and verification functions are supported. This fundamentally solves the problems of rigid protocol conversion, data processing delay, and rigid resource allocation that exist when accessing heterogeneous networks, and meets the diverse requirements of control, intelligent processing, and other functions in different application scenarios. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of a communication system that applies an Ethernet device to a GLink network, provided as an embodiment of the present invention;

[0025] Figure 2 This is a logic architecture diagram of a GLink bridge FPGA provided in an embodiment of the present invention;

[0026] Figure 3 This is a flowchart of the CtrlNC message CtrlNC->CtrlNT data transmission process provided in an embodiment of the present invention;

[0027] Figure 4 A flowchart of CtrlNC configuration provided for an embodiment of the present invention;

[0028] Figure 5 This is a design architecture diagram of the EMIF module provided in an embodiment of the present invention;

[0029] Figure 6 This is a flowchart of the CtrlNC message CtrlNT->CtrlNC data transmission process provided in an embodiment of the present invention;

[0030] Figure 7 This is a flowchart of the CtrlNC->CtrlNT data transmission process for the CtrlNT message provided in an embodiment of the present invention;

[0031] Figure 8 A flowchart of the CtrlNT configuration process provided in this embodiment of the invention;

[0032] Figure 9 This is a flowchart of the CtrlNT message CtrlNT->CtrlNC data transmission process provided in an embodiment of the present invention;

[0033] Figure 10 This is a flowchart of the SmartNC long message SmartNC->SmartNT data transmission process provided in an embodiment of the present invention;

[0034] Figure 11 This is a flowchart of the SmartNC configuration process provided in an embodiment of the present invention;

[0035] Figure 12 This is a diagram of the downlink UDP data format of the GLink emulation terminal provided in this embodiment of the invention;

[0036] Figure 13 This is a diagram of the uplink UDP data format of the GLink emulation terminal provided in this embodiment of the invention;

[0037] Figure 14 A flowchart illustrating a communication method for applying an Ethernet device to a GLink network, provided by an embodiment of the present invention;

[0038] Figure 15 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0040] In some embodiments, such as Figure 1 As shown, Figure 1 This invention provides a schematic diagram of a communication system for applying an Ethernet device to a GLink network, as provided in an embodiment of the invention. The communication system for applying an Ethernet device to a GLink network, as provided in the invention, includes:

[0041] GLink bridge device, Ethernet switch connected to GLink bridge device via network cable, and GLink switch connected to GLink bridge device via fiber optic cable;

[0042] The PL end of the GLink bridge device establishes a UDP communication link with the GLink emulation terminal through an Ethernet switch; the GLink emulation terminal includes CtrlNC sub-terminal, CtrlNT sub-terminal, SmartNC sub-terminal, and SmartNT sub-terminal; the PS end of the GLink bridge device establishes an optical fiber communication link with the GLink node device through a GLink switch; the number of sub-devices in the GLink node device is the same as the number of sub-terminals in the GLink emulation terminal.

[0043] The GLink bridge device includes the JLK1263 chip. When transmitting control messages, the JLK1263 chip notifies the PS end to transmit UDP messages to the GLink emulation terminal via an interrupt. When transmitting data messages, long data messages are buffered by DDR and then transmitted to the JLK1263 chip through the FIFO interface, while short data messages are transmitted directly to the JLK1263 chip through the FIFO interface.

[0044] In this embodiment, a communication bridge is successfully established between the Glink emulation terminal and the Glink node device by connecting the Ethernet switch and the Glink switch through the GLink bridge device. The Glink emulation terminal includes various types of sub-terminals, such as CtrlNC, CtrlNT, SmartNC, and SmartNT sub-terminals. This diverse terminal design facilitates the expansion of system functions, allowing for the flexible addition or adjustment of different types of sub-terminals according to actual needs to meet the diverse requirements of control, intelligent processing, and other functions in different application scenarios. Simultaneously, the number of sub-devices in the Glink node device is the same as the number of sub-terminals in the Glink emulation terminal. This correspondence ensures that the system maintains structural balance and consistency during expansion, facilitating management and maintenance. In addition to the JLK1263 chip, the GLink bridge device also includes an FPGA (Field-Programmable Gate Array). The FPGA integrates the PL (Programmable Logic) end and the PS (Processing System) end. The PL end consists of a large number of programmable logic units, such as lookup tables (LUTs), flip-flops (FFs), interconnect resources, block RAM (BRAM), and digital signal processing units (DSPs), excelling in parallel processing and capable of operating on multiple data simultaneously. The PS is essentially a complete embedded processor system, generally based on the ARM Cortex series core. In addition to the processor core, it integrates a wealth of peripherals, including memory controllers, storage interfaces, and network interfaces. It has powerful general-purpose processing capabilities, can run operating systems, and supports multitasking and complex application development.

[0045] In some embodiments, the PS terminal performs initialization operations and dynamic register configuration on the JLK1263 chip through the EMIF interface, including: communicating with the PL terminal through the AXI-Lite interface, and the PL terminal parses the data and maps the signal passing through the AXI-Lite interface into the form of an EMIF signal to communicate with the JLK1263 chip.

[0046] In this embodiment, the application on the PS side generates corresponding control commands and data according to initialization or configuration requirements, and transmits these commands and data to the PL side via the AXI-Lite bus. Upon receiving the signal from the AXI-Lite interface, the PL side parses it, extracts key control information and data content, and maps the parsed AXI-Lite signal into EMIF signal form according to the EMIF interface protocol specification. The converted signal is then sent to the JLK1263 chip via the EMIF interface to complete the chip's initialization operation or dynamic register configuration.

[0047] In some embodiments, the Glink emulation terminal includes two CtrlNC sub-terminals, one CtrlNT sub-terminal, four SmartNC sub-terminals, and four SmartNT sub-terminals, and the Glink node device includes two CtrlNT sub-devices, one CtrlNC sub-device, four SmartNC sub-devices, and four SmartNT sub-devices.

[0048] Please refer to it again. Figure 1The devices in the first column are GLink emulators, with the number corresponding to the number of NC and NT devices supported by the JLK1263, i.e., a maximum of 2 CtrlNC, 1 CtrlNT, 4 SmartNC, and 4 SmartNT. The devices in the second column are Ethernet switches, connecting up to 11 GLink emulators on the left and GLink bridge devices on the right. Both sides of the Ethernet switch are connected via Ethernet cable. The devices in the third column are GLink bridge devices, connecting to the Ethernet switch on the left via Ethernet cable and to the GLink switch on the right via fiber optic cable, performing the cable-to-fiber conversion within this device. The devices in the fourth column are GLink switches, connecting to the GLink bridge devices on the left via fiber optic cable and connecting up to 11 GLink node devices on the right via fiber optic cable. The devices in the fifth column are GLink node devices, with the number corresponding to the number of GLink emulators, i.e., a maximum of 2 CtrlNT, 1 CtrlNC, 4 SmartNC, and 4 SmartNT. This connection method enables Ethernet devices to successfully access the Glink network and communicate via Ctrl / Smart messages. The key component is the Glink bridge device, with a network cable connection on the left and a fiber optic connection on the right, facilitating communication between the GLink emulation terminal and the GLink node device.

[0049] In an alternative embodiment, please refer to Figure 2 , Figure 2The following is a logical architecture diagram of the GLink bridge FPGA provided in this embodiment of the invention; the detailed structure of each module is as follows: SmartGroup1 implements long and short message processing for SmartNC1, SmartNC2, SmartNT1, and SmartNT2. SmartGroup2 implements long and short message processing for SmartNC3, SmartNC4, SmartNT3, and SmartNT4. Message filtering specifically filters messages received from the UDP protocol stack or dual redundancy, allowing only messages matching the set sequence number to pass. AXIS Arbiter, i.e., arbitration of multiple AXI-Stream data streams, allows only one AXI-Stream data stream to pass at a time. AXIS1to2, i.e., splits one AXI-Stream data stream into two identical AXI-Stream data streams. The collaborative work of the UDP protocol stack and the three-speed Ethernet MAC IP core realizes full protocol stack processing from the physical layer to the transport layer. Simultaneously, its interface is encapsulated as an AXI-Stream interface. TEMAC is the official Xilinx Ethernet MAC IP Core. SGMII is the official Xilinx SGMII IP Core. Redundancy 1 is configured so that when the Ethernet network of the other board is unavailable, the Ethernet of this board will act as the Ethernet of the other board. This block implements GTX transmission and reception between the two boards and converts it into an AXI-Stream data stream. Redundancy 2 is configured so that when the Ethernet network of this board is unavailable, the Ethernet of the other board will act as the Ethernet of this board. This block implements GTX transmission and reception between the two boards and converts it into an AXI-Stream data stream. PS, i.e., the official Xilinx hard core processor, runs the VxWorks real-time operating system and completes the processing of GLink Ctrl messages. It includes two MACs, one for the PS debugging network port and the other for receiving the second-level date from the Ethernet, used to generate the timestamp of the network listening module; DMA is the official Xilinx DMAIP Core, responsible for transferring data between the PS and the UDP protocol stack (or dual-redundant reception), and is an important bridge for data interaction between the PS and PL. The timestamp generator is configured to provide timestamps for the network monitoring module. The timestamps consist of a date in seconds and a time in milliseconds; the date in seconds is provided by the PS, and the time in milliseconds is obtained from the pulse input. The network monitoring module is configured to receive GLink messages from the optical module, timestamp them, and then send them to the simulation terminal via PL Ethernet. EMIF implements a direct mapping from AXI-Lite bus signals to EMIF bus signals.

[0050] In some embodiments, please refer to Figure 3 , Figure 3The following is a flowchart of the CtrlNC->CtrlNT data transmission process provided in this embodiment of the invention: When the JLK1263 chip acts as CtrlNC, the GLink emulation terminal encapsulates the GLink message into a UDP message and sends it to the PS end of the GLink bridge device. The PS end receives and parses the UDP message and initiates Ctrl message transmission through the EMIF interface. After receiving the command sequence from the JLK1263 chip, the GLink node device responds with a status sequence. The JLK1263 chip notifies the PS end via an interrupt, and the PS end sends a UDP message to the GLink emulation terminal after receiving the notification.

[0051] In this embodiment, please refer to Figure 4 , Figure 4This is a flowchart of the CtrlNC configuration provided in this embodiment of the invention. The software initialization process of the chip is triggered by writing 16'h0001 to the reset and control register. The interrupt mask register is initialized. For most control-flow NC applications, the control-flow NC switch group end interrupt is typically enabled. In addition, interrupts such as switch end interrupt, switch format error interrupt, NC control word specified switch end interrupt, switch retransmission interrupt, and command stack address wrapback can be enabled according to actual application needs. The control-flow NC configuration register 1 is initialized, setting options such as switch group cyclic mode, switch / switch group abnormal exit strategy, active region selection, switch interval enable, and retransmission enable. The control-flow NC configuration register 2 is initialized, setting the switch description block stack depth. If using the NC switch group cyclic mode, the transmission cycle register in the automatic cyclic mode of the control-flow NC switch group is initialized. If necessary, the timestamp register (offset address 0x08) is initialized. It should be noted that the NC terminal CPU can trigger the switch transmission and simultaneously clear the timestamp register by writing 16'h0014 to the reset and control register (offset address 0x01). Initialize the transmission timeout configuration table (0x0000-0x00ff); set the memory address corresponding to the network domain to which the network terminal to which the control flow NC needs to access belongs, and initialize the timeout time of unused network domains to 0. Initialize the NC active area stack pointers stackpointerA / B, initial stack pointers initial stackpointerA / B, exchange count exch counterA / B, and initial exchange count initial exch counterA / B; initialize stack area data, set exchange interval time and exchange data block pointers; in addition, clear the block status word to indicate that the corresponding exchange has not yet started processing; the terminal software obtains exchange processing status information by querying SOE and EOE; initialize the NC exchange control word and the storage space for data to be sent; if the external trigger enable in the NC configuration register 1 is set to 0, the NC terminal CPU can achieve a soft start of exchange initiation by writing 16'h0010 to the reset and control register (offset address 0x01); if the external trigger enable in the NC configuration register 1 is set to 1, exchange transmission can be triggered by soft triggering or by applying a rising edge transition on the EXT_TRIG input pin.

[0052] The UDP packets sent from the Glink emulation terminal to the PS end of the Glink bridge device need to be processed by the PL end for protocol conversion and data forwarding. When receiving data from the Ethernet switch through the FPGA's IO differential port, the data first enters the UDP protocol stack module that integrates a 1G / 2.5G Ethernet PCS / PMA or SGMII IP core. This IP core implements the Physical Coding Sublayer (PCS) and Physical Media Accessory (PMA) functions, and supports the conversion of txp / txn / rxp / rxn differential signals into 8-bit wide gmii_txd and gmii_rxd parallel signals, completing the protocol conversion between the physical layer differential signal and the data link layer interface. The converted data enters the three-speed Ethernet MAC IP core to implement MAC layer processing, including frame encapsulation, frame synchronization, CRC check and flow control. The processed gmii_rxd[7:0] signal is output as an 8-bit AXI-Stream format rx_axis_mac_tdata[7:0] through the m_axis_rx interface. Because the 8-bit data stream does not match the 64-bit width of the subsequent processing modules, it needs to be converted using the `axis_dwidth_converter` module. Simultaneously, due to the difference between its clock domain (`tx_mac_aclk`) and the system data processing clock (`udp_core_clk`), the `axis_data_fifo` IP core is used for cross-clock domain conversion. The converted data is stored in the `axis_data_fifo` module configured in PACKET MODE. This module continuously buffers data packets when no TLAST signal is detected, and only outputs the complete data packet to the main interface at once when a TLAST signal is received or the FIFO is full. This mechanism effectively reduces the overhead of high-frequency handshake signals and ensures the integrity of data packet processing. The `uiudp_stack` module, as a UDP protocol stack module, works in conjunction with the three-speed Ethernet MAC IP core to achieve full protocol stack processing from the physical layer to the transport layer. The processed data, after being buffered by `axis_data_fifo`, is transmitted to the S_AXIS_S2MM interface of the DMA controller via the AXI-Stream interface. The `axi_direct_memory_access` IP core converts the data stream into an AXI4 memory-mapped transaction, initiates a write request to the HP interface via the `M_AXIS_S2MM` interface, and ultimately writes the data to the specified address in the Zynq processing system's DDR memory, completing the data transfer from the PL to the PS. When the response data processed by the PS is sent back to the PL via the GP high-speed interface, the AXI-Lite to EMIF protocol conversion needs to be implemented in the EMIF module. Please refer to [link / reference here]. Figure 5 , Figure 5This is a design architecture diagram of the EMIF module provided in an embodiment of the present invention. The module includes a five-channel logic implementing the AXI-Lite bus standard and an FSM state machine controlling the EMIF read / write timing. During a write operation, the FSM receives the write address and write data and executes the EMIF write timing, triggering a write response upon completion. During a read operation, the FSM obtains the read address and executes the EMIF read timing, setting the rvalid signal after data reading is complete. The converted EMIF signal is connected to the JLK1263 chip through the top-level I / O interface. After the chip completes the transmission of the GLink node device command sequence, it triggers the PS end to send a termination UDP packet to end communication via an interrupt mechanism.

[0053] When performing CtrlNT->CtrlNC data transfer, the processes such as CtrlNC initialization, UDP parsing, and EMIF control flow transmission are similar to those in CtrlNC->CtrlNT transfer. Therefore, only the overall data flow path will be described, such as... Figure 6 As shown, Figure 6 The following is a flowchart of the CtrlNC message CtrlNT->CtrlNC data transmission process provided in this embodiment of the invention; its description is as follows: The GLink emulation terminal acts as the CtrlNC, encapsulating the GLink message into a UDP message and sending it to the FPGA PS. The PS receives the UDP message, parses it into a GLink message, and sends it to the JLK1263 through the EMIF interface. The JLK1263 sends the GLink message to the GLink node device through the high-speed GT interface. At this time, the GLink node device CtrlNT has acknowledgment data, and the JLK1263 sends the acknowledgment data to the FPGA PS through the EMIF. The JLK1263 notifies the PS via an interrupt. After receiving the interrupt, the PS sends a UDP message to the GLink emulation terminal.

[0054] In some embodiments, please refer to Figure 7 , Figure 7 The following is a flowchart of the CtrlNT message CtrlNC->CtrlNT data transmission process provided in this embodiment of the invention: When the JLK1263 chip acts as CtrlNT, the GLink node device acts as CtrlNC and sends a command sequence to the JLK1263 chip; the JLK1263 chip responds with the command sequence and notifies the PS end via an interrupt; after receiving the interrupt notification, the PS end obtains the GLink message through the EMIF interface, packages it into a UDP message, and sends it to the GLink emulation terminal.

[0055] In this embodiment, please refer to Figure 8 , Figure 8The following is a flowchart of the CtrlNT configuration provided in this embodiment of the invention. First, the JLK1263 is initialized with CtrlNT. The chip software initialization process is triggered by writing 16'h0001 to the reset and control register. The interrupt mask register is initialized. For most control flow NT applications, the switch end interrupt is usually enabled. In addition, interrupts such as mode code interrupt, specific switch end interrupt and ring buffer address wrapback can be enabled according to the actual application needs. The stack pointer of the control flow NT active area is initialized. The stack area data is initialized, such as clearing the block status word to indicate that the corresponding switch has not started processing. The terminal software obtains the switch processing status information by querying SOE and EOE. The 16-way control flow NT enable configuration memory is initialized. For unused control flow NT, the corresponding memory bit

[15] should be written with '0'. For enabled control flow NT, the active area A# / B and service request bit of the corresponding configuration memory space are initialized. The active area sub-address storage address lookup table is initialized. Within this lookup table, the memory address used by each transmit, receive, or broadcast sub-address should be initialized; if the memory management enhancement mode configuration register (bit [7] of the control flow NT configuration register 1) is '1', the terminal CPU should also initialize the control word of each sub-address in the lookup table, specify the data storage mode and interrupt option at the end of the exchange for each sub-address; if there are unused sub-addresses, it is recommended to set the same memory address for these sub-addresses when initializing the lookup table, which helps to save memory space. If the mode command enhancement mode is not used, when initializing the sub-address storage address lookup table, the same memory pointer is set for the receive sub-addresses 0 and 31, and similarly, the same memory pointer is set for the transmit sub-addresses 0 and 31; in this way, for the same mode code command for the two sub-addresses, the control flow uses the same memory space; if the mode command enhancement mode is used, the 2 bytes of data received or transmitted by the mode code command are stored in the memory address range of 0x10-0x2f. Initialize the control flow NT configuration register 1; set the active area of ​​the control flow NT, memory management enhancement mode, mode command enhancement mode, deferred cache invalid data overwrite mode, and other options. Initialize the control flow NT configuration register 2; set the command stack depth and the initial values ​​of the status bits in the return status frame. If the command illegal configuration function is used, the terminal CPU should initialize the offset address space of the single-channel CtrlNT configuration memory (0x0180-0x01bf and 0x01c0-0x01ff) occupied by the illegal lookup table. If the sub-address busy bit lookup table function is used, the terminal CPU should initialize the memory space of the busy bit lookup table (0x0030-0x0033). If the mode command enhanced mode is used, the terminal CPU should initialize the memory space of the mode command interrupt selection table (0x0008-0x000b).The terminal CPU writes the data to be sent to each sub-address into the corresponding sub-address data block. Simultaneously, the terminal CPU can clear the data block corresponding to the receiving sub-address. The operating mode configuration register is initialized, and the control flow NT mode is enabled.

[0056] Furthermore, the process of acquiring GLink messages via EMIF, packaging them into UDP packets, and sending them to the GLink emulation terminal requires the PL end of the GLink bridge device. The specific process is as follows: The PL end receives the EMIF protocol data stream through the EMIF interface and performs a format conversion operation from EMIF to AXI-Lite protocol. The converted AXI-Lite protocol data stream is transmitted to the PS end via the bus for protocol preprocessing. Then, through the HP high-speed interface of the Zynq architecture, the data is temporarily stored in the axis_data_fifo buffer module using the AXI-DMA transmission mechanism before being sent back to the PL end for further processing. The data stream is input to the UDP protocol stack at the PL end for protocol encapsulation. Key parameters, including packet length, UDP port number, and IP address, are parsed and extracted, and input together with the payload data into the UIUDP_Stack module to complete UDP protocol encapsulation. The encapsulated data stream undergoes two levels of AXIS_FIFO buffering: the first buffer achieves clock domain isolation between udp_core_clk (UDP protocol processing clock) and tx_mac_aclk (transmit MAC clock), and the second buffer completes packet reassembly and transmission timing adjustment. Given that the current data bus width is 64 bits, the `axis_dwidth_converter` IP core is needed to perform width conversion to adjust the data stream to an 8-bit standard interface. The protocol-processed data stream is then input to the Ethernet data link layer (MAC layer), where protocol conversion generates the GMII interface standard signal. Finally, the physical layer encoding and parallel-to-serial conversion are completed using the 1G / 2.5G EthernetPCS / PMA or SGMII IP core. The converted serial data is then transmitted to the Glink emulation terminal via the PHY interface, thus fully realizing the data transmission link from CtrlNC to CtrlNT devices.

[0057] When performing CtrlNT->CtrlNC data transfer, the processes such as CtrlNT initialization, UDP parsing, and EMIF control flow transmission are similar to those in CtrlNC->CtrlNT transfer. Therefore, only the overall data flow path will be described, such as... Figure 9As shown, the description is as follows: The GLink emulation terminal, acting as CtrlNT, pre-packages GLink messages into UDP packets and sends them to the FPGAPS; the FPGAPS writes the GLink messages into the JLK1263's data buffer via EMIF and initializes the stack. The GLink node device sends a command sequence to the JLK1263, which responds with a status sequence and simultaneously notifies the FPGAPS via an interrupt; upon receiving the JLK1263 interrupt, the PS queries the message sending status and sends a UDP packet to the GLink emulation terminal.

[0058] In some embodiments, please refer to Figure 10 When the JLK1263 chip is used as a SmartNC and set to long message mode, the GLink emulation terminal packages the SmartNC long message into several UDP packets and sends them to the PL end one by one. While receiving the UDP packets, the PL end writes the UDP packets to the DDR and reads the UDP packets from the DDR and sends them to the JLK1263 chip. The JLK1263 chip sends the command sequence and UDP packets to the GLink node device. After receiving the data, the GLink node device returns a status sequence to the JLK1263 chip. After the PL end has sent all the GLink message data to the JLK1263 chip, it sends UDP packets to the GLink emulation terminal.

[0059] In this embodiment, the JLK1263 must first be initialized using SmartNC, as follows: Figure 11As shown, the process can be divided into the following steps: Initialize the NC large data stream configuration register, setting the typical transmission bandwidth, the maximum load capacity of the FC frame, the stack depth of the exchange command initiated by the large data NC, the exchange transmission priority, long / short message mode, retransmission enable in short message mode, and the number of retransmissions; the stack description block is only used for status detection and fault diagnosis during the large data stream transmission process and does not require a large amount of RAM space; it is recommended to set the command stack depth register bit value to "00", corresponding to 64 exchanges, occupying 1KB of memory space; users can enable the command stack in debug mode and can choose to disable the command stack function in normal working mode. Initialize the SmartNC timeout setting register. Initialize the SmartNC command stack pointer (memory offset address is 0x0108 / 0x0109 / 0x010a / 0x010b). Initialize the working mode configuration register and enable the corresponding SmartNC path. In the process of Glink bridge device processing Smart messages, the data is also first input into the UDP protocol stack module to perform protocol parsing processing, including serial-to-parallel conversion, bit width adaptation, UDP packet decapsulation and data buffering operations. Unlike the Ctrl message handling mechanism, Smart messages are not directly transmitted to the PS end. Instead, they are first isolated by clock domain processing through the AXIS_Data_FIFO module, synchronizing the data clock from udp_core_clk to the 100MHz logic processing clock domain. The clock-synchronized data stream is then input into the Smart long message processing module for protocol conversion. This module mainly performs the following core functions: First, it performs long message fragmentation processing, splitting the data stream into several 512-byte standard data packets according to the SmartNC specification's maximum single transmission capacity of 512 bytes. The actual length of the terminal packet is dynamically adjusted based on the total amount of payload data. After fragmentation, it performs AXI4 bus protocol encapsulation and writes the data packets to DDR memory for batch caching. When reading DDR data, since the memory bus is 64-bit wide while the JLK1263 interface uses a 16-bit FIFO transmission mechanism, the AXIS_FIFO module is needed for bit width adaptation and output timing adjustment to ensure stable data transmission according to the target interface specification.

[0060] The system determines the completion status of large data transmission by jointly monitoring the idle status indicator (idle) and packet termination flag (last) returned by JLK1263. Upon confirmation of transmission completion, it proactively constructs a UDP response message containing metadata such as the total number of packets, packet type, and current packet sequence number. Based on the uplink and downlink transmission directions and device node types of the Glink simulation terminal, eight structured UDP data format specifications are defined (e.g., ...). Figure 12 , 13 As shown in the figure, this embodiment adopts Figure 13The SmartNC format specification shown is used for message framing. The constructed protocol data stream undergoes clock domain synchronization and packet reassembly via the AXIS interface, followed by MAC layer encapsulation processing via the UDP protocol stack, and finally transmission to the Glink simulation terminal via the PHY interface, thus fully realizing the data transmission protocol stack for SmartNC->SmartNT devices.

[0061] When performing SmartNC short message mode transmission, the initialization process is the same; simply select short message mode when configuring long / short message mode. Taking the SmartNC->SmartNT data transmission process as an example, since the data processing method inside the FPGA PL is largely the same, only the overall data flow path will be described, such as... Figure 14 As shown, the description is as follows: SmartNT short message data length is 0-512 bytes, so the GLink emulation terminal only needs one UDP data packet to send the GLink short message to the FPGAPL. The FPGAPL receives and parses the UDP message, and sends the GLink message to the JLK1263 through the high-speed FIFO interface. The JLK1263 sends the command sequence to the GLink node device, and the GLink node device responds to the JLK1263 with a status sequence. The JLK1263 sends the status and possible data to the FPGAPL through the high-speed FIFO interface, and the FPGAPL then packages it into a UDP message and sends it to the GLink emulation terminal.

[0062] In some embodiments, the schematic diagram is similar to that of the above embodiments. When the JLK1263 chip is used as SmartNT and set to long message mode, the GLink node device sends Smart long messages to the JLK1263 chip through command sequence and data sequence in SmartNC long message mode; the JLK1263 chip sends GLink messages to the PL end through the high-speed FIFO interface, and responds to the GLink node device through status sequence after the JLK1263 chip has finished sending; the PL end receives long message messages from the high-speed FIFO interface and writes them into the DDR buffer, and at the same time, the PL end reads GLink messages from DDR and splits the GLink messages into multiple UDP packets and sends them to the GLink emulation terminal.

[0063] In this embodiment, the large data NT stream configuration register is initialized, and the long message working mode is set. In long message mode, the ID number and serial number of the paired SmartNC also need to be initialized. The working mode configuration register is initialized to enable the corresponding SmartNC. After the FPGAPL receives the REQ data processing request signal from JLK1263 through the high-speed FIFO, the PL starts reading the data from the FIFO interface. The first three input data need to be extracted, which includes the source NC ID, source NC type, and transmission byte length information for subsequent UDP packet assembly. The data payload of the FIFO interface is 16 bits wide. Four data are grouped together to form a 64-bit wide data and stored in the FIFO buffer. Then, it is read out, converted to AXI4 format, and stored in the DDR buffer. The data read from DDR is again buffered in the FIFO buffer and can be used for UDP packet assembly. The assembled packets are processed across clock domains and packaged in AXI format. Then, they are passed to the UDP protocol stack for format conversion and sent to the GLink simulation terminal through the external IO interface, completing this SmartNC->SmartNT data transmission process. When transmitting in SmartNT short message mode, the initialization process is the same. Simply select short message mode when configuring long / short message mode. Taking the SmartNC->SmartNT data transmission process as an example, since the data processing method within the FPGAPL is largely the same, only the overall data flow path is described as follows: In SmartNC short message mode, the GLink node device sends a status sequence to the JLK1263. The JLK1263 then requests data from the FPGAPL. The FPGAPL sends the data to the JLK1263 via a high-speed FIFO interface (to avoid JLK1263 request timeout, the GLink emulation terminal should send a UDP packet to the FPGAPL in advance). The JLK1263 responds to the GLink node device with a status sequence. After the FPGAPL finishes sending data to the JLK1263, the FPGAPL sends a UDP packet to the GLink emulation terminal.

[0064] In some embodiments, please refer to Figure 14 , Figure 14 This invention provides a flowchart illustrating a communication method for applying an Ethernet device to a GLink network, as described in an embodiment of the present invention. The method, applied to the aforementioned communication system for applying an Ethernet device to a GLink network, includes:

[0065] S1410, acquire the transmitted message and detect the message type of the transmitted message;

[0066] S1420: If the message type is a control message, the PS terminal is notified to transmit the UDP message to the GLink emulation terminal via an interrupt; if the message type is a data message and it is long data, the message is transmitted to the JLK1263 chip through the FIFO interface after being buffered by DDR; if the message type is a short message and it is short data, the message is transmitted to the JLK1263 chip through the FIFO interface.

[0067] It should be noted that the communication method for applying Ethernet devices to GLink networks provided in this application embodiment and the communication system for applying Ethernet devices to GLink networks provided in this application embodiment are based on the same application concept. Therefore, the specific implementation of this embodiment can refer to the aforementioned implementation of the communication system for applying Ethernet devices to GLink networks, and the repeated parts will not be described again.

[0068] In some embodiments, please refer to Figure 15 , Figure 15 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 1500 provided in this application includes a processor 1510 and a memory 1520; the memory 1520 stores a computer program, wherein the computer program, when executed by the processor, implements the aforementioned communication method for applying an Ethernet device to a GLink network.

[0069] Specifically, processor 1510 may include, for example, a general-purpose microprocessor, an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. Processor 1510 may also include onboard memory for caching purposes. Processor 1510 may be a single processing unit or multiple processing units for performing different actions of the method flow according to embodiments of this application.

[0070] The memory 1520 may be any medium capable of containing, storing, transmitting, propagating, or transmitting instructions. For example, the memory 1520 may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, instruments, or propagation media. Specific examples of the memory 1520 include: magnetic storage devices such as magnetic tape or hard disk drives (HDDs); optical storage devices such as optical discs (CD-ROMs); and may also be random access memory (RAM) or flash memory; and / or wired / wireless communication links.

[0071] This application also provides a computer-readable medium storing a computer program thereon, which, when executed by a processor, implements the aforementioned communication method for applying an Ethernet device to a GLink network. This computer-readable medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into that device / apparatus / system. The aforementioned computer-readable medium carries one or more programs, which, when executed, implement the method according to the embodiments of this application.

[0072] According to embodiments of this application, a computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wired, optical fiber, radio frequency signals, etc., or any suitable combination thereof.

[0073] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments and / or claims of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application. Therefore, the scope of this application should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A communication system for applying Ethernet devices to a GLink network, characterized in that, include: A GLink bridge device, an Ethernet switch connected to the GLink bridge device via a network cable, and a GLink switch connected to the GLink bridge device via an optical fiber; The PL end of the GLink bridge device establishes a UDP communication link with the Glink emulation terminal through the Ethernet switch; the Glink emulation terminal includes a CtrlNC sub-terminal, a CtrlNT sub-terminal, a SmartNC sub-terminal, and a SmartNT sub-terminal; the PS end of the GLink bridge device establishes an optical fiber communication link with the Glink node device through the GLink switch; the number of sub-devices in the Glink node device is the same as the number of sub-terminals in the Glink emulation terminal. The GLink bridge device includes a JLK1263 chip. When transmitting control messages, the JLK1263 chip notifies the PS end to transmit UDP messages to the GLink emulation terminal via an interrupt. When transmitting data messages, long data messages are buffered by DDR and then transmitted to the JLK1263 chip through the FIFO interface, while short data messages are directly transmitted to the JLK1263 chip through the FIFO interface. When the JLK1263 chip is used as SmartNC and set to long message mode, the GLink emulation terminal will package the SmartNC long message into several UDP packets and send them to the PL end one by one. While receiving UDP packets, the PL terminal writes the UDP packets into the DDR and reads the UDP packets from the DDR to send to the JLK1263 chip. The JLK1263 chip sends the command sequence and the UDP packets to the GLink node device. After receiving the data, the GLink node device returns a status sequence to the JLK1263 chip. After the PL terminal has finished sending all GLink packet data to the JLK1263 chip, it sends the UDP packets to the GLink emulation terminal. When the JLK1263 chip is configured as SmartNT and set to long message mode, the GLink node device, in SmartNC long message mode, sends Smart long messages to the JLK1263 chip via command and data sequences. The JLK1263 chip sends GLink messages to the PL terminal via a high-speed FIFO interface. After the JLK1263 chip finishes sending, it responds to the GLink node device via a status sequence. The PL terminal receives long message messages from the high-speed FIFO interface and writes them into the DDR buffer. Simultaneously, the PL terminal reads GLink messages from the DDR and splits the GLink messages into multiple UDP packets, which are then sent to the GLink emulation terminal.

2. The communication system for applying Ethernet devices to a GLink network as described in claim 1, characterized in that, The PS terminal performs initialization operations and dynamic register configuration on the JLK1263 chip through the EMIF interface, including: communicating with the PL terminal through the AXI-Lite interface, and the PL terminal parses the data and maps the signal passing through the AXI-Lite interface into the form of an EMIF signal to communicate with the JLK1263 chip.

3. The communication system for applying Ethernet devices to a GLink network as described in claim 1, characterized in that, The Glink simulation terminal includes 2 CtrlNC sub-terminals, 1 CtrlNT sub-terminal, 4 SmartNC sub-terminals, and 4 SmartNT sub-terminals. The Glink node device includes 2 CtrlNT sub-devices, 1 CtrlNC sub-device, 4 SmartNC sub-devices, and 4 SmartNT sub-devices.

4. The communication system for applying Ethernet devices to a GLink network as described in claim 1, characterized in that, When the JLK1263 chip is used as CtrlNC, the GLink emulation terminal encapsulates GLink messages into UDP messages and sends them to the PS end of the GLink bridge device. The PS end receives and parses the UDP messages and initiates Ctrl message transmission through the EMIF interface. After receiving the command sequence from the JLK1263 chip, the GLink node device responds with a status sequence. The JLK1263 chip notifies the PS end via an interrupt, and the PS end sends a UDP message to the GLink emulation terminal after receiving the notification.

5. The communication system for applying Ethernet devices to a GLink network as described in claim 1, characterized in that, When the JLK1263 chip is used as CtrlNT, the GLink node device is used as CtrlNC and sends a command sequence to the JLK1263 chip. The JLK1263 chip responds with the command sequence and notifies the PS terminal via an interrupt. After receiving the interrupt notification, the PS terminal obtains the GLink message through the EMIF interface, packages it into a UDP message, and sends it to the GLink emulation terminal.

6. A communication method for applying an Ethernet device to a GLink network, applied to the communication system for applying an Ethernet device to a GLink network as described in any one of claims 1 to 5, characterized in that, include: Acquire the transmitted message and detect the message type of the transmitted message; If the message type is a control message, the PS terminal is notified to transmit a UDP message to the GLink emulation terminal via an interrupt; if the message type is a data message, and it is long data, the transmission message is buffered in DDR and then transmitted to the JLK1263 chip through the FIFO interface; if the message type is a short message, and it is short data, the transmission message is transmitted to the JLK1263 chip through the FIFO interface.

7. An electronic device, comprising a processor and a memory; said memory having storage for computer programs, wherein, When executed by the processor, the computer program implements the communication method of applying an Ethernet device to a GLink network as described in claim 6.

8. A computer storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the communication method for applying an Ethernet device to a GLink network as described in claim 6.

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